Method, system and epi wafer for improving particle contamination of silicon wafers during epitaxy

Abstract

This disclosure provides a method, system, and epitaxial wafer for improving particulate contamination of silicon wafers during epitaxy. The method includes: selecting at least one test silicon wafer from a batch of silicon wafers to be processed, and determining a target power range to be applied to the epitaxial furnace based on the test results of the test silicon wafer; adjusting the effective power applied to the epitaxial furnace to the target power range before the silicon wafer to be processed is fed into the epitaxial chamber of the epitaxial furnace, so that the temperature inside the epitaxial chamber is within a target temperature range; maintaining the effective power of the epitaxial furnace within the target power range until the silicon wafer to be processed enters the epitaxial chamber, thereby using the target temperature range to suppress thermal deformation of the silicon wafer to be processed; and growing an epitaxial layer on the surface of the silicon wafer to be processed after it enters the epitaxial chamber. This disclosure can effectively reduce particulate contamination of the silicon wafer to be processed during epitaxy.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method, system, and epitaxial wafer for improving particulate contamination of silicon wafers during epitaxy. Background Technology

[0002] Epitaxy refers to the process of growing a thin, single-crystal layer with controlled thickness and resistivity on the surface of a single-crystal silicon substrate, or silicon wafer, through chemical vapor deposition, thus obtaining an "epitaxy wafer." This epitaxial layer can be homogeneous with or heterogeneous to the silicon wafer, and is ultimately used to fabricate high-end semiconductor products such as power devices and very large-scale integrated circuits. A typical process includes: silicon wafer cleaning, loading into an epitaxial furnace, high-temperature baking with hydrogen (H2) to remove the native oxide layer, introducing a silicon source (SiH4, SiH2Cl2, etc.) for epitaxial growth, and cooling and removal. The thickness uniformity, surface defect density, and crystal integrity of the epitaxial layer directly determine the yield and device performance of hundreds of subsequent processes such as photolithography, ion implantation, and etching.

[0003] In this process, after polishing, the silicon wafer undergoes wet cleaning to remove metals, organic matter, and oxide layers before being transferred to the epitaxial wafer. Inside the epitaxial wafer, it is baked at approximately 1100°C in an H2 atmosphere to further remove the surface oxide film and repair micro-damage. Epitaxial growth is then performed within the range of 800°C–1150°C using a silicon source gas. After growth, the wafer is purged with nitrogen, cooled, and then removed for online particle / thickness / resistivity testing. The key to particle control in this process lies in the front-end cleaning and baking, which reduces particulate contamination of the silicon wafer itself to ensure the quality of the epitaxial layer.

[0004] However, the relevant solutions overlook the secondary particulate contamination problem encountered in the critical initial stage when the silicon wafer first enters the epitaxial chamber, and lack means to suppress secondary particulate contamination. Summary of the Invention

[0005] This disclosure provides a method, system, and epitaxial wafer for improving particulate contamination of silicon wafers during epitaxy, which can reduce secondary particulate contamination in the early stage of silicon wafer loading into the furnace and improve the integrity and thickness uniformity of the epitaxial layer.

[0006] The technical solution disclosed herein is implemented as follows: In a first aspect, this disclosure provides a method for improving particulate contamination of silicon wafers during epitaxy, comprising: At least one test silicon wafer is selected from the same batch of silicon wafers as the silicon wafer to be processed, and the target power range to be applied to the epitaxial furnace is determined based on the test results of the test silicon wafer. Before the silicon wafer to be processed is fed into the epitaxial chamber of the epitaxial furnace, the effective power applied to the epitaxial furnace is adjusted to the target power range so that the temperature inside the epitaxial chamber is within the target temperature range; The effective power of the epitaxial furnace is maintained within the target power range until the silicon wafer to be processed enters the epitaxial chamber, so as to suppress thermal deformation of the silicon wafer to be processed by utilizing the target temperature range; After the silicon wafer to be processed enters the epitaxial chamber, an epitaxial layer is grown on the surface of the silicon wafer to be processed.

[0007] In some embodiments, selecting at least one test silicon wafer from the same batch as the silicon wafer to be processed, and determining the target power range to be applied to the epitaxial furnace based on the test results of the test silicon wafer, includes: Divide the same batch of silicon wafers into at least one consecutive production group; The first silicon wafer in each production group is used as the test wafer to determine the optimal test effective power range applicable to the production group. The optimal effective power range for testing is used as the target power range for the remaining silicon wafers to be processed in the production group.

[0008] In some examples, the method further includes: Obtain epitaxial growth evaluation data for silicon wafers awaiting processing in the production group; If the epitaxial growth evaluation data of at least one production group meets the first preset condition, the number of silicon wafers in each production group is increased, and the proportion of test silicon wafers selected in the same production batch is reduced. Corresponding to the epitaxial growth evaluation data meeting the second preset condition, the total number of silicon wafers in each production group is reduced to increase the selection ratio of test silicon wafers in the same production batch.

[0009] In some examples, the method further includes: If the epitaxial growth evaluation data of the silicon wafer to be processed is lower than the third preset condition, the next silicon wafer in the production group that is to be processed is set as the test silicon wafer, and the target power range is updated based on the set test silicon wafer. The process continues until the epitaxial growth evaluation data of the silicon wafer to be processed, based on the updated target power range, meets the first preset condition.

[0010] In some examples, the first silicon wafer in each production group is used as the test wafer to determine the optimal test effective power range applicable to the production group, including: Before the test silicon wafer is sent into the epitaxial chamber, multiple effective test powers are applied to the epitaxial furnace to keep the temperature in the epitaxial chamber within the corresponding test temperature range. Acquire test deformation data of the test silicon wafer during the initial stage of entering the epitaxial chamber due to exposure to multiple test temperature ranges; Among all the test deformation data, the target power range is determined based on the effective power range corresponding to the test deformation data that minimizes the deformation of the test silicon wafer and has the fastest deformation recovery speed.

[0011] In some examples, test deformation data are determined based on measurements taken at multiple points at predetermined radial distances on the surface of the test silicon wafer.

[0012] In some examples, obtaining multiple test deformation data includes: During the initial deformation of the test silicon wafer, the instantaneous height values ​​of multiple measurement points relative to the reference plane are measured in real time. For each test temperature range, the instantaneous height value of each measurement point is compared in real time to determine the maximum height value at each measurement point, and the maximum value among the multiple maximum height values ​​corresponding to multiple measurement points is taken as the test deformation data.

[0013] In some examples, the method further includes: In the initial stage after the silicon wafer to be processed enters the epitaxial chamber, the effective power is maintained within the target power range and reaches the set time threshold to improve the deformation recovery speed of the silicon wafer to be processed and shorten the time for the silicon wafer to reach thermal equilibrium. The time threshold includes the time period from when the silicon wafer to be processed enters the epitaxial chamber to when it completes mechanical placement and reaches thermal equilibrium.

[0014] In some examples, the diameter of the silicon wafer to be processed is 300 mm, and the target temperature range is 780±10℃.

[0015] Secondly, this disclosure provides a system for improving particulate contamination of silicon wafers during epitaxy, comprising: An epitaxial furnace having an epitaxial chamber for growing epitaxial layers on the surface of a silicon wafer to be processed; A power regulator configured to regulate the effective power applied to the epitaxial furnace; The controller, coupled to the power regulator, is configured to: select at least one test silicon wafer from the same batch of silicon wafers as the silicon wafer to be processed, and determine a target power range to be applied to the epitaxial furnace based on the test results of the test silicon wafer; adjust the effective power applied to the epitaxial furnace to the target power range before the silicon wafer to be processed is fed into the epitaxial chamber of the epitaxial furnace, so that the temperature inside the epitaxial chamber is within the target temperature range; and maintain the effective power of the epitaxial furnace within the target power range until the silicon wafer to be processed enters the epitaxial chamber, so as to suppress thermal deformation of the silicon wafer to be processed by utilizing the target temperature range.

[0016] In some examples, the controller is also configured as follows: Divide the same batch of silicon wafers into at least one consecutive production group; The first silicon wafer in each production group was used as the test wafer to determine the optimal effective power range for testing within the production group; and The optimal effective power range for testing will be used as the target power range for the remaining unprocessed silicon wafers in the production group.

[0017] In some examples, the controller is also configured as follows: Obtain epitaxial growth evaluation data for silicon wafers awaiting processing in the production group; If the epitaxial growth evaluation data of at least one production group meets the first preset condition, the number of silicon wafers in each production group is increased, and the proportion of test silicon wafers selected in the same production batch is reduced. Corresponding to the epitaxial growth evaluation data meeting the second preset condition, the total number of silicon wafers in each production group is reduced to increase the selection ratio of test silicon wafers in the same production batch.

[0018] In some examples, the controller is also configured as follows: If the epitaxial growth evaluation data of the silicon wafer to be processed is lower than the third preset condition, the next silicon wafer in the production group that is to be processed is set as the test silicon wafer, and the target power range is updated based on the set test silicon wafer. The process continues until the epitaxial growth evaluation data of the silicon wafer to be processed, based on the updated target power range, meets the first preset condition.

[0019] In some examples, the controller is configured as follows: Before the test silicon wafer is placed into the epitaxial chamber, multiple effective test powers are applied to the epitaxial furnace to keep the temperature inside the epitaxial chamber within the corresponding test temperature range; and the system further includes: The deformation analysis unit is configured to acquire multiple test deformation data of the test silicon wafer during the initial stage of entering the epitaxial chamber due to exposure to multiple test temperature ranges; The optimization selection unit, coupled to the deformation analysis unit and the controller, is configured to determine the target power range based on the effective power range corresponding to the test deformation data that minimizes the deformation of the test silicon wafer and has the fastest deformation recovery speed among all test deformation data, and output the target power range to the controller.

[0020] In some examples, the deformation analysis unit is configured to determine test deformation data based on measurements taken at multiple measurement points at predetermined radial distances on the surface of the test silicon wafer.

[0021] In some examples, the deformation analysis element includes: The multi-point displacement sensing module is configured to measure the instantaneous height values ​​of multiple measurement points relative to a reference plane in real time during the initial stage of deformation of the test silicon wafer. The maximum value extraction module, coupled to the multi-point displacement sensing module, is configured to compare the instantaneous height value of each measurement point in real time for each test temperature range to determine the maximum height value at each measurement point, and take the maximum value among the multiple maximum height values ​​corresponding to multiple measurement points as the test deformation data.

[0022] Thirdly, this disclosure provides an epitaxial wafer obtained by growing an epitaxial layer on a silicon wafer to be processed. The epitaxial wafer is obtained by a method for improving particulate contamination of the silicon wafer during epitaxy as described in the first aspect, or by a system for improving particulate contamination of the silicon wafer during epitaxy as described in the second aspect. The epitaxial wafer has an average number of local light scatterers on its surface of less than or equal to 0.15 when the detection size is greater than or equal to 200 nm. The average number refers to the ratio of the total number of local light scatterers obtained by detecting multiple said epitaxial wafers to the total number of epitaxial wafers.

[0023] This disclosure provides a method, system, and epitaxial wafer for improving particulate contamination of silicon wafers during epitaxy. The method involves selecting test silicon wafers from the same batch for testing and using the test results to determine the target power range to be applied to the epitaxial furnace. This ensures that the determined target power range is compatible with the current batch of silicon wafers to be processed, improving the matching degree between the initial thermal environment of the epitaxial equipment and the characteristics of the silicon wafers. Furthermore, before the silicon wafer is fed into the epitaxial chamber, the effective power is adjusted to a target power range compatible with the silicon wafer, and this effective power is maintained until the silicon wafer enters the epitaxial chamber. This reduces the thermal shock when room temperature silicon wafers enter the high-temperature chamber. By utilizing the target temperature range adapted to this batch of silicon wafers, thermal deformation (such as warping) that occurs after the silicon wafers enter the epitaxial chamber is suppressed, thus maintaining the flatness of the silicon wafers. This maintains stable laminar flow of gas within the chamber, avoiding the settling of suspended particles caused by airflow eddies; it also reduces the risk of abnormal mechanical scratching between the silicon wafers and the conveying mechanism in the epitaxial furnace due to warping, thereby reducing the risk of secondary particle contamination of the silicon wafers. Attached Figure Description

[0024] Figure 1 The schematic diagram illustrates the composition of a system for improving silicon wafer particle contamination integrated into an epitaxial furnace according to an embodiment of the present disclosure.

[0025] Figure 2 schematically shown Figure 1 The system's extended structure includes deformation analysis units and optimization selection units, used to determine the target power range during the testing phase.

[0026] Figure 3 The diagram schematically depicts a situation where multiple measurement points are uniformly arranged at the same radial distance on the surface of the test silicon wafer and instantaneous height is monitored.

[0027] Figure 4 A flowchart illustrates a method for improving silicon wafer particle contamination during epitaxial growth according to an embodiment of this disclosure.

[0028] Figure 5 This is a schematic diagram of the process for determining the target power range based on a test silicon wafer, as provided in this disclosure.

[0029] Figure 6 Presented in the form of a flowchart Figure 5 The extended steps of the method include a complete process of acquiring deformation data through test silicon wafers and optimizing the selection of target power ranges.

[0030] Figure 7 Show in detail in the form of a flowchart Figure 6 The sub-steps for obtaining test deformation data include real-time measurement and maximum value extraction.

[0031] Figure 8 An epitaxial wafer prepared by the system or method of this disclosure is shown schematically. Detailed Implementation

[0032] The technical solutions in this disclosure will now be clearly and completely described with reference to the accompanying drawings.

[0033] Epitaxial growth is based on the fundamental consensus that "the cleaner the silicon wafer surface, the higher the quality of the epitaxial layer." Therefore, all efforts have focused on the cleaning, drying, and high-temperature baking processes before the silicon wafer enters the epitaxial furnace. However, the microenvironment in which the silicon wafer is placed when it enters the epitaxial chamber has long been neglected. For example, the chamber walls, gas nozzles, support pins, and even the robotic arm may release particles during standby or heating phases. These particles, accompanied by carrier gas or simply due to gravity, fall onto the silicon wafer surface that has not yet been covered by the epitaxial layer.

[0034] Since the relevant solutions cannot provide any suppression or monitoring methods at this stage, the silicon wafer is exposed to secondary particulate contamination in the first ten seconds or so of the "furnace entry—heating—growth commencement" process. Experimental data shows that the number of newly introduced particles of 0.12 µm and above during this period is often enough to weaken the effect of front-end cleaning and may even become the main source of subsequent defects.

[0035] More seriously, these later-deposited particles are not uniformly distributed. Instead, they are locally concentrated at the edges or warped peaks and valleys of the silicon wafer due to the combined effects of airflow vortices, thermal convection, and the thermal deformation of the silicon wafer itself. This induces localized growth retardation, lattice mismatch, and resistivity drift during the epitaxial growth stage, ultimately resulting in discrete electrical failures of the device. In other words, while cleaning and baking reduce the particles carried by the silicon wafer itself, they are ineffective against secondary contamination caused by particles deposited in the chamber during the initial stage of wafer entry. Once contamination occurs, existing solutions cannot either embed or eliminate the particles in subsequent steps or correct them in real time during the process. The only recourse is to passively accept the decrease in epitaxial wafer yield and additional rework in subsequent processes. Therefore, how to actively suppress and reduce the deposition of secondary particles on the silicon wafer surface within this extremely short but critical time window—"after entering the epitaxial chamber and before the epitaxial layer begins to grow"—has become an untapped yet urgently needed area for resolution.

[0036] Based on this, see Figure 1 This disclosure provides a system 10 for improving particulate contamination on a silicon wafer W during epitaxy. In this disclosure, the silicon wafer W may also be referred to as the silicon wafer to be processed. For example, in... Figure 1 As shown, the system 10 is integrated into a standard epitaxial furnace EF for performing epitaxial growth processes in semiconductor manufacturing. The overall structure of the epitaxial furnace EF is well-known to those skilled in the art; its core is an epitaxial chamber EC for chemical vapor deposition, enclosed by an upper bell jar C1 and a lower bell jar C2 made of quartz. Inside the epitaxial chamber EC, a base SU is provided, made of high-purity graphite material and typically coated with silicon carbide (SiC) to enhance its chemical stability and durability. This base SU not only serves as a platform supporting the silicon wafer W, but more importantly, it efficiently absorbs and uniformly transfers heat to the silicon wafer W above it. During the process, the base SU is driven by a precision motor, enabling stable rotation around its central axis. This design aims to ensure a highly uniform temperature distribution for the silicon wafer W throughout the heating and growth stages.

[0037] To provide the necessary thermal energy to the epitaxial chamber EC, multiple sets of high-power halogen lamps HL are densely arranged around the exterior of the epitaxial furnace EF. These halogen lamps HL serve as a heat source for rapid heat treatment, enabling rapid temperature rise and fall and precise control of the epitaxial chamber EC. In addition, the epitaxial chamber EC is also designed with inlets IF for introducing various gases according to the process flow, such as high-purity hydrogen (H2) for baking and as a carrier gas, and gases used as silicon sources (such as SiH4, SiH2Cl2, etc.). Simultaneously, the epitaxial chamber EC is also equipped with an exhaust port XF, which is connected to a complex vacuum pump system to precisely maintain the different pressure levels inside the epitaxial chamber EC required by the process.

[0038] The system 10 provided in this embodiment includes a high-performance power regulator 12 and a controller 14 that serves as the system control center.

[0039] The power regulator 12 is specifically configured to perform real-time, high-precision regulation of the overall effective power applied to the epitaxial furnace EF. Technically, the power regulator 12 can be a power control unit based on a thyristor or silicon controlled rectifier. It achieves millisecond-level response and linear regulation of the total heating power by controlling the phase angle or pulse duty cycle of the AC power supplied to multiple halogen lamps HL. This precise power regulation capability is the physical basis for enabling the temperature inside the epitaxial chamber EC to be quickly and stably controlled within any preset target temperature range.

[0040] The controller 14, in hardware, can be an industrial-grade programmable logic controller or an embedded microprocessor system, running a specially developed control algorithm. The controller 14 is tightly coupled to the power regulator 12 via a data bus. Its core function is that it is programmed to proactively control the power regulator 12 during the standby or preparation phase before the silicon wafer W for production is fed into the epitaxial chamber EC by the transfer arm (not shown in the figure). This proactively adjusts the effective power applied to the epitaxial furnace EF to an optimized target power range determined after testing with a test silicon wafer. Specifically, the controller 14 selects at least one test silicon wafer from the same batch as the wafer to be processed and determines the target power range applied to the epitaxial furnace based on the test results of that test silicon wafer. In this way, the measured target power range can eliminate the influence of fluctuations in thermal absorption rate caused by differences in initial warpage, doping type, and concentration between different batches of silicon wafers.

[0041] Specifically, based on the Joule-Lenz law and the complex thermodynamic model of the epitaxial chamber (EC), a stable and precise effective power input necessarily corresponds to a stable and uniform steady-state temperature of the EC, i.e., the target temperature range. By selecting this target power range and the corresponding target temperature range, this disclosure can proactively and predictively suppress the instantaneous thermal deformation of the silicon wafer W due to severe thermal shock in the initial stage of entering the high-temperature EC from a room temperature environment (usually within the first few seconds to a dozen seconds after entering the EC).

[0042] The technical effect achieved by this embodiment is that by creating a thermal environment before the silicon wafer W enters the epitaxial chamber EC, the problem of particulate contamination is significantly solved at its source. Its underlying mechanism can be understood from the following aspects.

[0043] First, in terms of physical mechanism, it effectively mitigates the thermal shock effect. When a silicon wafer W at room temperature (approximately 25°C) is suddenly inserted into an epitaxial chamber EC that is in a conventional standby or high-temperature state (e.g., exceeding 900°C), the silicon wafer experiences a significant temperature shock. Since heat conduction from the edge to the center of the silicon wafer takes time, the edges heat up and expand faster than the central region. This uneven thermal expansion generates enormous thermal stress within the silicon wafer, leading to significant warping deformation, typically "bowl-shaped" or "saddle-shaped." The target temperature range set in this disclosure reduces the initial temperature difference faced by the silicon wafer when entering the epitaxial chamber EC, thereby slowing down the accumulation rate and peak of thermal stress, and suppressing the overall deformation of the silicon wafer to a lower level.

[0044] Secondly, at the fluid dynamics level, suppressing the deformation of the silicon wafer W directly optimizes the airflow field on the wafer surface. A highly flat silicon wafer surface facilitates the formation of a uniform and stable laminar flow state for the H2 gas, which serves as the carrier gas, within the epitaxial chamber EC. This laminar flow can smoothly pass over the silicon wafer surface and effectively carry away tiny particles suspended in the epitaxial chamber EC, which may be generated by equipment movement or airflow disturbances, and discharge them through the exhaust port XF. Conversely, a severely warped silicon wafer W will severely disrupt the laminar flow state near its surface, generating complex gas vortices and local stagnation zones in the "peaks" and "valleys" formed by the warping. The gas velocity in these areas is extremely low, making it easy for particles originally suspended in the airflow to deposit on the silicon wafer surface due to gravity or electrostatic attraction, resulting in secondary contamination.

[0045] Furthermore, from a mechanical contact perspective, maintaining the flatness of the silicon wafer also avoids particles generated by physical contact. During the placement of a deformed silicon wafer W onto the base SU by the transfer arm, its warped edges or center are more prone to unwanted scratching, collisions, or sliding with the end effector of the arm or the support pins on the base SU. These mechanical contacts are a significant but often overlooked source of additional particulate contamination. The solution disclosed herein avoids the generation of such contact-related particles.

[0046] Moreover, corresponding to the suppression of deformation of the silicon wafer W, the deformation recovery speed is much faster. A fast deformation recovery speed means that the time required for the silicon wafer W to reach its final stable flat state (thermal equilibrium state) from the moment it enters the chamber and comes into contact with the high-temperature environment is extremely short. In other words, the duration of the "non-ideal flat state" is shortened. This greatly reduces the effective time window for particles to overcome the airflow drag and settle onto the surface of the silicon wafer W, because particles need sufficient time to settle in the low-velocity region, while the rapidly recovering silicon wafer W leaves them almost no such time. In other words, the brief existence of the vortex / low-velocity region is insufficient to effectively capture and deposit particles; before the particles have a chance to effectively settle in a localized area, the silicon wafer W has already returned to flatness, and the flow field quickly returns to a uniform laminar flow, smoothly carrying away the particles.

[0047] In summary, this embodiment suppresses initial thermal deformation of the epitaxial chamber EC by actively and precisely controlling its temperature before the silicon wafer W enters the epitaxial growth station, ensuring it remains in an extremely clean microenvironment. This method addresses the unavoidable secondary particle contamination problem in related solutions by optimizing the airflow field to actively remove suspended particles and eliminating mechanical contact to reduce new particle growth. The ultimate technical effect is improved crystal integrity of the subsequently grown epitaxial layer, and a reduction in the density of fatal defects such as stacking faults and pits caused by particles acting as "epitaxygian defect nuclei." Simultaneously, the shielding effect of particles on the reactive gases is significantly weakened, resulting in a marked improvement in the uniformity of the epitaxial layer thickness and resistivity across the entire silicon wafer W, laying a solid foundation for the success of subsequent chip manufacturing processes.

[0048] The impact of effective power on particulate contamination is verified below using production line data from actual production processes. Specifically, the actual epitaxial production process of a certain type of epitaxial furnace was monitored. The monitoring sample consisted of 10 silicon wafers (30 wafers in total) at each set effective power, with effective power settings of 33 kW, 36 kW, and 40 kW, and a monitored particle size of 200 nm. The monitoring results are shown in Table 1 below.

[0049] Table 1: Monitoring Results (Statistics by Pollution Level)

[0050] As shown in Table 1, the degree of particulate contamination exhibits a non-linear relationship of "first decreasing and then increasing" with effective power. 36 kW is the optimal power point; under this condition, severe contamination is zero, the proportion of slight contamination is highest (90%), and overall contamination is lightest. Both 33 kW and 40 kW lead to a higher proportion of significant contamination, indicating that power deviations from 36 kW weaken the suppression effect on particulate contamination. These experimental results demonstrate that selecting a target power range can effectively reduce particulate contamination in the initial stage of silicon wafer entry into the epitaxial chamber.

[0051] In some embodiments of this disclosure, see Figure 2 The controller 14 is also configured to control the power regulator 12 to apply multiple effective test powers to the epitaxial furnace EF before the test silicon wafer TW, which is in the same production batch as the silicon wafer W, is fed into the epitaxial chamber EC, so that the temperature inside the epitaxial chamber EC is within a corresponding multiple test temperature ranges. Furthermore, the system 10 may also include a deformation analysis unit 16 and an optimization selection unit 18.

[0052] The deformation analysis unit 16 is configured to acquire multiple test deformation data generated by the test silicon wafer TW during the initial stage of entering the epitaxial chamber EC due to exposure to multiple test temperature ranges.

[0053] The optimization selection unit 18 is coupled to the deformation analysis unit 16 and the controller 14, and is configured to determine the target power range based on the effective power range corresponding to the test deformation data that minimizes the deformation of the test silicon wafer and has the fastest deformation recovery speed among all test deformation data, and output the target power range to the controller 14.

[0054] Specifically, this embodiment further provides a systematic optimization selection method and corresponding system functional modules based on system 10. This functionally expanded system 10, in addition to including the basic power regulator 12 and controller 14, further integrates a deformation analysis unit 16 specifically for quantitative analysis of silicon wafer deformation, and an optimization selection unit 18 for data processing and decision-making.

[0055] The process described in this embodiment can be understood as a highly automated "process parameter calibration and optimization" process performed before formal mass production. Its detailed, step-by-step workflow is as follows.

[0056] The first step is experimental preparation. Before sending the expensive silicon wafers W, intended for mass production, into the epitaxial chamber EC, a series of exploratory experiments are conducted using specialized test silicon wafers TW. In some examples, the test silicon wafer TW can be a lower-cost baffle or a specially fabricated, representative test wafer. When the test silicon wafer TW is in the same production batch as the silicon wafer W, the test silicon wafer can be the first wafer in the batch or a specific proportion, such as 10% of the wafers. Understandably, a very small number of test silicon wafers may produce more particles during the testing process due to experiencing suboptimal temperatures. However, at the cost of this, the testing process allows for the precise calibration of the target power (e.g., corresponding to 780°C) that suits the physical characteristics of the batch. Subsequently, the remaining production silicon wafers W in the batch will directly utilize this target power for initial stage control. This allows for the formation of customized mass production parameters for each batch of silicon wafers, thereby improving the crystal integrity and thickness uniformity of the entire batch of epitaxial wafers with minimal cost sacrifice.

[0057] The second step is parameter scanning. Controller 14 initiates a preset test program. Under this program, controller 14 systematically controls the power regulator 12 to apply a series of multiple discrete test power values ​​covering a wide range to the epitaxial furnace EF. For example, starting from a lower power value, it increases in fixed steps until a higher power value is reached. Each set test power value is used to precisely stabilize the temperature within the epitaxial chamber EC within a corresponding test temperature range through closed-loop control.

[0058] The third step is deformation measurement. For each stabilized test temperature range, the system automatically sends a brand-new test silicon wafer (TW) into the epitaxial chamber (EC). In the initial stage of the test silicon wafer (TW) entering the chamber and undergoing thermal shock, the deformation analysis unit 16 is activated synchronously. Its built-in sensors capture and measure the deformation of the test silicon wafer (TW) under that specific test temperature range in real time and dynamically, and quantify it into one or a set of specific test deformation data.

[0059] The fourth step is cyclic testing and data acquisition. The aforementioned "feed-measure-retrieve" process is automatically and repeatedly performed for each preset test temperature range. After each test, the deformation analysis unit 16 associates the measured deformation data with the corresponding test temperature range and stores it. Finally, when all test points are completed, the system obtains a complete set of data, which clearly reveals the functional relationship between the silicon wafer deformation and the preset temperature of the chamber.

[0060] Step 5: Data Analysis and Optimization Decision. The optimization selection unit 18, as an intelligent software module, is coupled to the controller 14 and is authorized to access all test deformation data collected by the deformation analysis unit 16. The core function of the optimization selection unit 18 is to perform in-depth analysis and comparison based on these valuable (temperature-deformation) data pairs obtained through actual measurements. For example, it can perform curve fitting between these discrete data points to find a mathematical model that accurately describes the deformation behavior. Then, by solving for the minimum value of this model, the preferred effective power range (and its corresponding preferred test temperature range) that minimizes the TW deformation of the test silicon wafer can be precisely determined.

[0061] Step 6: Parameter Consolidation. Finally, the optimization selection unit 18 will output and store the optimal effective power range determined through the above process as the final target power range in the process recipe database of the controller 14. In the subsequent formal production process of all similar products, the controller 14 will always call this experimentally verified target power range to preset the initial environment of the epitaxial chamber EC.

[0062] The technical advantage of this embodiment lies in its elimination of the inefficient approach of relying on engineers' experience, rough theoretical estimations, or repeated trial and error in related solution development. Instead, it provides a scientific, rigorous, repeatable, and data-driven automated method to determine the most critical process parameters. By conducting multiple sets of systematic experiments on real test silicon wafers (TW) and precisely quantifying their deformation data, the optimal temperature for suppressing deformation can be found. This ensures that the selected target temperature range is applicable and effective for specific epitaxial furnace (EF) equipment models, specific silicon wafer (W) specifications (e.g., different diameters, thicknesses, crystal orientations, doping types, etc.), and the current state of the chamber (e.g., lifespan, cleanliness, etc.), thereby suppressing secondary particulate contamination and improving process stability and yield.

[0063] In some embodiments, during high-volume manufacturing (HVM) of semiconductor epitaxy, as the number of wafers processed increases, the internal state of the chamber, such as the coating thickness on the graphite substrate and quartz bell jar surface, will drift, resulting in changes in the actual thermal environment generated by the same effective power. Therefore, the target power range is not fixed, but is acquired and continuously updated in real time based on the test results of dynamically selected test silicon wafers within the same production batch.

[0064] Specifically, to achieve the aforementioned real-time updates, the controller 14 can also be configured to divide the silicon wafers of the same production batch into at least one consecutive production group. For example, for a production batch containing 100 silicon wafers, initially, each production group consists of 10 wafers. Within each production group, the controller 14 tests the first-ranked wafer as the test wafer, determining the optimal test power range suitable for that production group by applying multiple test power levels and measuring deformation. Subsequently, the controller 14 uses this optimal test power range as the target power range for the remaining wafers to be processed in that production group. That is, before the last nine wafers to be processed enter the epitaxial chamber, the controller adjusts the effective power applied to the epitaxial furnace to this target power range to keep the temperature within the epitaxial chamber within the target temperature range. This can compensate for thermal errors caused by chamber state drift.

[0065] In some embodiments, in order to achieve a balance between silicon wafer yield and equipment capacity, the controller 14 may also be configured to dynamically adjust the selection frequency of test silicon wafers based on the epitaxial growth effect.

[0066] Specifically, in actual production, the controller 14 will also acquire epitaxial growth evaluation data of the silicon wafer to be processed in real time or periodically to evaluate the epitaxial growth effect. For example, the epitaxial growth evaluation data may include data such as the number of localized light scatterers (LLS) on the silicon wafer surface and the uniformity of the epitaxial layer thickness, which are obtained through online measurement equipment.

[0067] When the epitaxial growth evaluation data of multiple consecutive production groups meet a first preset condition, such as the average number of LLS (Limited Series Saturation) of the silicon wafers to be processed in three consecutive production groups being lower than a set threshold, it indicates that the current epitaxial chamber state is stable and the epitaxial growth effect of the silicon wafers to be processed is qualified. In this case, the controller 14 increases the total number of silicon wafers in each production group to reduce the proportion of test silicon wafers selected in the same production batch. For example, the controller 14 dynamically adjusts the original group of 10 wafers to a group of 20 wafers, with the first wafer used as a test wafer and the subsequent 19 wafers used as wafers to be processed, thereby reducing the time required for testing and increasing production capacity.

[0068] When the epitaxial growth evaluation data meets a second preset condition, such as the number of LLS (Limited Series Seams) on the silicon wafer after epitaxial growth showing an upward trend or approaching a warning threshold, indicating fluctuations in the epitaxial chamber state, the controller 14 reduces the total number of silicon wafers in each production group to increase the selection ratio of test silicon wafers in the same production batch. For example, the production group capacity is reduced to a group of 5 wafers, with the first wafer used as a test wafer and the subsequent 4 wafers used as wafers to be processed. This allows for more intensive testing and power updates to narrow the process window and prevent further deterioration of yield.

[0069] In some embodiments, an abnormal triggering mechanism can be introduced to address sudden severe process deviations. Specifically, during continuous production, when the epitaxial growth evaluation data of the silicon wafer to be processed falls below a third preset condition, it indicates that the epitaxial growth effect of the silicon wafer to be processed has not met the qualification standard, such as the number of LLS exceeding the scrap limit. In this case, the controller 14 can interrupt the current production group division rule, that is, abolish the current grouping logic of 10 wafers, 20 wafers, or 5 wafers, and set the next silicon wafer as a test wafer. The test is then re-performed using the newly set test wafer, and the target power range is updated. The interrupted production group division rule is resumed only after the epitaxial growth effect of the silicon wafer to be processed according to the updated target power range recovers to the qualification standard, that is, after the epitaxial growth evaluation data of the silicon wafer to be processed according to the updated target power range meets the aforementioned first preset condition. In this way, the loss caused by process deviation can be controlled at the single-wafer level, reducing the risk of scrapping the entire batch of silicon wafers.

[0070] In some embodiments of this disclosure, see Figure 3 The deformation analysis unit 16 can be configured to determine test deformation data based on measurements of multiple measurement points P at predetermined radial distances on the surface of the test silicon wafer TW.

[0071] Specifically, the predetermined radial distance refers to the radius of the circle from the center point O of the silicon wafer to the measurement point P. This distance can be selected according to the testing requirements. For example, based on theoretical analysis or experience, the maximum deformation may occur at approximately two-thirds of the silicon wafer radius, so this radial distance can be selected for measurement; similarly, it can also be selected at half the silicon wafer radius, such as at... Figure 3 As shown, if the radius of the silicon wafer is R, multiple measurement points are taken at a distance of R / 2 from the center point O of the wafer, or very close to the edge of the wafer, to capture deformation characteristics in different areas. Crucially, all measurement points P used for a single evaluation are located on the same circumference, equidistant from the center. This allows for sensitive and effective capture of features that reflect the overall severity of deformation.

[0072] In some embodiments of this disclosure, see Figure 3 The deformation analysis unit 16 may include a multi-point displacement sensing module 162 and a maximum value extraction module 164.

[0073] The multi-point displacement sensing module 162 is configured to measure the instantaneous height values ​​of multiple measurement points P relative to the reference plane in real time during the initial stage of deformation of the test silicon wafer TW.

[0074] More specifically, the multi-point displacement sensing module 162, during the entire initial dynamic phase of the test silicon wafer TW from its insertion into the chamber until its temperature stabilizes, can measure the instantaneous height values ​​of the aforementioned multiple measurement points P relative to a fixed reference plane in real time with extremely high time resolution (e.g., hundreds of times per second). This reference plane can be a virtual plane predefined during system calibration, representing the silicon wafer W in an ideal, undeformed state. To comprehensively capture various possible deformation modes, these measurement points P are uniformly distributed in the circumferential direction of the test silicon wafer TW, such as... Figure 3 As shown, a measurement point P is set every 22.5 degrees on the circumference. This allows for accurate measurement of symmetrical "bowl-shaped" bends as well as precise capture of asymmetrical "saddle-shaped" twists. In terms of hardware implementation, the multi-point displacement sensing module 162 can be constructed from a set of non-contact, high-precision laser triangulation displacement sensor arrays, or a more advanced optical profile measurement system (such as a white light interferometer or structured light scanner) to ensure non-invasiveness and high accuracy of the measurement.

[0075] The maximum value extraction module 164 is coupled to the multi-point displacement sensing module 162 and is configured to compare the instantaneous height value of each measurement point P in real time for each test temperature range to determine the maximum height value of each measurement point P, and take the maximum value among the multiple maximum height values ​​corresponding to multiple measurement points P as the test deformation data.

[0076] More specifically, the maximum value extraction module 164 can actually be an advanced data processing algorithm embedded in the controller 14 or a dedicated data acquisition card. Its core responsibility is to process the height data stream acquired by the multi-point displacement sensing module 162. Its detailed processing logic is as follows: for a complete measurement process conducted within a specific test temperature range, the maximum value extraction module 164 compares the instantaneous height values ​​of each measurement point P at different times in parallel and in real time, thereby determining the maximum height value deviating from the reference plane that measurement point P has experienced during this dynamic process. After obtaining the maximum height values ​​corresponding to all measurement points P, the module 164 performs a final comparison and filtering of these maximum height values, selecting the global maximum value. This final filtered maximum value serves as the test deformation data representing the degree of deformation severity at that test temperature.

[0077] This refined measurement and data processing method, characterized by "multi-point monitoring, dynamic tracking, and extreme value extraction," greatly ensures the accuracy, objectivity, and robustness of deformation assessment results. It provides not merely a vague, average deformation figure, but precisely captures the most severe local deformation occurring throughout the entire dynamic process and in the critical area. In engineering practice, it is precisely these most extreme local deformations that are most likely to cause catastrophic airflow turbulence or destructive mechanical collisions. Therefore, optimizing process parameters based on this hard data representing the "worst-case scenario" ensures that the ultimately selected target temperature range is truly effective in suppressing the most harmful deformation events, thereby enabling the control of particulate contamination to reach its optimal physical limits.

[0078] In some embodiments of this disclosure, the diameter of the silicon wafer W can be 300 mm, and the target temperature range can be 780±10℃.

[0079] Specifically, this embodiment targets current mainstream semiconductor manufacturing lines. System 10 is specifically designed for processing large-size silicon wafers W with a diameter of 300 mm, which represent the largest and most technically challenging size in the industry standard. These large-size silicon wafers W are mechanically more fragile due to their extremely large surface area and relatively small thickness-to-diameter ratio. When subjected to severe thermal shock, the resulting internal thermal stress concentration and macroscopic warping deformation are particularly prominent and severe. Therefore, the technical solution disclosed herein offers the most significant and critical process improvement for these large-size wafers.

[0080] By following the process described in the foregoing embodiments—that is, by using a 300 mm test silicon wafer TW to perform deformation tests within a test temperature range, and by accurately acquiring and deeply analyzing the deformation data using a high-precision multi-point displacement sensing module 162 and an intelligent maximum value extraction module 164—a preferred target temperature range can be determined for the 300 mm silicon wafer W. After extensive experimental verification, a particularly effective and robust target temperature range was determined to be 780 ± 10 °C.

[0081] The materials science and solid mechanics principles underlying the selection of this specific temperature range (780±10℃) are as follows. The area around 780℃ represents a crucial "elastoplastic" transition region in the thermo-mechanical properties of a 300 mm single-crystal silicon wafer. Below this range, silicon exhibits significant brittleness, behaving more like a pure elastic body. The enormous internal stress caused by uneven thermal expansion cannot be released through microscopic lattice slip, but only through macroscopic, large-scale, reversible elastic warping. Above this range, however, silicon fully enters the plastic deformation region. Dislocation movement within the crystal becomes excessively active and uncontrollable. While stress can be released, this leads to non-uniform, irreversible plastic flow in the silicon wafer, i.e., permanent deformation, which is fatal to subsequent processes such as photolithography. Therefore, the 780±10℃ process window represents a temperature range that balances effective internal stress release with the suppression of excessive macroscopic deformation. Within this temperature range, the silicon crystal can activate a moderate dislocation slip mechanism, allowing thermal stress to be relaxed promptly and effectively through small, uniform, and controllable plastic deformation without triggering large-scale, uncontrollable permanent deformation. The ultimate effect is that a 300 mm silicon wafer W can maintain its original flatness to the maximum extent possible during the initial stage of entering the epitaxial chamber EC.

[0082] The above embodiment provides a specific process parameter window for the epitaxial process of 300 mm large-size silicon wafers and enables production practice. By precisely controlling the pre-entry temperature of the epitaxial chamber EC within the process window of 780±10℃, the initial deformation of the 300 mm silicon wafer W can be suppressed to the greatest extent, thereby suppressing secondary particle contamination on the surface and improving the final quality and production yield of large-size epitaxial wafers.

[0083] See Figure 4 and combined Figure 1 This disclosure also provides a method for improving particulate contamination of silicon wafer W during epitaxy, which may include the following steps S401 to S404.

[0084] In step S401, at least one test silicon wafer is selected from the silicon wafers in the same batch as the silicon wafer to be processed, and the target power range to be applied to the epitaxial furnace is determined based on the test results of the test silicon wafer.

[0085] In step S402, before the silicon wafer to be processed is fed into the epitaxial chamber of the epitaxial furnace, the effective power applied to the epitaxial furnace is adjusted to the target power range so that the temperature inside the epitaxial chamber is within the target temperature range.

[0086] In step S403, the effective power of the epitaxial furnace is maintained within the target power range until the silicon wafer to be processed enters the epitaxial chamber, so as to suppress thermal deformation of the silicon wafer to be processed by utilizing the target temperature range.

[0087] In step S404, after the silicon wafer to be processed enters the epitaxial chamber, an epitaxial layer is grown on the surface of the silicon wafer to be processed.

[0088] based on Figure 4 The technical solution disclosed herein involves selecting test silicon wafers from the same batch for testing, and then determining the target power range to be applied to the epitaxial furnace based on the test results. This ensures that the determined target power range is compatible with the current batch of silicon wafers to be processed, improving the matching degree between the initial thermal environment of the epitaxial equipment and the characteristics of the silicon wafers. Furthermore, before the silicon wafers to be processed are fed into the epitaxial chamber, the effective power is adjusted to a target power range compatible with the wafers, and this effective power is maintained until the wafers enter the epitaxial chamber. This reduces the thermal shock when room temperature silicon wafers enter the high-temperature chamber, and by utilizing a target temperature range compatible with the batch of silicon wafers, thermal deformation (such as warping) of the wafers after entering the epitaxial chamber is suppressed, maintaining the flatness of the wafers. This maintains stable laminar flow of gas within the chamber, avoiding the settling of suspended particles due to airflow eddies; it also reduces the risk of abnormal mechanical scratching of the silicon wafers due to warping against the conveyor mechanism in the epitaxial furnace, reducing the risk of secondary particle contamination of the silicon wafers.

[0089] In some embodiments of this disclosure, see Figure 5 Step S401, which involves selecting at least one test silicon wafer from the same batch of silicon wafers as the silicon wafer to be processed and determining the target power range to be applied to the epitaxial furnace based on the test results of the test silicon wafer, may include steps S501 to S503.

[0090] In step S501, the same batch of silicon wafers is divided into at least one consecutive production group.

[0091] In step S502, the first silicon wafer in each production group is used as a test wafer for testing to determine the optimal effective power range for testing applicable to the production group.

[0092] In step S503, the optimal effective power range for testing is taken as the target power range for the remaining silicon wafers to be processed in the production group.

[0093] In some embodiments of this disclosure, Figure 5 The proposed scheme may also include: Obtain epitaxial growth evaluation data for silicon wafers awaiting processing in the production group; If the epitaxial growth evaluation data of at least one production group meets the first preset condition, the number of silicon wafers in each production group is increased, and the proportion of test silicon wafers selected in the same production batch is reduced. Corresponding to the epitaxial growth evaluation data meeting the second preset condition, the total number of silicon wafers in each production group is reduced to increase the selection ratio of test silicon wafers in the same production batch.

[0094] In some examples, Figure 5 The method shown may also include: If the epitaxial growth evaluation data of the silicon wafer to be processed is lower than the third preset condition, the next silicon wafer in the production group that is to be processed is set as the test silicon wafer, and the target power range is updated based on the set test silicon wafer. The process continues until the epitaxial growth evaluation data of the silicon wafer to be processed, based on the updated target power range, meets the first preset condition.

[0095] In some embodiments of this disclosure, see Figure 6 and combined Figure 2 The step S502, which describes testing the first silicon wafer in each production group as a test silicon wafer to determine the optimal effective power range for testing applicable to the production group, may further include steps S601 to S603 as described below.

[0096] In step S601, before the test silicon wafer is sent into the epitaxial chamber, multiple effective test powers are applied to the epitaxial furnace for the test silicon wafer so that the temperature inside the epitaxial chamber is within the corresponding multiple test temperature ranges.

[0097] In step S602, multiple test deformation data are obtained as the test silicon wafer is exposed to multiple test temperature ranges during the initial stage of entering the epitaxial chamber.

[0098] In step S603, among all the test deformation data, the target power range is determined based on the effective power range corresponding to the test deformation data that minimizes the deformation of the test silicon wafer and has the fastest deformation recovery speed.

[0099] Specifically, before formal production, a "scan-measure-optimize" cycle can be performed on test silicon wafers (TW) at multiple power-temperature points. This involves first collecting deformation data at different power levels in batches, and then selecting the power range that minimizes deformation as the target power range for subsequent production. This method uses measured data instead of empirical estimation to ensure that the target power setting can suppress particulate contamination stably and over the long term.

[0100] In some embodiments of this disclosure, see also [link to previous document]. Figure 3 The test deformation data is determined by measuring multiple measurement points P at predetermined radial distances on the surface of the test silicon wafer TW.

[0101] In detail, by concentrating the measurement points P on a circle with the same radial distance, the critical areas of the silicon wafer most prone to warping can be captured with high sensitivity; the resulting deformation data is more representative of the overall warping risk, ensuring that the subsequent power optimization results are accurate and effective.

[0102] In some embodiments of this disclosure, see Figure 7 and combined Figure 3 Acquiring multiple test deformation data of the test silicon wafer TW during the initial stage of entering the epitaxial chamber EC due to exposure to multiple test temperature ranges may include the following steps S701 and S702.

[0103] S701: During the initial deformation of the test silicon wafer, the instantaneous height values ​​of multiple measurement points relative to the reference plane are measured in real time.

[0104] S702: For each test temperature range, the instantaneous height value of each measurement point is compared in real time to determine the maximum height value at each measurement point, and the maximum value among the multiple maximum height values ​​corresponding to multiple measurement points is taken as the test deformation data.

[0105] Specifically, during the TW deformation test of the silicon wafer, the instantaneous height is sampled at multiple points, and the maximum value is extracted in real time to obtain the most extreme local warpage. This extreme value-driven data processing method ensures that the selected target power can cover the worst-case operating conditions, further improving the particle suppression effect.

[0106] In some embodiments of this disclosure, Figure 4 The method may further include: in the initial stage when the silicon wafer to be processed is fed into the epitaxial chamber, maintaining the effective power within the target power range and reaching a set time threshold, so as to improve the deformation recovery speed of the silicon wafer to be processed and shorten the time for the silicon wafer to be processed to reach the thermal equilibrium state.

[0107] In this disclosure, the initial stage includes a transfer arm feeding the silicon wafer to be processed into the epitaxial chamber, and a support member supporting the silicon wafer to be processed after the transfer arm leaves. In this initial stage, the target temperature range is 780±10°C.

[0108] In this disclosure, the set time threshold includes the time period from when the silicon wafer to be processed enters the epitaxial chamber to when mechanical placement is completed and thermal equilibrium is reached. In some examples, the value of this time threshold ranges from 10 seconds to 15 seconds.

[0109] See Figure 8This disclosure also provides an epitaxial wafer 100, obtained by growing an epitaxial layer EL on a silicon wafer W. The silicon wafer W can be obtained by a system 10 for improving particulate contamination of the silicon wafer W during the epitaxial process according to the foregoing embodiments of this disclosure, or by a method for improving particulate contamination of the silicon wafer W during the epitaxial process according to the foregoing embodiments of this disclosure.

[0110] To further verify the effectiveness of the system 10 and method described in this disclosure in improving silicon wafer particle contamination, the epitaxial wafer 100 prepared by the above process needs to undergo rigorous surface quality characterization. In this embodiment, Localized Light Scatterer (LLS) is used as the core parameter for measuring the surface cleanliness and topological integrity of the epitaxial wafer. LLS refers to isolated features on the surface of the epitaxial wafer that cause laser scattering intensity significantly higher than the surrounding flat background. The number of LLS directly reflects the degree of secondary particle contamination introduced by the chamber microenvironment during the critical time window of the initial stage of entering the epitaxial chamber EC.

[0111] In the testing embodiments disclosed herein, LLS measurements are performed in an ultra-clean environment using a scanning surface inspection system based on the principle of deep ultraviolet laser polarization scattering. Before testing, the equipment's sensitivity is calibrated to ensure high repeatability of the test results. Specifically, the minimum detection size threshold is set to 200 nm, and the edge removal area is set to 2 mm to eliminate noise interference caused by physical fluctuations at the silicon wafer edges. A high-sensitivity oblique incidence scanning mode is employed to comprehensively capture defects such as deposited particles, micro-bumps, and stacking faults induced by epitaxial growth throughout the entire functional area of ​​the wafer.

[0112] To more accurately assess the contribution of this disclosure to ultra-clean surfaces, a batch statistical method was employed. In this embodiment, the "average number" is defined as a metric, which is obtained by calculating the arithmetic mean of the total number of LLS on 100 epitaxial wafers produced in succession.

[0113] Experimental test results show that, because the power regulator 12 is actively adjusted by the controller 14, the epitaxial chamber EC is preset to the optimal target temperature range before the silicon wafer enters (e.g., 780±10℃ for a 300 mm silicon wafer). The transient warpage deformation of the silicon wafer upon entry is successfully suppressed, thereby ensuring that the carrier gas flow field maintains a stable laminar flow state above the silicon wafer. Under this optimized physical environment, the epitaxial wafer 100 prepared by the embodiments of this disclosure exhibits higher surface quality: under the condition that the detection size is greater than or equal to 200 nm, the average number of LLS on the surface of the epitaxial wafer prepared by the system and method described in this disclosure is stably maintained at an extremely low level of less than or equal to 0.15 per wafer (e.g., in a sample of 100 epitaxial wafers, the total number of LLS is only 8-10, and more than 90% of the epitaxial wafers have a detection result of 0).

[0114] In contrast, this disclosure compares epitaxial wafers obtained using a conventional epitaxial method (i.e., without suppressing the effective power during the wafer insertion stage, allowing the furnace tube to operate at a conventional constant high-temperature standby power). Comparative data shows that epitaxial wafers produced using the conventional method have an average LLS count significantly higher than 0.15 per wafer at the same 200 nm detection limit. Microscopic morphology examination revealed that these additional LLS signals primarily originate from cavity-suspended particles captured by airflow vortices induced by thermal deformation of the silicon wafer during the initial wafer insertion stage. Data comparison further confirms that the technical solution of this disclosure can significantly reduce the risk of new particles on the epitaxial wafer surface, greatly improve the crystal integrity of the epitaxial layer, and significantly suppress the generation of "defect nuclei" that may lead to device failure in subsequent processes.

[0115] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily as long as they do not conflict.

[0116] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for improving particulate contamination of silicon wafers during epitaxial growth, characterized in that, include: At least one test silicon wafer is selected from the same batch of silicon wafers as the silicon wafer to be processed, and the target power range to be applied to the epitaxial furnace is determined based on the test results of the test silicon wafer. Before the silicon wafer to be processed is fed into the epitaxial chamber of the epitaxial furnace, the effective power applied to the epitaxial furnace is adjusted to the target power range so that the temperature inside the epitaxial chamber is within the target temperature range; The effective power of the epitaxial furnace is maintained within the target power range until the silicon wafer to be processed enters the epitaxial chamber, so as to suppress thermal deformation of the silicon wafer to be processed by utilizing the target temperature range; After the silicon wafer to be processed enters the epitaxial chamber, an epitaxial layer is grown on the surface of the silicon wafer to be processed.

2. The method for improving particulate contamination of silicon wafers during epitaxy according to claim 1, characterized in that, The step of selecting at least one test silicon wafer from the same batch as the silicon wafer to be processed, and determining the target power range to be applied to the epitaxial furnace based on the test results of the test silicon wafer, includes: Divide the same batch of silicon wafers into at least one consecutive production group; The first silicon wafer in each production group is used as the test wafer to determine the optimal test effective power range applicable to the production group. The optimal effective power range for testing is used as the target power range for the remaining silicon wafers to be processed in the production group.

3. The method according to claim 2, characterized in that, The method further includes: Obtain the epitaxial growth evaluation data of the silicon wafers to be processed in the production group; If the epitaxial growth evaluation data of at least one production group meets the first preset condition, the number of silicon wafers in each production group is increased, and the selection ratio of the test silicon wafers in the same production batch is reduced. If the epitaxial growth evaluation data meets the second preset condition, the total number of silicon wafers in each production group is reduced to increase the selection ratio of the test silicon wafers in the same production batch.

4. The method according to claim 3, characterized in that, The method further includes: If the epitaxial growth evaluation data of the silicon wafer to be processed is lower than the third preset condition, the next silicon wafer in the production group to be processed is set as the test silicon wafer, and the target power range is updated based on the set test silicon wafer. The process continues until the epitaxial growth evaluation data of the silicon wafer to be processed, based on the updated target power range, meets the first preset condition.

5. The method according to claim 2, characterized in that, The first silicon wafer in each production group is used as a test wafer to determine the optimal effective power range for that production group, including: Before the test silicon wafer is sent into the epitaxial chamber, multiple effective test powers are applied to the epitaxial furnace to make the temperature inside the epitaxial chamber within the corresponding multiple test temperature ranges. Acquire the corresponding test deformation data of the test silicon wafer during the initial stage of entering the epitaxial chamber due to exposure to the multiple test temperature ranges; Among all the test deformation data, the target power range is determined based on the effective power range corresponding to the test deformation data that minimizes the deformation of the test silicon wafer and has the fastest deformation recovery speed.

6. The method for improving particulate contamination of silicon wafers during epitaxy according to claim 5, characterized in that, The test deformation data is determined based on measurements taken at multiple points at predetermined radial distances on the surface of the test silicon wafer.

7. The method for improving particulate contamination of silicon wafers during epitaxy according to claim 5, characterized in that, Obtaining the multiple test deformation data includes: During the deformation of the test silicon wafer in the initial stage, the instantaneous height values ​​of the multiple measurement points relative to the reference plane are measured in real time. For each of the aforementioned test temperature ranges, the instantaneous height values ​​of each measurement point are compared in real time to determine the maximum height value at each measurement point, and the maximum value among the multiple maximum height values ​​corresponding to the multiple measurement points is taken as the test deformation data.

8. The method for improving particulate contamination of silicon wafers during epitaxy according to claim 1, characterized in that, The method further includes: In the initial stage after the silicon wafer to be processed enters the epitaxial chamber, the effective power is maintained within the target power range and reaches a set time threshold to improve the deformation recovery speed of the silicon wafer to be processed and shorten the time for the silicon wafer to be processed to reach thermal equilibrium. The time threshold includes the time period from when the silicon wafer to be processed enters the epitaxial chamber to when it completes mechanical placement and reaches thermal equilibrium.

9. The method for improving particulate contamination of silicon wafers during epitaxy according to claim 1, characterized in that, The diameter of the silicon wafer to be processed is 300 mm, and the target temperature range is 780±10℃.

10. A system for improving particulate contamination of silicon wafers during epitaxy, characterized in that, include: An epitaxial furnace having an epitaxial chamber for growing an epitaxial layer on the surface of the silicon wafer to be processed; A power regulator configured to regulate the effective power applied to the epitaxial furnace; A controller, coupled to the power regulator, is configured to: select at least one test silicon wafer from silicon wafers in the same batch as the silicon wafer to be processed, and determine a target power range to be applied to the epitaxial furnace based on the test results of the test silicon wafer; adjust the effective power applied to the epitaxial furnace to the target power range before the silicon wafer to be processed is fed into the epitaxial chamber of the epitaxial furnace, so that the temperature inside the epitaxial chamber is within the target temperature range; and maintain the effective power of the epitaxial furnace within the target power range until the silicon wafer to be processed enters the epitaxial chamber, so as to suppress thermal deformation of the silicon wafer to be processed using the target temperature range.

11. An epitaxial wafer, obtained by growing an epitaxial layer on a silicon wafer to be processed, characterized in that, The epitaxial wafer is obtained by a method for improving particulate contamination of silicon wafers during epitaxy according to any one of claims 1 to 9, or by a system for improving particulate contamination of silicon wafers during epitaxy according to claim 10, wherein, when the detection size of the epitaxial wafer is greater than or equal to 200 nm, the average number of local light scatterers on its surface is less than or equal to 0.15, and the average number refers to the ratio of the total number of local light scatterers obtained by detecting multiple epitaxial wafers to the total number of epitaxial wafers.

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