Test system and test method for gallium nitride transistors

Abstract

This invention provides a testing system and method for gallium nitride (GaN) transistors, applicable to the field of transistor testing technology. The system includes: a multi-station testing architecture; an asymmetric full-bridge testing circuit within the testing module for performance testing of the GaN transistor under test; a data acquisition and control module for generating pulse-width modulation signals and acquiring performance parameters of the GaN transistor under test during the testing process; a processor for optimizing target test configuration information using a test configuration decision tree model based on predetermined configuration constraints and configuration adjustment strategies, and generating control commands based on the target test configuration information; feature extraction of performance parameters to obtain multi-dimensional time-frequency state features; prediction processing of the multi-dimensional time-frequency state features using a degradation prediction model to obtain target degradation information; and detection processing of parameter correlation features and frequency domain periodic features in the multi-dimensional time-frequency state features using an anomaly detection model to obtain target anomaly information.

Description

Technical Field

[0001] This invention relates to the field of transistor testing technology, and more specifically to a testing system and method for gallium nitride transistors. Background Technology

[0002] Gallium nitride (GaN) transistors are semiconductor power devices with advantages such as high electron mobility, high breakdown voltage, low on-resistance, and fast switching characteristics, making them widely applicable in technological fields such as electric vehicles and photovoltaic inverters. Therefore, performance evaluation and testing of GaN transistors before application has become a crucial step.

[0003] In the process of realizing the above-mentioned inventive concept, it was found that the existing test architecture is difficult to support centralized testing of a large number of gallium nitride transistors, and it is difficult to simultaneously take into account the wide voltage and high current test environment required for testing, resulting in a long test cycle and high test cost. At the same time, due to the device differences between multiple gallium nitride transistors, it is difficult to construct a targeted test scheme and obtain accurate test results during batch testing. Summary of the Invention

[0004] In view of the above problems, the present invention provides a testing system and testing method for gallium nitride transistors.

[0005] According to a first aspect of the present invention, a testing system for gallium nitride (GaN) transistors is provided, comprising: a multi-station testing architecture, distributed in multiple testing areas of a testing cabinet; each station testing architecture including an independently operating testing module and an acquisition control module; the testing module, electrically connected to the acquisition control module, including a daughterboard slot and an asymmetric full-bridge test circuit electrically connected to the daughterboard slot; the daughterboard slot being used to insert a GaN transistor under test; and the asymmetric full-bridge test circuit being used to perform performance testing on the GaN transistor under test electrically connected to the asymmetric full-bridge test circuit in response to a pulse width modulation (PWM) signal; the acquisition control module being used to generate a PWM signal according to a control command and send it to the testing module, acquire performance parameters of the GaN transistor under test during the testing process, and send them to a processor; and the processor, electrically connected to the acquisition control module, being used to perform performance testing based on a predetermined configuration. The system employs constraints and configuration adjustment strategies, utilizing a test configuration decision tree model to optimize and obtain target test configuration information from the test configuration database. Based on this information, control commands are generated to control the acquisition module to collect performance parameters, including the operating parameters and dynamic on-resistance of the gallium nitride transistor under test (GaN). Feature extraction is performed on these performance parameters to obtain multi-dimensional time-frequency state characteristics of the GaN. A degradation prediction model is then used to predict these multi-dimensional time-frequency state characteristics, yielding target degradation information. This target degradation information characterizes the predicted trend of dynamic on-resistance changing over time. Finally, an anomaly detection model is used to detect parameter correlation features and frequency domain periodic features within the multi-dimensional time-frequency state characteristics, obtaining target anomaly information. This target anomaly information includes abnormal operating parameters and abnormal change trends of the GaN.

[0006] A second aspect of the present invention provides a method for testing gallium nitride (GaN) transistors, comprising: based on predetermined configuration constraints and configuration adjustment strategies, optimizing target test configuration information from a test configuration database using a test configuration decision tree model, and generating control commands based on the target test configuration information to control an acquisition control module to acquire performance parameters of the GaN transistor under test, the performance parameters including the operating parameters and dynamic on-resistance of the GaN transistor under test; performing feature extraction on the performance parameters acquired by the acquisition control module to obtain multi-dimensional time-frequency state features of the GaN transistor under test; performing prediction processing on the multi-dimensional time-frequency state features using a degradation prediction model to obtain target degradation information, wherein the target degradation information characterizes the predicted trend of dynamic on-resistance changing over time; and performing detection processing on the parameter correlation features and frequency domain periodic features in the multi-dimensional time-frequency state features using an anomaly detection model to obtain target anomaly information, wherein the target anomaly information includes abnormal operating parameters and abnormal change trends of the GaN transistor under test.

[0007] A third aspect of the present invention provides an electronic device comprising: one or more processors; and a memory for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors perform the method described above.

[0008] A fourth aspect of the present invention also provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, cause the processor to perform the methods described above.

[0009] A fifth aspect of the invention also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0010] According to the gallium nitride transistor testing system and method of the present invention, the test cabinet can be equipped with multiple test areas, and each test area can be equipped with multiple workstation test architectures. Each multi-workstation test architecture within a test area can be uniformly powered by a power supply bus, and each workstation test architecture is independent yet synchronously controllable. This enables centralized and unified synchronous testing of a large number of gallium nitride transistors under test, improving testing efficiency while also allowing for high-precision reliability verification of a large number of gallium nitride transistors under test.

[0011] Furthermore, to meet the current testing requirements of gallium nitride transistors (GaN) under test (GaN) with wide voltage and high current, the GaN under test is electrically connected to the asymmetric full-bridge test circuit via a daughterboard slot. The asymmetric full-bridge test circuit not only supports wide voltage and high current testing environments but also reduces testing energy consumption and improves the reliability of the test circuit due to improvements in its internal circuitry. Each station's test architecture can adopt an independent modular design, improving the convenience of packaging and device replacement while providing a high-precision measurement and testing solution for GaN transistors under test with anti-interference capabilities.

[0012] Furthermore, by pairing it with a processor capable of characterizing the performance parameters of the gallium nitride (GaN) transistors under test, prior to testing, the system, based on the selection criteria for the device ratings of the GaN transistors under test and the evaluation of real-time testing, and under predetermined configuration constraints and adjustment strategies, optimizes the target test configuration information most suitable for the current reliability assessment from a test configuration database with closed-loop feedback. This allows for targeted and personalized customized test environment configurations for multiple GaN transistors under test. Then, performance parameters are characterized from multiple dimensions, including time domain, frequency domain, and correlation, yielding multi-dimensional time-frequency state characteristics. Finally, pre-built degradation prediction and anomaly detection models are used to process the multi-dimensional time-frequency state characteristics for degradation prediction and anomaly detection, enabling accurate detection of operational degradation trends in the time domain and anomaly trends in the frequency domain and real-time operating status of the GaN transistors under test. This system utilizes a pre-trained model to perform reliability assessments on gallium nitride transistors (GaN) at the current test station architecture, as well as to conduct a system-wide correlation assessment of multiple GaN transistors across multiple test station architectures. This improves assessment accuracy and efficiency while constructing an adaptively updated closed-loop feedback system, thereby reducing testing costs. Attached Figure Description

[0013] The above-mentioned contents, as well as other objects, features and advantages of the present invention, will become clearer from the following description of embodiments of the present invention with reference to the accompanying drawings.

[0014] Figure 1 A schematic diagram of a test system for gallium nitride transistors according to an embodiment of the present invention is shown.

[0015] Figure 2 A schematic diagram of a multi-station test architecture according to an embodiment of the present invention is shown.

[0016] Figure 3 A schematic diagram of an asymmetric full-bridge test circuit according to an embodiment of the present invention is shown.

[0017] Figure 4 A schematic diagram of a multi-station test architecture according to another embodiment of the present invention is shown.

[0018] Figure 5 A schematic diagram of the test power of a gallium nitride transistor according to an embodiment of the present invention is shown.

[0019] Figure 6a A schematic diagram of the stress state of a gallium nitride transistor according to an embodiment of the present invention is shown.

[0020] Figure 6b A partially enlarged schematic diagram of the stress state according to an embodiment of the present invention is shown.

[0021] Figure 7 A schematic diagram of the model architecture within a processor according to an embodiment of the present invention is shown.

[0022] Figure 8a A graph showing the adjustment of test parameters according to an embodiment of the present invention is provided.

[0023] Figure 8b A graph showing the adjustment of test parameters according to another embodiment of the present invention is shown.

[0024] Figure 8c A graph showing the adjustment of test parameters according to yet another embodiment of the present invention is shown.

[0025] Figure 9 A schematic diagram of target degradation information is shown according to an embodiment of the present invention.

[0026] Figure 10a A schematic diagram of the multi-station test results according to an embodiment of the present invention is shown.

[0027] Figure 10b A schematic diagram of the results of a multi-station test according to another embodiment of the present invention is shown.

[0028] Figure 11 A flowchart of a test method for gallium nitride transistors according to an embodiment of the present invention is shown. Detailed Implementation

[0029] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0031] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0032] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0033] In the technical solution of this invention, the user information (including but not limited to user personal information, user image information, user device information, such as location information) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, storage, use, processing, transmission, provision, disclosure, and application of related data all comply with relevant laws, regulations, and standards, take necessary confidentiality measures, do not violate public order and good morals, and provide corresponding operation entry points for users to choose to authorize or refuse.

[0034] Gallium nitride (GaN) power devices, due to their high electron mobility, high breakdown voltage, low on-resistance, and fast switching characteristics, have become core components for next-generation power conversion applications and can be widely used in electric vehicles, data center power supplies, photovoltaic inverters, 5G base stations, and other fields. With the large-scale deployment of GaN power devices in high-frequency, high-voltage, and high-current applications, long-term reliability assessment has become crucial.

[0035] According to the continuous switching evaluation test standards for gallium nitride (GaN) power devices, the evaluation of the switching reliability of GaN power devices needs to be carried out under continuous switching conditions, including both hard switching and soft switching evaluation modes. Because GaN lateral power transistors have small input and output capacitances, their switching speeds can typically be in the nanosecond range. However, while fast switching can reduce the self-heating effect of GaN power devices, the simultaneous application of high drain-source voltage and high drain current during multiple switching events causes the transistor to experience electrical stress. This repeated stress during continuous operation may lead to cumulative degradation of GaN power devices over time, affecting switching reliability. During the research and development process, it was found that existing test architectures are difficult to support centralized testing of a large number of GaN transistors, and it is difficult to simultaneously accommodate the wide voltage and high current testing environment required for testing. This results in long test cycles and high test costs. Furthermore, due to device differences among multiple GaN transistors, it is difficult to construct targeted test schemes and obtain accurate test results during batch testing.

[0036] In view of this, embodiments of the present invention provide a gallium nitride (GaN) transistor testing system, comprising: a multi-station testing architecture, distributed in multiple testing areas of a testing cabinet; each station testing architecture including an independently operating testing module and an acquisition control module; a testing module electrically connected to the acquisition control module, including a daughterboard slot and an asymmetric full-bridge test circuit electrically connected to the daughterboard slot; the daughterboard slot being used to insert a GaN transistor under test; and the asymmetric full-bridge test circuit being used to perform performance testing on the GaN transistor under test electrically connected to the asymmetric full-bridge test circuit in response to a pulse width modulation signal; an acquisition control module being used to generate a pulse width modulation signal according to control instructions and send it to the testing module, acquire performance parameters of the GaN transistor under test during the testing process, and send them to a processor; and a processor electrically connected to the acquisition control module being used to perform performance testing based on a predetermined configuration. The system employs constraints and configuration adjustment strategies, utilizing a test configuration decision tree model to optimize and obtain target test configuration information from the test configuration database. Based on this information, control commands are generated to control the acquisition module to collect performance parameters, including the operating parameters and dynamic on-resistance of the gallium nitride transistor under test (GaN). Feature extraction is performed on these performance parameters to obtain multi-dimensional time-frequency state characteristics of the GaN. A degradation prediction model is then used to predict these multi-dimensional time-frequency state characteristics, yielding target degradation information. This target degradation information characterizes the predicted trend of dynamic on-resistance changing over time. Finally, an anomaly detection model is used to detect parameter correlation features and frequency domain periodic features within the multi-dimensional time-frequency state characteristics, obtaining target anomaly information. This target anomaly information includes abnormal operating parameters and abnormal change trends of the GaN.

[0037] Figure 1 A schematic diagram of a test system for gallium nitride transistors according to an embodiment of the present invention is shown.

[0038] like Figure 1 As shown, a gallium nitride transistor testing system may include a multi-station testing architecture 101 and a processor 104. Each station testing architecture may include a testing module 102 and a data acquisition and control module 103. Figure 1 As shown, the test cabinet can include a test architecture with Z workstations.

[0039] Specifically, the multi-station test architecture 101 can be set up in multiple test areas of the test cabinet, and each station test architecture includes an independently operating test module 102 and a data acquisition and control module 103.

[0040] The test cabinet can include four independent test areas, each capable of configuring 20 test stations. Each test area can accommodate four test motherboards, each integrating five test stations. Some electronic components within each test station can be replaced according to actual testing needs. This allows for unified batch testing of multiple gallium nitride transistors. Furthermore, each test station can be designed with anti-interference features through corresponding wiring layouts and functional partitions to prevent crosstalk between multiple test stations during simultaneous testing.

[0041] Each test area can be powered by an independent power supply, providing both high-voltage and low-voltage power to meet different test requirements.

[0042] The test module 102 can be electrically connected to the acquisition and control module 103. It includes a daughterboard slot and an asymmetric full-bridge test circuit electrically connected to the daughterboard slot. The daughterboard slot is used to insert the gallium nitride transistor under test. The asymmetric full-bridge test circuit is used to perform performance testing on the gallium nitride transistor under test electrically connected to the asymmetric full-bridge test circuit in response to the pulse width modulation signal.

[0043] On the test motherboard of each workstation test architecture, a test module can be set up. The test module can include a daughterboard slot and an asymmetric full-bridge test circuit electrically connected to the daughterboard slot.

[0044] Before testing the gallium nitride (GaN) transistor under test (GaN), it needs to be inserted into the daughterboard slot to electrically connect the GaN transistor to the asymmetric full-bridge test circuit. The asymmetric full-bridge test circuit, based on the pulse width modulation signal received from the acquisition and control module, can perform simulated testing on the GaN transistor under test to analyze its operational reliability.

[0045] The daughterboard slot can support various types of slots with multiple package forms. When testing multiple gallium nitride transistors under test simultaneously, the synchronous operation of the control switches related to the test can be achieved through the interactive communication between the processor 104 and the acquisition control module 103, so as to facilitate synchronous testing.

[0046] The acquisition and control module 103 can be used to generate pulse width modulation signals according to control commands and send them to the test module 102, acquire the performance parameters of the gallium nitride transistor under test during the test process, and send them to the processor 104.

[0047] The acquisition and control module 103 may include corresponding sampling submodules, microcontroller control submodules, drive submodules, and temperature control submodules, as well as other functional modules related to the control and acquisition of the gallium nitride transistor under test (GaN transistor). During real-time testing of the GaN transistor under test, the acquisition and control module 103 can transmit the acquired performance parameters of the GaN transistor to the processor 104, so that the processor 104 can analyze the performance parameters and obtain the reliability assessment results of the GaN transistor under test.

[0048] The processor 104, electrically connected to the acquisition control module 103, is used to optimize the target test configuration information from the test configuration database based on predetermined configuration constraints and configuration adjustment strategies using a test configuration decision tree model. It then generates control commands based on the target test configuration information to control the acquisition control module to acquire performance parameters. Feature extraction is performed on the performance parameters to obtain the multi-dimensional time-frequency state characteristics of the gallium nitride transistor under test. A degradation prediction model is used to predict the multi-dimensional time-frequency state characteristics to obtain target degradation information. An anomaly detection model is used to detect the parameter correlation features and frequency domain periodic features in the multi-dimensional time-frequency state characteristics to obtain target anomaly information.

[0049] The performance parameters include the operating parameters and dynamic on-resistance of the gallium nitride transistor under test. The target degradation information characterizes the predicted trend of the dynamic on-resistance changing over time. The target anomaly information includes the abnormal operating parameters and abnormal change trends of the gallium nitride transistor under test.

[0050] The predetermined configuration constraints can be characterized as performing security verification on multiple sets of screened test configuration information, and using the test configuration information that meets the security verification as the target test configuration information. The configuration adjustment strategy can be characterized as adaptively adjusting the security-verified test configuration information based on information such as the degradation parameters or stress parameters of the gallium nitride transistor under test to obtain the target test configuration information, so that the acquisition and control module can generate the corresponding pulse width modulation signal and test the gallium nitride transistor under test under the corresponding test parameters.

[0051] After acquiring the relevant performance parameters of the gallium nitride transistor under test, feature extraction can be performed on the performance parameters based on multi-dimensional features such as time domain and frequency domain to obtain time-frequency state features that can include time domain, frequency domain, parameter correlation, and other dimensions.

[0052] By using degradation prediction models and anomaly detection models to perform feature analysis on time-frequency state characteristics, the trend characteristics of the dynamic on-resistance of the gallium nitride transistor under test as a function of time, as well as the abnormal operating states and abnormal operating trends during the test process, can be obtained.

[0053] According to embodiments of the present invention, the test cabinet can be equipped with multiple test zones, and each test zone can be equipped with multiple workstation test architectures. Each multi-workstation test architecture within a test zone can be uniformly powered by a power supply bus, and each workstation test architecture is independent yet synchronously controllable. This enables centralized and unified synchronous testing of a large number of gallium nitride transistors under test, improving testing efficiency while also allowing for high-precision reliability verification of a large number of gallium nitride transistors under test.

[0054] Furthermore, to meet the current testing requirements of gallium nitride transistors (GaN) under test (GaN) with wide voltage and high current, the GaN under test is electrically connected to the asymmetric full-bridge test circuit via a daughterboard slot. The asymmetric full-bridge test circuit not only supports wide voltage and high current testing environments but also reduces testing energy consumption and improves the reliability of the test circuit due to improvements in its internal circuitry. Each station's test architecture can adopt an independent modular design, improving the convenience of packaging and device replacement while providing a high-precision measurement and testing solution for GaN transistors under test with anti-interference capabilities.

[0055] Furthermore, by pairing it with a processor capable of characterizing the performance parameters of the gallium nitride (GaN) transistors under test, prior to testing, the system, based on the selection criteria for the device ratings of the GaN transistors under test and the evaluation of real-time testing, and under predetermined configuration constraints and adjustment strategies, optimizes the target test configuration information most suitable for the current reliability assessment from a test configuration database with closed-loop feedback. This allows for targeted and personalized customized test environment configurations for multiple GaN transistors under test. Then, performance parameters are characterized from multiple dimensions, including time domain, frequency domain, and correlation, yielding multi-dimensional time-frequency state characteristics. Finally, pre-built degradation prediction and anomaly detection models are used to process the multi-dimensional time-frequency state characteristics for degradation prediction and anomaly detection, enabling accurate detection of operational degradation trends in the time domain and anomaly trends in the frequency domain and real-time operating status of the GaN transistors under test. This system utilizes a pre-trained model to perform reliability assessments on gallium nitride transistors (GaN) at the current test station architecture, as well as to conduct a system-wide correlation assessment of multiple GaN transistors across multiple test station architectures. This improves assessment accuracy and efficiency while constructing an adaptively updated closed-loop feedback system, thereby reducing testing costs.

[0056] Figure 2 A schematic diagram of a multi-station test architecture according to an embodiment of the present invention is shown.

[0057] like Figure 2 As shown, Figure 2This is a schematic diagram of the test cabinet of the present invention. As can be seen from the figure, the test cabinet electrically connected to the processor 104 may include four test areas (the first test area, the second test area, the third test area, and the fourth test area). Each test area may include multiple workstation test architectures to facilitate batch testing of a large number of gallium nitride transistors under test.

[0058] Figure 3 A schematic diagram of an asymmetric full-bridge test circuit according to an embodiment of the present invention is shown.

[0059] like Figure 3 As shown, the asymmetric full-bridge test circuit may include a first transistor Q0, a first freewheeling diode D0, a second freewheeling diode D1, a load resistor R1, a current sampling resistor R-cr, a load inductor L1, and a filter capacitor C1.

[0060] Specifically, the first transistor Q0 has its first terminal electrically connected to the first power supply bus, its second terminal electrically connected to the first terminal of the first freewheeling diode D0, and its third terminal electrically connected to the acquisition and control module. It is used to turn on or off under the control of the pulse width modulation signal, so as to facilitate the performance testing of the gallium nitride transistor DUT.

[0061] The first transistor Q0 can be turned on or off synchronously with the gallium nitride transistor DUT inserted in the daughterboard slot to form a complete current loop.

[0062] The first freewheeling diode D0 has its second terminal grounded.

[0063] The second freewheeling diode D1 has its first end electrically connected to the first power supply bus and its second end electrically connected to the first end of the daughterboard slot.

[0064] The first freewheeling diode D0 and the second freewheeling diode D1 can form a complete freewheeling circuit when the first transistor Q0 and the gallium nitride transistor under test DUT are turned off simultaneously, so that the energy in the load inductor L1 can be recovered to the first power supply bus and the filter capacitor C1 can be charged.

[0065] The load resistor R1 is electrically connected to the second terminal of the first transistor Q0, and the second terminal of the load resistor R1 is electrically connected to the first terminal of the load inductor L1.

[0066] The load resistor R1 is used to limit the steady-state current and dissipate circuit power to achieve circuit thermal balance. The resistance value of the load resistor R1 can be determined according to the target test current required for the test. That is, the resistance value of the load resistor R1 needs to meet the steady-state condition R1=VBUS / IDS(ON), the rated power needs to meet the continuous power dissipation requirement P=IDS(ON)²×R1, and the temperature coefficient of resistance of the load resistor needs to be lower than 100ppm / °C. Here, VBUS can represent the power supply of the first power supply bus, IDS(ON) can represent the magnitude of the steady-state current, and P can represent the rated power of the load resistor.

[0067] The current sampling resistor R-cr has its first terminal electrically connected to the second terminal of the daughterboard slot, and its second terminal grounded.

[0068] The current sampling resistor R-cr can be used to detect the on-current flowing through the gallium nitride transistor (DUT) in real time.

[0069] The load inductor L1 is connected to the second terminal of the second freewheeling diode D1.

[0070] The load inductor L1 can be used to provide inductive switching stress. When the first transistor Q0 and the GaN transistor DUT are turned on, the load inductor L1 can be in an energy storage state. When the first transistor Q0 and the GaN transistor DUT are turned off, the load inductor L1 can be in an energy dissipation state until the inductance current of the load inductor L1 gradually decays until the next turn-on cycle of the first transistor Q0 and the GaN transistor DUT begins.

[0071] The filter capacitor C1 has its first terminal electrically connected to the first power supply bus, and its second terminal grounded.

[0072] The filter capacitor C1 can be used to stabilize the bus voltage and provide transient current. When the first transistor Q0 and the gallium nitride transistor under test (DUT) are turned on, the filter capacitor C1 can be in a discharging state. When the first transistor Q0 and the gallium nitride transistor under test (DUT) are turned off, the filter capacitor C1 can be in a charging state.

[0073] The drain-source voltage range of the first transistor Q0 can be 0~1000V; the peak current that the first transistor Q0 can withstand can be 0~40A; the gate-source voltage range of the first transistor Q0 can be adjusted from -1 to 5V (total voltage difference 6V); when the drain-source voltage is <500V, the switching frequency of the first transistor Q0 can be 5kHz~1MHz, and when the drain-source voltage is >500V, the switching frequency of the first transistor Q0 can be 5kHz~500kHz; the duty cycle of the first transistor Q0 can be 5%~50%.

[0074] According to an embodiment of the present invention, an asymmetric full-bridge test circuit including a filter capacitor and a load resistor can achieve steady-state current balance in continuous switching mode, enabling the gallium nitride transistor under test to operate stably for a long time (thousands of hours) in a large current range of 0~40A, thus meeting the requirements of related long-cycle aging tests.

[0075] Furthermore, by replacing the transistors on the two arms of the asymmetric full-bridge test circuit with freewheeling diodes, the number of switching devices requiring precise timing control is reduced, lowering the risk of short circuits in the bridge arms and the complexity of the test circuit design, thus improving the reliability of the circuit during long-term continuous operation. Consequently, during the testing of the gallium nitride transistor under test, only the first transistor and the gallium nitride transistor under test need to be driven, reducing drive power consumption by approximately 50%. Simultaneously, the conduction and switching losses of the freewheeling diodes are far lower than those of the transistors, further reducing circuit power consumption. In parallel operation of a multi-station test architecture, this effectively reduces the system's heat dissipation pressure and power capacity requirements.

[0076] Furthermore, by selecting the load resistor value based on the ideal voltage and ideal current required for the test, considering factors such as heat dissipation and power, it is possible to maintain current stability within the test circuit while achieving thermal balance in continuous switching mode through the resistor's own performance and appropriate heat dissipation design. This avoids heat accumulation and thermal runaway in the test circuit, as well as the impact on the testing of the gallium nitride transistor under test.

[0077] According to an embodiment of the present invention, when the first transistor is turned on, the filter capacitor and the first power supply bus discharge together, and the test current forms a loop through the first transistor, the load resistor, the load inductor, the gallium nitride transistor under test, and the current sampling resistor; when the first transistor is turned off, the first freewheeling diode and the second freewheeling diode together form a freewheeling loop, so that the test current flows into the filter capacitor through the first freewheeling diode, the load resistor, the load inductor, and the second freewheeling diode, so as to charge the filter capacitor.

[0078] The switching on and off of the first transistor and the GaN transistor under test can depend on the pulse width modulation signal sent by the driver submodule. When the pulse width modulation signal is high, both the first transistor and the GaN transistor under test can be in the on state. Current can flow from the first power supply bus, through the first transistor Q0 → load resistor R1 → load inductor L1 → GaN transistor under test DUT → current sampling resistor R-cr to ground GND. During this process, the load inductor L1 stores energy and the load resistor R1 limits the current.

[0079] When the pulse width modulation signal is low, both the first transistor and the gallium nitride transistor under test can be in the off state. The current can flow from ground GND through the freewheeling loop of the first freewheeling diode D0 → load resistor R1 → load inductor L1 → second freewheeling diode D1 to feed energy back to the filter capacitor C1, so as to realize freewheeling charging.

[0080] According to an embodiment of the present invention, a steady-state balance of current can be achieved in continuous switching mode by using an asymmetric full-bridge test circuit including a filter capacitor and a load resistor. At the same time, during the turn-off period of the first transistor and the gallium nitride transistor under test, the energy stored in the load inductor can be fed back to the filter capacitor through the first freewheeling diode and the second freewheeling diode, thereby avoiding inductor saturation and enabling the gallium nitride transistor under test to operate stably for a long time (thousands of hours) in a large current range of 0~40A, meeting the requirements of related long-cycle aging tests.

[0081] Figure 4 A schematic diagram of a multi-station test architecture according to another embodiment of the present invention is shown.

[0082] like Figure 4 As shown, each test area includes a first power supply bus and a second power supply bus; the acquisition and control module includes a voltage sampling circuit and a current sampling circuit. Figure 4 The diagram shows a schematic of a module within any one of the five workstation test architectures on a test motherboard.

[0083] Specifically, the first power supply bus can be electrically connected to multiple test modules located in the same test area to provide test current to the multiple test modules for performance testing of multiple gallium nitride transistors under test.

[0084] Within the same test area, a first power supply bus and a second power supply bus can be uniformly set up. The first power supply bus can be a power supply bus used to supply power to the asymmetric full-bridge test circuit. The voltage range provided by the first power supply bus can be 0~1000V.

[0085] The second power supply bus can be electrically connected to multiple acquisition and control modules located in the same test area to provide operating voltage to the multiple acquisition and control modules so that the multiple acquisition and control modules are in normal working condition.

[0086] The second power supply bus can be a power supply bus used to provide power to the acquisition and control modules in each workstation test architecture. The second power supply bus can be a 24V low-voltage DC power supply after step-down conversion of 220V AC mains power.

[0087] The first power supply bus and the second power supply bus can be independent of each other, and the power lines within each workstation test architecture are also isolated from each other to avoid power coupling interference between various drive circuits.

[0088] like Figure 4 As shown, each sampling control module within the architecture includes a voltage sampling circuit and a current sampling circuit.

[0089] The voltage sampling circuit, which can be electrically connected to the test module, includes a resistor divider network. This network, consisting of multiple series resistors, is used to step down the operating test voltage of the gallium nitride transistor under test, obtaining the operating step-down voltage. The voltage sampling range of the voltage sampling circuit is 0V to 1000V.

[0090] A high-precision resistor voltage divider network (with a voltage division ratio of approximately 200:1) can attenuate the 0-1000V high-voltage signal supplied by the first power supply bus to the 0-5V range. By employing a multi-stage series resistor voltage divider to balance the voltage stress on each resistor, the high-voltage signal is attenuated in a balanced manner. The attenuated low-voltage signal is then processed by a differential amplifier with a high common-mode rejection ratio in the voltage sampling circuit to output a low-voltage analog signal compatible with a digital-to-analog converter (ADC). This achieves equivalent linear sampling from high voltage to low voltage for the gallium nitride transistor under test.

[0091] The power and isolation devices within the voltage sampling circuit can be selected based on a maximum operating voltage of 1000V, ensuring the reliability of different electronic components under low-voltage operation and the safety under high-voltage operation. The PCB layout inside the voltage sampling circuit can adopt a uniform high-voltage spacing design (i.e., a uniform design based on a maximum operating voltage of 1000V, with an electrical clearance of not less than 6mm between high-voltage and low-voltage traces, a creepage distance of not less than 8mm, and the PCB substrate in the high-voltage area can be made of FR-4 material with a relative tracking index of not less than 400V). This substrate maintains sufficient electrical clearance even during low-voltage testing, thus simplifying design complexity while ensuring full-range compatibility.

[0092] The current sampling circuit can be electrically connected to the test module and includes a first-range sampling circuit and a second-range sampling circuit. The first-range sampling circuit is used to collect the working test current in the first current range, and the second-range sampling circuit is used to collect the working test current in the second current range.

[0093] The first current range is smaller than the second current range, with the first current range being 0~3A and the second current range being 3~40A.

[0094] Through multiple rounds of iterative sampling tests based on the single-range sampling scheme, it was found that the single-range current sampling has a large offset error. Therefore, in order to adapt to the sampling range of large current and improve the sampling accuracy, a multi-range sampling scheme is used to sample the test current.

[0095] The first-range sampling circuit and the second-range sampling circuit are each configured with different sampling resistor plug-in boards. In response to the requirements of the current test environment, the first sampling resistor plug-in board corresponding to the first-range sampling circuit can be set on the test motherboard, or the second sampling resistor plug-in board corresponding to the second-range sampling circuit can be set on the test motherboard.

[0096] A high-resistance sampling resistor can be used in the first sampling resistor plug-in, in conjunction with a pre-stage low-pass filter and a low-noise amplifier. During the process of switching from a large range current sampling to a small range current sampling, the spike interference present at the moment of switching is filtered out, the switching blanking time is increased, and high-precision measurement in the range of 0~3A is achieved.

[0097] The second sampling resistor module can employ a low-resistance sampling resistor (e.g., a low-temperature drift alloy sampling resistor with a temperature coefficient of less than 50 ppm / ℃), which, in conjunction with a bandwidth amplifier, enables high-speed, high-precision measurements in the range of 0.1A to 40A. The second sampling resistor module is typically compatible with a sampling current range of 3 to 40A.

[0098] Meanwhile, the sampling resistor in the current sampling circuit can usually adopt a four-terminal structure. Two terminals can be led out to the high current loop (power line), and the other two terminals can be independently led out to the voltage measurement circuit (induction line). This eliminates the influence of the voltage drop generated by the high current on the lead and contact resistance on the sampling accuracy. In addition, the power ground and signal ground in the current sampling circuit are connected at a single point to avoid the formation of a voltage drop between the high current and the signal ground.

[0099] The first range sampling circuit and the second range sampling circuit can both use the same 18-bit digital-to-analog converter.

[0100] According to embodiments of the present invention, by deploying the first and second power supply buses as a whole, the power supply design within the test area can be simplified, allowing the power supply buses to only handle uniform load step changes. To adapt to the current testing environment requirements for high voltage and high current corresponding to the gallium nitride transistor under test, a voltage sampling circuit including a high-precision, low-temperature-drift resistor divider network with multiple series resistors, and a current sampling circuit including two sampling ranges with low temperature drift and high stability can be specifically adopted. Simultaneously, before testing, the voltage sampling circuit and current sampling circuit are calibrated in segments at multiple points (voltage calibration points may include 100V, 200V, 500V, 800V, 1000V, etc.; small current calibration points may include 0.1A, 0.5A, 1A, 2A, 3A; and large current calibration points may include 1A, 5A, 10A, 20A, 30A, 40A). A high-precision standard voltage source is used to provide the reference voltage, the readings of the digital-to-analog converter are recorded, and the gain and offset calibration coefficients of each segment are calculated. This allows for calibration compensation of the sampled measurements during testing, thereby ensuring that the linearity across the entire range is better than 0.5%.

[0101] According to an embodiment of the present invention, the sampling control module may further include: a filter circuit, an auxiliary power supply, a load connector, a power connector, a microcontroller digital control area, and a driver sub-board (drive + overcurrent protection).

[0102] Each workstation's test architecture can include independent test modules and acquisition control modules. For the asymmetric full-bridge test circuits and daughterboard slots within the test modules, and for the voltage sampling circuits, current sampling circuits, filtering circuits, auxiliary power supplies, load connectors, power connectors, microcontroller digital control areas, and driver daughterboards within the acquisition control modules, a strict high- and low-voltage zone isolation layout design is adopted. That is, the high-voltage area and low-voltage area are physically separated; high-voltage high-current traces (drain-source voltage traces, drain current traces) and low-voltage small-signal traces (drive voltage traces, measurement signals) are placed in different areas of the circuit board, maintaining sufficient safety spacing. The sampling circuits are separately arranged from the microcontroller digital control area and driver daughterboards, with analog ground and digital ground connected at a single point. In particular, switching nodes within the high-voltage area can use RC snubber circuits (RC snubber circuits) to suppress ringing and electromagnetic interference.

[0103] The physical circuit architecture of the five stations (test architecture) on the same test motherboard can be arranged in parallel, but electrically isolated from each other, sharing only the first power supply bus and the second power supply bus; the traces of key test signals and sampling signals can be surrounded by shielding rings, and grounded copper foil can be arranged to form shielding rings, effectively suppressing crosstalk between adjacent signals.

[0104] Specifically, such as Figure 4As shown, the filter circuit can be placed between the first power supply bus and the asymmetric full-bridge test circuit, or between the second power supply bus and the acquisition and control module (not shown in the figure). The filter circuit may include surge protection devices such as electromagnetic interference filters, common-mode inductors, transient voltage suppressors, and varistors to suppress power ripple and high-frequency switching noise on the high-voltage bus to prevent conduction to adjacent workstations or power supply buses. The resistance between the filter circuit's casing and the grounding resistor can be less than 10 ohms to facilitate good Faraday cage shielding.

[0105] The auxiliary power supply can be electrically connected to the second power supply bus, the acquisition and control module, and the water-cooled plate. The auxiliary power supply can provide the required multiple low-voltage DC power supplies, such as +5V / -1V gate programmable drive power supplies, to the driver sub-boards within each test station architecture; it can also provide the required sampling power supplies, such as +3.3V / +5V digital logic power supplies, to the acquisition and control module. The auxiliary power supplies within each test station architecture are isolated from each other to eliminate power coupling interference between different drive circuits. A star grounding topology can be used on the test motherboard to avoid electrical coupling between multiple current paths formed by different test station architectures via a common ground terminal.

[0106] Load connectors are used to connect electronic components such as load resistors and load inductors. In other words, for different testing requirements of gallium nitride transistors under test, there are different test environments (selection of parameters such as load resistors and load inductors). Therefore, it is necessary to replace load resistors, load inductors and other electronic components with different resistance values ​​and temperature coefficients according to different test requirements.

[0107] A power connector is used to connect to the first power supply bus to provide high-voltage power to the asymmetric full-bridge test circuit.

[0108] The daughterboard slots, load connectors, and power connectors can all be located in the high-voltage power loop area of ​​the motherboard. Shielded connectors and slots can be used, and the connecting cables between circuit modules can all be shielded and grounded to improve common-mode interference immunity.

[0109] In addition to daughterboard slots, load connectors, and power connectors, various functional interfaces matching testing requirements can be provided, such as temperature sensor interfaces, drive signal interfaces, and measurement signal interfaces. Different package designs can be used for different interface modules. For example, daughterboard slot types can include: TO220 type daughterboards (suitable for TO-220 type packaged devices, using screw press-fit fixing), TO247 type daughterboards (suitable for TO-247 type packaged devices, using screw press-fit fixing), and PDFN type daughterboards (suitable for PDFN type surface mount packaged devices, with the device pre-soldered on the daughterboard and mounted to the motherboard via connectors), etc.

[0110] The microcontroller's digital control area can be electrically connected to the current sampling circuit and the voltage sampling circuit. It is used to perform analog-to-digital conversion on the working analog voltage and working analog current collected by the voltage sampling circuit and the current sampling circuit during the test process, respectively, to obtain the working digital voltage and working digital current. Then, through the internal digital control logic circuits such as the communication interface, the performance parameters such as the working digital voltage and working digital current can be transmitted to the processor via the communication interface. At the same time, under the same synchronous clock signal and pulse width modulation signal, the microcontroller's digital control area can synchronously distribute the generated synchronous switching timing signal to the driver sub-board through the high-speed differential signal line to facilitate the testing of the gallium nitride transistor under test.

[0111] The driver sub-board can be electrically connected to the microcontroller's digital control area. After receiving the synchronous switch timing signal, multiple driver sub-boards can simultaneously generate pulse width modulation signals to enable all workstation test architectures in the same test area to be turned on and off simultaneously.

[0112] This can eliminate the switching timing differences between multiple workstation test architectures within the same test area, reduce mutual interference, and facilitate the observation and analysis of the consistency of devices in the same batch.

[0113] Furthermore, the five test stations located on the same test motherboard can share the same water-cooling design, i.e., the same water-cooling plate. The daughterboard slots in each test station can be connected to the water-cooling plate via ceramic plates and aluminum heat sinks. The cooling water flow of each water-cooling plate is independently controllable to facilitate heat dissipation through the water-cooling plate.

[0114] Meanwhile, the water-cooled plate can also be used to prevent crosstalk between adjacent workstation test architectures caused by the rate of voltage change (dV / dt) of power device switching. The daughterboard slot and the water-cooled plate can be electrically isolated by ceramic sheets. The ceramic sheets have high thermal conductivity and high insulation strength, so they can efficiently conduct heat and block the coupling path of the rate of voltage change.

[0115] Water-cooled plates can be made of metal and grounded to form an electromagnetic shielding layer. They should be located between adjacent test architectures on the same test motherboard and maintain sufficient physical distance to further reduce thermal and electromagnetic coupling.

[0116] By comprehensively applying the above-mentioned triple measures of ceramic sheet electrical isolation, metal shielding grounding, and physical distance spacing, effective thermal and electromagnetic isolation protection can be provided for the test architecture of each station, ensuring that the sub-board slots (gallium nitride transistors under test) of each station operate under relatively consistent temperature conditions, thereby improving the comparability of test data.

[0117] Furthermore, to improve the reliability of the test architecture, a redundant structure can be introduced: an overcurrent protection circuit is set on the driver subboard. This circuit monitors the current signal on the load resistor in real time from a hardware perspective. When the current exceeds a set threshold, the pulse width modulation signal is directly shut off within microseconds. Simultaneously, from a software perspective, the sampled operating parameters are compared with the predetermined threshold. When the operating parameters exceed the limit, the control logic can shut down the driver, enabling independent operation and mutual backup of the dual protection mechanism of hardware and software protection. From a software perspective, the sampled data parameters can be low-pass filtered to remove high-frequency noise.

[0118] Temperature monitoring can employ both thermocouple and infrared temperature measurement solutions; communication interfaces, connectors, slots, etc., can all adopt a primary and backup redundancy design to ensure data integrity during long-term operation.

[0119] Table 1

[0120]

[0121] Table 1 shows the performance parameter data obtained from multiple tests on the gallium nitride transistors. As shown in Table 1, DUT1 can be represented as the gallium nitride transistor under test located in the first daughterboard slot, DUT2 can be represented as the gallium nitride transistor under test located in the second daughterboard slot, DUT3 can be represented as the gallium nitride transistor under test located in the third daughterboard slot, and DUT4 can be represented as the gallium nitride transistor under test located in the fourth daughterboard slot. By performing multiple tests on the four gallium nitride transistors under test at different time periods, partial performance test data corresponding to each gallium nitride transistor under test can be obtained.

[0122] Figure 5 A schematic diagram of the test power of a gallium nitride transistor according to an embodiment of the present invention is shown.

[0123] like Figure 5 As shown, Figure 5The horizontal axis can be represented as the time (ns) of the gallium nitride transistor under test in a single switching cycle, and the vertical axis can be represented as the transient power (W) of the gallium nitride transistor under test.

[0124] Figure 6a A schematic diagram of the stress state of a gallium nitride transistor according to an embodiment of the present invention is shown. Figure 6b A partially enlarged schematic diagram of the stress state according to an embodiment of the present invention is shown.

[0125] like Figure 6a and 6b As shown, the horizontal axis represents the time axis of the switching cycle, and the vertical axis represents the parameters collected by the voltage sampling network and the current sampling network, respectively. The brown line represents the drain-source voltage, the green line represents the on-state voltage drop, the orange line represents the gate-source voltage, and the blue line represents the drain current. By testing the gallium nitride transistor under test, the current-voltage trajectory of the transistor under test under hard-switching and soft-switching conditions can be observed, which facilitates the evaluation of the device's switching stress state.

[0126] Figure 7 A schematic diagram of the model architecture within a processor according to an embodiment of the present invention is shown.

[0127] like Figure 7 As shown, the model architecture within the processor can include: a test configuration decision tree model, a degradation prediction model, and an anomaly detection model. The test configuration decision tree model can output corresponding parameter recommendations and adaptive adjustment schemes before testing. In response to the operating parameters (performance parameters, physical parameters) sampled during the testing of the gallium nitride transistor under test, and the configuration library constructed based on these parameters, feature extraction is performed to obtain time-domain performance features, degradation trend features, parameter correlation features, and frequency-domain periodic features. Then, the degradation prediction model and anomaly detection model are used to analyze and predict these features, obtaining target degradation information and target anomaly information. Based on this target degradation information and target anomaly information, the test configuration decision tree model is self-adjusted.

[0128] According to an embodiment of the present invention, the processor may perform the following operations.

[0129] According to an embodiment of the present invention, based on the physical parameters of the gallium nitride transistor under test, a first candidate configuration template and a second candidate configuration template corresponding to the gallium nitride transistor under test are determined from the device parameter configuration library and the historical parameter configuration library, respectively.

[0130] The first candidate configuration template includes multiple test configuration parameters corresponding to the gallium nitride transistor under test, and the second candidate configuration template includes multiple historical test configuration parameters corresponding to the gallium nitride transistor under test.

[0131] The device parameter configuration library can be characterized as a library of characteristic parameters (including rated voltage, rated current, typical dynamic on-resistance, recommended switching frequency range, etc.) that store test parameter templates recommended by the original manufacturer. Based on the physical parameters of the gallium nitride transistor under test, the first candidate configuration template can be determined from the device parameter configuration library.

[0132] For example, for a gallium nitride transistor under test with a rated voltage of 650V and a rated current of 30A, the first candidate configuration template determined from the device parameter configuration library can be: drain-source voltage Vds = 520V, that is, 80% of the rated voltage of the gallium nitride transistor under test; drain current Ids = 24A, that is, 80% of the rated current of the gallium nitride transistor under test; switching frequency 100kHz, duty cycle 20%, Vgs drive voltage -1V~5V, test temperature Tj = 150℃, load resistance R1 = VBUS / IDS(ON) ≈ 22Ω, etc.

[0133] A historical parameter configuration library can be characterized as a library of characteristic parameters storing historical test parameter templates for different gallium nitride transistors under test. Based on the physical parameters of the gallium nitride transistor under test or other rated parameters close to those of the current gallium nitride transistor under test, a second candidate configuration template can be determined from the historical parameter configuration library.

[0134] According to an embodiment of the present invention, a test configuration database is constructed based on a device parameter configuration library and a historical parameter configuration library.

[0135] The test configuration database can be characterized as a database containing test parameters of various dimensions, as well as historical test results and historical test information corresponding to each test parameter.

[0136] According to an embodiment of the present invention, the physical parameters of the gallium nitride transistor under test and the test configuration database are input into the test configuration decision tree model. Based on the historical best test configuration parameters, the mean square error is calculated and the residual is predicted for each candidate configuration template in the test configuration database using multiple test configuration decision trees in the test configuration decision tree model, so as to obtain the third candidate configuration template.

[0137] Based on the physical parameters of the gallium nitride transistor under test, multiple test configuration decision trees in the gradient boosting test configuration decision tree model are used to optimize and obtain the third candidate configuration template from the test configuration database under the constraint of the historical best test configuration parameters.

[0138] The test configuration decision tree model can include 100 test configuration decision trees with a decision depth of 6. Each test configuration decision tree fits the prediction residuals of all preceding trees, thereby gradually reducing the overall prediction error. The number of test configuration decision trees and the decision depth can be selected according to the actual situation.

[0139] For example, assuming the test configuration database can include 5 parameter schemes, the first test configuration decision tree, under the constraints of the physical parameters of the gallium nitride transistor under test and the splitting of the mean square error, can, through a predetermined decision depth, traverse and optimize from all parameters corresponding to the 5 parameter schemes after normalization to obtain the first set of candidate parameter templates and the corresponding normalized template labels. Based on the historical test information corresponding to the 5 parameter schemes, the optimal historical scheme is determined. Based on each historical optimal parameter in the normalized historical optimal scheme and each parameter in the normalized first set of candidate parameter templates, the corresponding residual is calculated to obtain the first set of residuals corresponding to the first set of candidate parameter templates.

[0140] Then, the second test configuration decision tree uses the first set of residuals corresponding to the first set of candidate parameter templates and the splitting evaluation of the mean squared error as core constraints. Through a predetermined decision depth, it iterates through all parameters corresponding to the five parameter schemes to obtain the second set of residual labels corresponding to the second set of candidate parameter templates. Then, based on the first set of residuals and the second set of residual labels, it obtains the second set of residuals (correction amount) and superimposes it with the first set of template labels to obtain the second set of template labels. Next, the third test configuration decision tree uses the second set of residuals as core constraints and repeats the above operations until the last test configuration decision tree is completed, obtaining the last set of template labels. These labels are then normalized and restored to obtain the optimal third candidate configuration template.

[0141] Furthermore, for the test configuration decision tree model, a training sample set can be constructed using a large amount of historical test data, and the initial decision tree model can be pre-trained using this set. After optimization, the final test configuration decision tree model can be obtained.

[0142] For example, the training sample set can be randomly shuffled and equally divided into 5 non-overlapping subsets (which can be called "folds"). During each training iteration, 4 subsets are selected as the training data set, and the remaining subset is used as the validation data set. The initial decision tree model is then trained, and the prediction error is evaluated on the validation subset. The entire training process can be repeated 5 times, using a different subset as the validation data set each time, to ensure that each data point is validated exactly once.

[0143] Then, the average of the mean squared errors from the five validations is taken as a comprehensive evaluation index that characterizes the performance prediction of the initial decision tree model under the current hyperparameter configuration. , where y i This can be represented as the actual optimal parameter value of the i-th sample in the validation dataset. is the model prediction value, and n is the total number of validation datasets.

[0144] If the comprehensive evaluation index is less than the predetermined threshold, the hyperparameters of the current initial decision tree model can be considered as optimal parameters, and the model tuning and updating should be stopped. If the comprehensive evaluation index is greater than or equal to the predetermined threshold, the hyperparameters of the current initial decision tree model need to be iteratively tuned until the comprehensive evaluation index is less than the predetermined threshold.

[0145] During model training, the initial decision tree model constructs decision trees sequentially, one by one. The training objective of each new tree is to fit the residual (i.e., prediction error) between the cumulative predicted values ​​of all previous trees and the true values. The splitting node and leaf node values ​​of each tree are determined by minimizing the mean squared error loss function, gradually reducing the overall prediction error. Hyperparameter tuning can employ a grid search strategy, traversing the following parameter space to search for the optimal combination: the number of decision trees can be selected from 50, 100, and 200; the maximum tree depth can be selected from 4, 6, and 8; the learning rate can be selected from 0.01, 0.05, and 0.1; and the minimum number of leaf node samples can be selected from 5, 10, and 20, but is not limited to these.

[0146] For example, the training sample set can include 200 complete test records of different gallium nitride transistors. Each record can include physical parameters (such as rated voltage 650V, rated current 30A, package type TO-247, initial dynamic on-resistance 35mΩ) and historical test parameters (such as optimal switching frequency 100kHz, duty cycle 20%, stress voltage 520V). These records are randomly divided into 5 subsets of 40 records each. In the first round of training, 160 records from subsets 2-5 are used for training, and 40 records from subset 1 are used for validation. In the second round, 160 records from subsets 1 and 3-5 are used for training, and 40 records from subset 2 are used for validation, and so on. Finally, the hyperparameter combination that minimizes the mean squared error of the 5 rounds of validation is selected, such as 100 decision trees, a maximum depth of 6, a learning rate of 0.05, and a minimum number of leaf node samples of 10, as the training parameter to obtain the test configuration decision tree model.

[0147] Furthermore, the target degradation information, target anomaly information, and related extracted features obtained in each round of testing can serve as one of the optimal evaluation criteria for historical solutions, thereby enabling timed closed-loop feedback updates to the test configuration database and test configuration decision tree model.

[0148] For the closed-loop feedback update of the test configuration database, the target degradation information and target anomaly information output by the degradation prediction model and the anomaly detection model in the current test round can serve as relevant evaluation criteria for parameter optimization in assessing the current test round and future trends. The target degradation information, target anomaly information, and corresponding test parameters obtained from each test round are written to the test configuration database in real time for iterative updates.

[0149] For the closed-loop feedback update of the test configuration decision tree model, the test parameters collected in some new tests and the score labels obtained based on target degradation information and target anomaly information can be used periodically as dataset samples for model training.

[0150] Using the newly added dataset samples, the test configuration decision tree model is trained using an incremental fine-tuning approach: based on the original trained test configuration decision tree model, new decision trees can be built by using only the newly added test data as training samples and with a small learning rate (such as 1 / 5 of the original training learning rate).

[0151] For example, incremental updates to the test configuration decision tree model can be achieved by adding new decision trees to the original model. That is, if the original model contains 100 trees, 10-20 new trees can be added after those 100 to form a new test configuration decision tree model. The newly added test configuration decision tree model still uses the residuals between the existing trees as the fitting target, gradually reducing the prediction error on new data to absorb new device types and parameter optimization experience. This achieves the goal of fully preserving historical experience while incorporating new knowledge, thus improving the optimization accuracy of the continuously updated test configuration decision tree model, while keeping the original test configuration decision tree model unchanged.

[0152] When the total number of samples in the accumulated training sample set increases by more than a predetermined threshold (such as 50%) compared to the initial training, the processor can perform a full retraining of the model (i.e., retraining) to make full use of the large-scale data to improve the overall performance of the model.

[0153] Simultaneously, for the first stress adjustment step parameters and the second stress adjustment step parameters, the processor can track and record the parameters after each update and adjustment, recording the device state indicators before and after the adjustment (such as the rate of change of dynamic on-resistance, junction temperature change, etc.), and whether the adjustment has achieved the expected goals (such as whether the temperature has fallen back to a safe range, whether the degradation rate has accelerated, etc.). This information can then be incorporated into the training data as evaluation labels for the test parameters. Through the continuous data accumulation and incremental model updates described above, the parameter recommendation accuracy and adaptive adjustment precision of the test configuration decision tree model can be improved. Furthermore, by introducing a mechanism for the autonomous updating and improvement of the test configuration decision tree model, the adaptive update efficiency of the test configuration decision tree model can be greatly improved.

[0154] According to an embodiment of the present invention, based on predetermined configuration constraints and configuration adjustment strategies, the first candidate configuration template, the second candidate configuration template, and the third candidate configuration template are verified respectively, and the target test configuration information is determined based on the verification results.

[0155] The predetermined configuration constraints can be characterized as requiring three levels of safety verification for the first, second, and third candidate configuration templates. Specifically, the first level of verification can be characterized as absolute limit verification to ensure that the drain-source voltage in the candidate configuration template does not exceed 90% of the device's rated voltage, the drain current does not exceed 90% of the rated current, and the gate-source voltage is within the datasheet's safe range. The second level of verification can be characterized as system hardware limit verification to ensure that the test parameters in the candidate configuration template do not exceed the hardware upper limit of 1000V / 40A. The third level of verification can be characterized as thermal safety verification to estimate the test parameters in the candidate configuration template and avoid the expected junction temperature exceeding the safe upper limit of 150℃. Based on the verification results of the three levels of safety verification for the first, second, and third candidate configuration templates, and combined with the current configuration adjustment strategy, the target test configuration information is determined.

[0156] If any level of verification fails, other alternative configuration templates can be used for verification. If the first, second, and third alternative configuration templates all fail verification, the corresponding parameters can be adaptively adjusted and feedback can be provided to the user in the form of a recommended solution. The user can directly adopt the solution or make manual adjustments based on it.

[0157] According to an embodiment of the present invention, a first candidate configuration template and a second candidate configuration template corresponding to the gallium nitride transistor under test (GaN) are first obtained from the device parameter configuration library and the historical parameter configuration library, respectively. Then, using a fully pre-trained test configuration decision tree model, based on the comprehensive performance of the physical parameters and historical parameter tests of the GaN under test, an optimal third candidate configuration template is obtained from the test configuration database, considering both historical test performance and multiple parameter combinations. Then, based on predetermined configuration constraints and configuration adjustment strategies, the three candidate configuration templates are subjected to security verification to determine the target test configuration information. This enables optimal recommendation and dynamic adaptive adjustment of test parameters before and during testing based on the real-time testing progress of the GaN under test, improving the efficiency of test scheme design and the scientific nature of the testing process.

[0158] According to an embodiment of the present invention, the processor may perform the following operations.

[0159] According to an embodiment of the present invention, based on predetermined configuration constraints and the physical parameters of the gallium nitride transistor under test, security checks are performed on the first candidate configuration template, the second candidate configuration template, and the third candidate configuration template to determine the target candidate configuration template.

[0160] Among them, the predetermined configuration constraint condition characterization will use the templates that all meet the rated limit, test limit and thermal safety verification as the target candidate configuration templates.

[0161] According to an embodiment of the present invention, when the historical anomaly detection results of the gallium nitride transistor under test indicate that the historical junction temperature of the device is greater than a predetermined temperature threshold, a fuzzy logic control algorithm is used to calculate the historical temperature deviation and the historical temperature change rate to obtain the first stress adjustment step parameter.

[0162] Among them, the historical temperature deviation and the historical temperature change rate are calculated based on the historical junction temperature of the device and a predetermined temperature threshold.

[0163] Once the target candidate configuration template is determined and the gallium nitride transistor under test is confirmed to be in the testing process, the junction temperature of the gallium nitride transistor under test can be determined based on the historical junction temperature in the historical anomaly detection information of the gallium nitride transistor under test to determine whether the junction temperature exceeds 90% of the safe threshold. If it is determined to be greater than the predetermined temperature threshold, the switching stress (switching frequency) of the first transistor and the gallium nitride transistor under test needs to be reduced.

[0164] The magnitude of the frequency reduction adjustment can be determined based on a fuzzy logic control algorithm. Specifically, the parameters are first fuzzified. For historical temperature deviation, an amplitude status label corresponding to the temperature deviation is defined; for historical temperature change rate, an amplitude status label corresponding to the temperature change rate is defined; and for stress adjustment magnitude, i.e., the first stress adjustment step parameter, an amplitude status label corresponding to the stress adjustment magnitude is defined. The amplitude status label can represent the evaluation judgment based on the parameter. For example, the amplitude status label corresponding to temperature deviation can include negative large (large and negative temperature deviation), negative small (small and negative temperature deviation), zero (no temperature deviation), positive small (small and positive temperature deviation), and positive large (large and positive temperature deviation); the amplitude status label corresponding to temperature change rate can include negative (negative change rate), zero (no change), and positive (positive change rate); and the amplitude status label corresponding to stress adjustment magnitude can include significant reduction (significantly reduce the switching frequency), slight reduction (slightly reduce the switching frequency), hold (switching frequency unchanged), slight recovery (slightly increase the switching frequency), and significant recovery (significantly increase the switching frequency).

[0165] Each amplitude status label can then be assigned a corresponding triangular or trapezoidal membership function. Using this function, historical temperature deviations and historical temperature change rates can be mapped to membership values ​​corresponding to each amplitude status label. The membership value corresponds to the proportion of each amplitude status label. Combining multiple preset fuzzy rules, the adjustment direction of the switching frequency and the minimum intersection value are determined.

[0166] For example, when the temperature deviation is large and the rate of change is positive, the output decreases significantly, and the adjustment direction is to prioritize a significant reduction in the switching frequency; when the temperature deviation is large but the rate of change is zero, the adjustment direction is to slightly decrease the output; when the temperature deviation is small and the rate of change is positive, the adjustment direction is to slightly decrease the output; when the temperature deviation is zero and the rate of change is zero, the adjustment direction is to maintain the output; when the temperature deviation is small and the rate of change is negative, the adjustment direction is to slightly recover the output, and the adjustment direction is to gradually recover the switching frequency; when the temperature deviation is large and the rate of change is negative, the adjustment direction is to significantly recover the output, etc.

[0167] Then, by integrating and summing the minimum intersection values ​​corresponding to each fuzzy rule, the first stress adjustment step parameters can be obtained. Wherein, the first stress adjustment step parameters... According to The calculation yielded that, It can be represented as the output membership function after summing the minimum values ​​of the intersections corresponding to each fuzzy rule, and u can be represented as the value of the output variable, that is, the adjustment value.

[0168] For example, with initial test parameters of a target temperature of 150℃ and a switching frequency of 100kHz, when the power consumption of the gallium nitride transistor under test (GaN) increases due to dynamic on-resistance degradation, and the historical junction temperature rises to 156℃ and continues to rise at a rate of 0.5℃ / min, the switching frequency needs to be adjusted. In this case, a fuzzy rule is met where the output decreases significantly when the temperature deviation is large and the rate of change is positive. Therefore, after calculation using the fuzzy algorithm, the processor can significantly reduce the switching frequency from 100kHz to 70kHz by 30%. If the junction temperature of the GaN transistor under test stabilizes at 153℃ after the frequency reduction and no longer rises, it can be maintained at 70kHz for further observation. If the junction temperature of the GaN transistor under test further drops to 151℃ and continues to decrease, the fuzzy rule of a slight recovery in output when the temperature deviation is small and the rate of change is negative is met. Therefore, the processor can gradually increase the switching frequency back to 80kHz, 90kHz, and finally restore it to 100kHz.

[0169] If the switching frequency has been reduced to the lower limit but the temperature still cannot be controlled, the duty cycle can be further reduced, that is, from the original 20% to 15%, 10%, etc. By reducing the on-time ratio and making smooth and continuous adjustments, the average power consumption can be reduced, avoiding the hysteresis problem of traditional threshold control.

[0170] According to an embodiment of the present invention, a second stress adjustment step parameter is determined based on the degradation stage in the historical degradation prediction information of the gallium nitride transistor under test.

[0171] Once the first stress adjustment step parameter that needs adjustment is determined, the degradation stage in the historical degradation information of the GaN transistor under test (DT) can be used to determine whether the aging process of the DT needs to be accelerated or decelerated. If the DT is determined to be in a slow degradation stage (the predicted normalized rate of change of dynamic on-resistance is less than 0.1% / 100h), the stress level of both the first transistor and the DT can be increased by increasing the switching frequency by 10%–20% or the duty cycle by 5%–10%, without exceeding the device safety threshold, thus accelerating the aging process and shortening the test cycle. If the DT is determined to be at a critical failure point (typically triggered when the predicted remaining service life is less than 200 hours), the stress level of the transistor can be reduced by decreasing the switching frequency by 10%–20%, and the data sampling density can be increased to 5–10 times the normal density to more precisely capture the failure process.

[0172] According to an embodiment of the present invention, based on a configuration adjustment strategy, the transistor on-time and duty cycle in the target candidate configuration template are adjusted using a first stress adjustment step parameter and a second stress adjustment step parameter to obtain target test configuration information.

[0173] Having obtained the first stress adjustment step parameter and the second stress adjustment step parameter, the frequency and duty cycle of the crystal transistor can be adjusted using the first stress adjustment step parameter and the second stress adjustment step parameter to obtain the final target test configuration information.

[0174] According to an embodiment of the present invention, when the gallium nitride transistor under test (GaN) is being tested and the target candidate configuration template has been determined, the parameters of the target candidate configuration template can be further adjusted based on the historical anomaly detection information and historical degradation information of the GaN under test. This adjusts the transistor's on-time and duty cycle to obtain the final target test configuration information. While improving the accuracy of the generated target test configuration information, it also allows for adaptive adjustments to the GaN under test during testing, enhancing the flexibility and robustness of the test.

[0175] In addition to adjusting the junction temperature and degradation stage of the gallium nitride transistor under test, adjustments can also be made to individual gallium nitride transistors under test based on batch consistency.

[0176] Specifically, for individual gallium nitride transistors (GaN) under test (GaN) with significantly faster or slower degradation rates within the same batch of tests, their test parameters can be adjusted independently according to a preset equalization strategy. The processor can quantify the stress accumulation level of each GaN by continuously monitoring the cumulative stress index of each GaN, i.e., the integral value of voltage × current × frequency × time. When the deviation of the cumulative stress index across all stations within a batch is controlled within ±10%, the consistency requirement is considered met. This ensures that all devices within a batch are compared under similar stress accumulation levels, improving the scientific rigor of reliability assessment.

[0177] The equalization strategy can be characterized by appropriately reducing the stress level of stations with faster degradation to bring their degradation rate closer to the batch average, and appropriately increasing the stress level of stations with slower degradation to accelerate their degradation process. The adjustment range is proportional to the degree of deviation, and the deviation judgment criterion can be whether the rate of change of the dynamic on-resistance of the gallium nitride transistor under test deviates from the batch average by more than 2 standard deviations.

[0178] Meanwhile, when test parameters are adjusted or the device degradation rate changes (more than twice that of the previous period), the processor can automatically shorten the data sampling interval from the normal interval (e.g., once per minute) to a high-density interval (e.g., once per second) and simultaneously increase the data retention frequency to ensure data integrity during critical phases. During stable operation, the sampling density can be appropriately reduced to decrease data storage overhead.

[0179] Figure 8aA graph showing the adjustment of test parameters according to an embodiment of the present invention is provided. Figure 8b A graph showing the adjustment of test parameters according to another embodiment of the present invention is shown. Figure 8c A graph showing the adjustment of test parameters according to yet another embodiment of the present invention is shown.

[0180] like Figures 8a-8c As shown, Figures 8a-8c The horizontal axis can be represented as aging time (h). Figure 8a The vertical axis can be represented by the switching frequency (kHz). Figure 8b The vertical axis can be represented as the duty cycle (%). Figure 8c The vertical axis can be represented by junction temperature (°C). The yellow area indicates that when the junction temperature is detected to be greater than 152°C (safe threshold), the switching frequency and duty cycle need to be reduced. The green area indicates that the degradation of the gallium nitride transistor under test in the slow aging stage needs to be accelerated, which requires increasing the switching frequency and duty cycle. The red area indicates that the degradation of the gallium nitride transistor under test in the slow aging stage needs to be slowed down in order to accurately record the degradation of the gallium nitride transistor under test, which requires reducing the switching frequency and duty cycle in order to collect its relevant data in detail.

[0181] After acquiring the performance parameters of the gallium nitride transistor under test, multi-dimensional feature extraction is required to obtain time-domain performance characteristics, degradation trend characteristics, parameter correlation characteristics, and frequency-domain periodic characteristics. These performance parameters may include drain-source voltage at turn-off, drain-source voltage at turn-on; Ipeak peak current; Ids drain current; dynamic on-resistance and static on-resistance; Tc case temperature, TL load temperature, Tj junction temperature, TR reference temperature; and Idss drain current, among other parameters.

[0182] Specifically, regarding time-domain performance characteristics, the processor can segment the collected performance parameters according to a predetermined sliding time window, calculating statistics for each time window: mean μ (reflecting the central tendency of the parameter), standard deviation σ (reflecting the amplitude of parameter fluctuation), linear fitting slope k (reflecting the rate of parameter change, obtained by linear regression of data points within the window using the least squares method), peak-to-peak value ΔP (the difference between the maximum and minimum values ​​within the window, reflecting the extreme fluctuation range of the parameter), skewness S (reflecting the asymmetry of the parameter distribution, calculated by normalization using the third central moment), and kurtosis K (reflecting the sharpness of the parameter distribution, calculated by normalization using the fourth central moment). These multiple statistics can describe the steady-state behavior and fluctuation characteristics of the parameters. The sliding time window can have a length of 1 hour and a step size of 10 minutes.

[0183] To address the degradation trend characteristics, dynamic on-resistance is used as the core degradation index. Based on the dynamic on-resistance actually sampled within each sampling period, degradation trend characteristic parameters are calculated. For example, the change in dynamic on-resistance ΔRdson = Rdson(t) - Rdson_initial, where Rdson_initial can be represented as the average dynamic on-resistance of the first 100 periods in the initial stage of testing, and Rdson(t) can be represented as the measured value of dynamic on-resistance at the current sampling moment.

[0184] The dynamic on-resistance can be obtained as follows: When the GaN transistor under test (DT) is in the off state, its drain-source voltage is relatively high (close to the power supply voltage). After the DT is turned on, the drain-source voltage can quickly drop to the on-state voltage drop Vds(ON). A voltage clamping circuit can then be used to clamp the high voltage during off-state, allowing only the low-voltage signal during on-state to pass through. This signal is then sampled by a high-precision voltage sampling network, and the drain current is measured simultaneously. The dynamic on-resistance can be calculated using the formula Rdson = Vds(ON) / Ids. The normalized rate of change of the dynamic on-resistance can be represented as ΔRdson / Rdson_initial. This normalized rate of change can be used to eliminate the influence of the initial dynamic on-resistance between different DTs, enabling cross-device degradation comparison.

[0185] The slope of the linear fit within the sliding window (obtained by least-squares linear regression of the time series of the change in dynamic on-resistance within the window, which can characterize the current degradation rate) and the fitting residual (the root mean square error of the linear fit, which can indicate a change in degradation mode when the residual suddenly increases) can characterize the direction, rate, and mode of degradation of the gallium nitride transistor under test.

[0186] To address parameter correlation characteristics, the Pearson correlation coefficient can be used to quantify the degree of linear correlation between various performance parameters within a sliding time window. The Pearson correlation coefficient can be obtained by calculating the correlation coefficient between two parameter sequences collected simultaneously within the same window; the coefficient can range from -1 to +1.

[0187] When the Pearson correlation coefficient is close to +1, it indicates a strong positive correlation between the two performance parameters (an increase in one parameter also increases the other). When the Pearson correlation coefficient is close to -1, it indicates a strong negative correlation (an increase in one parameter also decreases the other). When the Pearson correlation coefficient is close to 0, it indicates no linear correlation. The formula for calculating the Pearson correlation coefficient r can be expressed as follows: .

[0188] Where, x iThis can be represented as the value of the i-th sampling point of the X-th performance parameter sequence within the sliding window, y i This can be represented as the value of the i-th sampling point in the Y-th performance parameter sequence within the sliding window. It can be represented as the mean of all sampling points of the Xth performance parameter sequence within the sliding window. It can be characterized as the mean of all sampling points of the Xth performance parameter sequence within the sliding window. The Xth and Yth performance parameter sequences can be any two of the time-varying sequences of various performance parameters obtained from sampling. For example, the Xth performance parameter sequence can be the dynamic on-resistance sequence, and the Yth performance parameter sequence can be the junction temperature sequence.

[0189] The processor can perform pairwise iterations of all performance parameters within each sliding time window to calculate the Pearson correlation coefficient and extract the correlation features between parameters.

[0190] The correlation coefficient between dynamic on-resistance and junction temperature can characterize the positive temperature coefficient of the on-resistance of the gallium nitride transistor under test. During the normal aging process of the gallium nitride transistor under test, its dynamic on-resistance can increase with the increase of junction temperature. The Pearson correlation coefficient between the two can usually be stabilized between 0.75 and 0.90.

[0191] Taking actual testing as an example, when the gallium nitride transistor under test operates at a target temperature of 150℃ for 800 hours, within a 1-hour window (approximately 1200 sampling points), its dynamic on-resistance slowly increases from 35mΩ to 37mΩ, while the junction temperature fluctuates from 148℃ to 151℃. At this time, the Pearson correlation coefficient is approximately 0.82, indicating normal coupling. However, when gate oxide degradation or interface charge accumulation occurs inside the gallium nitride transistor under test, the dynamic on-resistance may increase rapidly (e.g., jumping from 37mΩ to 40mΩ), but the junction temperature only changes slightly (e.g., only from 149℃ to 150℃). At this time, the Pearson correlation coefficient can drop sharply to 0.2–0.4, indicating that the degradation mechanism has changed from a normal temperature-dominated type to a defect-dominated type, thus providing an early warning.

[0192] The correlation coefficient between the on-state voltage drop and the drain current can be characterized as follows: when the gallium nitride transistor under test is in normal condition, its on-state voltage drop and drain current are strongly positively correlated with Ohm's law, that is, the Pearson correlation coefficient is >0.85; if there is an abnormal shift in the on-state voltage drop but the drain current remains stable, the Pearson correlation coefficient can be <0.5, which can indicate that the channel characteristics of the gallium nitride transistor under test have changed abnormally.

[0193] The correlation coefficient between drain current and drain-source voltage at turn-off can be used to characterize changes in the relationship between drain current and turn-off voltage, and is used to detect gate leakage degradation. When the Pearson correlation coefficient deviates from its historical baseline by more than 2σ', the processor can determine that there is abnormal coupling behavior between the drain current and the drain-source voltage at turn-off, indicating that physical degradation processes such as defect propagation and interface charge accumulation may have occurred inside the gallium nitride transistor under test. The historical baseline can be taken as the statistical result of the Pearson correlation coefficient between drain current and drain-source voltage at turn-off within 200 hours before the test, and this can be considered as the normal range of the historical baseline between drain current and drain-source voltage at turn-off; that is, this range can be equivalent to the mean. , It can characterize the standard deviation of the Pearson correlation coefficient with respect to the parameter during the baseline period of the first 200 hours.

[0194] For frequency domain periodic features, the processor can continuously record the time sequence of each performance parameter at a predetermined sampling interval. After applying a Hanning window to the time sequence of each performance parameter and performing a Fourier transform, frequency domain features including the frequency and amplitude of the main frequency component and the spectral energy distribution can be extracted.

[0195] By performing spectral analysis on the frequency domain characteristics, the processor can identify and eliminate known periodic components related to external factors such as ambient temperature fluctuations and power supply ripple. When a new frequency component that does not match a known interference source appears in the spectrum, or when the amplitude of an existing component changes significantly, the processor can mark it as an abnormal frequency feature. Abnormal frequency features can be associated with the periodic evolution of internal defects in the device (such as crack propagation, interface delamination, etc.).

[0196] According to embodiments of the present invention, the multidimensional time-frequency state characteristics also include time-domain performance characteristics and degradation trend characteristics.

[0197] According to an embodiment of the present invention, the processor may perform the following operations.

[0198] According to an embodiment of the present invention, the time-domain performance features, degradation trend features, parameter correlation features and frequency-domain periodic features are time-series encoded using the coding layer of the degradation prediction model to obtain the time-domain performance latent vector, degradation trend latent vector, parameter correlation latent vector and frequency-domain periodic latent vector.

[0199] After extracting the temporal performance features, degradation trend features, parameter correlation features, and frequency domain periodic features, these features can be input into a pre-trained degradation prediction model. The degradation prediction model can be a prediction architecture built based on a long short-term memory neural network, including an input layer, an encoding layer, an attention mechanism layer, and a prediction output layer.

[0200] The input layer can input temporal performance features, degradation trend features, parameter correlation features, and frequency domain periodic features into the coding layer.

[0201] The encoding layer can employ a three-layer stacked LSTM (Long Short-Term Memory) network, with 128 hidden units in each layer. It sequentially encodes the input temporal performance features, degradation trend features, parameter correlation features, and frequency domain periodic features. For any feature, a sliding window of one hour can contain approximately 1200 consecutive sampling points, each of which can be a feature vector. Sequence encoding can be represented as using the LSTM network to process the 1200 sampling points of each feature in chronological order to obtain the hidden vector of the corresponding feature. The gating mechanism of the LSTM network can effectively capture the slow drift trend and stage-by-stage changes of each feature during the long-term aging process.

[0202] According to an embodiment of the present invention, the time-domain performance latent vector, the degradation trend latent vector, the parameter correlation latent vector, and the frequency-domain periodic latent vector are spliced ​​and fused to obtain the target latent state sequence.

[0203] The target hidden state sequence includes multiple fused hidden vectors corresponding to multiple consecutive time steps.

[0204] According to an embodiment of the present invention, the attention mechanism layer of the degradation prediction model uses the degradation prediction matrix to perform a linear mapping on the target hidden state sequence to obtain the degradation query vector, degradation key vector and degradation value vector.

[0205] The degradation prediction matrix includes the query prediction matrix, the key prediction matrix, and the value prediction matrix.

[0206] The target hidden state sequence is input into the attention mechanism layer, which then processes the target hidden state sequence H=[h1,h2,...,h...]. N (There are N time steps in total, and each hidden state vector (h1~h2) N Attention is calculated using 128-dimensional vectors to determine which historical time steps in the sequence are most important for the current degradation prediction.

[0207] Specifically, each hidden state vector in the sequence can be mapped using three predetermined independent linear transformation matrices, where the three independent linear transformation matrices are the query prediction matrix and the query prediction matrix, respectively. (Dimensions are 128×d) k Key prediction matrix (Dimensions are 128×d) k Sum prediction matrix (Dimensions are 128×d) v By using three matrices to perform a linear mapping on each hidden state feature vector, the hidden state vector can be mapped to a degenerate query vector. Degenerate bond vector k n =h n ×W k and degenerate value vector v n =h n ×W v Among them, d k This can be represented as the dimension of the degenerate key vector, d v It can be represented as the dimension of the degenerate value vector, h n It can be represented as the nth hidden state vector, and d k =d v =64.

[0208] The role of linear transformation is to project the original hidden state vector onto different semantic subspaces, so that the degenerate query vector obtained by the mapping can represent what information is needed from the target hidden state sequence; the degenerate key vector can represent what information can be provided from the target hidden state sequence; and the degenerate value vector can represent the actual content in the target hidden state sequence.

[0209] According to an embodiment of the present invention, based on the attention weight rule, the degradation query vector and degradation key vector are scored and normalized to obtain the predicted degradation weight corresponding to each time step.

[0210] Attention is calculated for the degenerate query vector and degenerate key vector corresponding to different time steps. Taking time steps i and j out of N time steps of the degenerate query vector as an example, the original attention scores are... , where q i It can be represented as the degenerate query vector corresponding to the i-th time step, k j It can be represented as the degenerate key vector corresponding to the j-th time step. This can be represented as a scaling factor to prevent the gradient of the Softmax function (Soft Maximum Function) from vanishing due to excessively large dot product values. The larger the original value of this attention, the stronger the correlation between the two time steps. Thus, the above calculation is performed between every two time steps.

[0211] Then, the calculated raw attention scores are normalized. ,in, This can be represented as iterating through N time steps, from the original attention scores at time step i and time step 1, to the sum of the original attention scores at time step i and time step N. Thus, the original scores are transformed into a probability distribution that sums to 1, which is the prediction degradation weight corresponding to each time step. .

[0212] According to an embodiment of the present invention, the degradation value vector is weighted and summed using the prediction degradation weight corresponding to each time step to obtain the target time series fusion vector.

[0213] The degradation value vector is weighted and summed according to the predicted degradation weights corresponding to each time step. This yields the target temporal fusion vector context, which incorporates global temporal information. i Among them, the predicted degradation weight This can be represented as the fusion ratio corresponding to the information at each time step. The greater the weight of a time step, the greater its contribution to the target temporal fusion vector. Higher weights can be obtained for some key degeneration turning points and time steps with drastic changes in dominant parameters. i It can be represented as a degenerate value vector corresponding to the i-th time step.

[0214] For example, when the gallium nitride transistor under test is around 800 hours old, its dynamic on-resistance can suddenly enter an accelerated degradation phase (slope jumps to 0.015 mΩ / h) from a slow increase (slope 0.002 mΩ / h). The attention mechanism can give this transition time step a higher weight (e.g., α=0.15, much higher than the average weight of 0.001 for the steady-state time step), ensuring that the model focuses on the critical moment when the degradation mode changes during prediction. Similarly, the time step when the Pearson correlation coefficient of dynamic on-resistance-junction temperature drops sharply from 0.85 to 0.3 can also be given a higher weight, because the sharp drop in the Pearson correlation coefficient can characterize the change in the degradation mechanism.

[0215] According to an embodiment of the present invention, based on the Monte Carlo algorithm, the prediction output layer of the degradation prediction model is used to perform dimensionality reduction and feature prediction processing on the target time series fusion vector to obtain multiple predicted dynamic on-resistance, remaining usage time information and target confidence interval within the prediction period.

[0216] The prediction output layer can include two fully connected networks (with hidden layer dimensions of 64 and 32 respectively, and ReLU (Rectified Linear Unit) activation function). These two fully connected networks perform dimensionality reduction and feature prediction on the target time-series fusion vector, thereby obtaining multiple predicted dynamic on-resistances and remaining usage time information within the prediction period. For the remaining usage time information, a predetermined failure threshold (which can be defaulted to 1.2 times the initial on-resistance but can be adjusted as needed) can be used as a criterion. By extrapolating the degradation curve of the predicted dynamic on-resistance into the future, the time point at which the predetermined failure threshold is first exceeded can be found. The difference between this time point and the current time is the remaining usage time information. For example, if the gallium nitride transistor under test has been tested for 700 hours, with a dynamic on-resistance of 38mΩ and a predetermined failure threshold of 42mΩ, and the model predicts the dynamic on-resistance will reach 42mΩ in approximately 850 hours, then the remaining usage time information is 850 - 700 = 150 hours.

[0217] Then, to quantify the uncertainty of the prediction results, the processor can use the Monte Carlo method to estimate the prediction confidence interval to measure the accuracy of the prediction results. That is, during the prediction process, T independent forward propagation calculations (e.g., T=50) are performed on the target temporal fusion vector. Since the neurons randomly shut down in each forward propagation are different, there are slight differences in each calculation; therefore, 50 forward propagations will produce 50 slightly different prediction values. The prediction output layer can average the 50 predicted values ​​and calculate the average of the 50 predicted values. This is used as the final predicted value, and the standard deviation corresponding to the 50 predicted values ​​is taken. As a quantitative indicator of prediction accuracy, the 95% target confidence interval is... .

[0218] in, These can be represented as the prediction values ​​obtained in the 1st, 2nd, ..., 50th Monte Carlo forward propagation, respectively. It can be represented as the prediction value obtained in the t-th Monte Carlo forward propagation, and T can be represented as the total number of forward propagations (T can be set to 50). It can be characterized as the standard deviation of 50 predicted values ​​obtained from 50 Monte Carlo runs around the average value μ' of the 50 predicted values, and can be used as a quantitative indicator for prediction uncertainty.

[0219] According to an embodiment of the present invention, target degradation information is generated based on the target confidence interval and the interval threshold, according to multiple predicted dynamic on-resistance and remaining usage time information.

[0220] According to embodiments of the present invention, by using a degradation prediction model to analyze and process the extracted multidimensional features, the target result information for accurately predicting the degradation information of the gallium nitride transistor under test can be obtained with the help of a model with high robustness and high reliability, thereby improving the analysis efficiency and analysis diversity of the gallium nitride transistor under test.

[0221] According to embodiments of the present invention, the processor may also perform the following operations.

[0222] According to an embodiment of the present invention, the accuracy of the prediction output of the degradation prediction model is judged based on the target confidence interval and the interval threshold, and a judgment result is obtained.

[0223] If the width of the target confidence interval is less than or equal to the interval threshold, the result indicates that the prediction accuracy is relatively high; if the width of the target confidence interval is greater than the interval threshold, the result indicates that the prediction accuracy is relatively low.

[0224] For example, when a gallium nitride transistor (GaN) under test has been under test for 700 hours, and its dynamic on-resistance is 38 mΩ, the model can predict the change in dynamic on-resistance over the next 100 hours. During the prediction process, after 50 Monte Carlo simulations, a predicted mean μ' = 41.2 mΩ and a standard deviation σ can be obtained. 50 =0.8mΩ, with a 95% confidence interval of [39.6mΩ, 42.8mΩ]. Given that the interval width of 3.2mΩ is less than the threshold, this is within the normal range, indicating a high confidence level in the model's prediction of the current stable degradation phase. However, when the gallium nitride transistor under test enters the degradation mode transition period (e.g., the initial stage of accelerated increase in dynamic on-resistance), after 50 samplings, μ'=44mΩ and σ 50 =2.5mΩ, the confidence interval expands to [39.1mΩ, 48.9mΩ]. With an interval width of 9.8mΩ greater than the interval threshold, it can be indicated that the model does not fully understand this non-steady-state stage.

[0225] According to an embodiment of the present invention, when the interval width of the target confidence interval characterized by the judgment result is less than or equal to the interval threshold, target degradation information is generated based on multiple predicted dynamic on-resistances and remaining usage time information within the prediction period.

[0226] According to an embodiment of the present invention, when the judgment result indicates that the width of the target confidence interval is greater than the interval threshold, alarm degradation information is generated based on multiple predicted dynamic on-resistances within the prediction period, remaining usage period information, and the width of the target confidence interval.

[0227] According to an embodiment of the present invention, by introducing a confidence interval, the prediction accuracy is evaluated while the predicted dynamic on-resistance and remaining usage time information obtained by the model are obtained, so as to combine the confidence interval to determine the prediction accuracy and adjust the model.

[0228] For degradation prediction models, real-time online updates can be performed. With the continuous accumulation of new data during the prediction process, the degradation prediction model can automatically trigger an online fine-tuning at predetermined intervals. The fine-tuning process can use a small learning rate (e.g., 1 / 10 of the initial pre-training learning rate) to update the parameters of the original degradation prediction model using gradients. Simultaneously, elastic weight consolidation regularization can be used to prevent the original degradation prediction model from forgetting previously trained degradation patterns.

[0229] Specifically, elastic weight consolidation regularization can assign importance to each model parameter in the original degradation prediction model using the Fisher information matrix before fine-tuning the original degradation prediction model.

[0230] For example, the gradient of the original model parameters can be calculated based on the loss function. Based on the loss function L, the gradient of each model parameter θ of the original model can be calculated. m Calculate its gradient Then, the expected value of its squared gradient can be taken as the Fisher information value F. m ,Right now, Among them, F m It can be represented as the Fisher information value corresponding to the m-th model parameter, θ m It can be represented as the m-th model parameter, and E[·] can be represented as the expected value calculation.

[0231] Based on the calculated Fisher information value corresponding to each model parameter, the predictive impact of that model parameter on the degradation prediction model is determined. That is, the larger the Fisher information value corresponding to the model parameter, the more likely a small change in that model parameter may lead to a sharp increase in the prediction error of the degradation prediction model.

[0232] Then, a regularization penalty term can be added to the loss function. Where L_new can be represented as the mean squared error loss between the actual remaining usage time information of the new data and the remaining usage time information predicted by the model, θ m * can be represented as the parameter value of the m-th model parameter in the model before fine-tuning, θ m 'It can be represented as the parameter value of the m-th model parameter being fine-tuned in the model, where λ is the regularization intensity coefficient.

[0233] This penalty term constrains the more important model parameters determined by Fisher's information values, preventing them from being updated drastically and thus protecting the important model parameters in the original degenerate prediction model. For less important model parameters, the penalty term has a weaker constraint, allowing them to be adjusted and updated with continuously updated sample datasets.

[0234] This approach allows for the timely updating of the degradation prediction model while appropriately retaining some important model parameters and training processes from the original update, thereby enhancing prediction capabilities and improving prediction accuracy.

[0235] According to embodiments of the present invention, the processor may also perform the following operations.

[0236] According to an embodiment of the present invention, parameter correlation features and frequency domain periodic features are spliced ​​together to obtain a spliced ​​feature sequence.

[0237] According to an embodiment of the present invention, the spliced ​​feature sequence is encoded and reconstructed using a three-layer fully connected network of the encoder and a decoder of the anomaly detection model to obtain a reconstructed latent space feature sequence.

[0238] The encoder of the anomaly detection model can consist of three fully connected layers (dimensions sequentially from input dimension → 64 → 32 → 16). The encoder can compress the concatenated feature sequence of the input layer by layer into a low-dimensional latent space. The decoder can be a mirror image of the encoder (16 → 32 → 64 → input dimension). The decoder's role is to start from the 16-dimensional latent space representation and restore it to a reconstructed output with the same dimensions as the original input.

[0239] The encoder can compress high-dimensional data into a low-dimensional space without losing key information. The key lies in the inherent physical constraints between the monitored parameters under normal operating conditions (e.g., the positive temperature coefficient relationship between dynamic on-resistance and junction temperature, and Ohm's law relationship between drain current and drain-source voltage). These parameters can form a low-dimensional manifold structure constrained by underlying physical mechanisms. During training, the encoder can extract the most essential mutual constraints between parameters (i.e., the physical laws under normal conditions) and discard redundant information, retaining the core correlations in a 16-dimensional representation.

[0240] For pre-training the anomaly detection model, the first 200 hours of normal data from a gallium nitride transistor can be randomly divided into a training subset and a validation subset in an 8:2 ratio. The Adam (Adaptive Moment) optimizer (learning rate 0.001) is used on the training subset to optimize the model parameters. Simultaneously, after each training epoch, the reconstruction error can be recalculated using the validation subset. If the reconstruction error in the validation subset no longer decreases after 15 consecutive iterations, early stopping can be triggered to terminate training. The initial model corresponding to the parameters with the lowest error in the validation set is then used as the trained anomaly detection model. This avoids the model over-memorizing noise and random fluctuations in the training data, thus preventing it from losing its ability to generalize and recognize normal patterns.

[0241] Furthermore, Monte Carlo constraints (ratio 0.1) can be added between the layers of the encoder to further enhance generalization performance. The predetermined error threshold can be obtained based on the mean and three times the standard deviation of the reconstruction error on the training subset.

[0242] According to an embodiment of the present invention, the mean square error of the spliced ​​feature sequence and the reconstructed latent space feature sequence is calculated to obtain the reconstruction error value.

[0243] The mean square error between the concatenated feature sequence Z and the reconstructed latent space feature sequence Z' is = Where d can be represented as the feature dimension, Z p It can be represented as the p-th vector in the concatenated feature sequence, Z' p It can be represented as the p-th reconstructed vector in the reconstructed latent space feature sequence.

[0244] According to an embodiment of the present invention, when the reconstruction error value is greater than a predetermined error threshold, multi-parameter collaborative anomaly information is generated based on the abnormal parameter association features and abnormal frequency domain periodic features corresponding to the reconstruction error value.

[0245] By using anomaly detection models to analyze and detect parameter correlation features and frequency domain periodic features, it is possible to obtain some anomaly detection information that cannot be detected solely by threshold detection.

[0246] For example, the dynamic on-resistance of a gallium nitride transistor under test can increase with increasing junction temperature, and the two can maintain a positive coupling relationship. By analyzing the features using an anomaly detection model, it is possible to determine whether an anomaly exists based on the dynamic coupling relationship between the two parameters, even if neither the dynamic on-resistance nor the junction temperature shows any anomalies at the threshold values ​​individually.

[0247] According to an embodiment of the present invention, based on a multi-dimensional fusion strategy, a fusion decision is made on multi-parameter collaborative anomaly information and feature anomaly information to determine the anomaly level of the gallium nitride transistor under test.

[0248] Among them, the feature anomaly information is obtained by judging the parameter correlation features and frequency domain periodic features based on the anomaly threshold and mutation rules. The feature anomaly information includes abnormal change trends.

[0249] Feature anomaly information can include parameter anomaly information generated by dynamically monitoring real-time acquired performance parameters based on statistical process control threshold detection and anomaly thresholds. Feature anomaly information can also include abnormal change trends. Based on change point detection mutation rules, a Bayesian online change point detection algorithm can be used to monitor the time series of each performance parameter in real time, automatically identifying the time points when significant abrupt changes occur in the parameter's statistical characteristics (mean, variance, or change trend), that is, whether the performance parameter has undergone drastic changes beyond the normal fluctuation range within a very short period of time (usually within several to dozens of sampling periods).

[0250] Among them, statistical process control threshold detection can detect continuous deviations and gradual degradation anomalies of a single performance parameter; anomaly detection model detection can detect hidden degradation patterns where a single performance parameter appears normal but the correlation between parameters is abnormal.

[0251] Mutation detection can identify changes in the statistical characteristics of performance parameters over time, making it suitable for real-time detection of precursors to abrupt failures. Examples include a sudden increase in dynamic on-resistance exceeding 50% of the change over the previous 1000 hours within minutes, or a sudden increase in leakage current by an order of magnitude.

[0252] Based on a multi-strategy fusion approach, decisions are made by fusing multi-parameter collaborative anomaly information and feature-based anomaly information. That is, when any strategy detects an anomaly, a primary warning can be issued; when two or more strategies detect an anomaly simultaneously, a high-level alarm can be issued and a recommendation for close monitoring can be made.

[0253] According to an embodiment of the present invention, target anomaly information is generated based on anomaly level, multi-parameter collaborative anomaly information, and feature anomaly information.

[0254] According to embodiments of the present invention, by utilizing an anomaly detection model, anomaly features can be analyzed and mined in detail and at a deeper level. By combining fusion decision-making, the complementary advantages of the three methods are fully utilized, the false alarm rate of a single method is reduced, and the overall reliability of anomaly detection of the gallium nitride transistor under test is improved.

[0255] Specifically, the presentation of target degradation information and target anomaly information can be summarized and presented through degradation prediction dashboards, anomaly alarm lists, batch consistency analysis reports, and other automatically generated reports.

[0256] The degradation prediction dashboard can display information obtained from the target degradation information, such as the predicted dynamic on-resistance, remaining usage time, target confidence interval, and degradation rate rating (normal / concern / warning / dangerous level 4) for each gallium nitride transistor under test.

[0257] The anomaly alarm list can list all detected abnormal events in chronological order and by severity, including detailed information such as the anomaly type (mutation / gradual change / related anomaly) in the target anomaly information, the parameters involved, the detection time, and the confidence level;

[0258] The batch consistency analysis report can automatically compare the degradation trajectories of devices in the same batch, identify individuals whose degradation rate deviates significantly from the batch average, and generate a batch consistency assessment report.

[0259] Automatic report generation: When the test ends or reaches a set node, a structured test report containing degradation analysis, summary of abnormal events, and information on the remaining usage time can be automatically generated.

[0260] Figure 9 A schematic diagram of target degradation information is shown according to an embodiment of the present invention.

[0261] like Figure 9 As shown in the figure, the horizontal axis represents aging time (h), the vertical axis represents dynamic on-resistance (mΩ), the blue line represents the actual sampled data, the red dashed line represents the target degradation information predicted by the degradation prediction model, and the red area represents the 95% confidence interval. It can be seen from the figure that under the test environment conditions of a drain-source voltage Vds of 400V, a switching frequency of 200kHz, a duty cycle of 20%, a junction temperature of 150°C, and an analog-to-digital converter resolution of 18bit, there is basically no significant error between the target degradation information predicted by the degradation prediction model and the degradation curve obtained from actual sampling. Only the area represented by the red dashed line can be considered as the predicted dynamic on-resistance and remaining usage time information obtained by the degradation prediction model. Furthermore, the confidence interval between this information and the information predicted by the degradation prediction model widens with time, meaning that the accuracy of the predicted degradation information decreases over time. The rated voltage of the gallium nitride transistor under test is 650V, and the rated current is 30A.

[0262] Figure 10a A schematic diagram of the multi-station test results according to an embodiment of the present invention is shown. Figure 10b A schematic diagram of the results of a multi-station test according to another embodiment of the present invention is shown.

[0263] like Figure 10a and Figure 10b As shown, Figure 10aThe horizontal axis can be represented by the workstation number, and the vertical axis can be represented by the drift rate (%) of the dynamic on-resistance. Figure 10b The ordinate can be represented as the detection confidence level (%). From Figure 10a As can be seen, the dynamic on-resistance drift rates of the 80 GaN transistors under test (DUTs) across the four test areas vary with test time. The DUTs at test stations 9, 30, and 56 are in a primary warning state, while those at test stations 17, 45, and 63 are in a high-level alarm state. Figure 10b The results show the confidence distribution of the detection results among the three gallium nitride transistors under test (GaN transistors at test stations 17, 45, and 63). When using threshold detection, the first and third GaN transistors are found to be abnormal; when using the anomaly detection model, the second and third GaN transistors are found to be abnormal; when using the mutation rule detection, the first GaN transistor is found to be abnormal; after comprehensive decision-making using a multi-dimensional fusion strategy, it can be seen that each GaN transistor under test needs to report anomaly information.

[0264] Figure 11 A flowchart of a test method for gallium nitride transistors according to an embodiment of the present invention is shown.

[0265] like Figure 11 As shown, the testing method for gallium nitride transistors in this embodiment may include operations S1110 to S1140.

[0266] In operation S1110, based on the predetermined configuration constraints and configuration adjustment strategy, the target test configuration information is obtained from the test configuration database by using the test configuration decision tree model, and control instructions are generated according to the target test configuration information to control the acquisition control module to acquire the performance parameters of the gallium nitride transistor under test.

[0267] The performance parameters include the operating parameters and dynamic on-resistance of the gallium nitride transistor under test.

[0268] In operation S1120, the performance parameters acquired by the acquisition and control module are feature extracted to obtain the multi-dimensional time-frequency state characteristics of the gallium nitride transistor under test.

[0269] In operation S1130, the degradation prediction model is used to predict the multi-dimensional time-frequency state features to obtain the target degradation information.

[0270] Among them, the target degradation information characterizes the predicted trend of dynamic on-resistance changing over time.

[0271] In operation S1140, the anomaly detection model is used to detect and process the parameter correlation features and frequency domain periodic features in the multidimensional time-frequency state features to obtain target anomaly information.

[0272] The target anomaly information includes the abnormal operating parameters and abnormal change trends of the gallium nitride transistor under test.

[0273] Those skilled in the art will understand that the features described in the various embodiments and / or claims of the present invention can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments and / or claims of the present invention can be combined or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.

Claims

1. A testing system for gallium nitride transistors, characterized in that, The system includes: The multi-station test architecture is distributed across multiple test areas within the test cabinet. Each station's test architecture includes its own independently operating test module and data acquisition and control module. The test module, electrically connected to the acquisition and control module, includes a sub-board slot and an asymmetric full-bridge test circuit electrically connected to the sub-board slot. The sub-board slot is used to insert a gallium nitride transistor under test (GaN transistor). The asymmetric full-bridge test circuit is used to perform performance testing on the GaN transistor under test electrically connected to the asymmetric full-bridge test circuit in response to a pulse width modulation signal. The acquisition and control module is used to generate the pulse width modulation signal according to the control command and send it to the test module, acquire the performance parameters of the gallium nitride transistor under test during the test process, and send them to the processor. The processor, electrically connected to the acquisition and control module, is used for... Based on predetermined configuration constraints and configuration adjustment strategies, the target test configuration information is obtained from the test configuration database using a test configuration decision tree model. The control command is then generated based on the target test configuration information to control the acquisition control module to acquire the performance parameters, which include the operating parameters and dynamic on-resistance of the gallium nitride transistor under test. Feature extraction is performed on the performance parameters to obtain the multidimensional time-frequency state features of the gallium nitride transistor under test; The multidimensional time-frequency state features are predicted using a degradation prediction model to obtain target degradation information, which characterizes the predicted trend of dynamic on-resistance changing over time. An anomaly detection model is used to detect and process the parameter correlation features and frequency domain periodic features in the multidimensional time-frequency state features to obtain target anomaly information, which includes the abnormal operating parameters and abnormal change trends of the gallium nitride transistor under test.

2. The testing system according to claim 1, characterized in that, The asymmetric full-bridge test circuit includes: The first transistor has a first terminal electrically connected to the first power supply bus, a second terminal electrically connected to the first terminal of the first freewheeling diode, and a third terminal electrically connected to the acquisition and control module. It is used to turn on or off under the control of the pulse width modulation signal so as to facilitate performance testing of the gallium nitride transistor under test. The first freewheeling diode has its second terminal grounded. The second freewheeling diode has its first end electrically connected to the first power supply bus and its second end electrically connected to the first end of the daughterboard slot. The first terminal of the load resistor is electrically connected to the second terminal of the first transistor, and the second terminal of the load resistor is electrically connected to the first terminal of the load inductor. The current sampling resistor has its first terminal electrically connected to the second terminal of the daughterboard slot, and its second terminal grounded. The load inductor is electrically connected to the second terminal of the second freewheeling diode. The filter capacitor has its first terminal electrically connected to the first power supply bus, and its second terminal grounded.

3. The testing system according to claim 2, characterized in that, When the first transistor is turned on, the filter capacitor and the first power supply bus discharge together, and the test current forms a loop through the first transistor, the load resistor, the load inductor, the GaN transistor under test, and the current sampling resistor. When the first transistor is turned off, the first freewheeling diode and the second freewheeling diode form a freewheeling loop together, so that the test current flows into the filter capacitor through the first freewheeling diode, the load resistor, the load inductor, and the second freewheeling diode, so as to charge the filter capacitor.

4. The testing system according to claim 1, characterized in that, Each test area includes a first power supply bus and a second power supply bus; the acquisition and control module includes a voltage sampling circuit and a current sampling circuit; The first power supply bus is electrically connected to multiple test modules located in the same test area, and is used to provide test current to the multiple test modules to perform performance testing on multiple gallium nitride transistors under test. The second power supply bus is electrically connected to multiple acquisition and control modules located in the same test area, and is used to provide operating voltage to the multiple acquisition and control modules so that the multiple acquisition and control modules are in normal working condition. A voltage sampling circuit, electrically connected to the test module, includes a resistor divider network for stepping down the acquired working test voltage of the gallium nitride transistor under test through a resistor divider network including multiple series resistors, to obtain a working step-down voltage. The voltage sampling range of the voltage sampling circuit is 0V~1000V. The current sampling circuit, electrically connected to the test module, includes a first range sampling circuit and a second range sampling circuit. The first range sampling circuit is used to collect the working test current in a first current range, and the second range sampling circuit is used to collect the working test current in a second current range. The first current range is smaller than the second current range. The first current range is 0~3A, and the second current range is 3~40A.

5. The testing system according to claim 1, characterized in that, The processor is also used for: Based on the physical parameters of the gallium nitride transistor under test, a first candidate configuration template and a second candidate configuration template corresponding to the gallium nitride transistor under test are determined from the device parameter configuration library and the historical parameter configuration library, respectively. The first candidate configuration template includes multiple test configuration parameters corresponding to the gallium nitride transistor under test, and the second candidate configuration template includes multiple historical test configuration parameters corresponding to the gallium nitride transistor under test. The test configuration database is constructed based on the device parameter configuration library and the historical parameter configuration library; The physical parameters of the gallium nitride transistor under test and the test configuration database are input into the test configuration decision tree model. Based on the historical best test configuration parameters, the mean square error is calculated and the residual is predicted for each candidate configuration template in the test configuration database using multiple test configuration decision trees in the test configuration decision tree model, so as to obtain the third candidate configuration template. Based on the predetermined configuration constraints and the configuration adjustment strategy, the first candidate configuration template, the second candidate configuration template, and the third candidate configuration template are verified respectively, and the target test configuration information is determined according to the verification results.

6. The testing system according to claim 5, characterized in that, The processor is also used for: Based on predetermined configuration constraints and the physical parameters of the gallium nitride transistor under test, the first candidate configuration template, the second candidate configuration template, and the third candidate configuration template are subjected to safety verification to determine the target candidate configuration template. The predetermined configuration constraints indicate that the template that meets the rated limit, test limit, and thermal safety verification is selected as the target candidate configuration template. When the historical anomaly detection results of the gallium nitride transistor under test indicate that the historical junction temperature of the device is greater than a predetermined temperature threshold, the historical temperature deviation and the historical temperature change rate are calculated using a fuzzy logic control algorithm to obtain the first stress adjustment step parameter. The historical temperature deviation and the historical temperature change rate are calculated based on the historical junction temperature of the device and the predetermined temperature threshold. The second stress adjustment step parameter is determined based on the degradation stage in the historical degradation prediction information of the gallium nitride transistor under test; Based on the configuration adjustment strategy, the transistor on-frequency and duty cycle in the target candidate configuration template are adjusted using the first stress adjustment step parameter and the second stress adjustment step parameter to obtain the target test configuration information.

7. The testing system according to claim 1, characterized in that, The multidimensional time-frequency state features also include time-domain performance features and degradation trend features, and the processor is further used for: The time-domain performance features, degradation trend features, parameter correlation features, and frequency-domain periodic features are time-series encoded using the encoding layer of the degradation prediction model to obtain time-domain performance latent vectors, degradation trend latent vectors, parameter correlation latent vectors, and frequency-domain periodic latent vectors. The time-domain performance latent vector, the degradation trend latent vector, the parameter correlation latent vector, and the frequency-domain periodic latent vector are concatenated and fused to obtain a target latent state sequence, wherein the target latent state sequence includes multiple fused latent vectors corresponding to multiple consecutive time steps. The attention mechanism layer of the degradation prediction model uses the degradation prediction matrix to perform a linear mapping on the target hidden state sequence to obtain a degradation query vector, a degradation key vector, and a degradation value vector, wherein the degradation prediction matrix includes a query prediction matrix, a key prediction matrix, and a value prediction matrix. Based on the attention weight rule, the degradation query vector and the degradation key vector are scored and normalized to obtain the predicted degradation weight corresponding to each time step; Using the predicted degradation weights corresponding to each time step, the degradation value vector is weighted and summed to obtain the target time series fusion vector; Based on the Monte Carlo algorithm, the target time-series fusion vector is subjected to dimensionality reduction and feature prediction processing using the prediction output layer of the degradation prediction model to obtain multiple predicted dynamic on-resistance, remaining usage time information and target confidence interval within the prediction period. Based on the target confidence interval and interval threshold, the target degradation information is generated according to the multiple predicted dynamic on-resistances and the remaining usage time information.

8. The testing system according to claim 7, characterized in that, The processor is also used for: Based on the target confidence interval and the interval threshold, the accuracy of the prediction output of the degradation prediction model is judged, and the judgment result is obtained. If the judgment result indicates that the width of the target confidence interval is less than or equal to the interval threshold, the target degradation information is generated based on multiple predicted dynamic on-resistances and remaining usage time information within the prediction period. If the judgment result indicates that the width of the target confidence interval is greater than the interval threshold, alarm degradation information is generated based on multiple predicted dynamic on-resistances, remaining usage time information, and the width of the target confidence interval during the prediction period.

9. The testing system according to claim 1, characterized in that, The processor is also used for: The parameter correlation features and frequency domain periodic features are concatenated to obtain a concatenated feature sequence. The spliced ​​feature sequence is encoded and reconstructed using the three-layer fully connected network of the encoder and the decoder of the anomaly detection model to obtain the reconstructed latent space feature sequence. The mean square error of the spliced ​​feature sequence and the reconstructed latent space feature sequence is calculated to obtain the reconstruction error value. When the reconstruction error value is greater than a predetermined error threshold, multi-parameter collaborative anomaly information is generated based on the abnormal parameter association features and abnormal frequency domain periodic features corresponding to the reconstruction error value. Based on a multi-dimensional fusion strategy, a fusion decision is made on multi-parameter collaborative anomaly information and feature anomaly information to determine the anomaly level of the gallium nitride transistor under test. The feature anomaly information is obtained by judging the parameter correlation features and the frequency domain periodic features based on anomaly thresholds and mutation rules. The feature anomaly information includes the anomaly change trend. The target anomaly information is generated based on the anomaly level, the multi-parameter collaborative anomaly information, and the feature anomaly information.

10. A method for testing gallium nitride transistors, characterized in that, A test system applied to gallium nitride transistors as described in any one of claims 1-9, the method comprising: Based on predetermined configuration constraints and configuration adjustment strategies, the target test configuration information is obtained from the test configuration database using a test configuration decision tree model. The control command is then generated based on the target test configuration information to control the acquisition control module to acquire the performance parameters of the gallium nitride transistor under test. The performance parameters include the operating parameters and dynamic on-resistance of the gallium nitride transistor under test. Feature extraction is performed on the performance parameters acquired by the acquisition and control module to obtain the multidimensional time-frequency state characteristics of the gallium nitride transistor under test; The multidimensional time-frequency state features are predicted using a degradation prediction model to obtain target degradation information, wherein the target degradation information characterizes the predicted trend of the dynamic on-resistance changing over time. An anomaly detection model is used to detect and process the parameter correlation features and frequency domain periodic features in the multidimensional time-frequency state features to obtain target anomaly information, wherein the target anomaly information includes the abnormal operating parameters and abnormal change trends of the gallium nitride transistor under test.

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