A synchronous rectifier-encapsulated chip operating status detection circuit and detection method

Abstract

This invention relates to the field of switching power supply and detection circuit technology, specifically to a detection circuit and method for detecting the operating status of a synchronous rectifier-encapsulated chip. The circuit includes: a main circuit comprising a main switching transistor and a freewheeling unit, wherein the freewheeling unit is composed of multiple synchronous rectifier-encapsulated chips connected in series, with its tail end connected to the source of the main switching transistor at a common switching node, and its head end grounded; and a status monitoring circuit comprising a conduction voltage drop sampling branch and a status monitoring signal conversion branch, both connected via an optocoupler. The input of the sampling branch is connected to the switching node, and the output, after optocoupler conversion, is output as a detection voltage by the signal conversion branch. This invention solves the problem of difficulty in detecting the conduction state of a synchronous rectifier-encapsulated chip when the gate is not brought out. By utilizing the characteristics of optocouplers, it achieves the signal detection function for the weak negative voltage drop during the conduction period of the synchronous rectifier-encapsulated chip, providing an accurate and non-invasive means of discrimination for yield control, aging monitoring, and system redundancy protection.

Description

Technical Field

[0001] This invention relates to the field of switching power supply and detection circuit technology, specifically to a synchronous rectification and encapsulation chip operating status detection circuit and detection method. Background Technology

[0002] In AC / DC and DC / DC switching power supply products, especially in applications with low output voltage and high current, traditional power supply solutions using diodes as freewheeling diodes face bottlenecks such as high freewheeling device losses and high temperature rise, making it difficult to meet increasingly stringent energy efficiency requirements. To solve this problem, the industry widely adopts MOSFET switching devices operating in the third quadrant to replace traditional diodes, forming a synchronous rectification freewheeling scheme. Since the channel forward voltage drop of a MOSFET in the third quadrant is much lower than that of a diode, this technology has significant advantages in terms of conduction losses and temperature rise control, and has become the preferred solution for modern high-efficiency switching power supplies. Taking a typical Buck topology as an example, the synchronous rectification circuit usually includes a fully controllable semiconductor switching device (such as a MOSFET) as a freewheeling diode, a controller and driver for controlling the switching operation of the freewheeling MOSFET, magnetic components for energy storage (such as inductors or transformers), and an output filter capacitor. In recent years, consumer power supplies have faced increasing demands for cost and size. Synchronous rectification solutions have shown a trend of development from discrete components to single-chip integrated packaging, which integrates the synchronous rectification controller, driver and power freewheeling MOSFET into the same chip, for example, using an SOP8 package.

[0003] However, such co-packaged chips have the following significant drawbacks: 1) Since the power MOSFET is packaged inside the chip, its gate signal is usually not brought out to an external pin separately, so the actual working state of the MOSFET cannot be determined by directly detecting the drive gate signal inside the chip; 2) This type of packaged chip operates in a high-frequency PWM state, with the MOSFET turned on in the third quadrant. When normally turned on, the channel voltage drop is usually around -100mV, while the voltage drop at the turn-off time can reach about 40V. The difference between the two is extremely large, making it difficult to reliably detect and identify the weak on-state voltage drop signal under strong interference.

[0004] The aforementioned reasons collectively make it difficult to directly and accurately monitor and determine the actual conduction state of the internal MOSFETs in existing packaged synchronous rectifier chips under normal operating conditions. For example, during the FT test in the production stage, it is necessary to verify whether each chip functions normally to ensure yield. During the reliability verification stage (such as HTOL), it is necessary to ensure that the chip can continue to operate normally without damage for 1000 hours. Furthermore, during the customer power system application stage, it is necessary to implement redundant design at the synchronous rectifier device level to improve system reliability. However, there is currently a lack of effective detection methods to determine whether the operating state of the internal MOSFETs of packaged chips is normal, which restricts yield control, reliability verification, and system-level protection design.

[0005] Therefore, accurately determining whether the MOSFET inside the synchronous rectification packaged chip is operating normally without relying on external gate pins and overcoming interference from weak on-state voltage drop signals has become a technical challenge that the upstream and downstream power supply industries urgently need to solve. Summary of the Invention

[0006] To address the above technical problems, this invention provides a technical solution for detecting the working status of a synchronous rectified and packaged chip, including a detection circuit and method.

[0007] The technical problem solved by this invention can be achieved by the following technical solution: a synchronous rectification and encapsulation chip operating status detection circuit, comprising: a main circuit, the main circuit including a main switching transistor and a freewheeling unit, the freewheeling unit including multiple synchronous rectification and encapsulation chips connected in series, wherein: the drain of the main switching transistor is connected to a DC voltage source, the tail end of the freewheeling unit and the source of the main switching transistor are connected to the same switching node, and the head end of the freewheeling unit is grounded; a status monitoring circuit, the status monitoring circuit including a conduction voltage drop sampling branch and a status monitoring signal conversion branch, wherein: the conduction voltage drop sampling branch and the status monitoring signal conversion branch share the same optocoupler, the input end of the optocoupler constitutes the output end of the conduction voltage drop sampling branch, and the output end of the optocoupler constitutes the input end of the status monitoring signal conversion branch; the input end of the conduction voltage drop sampling branch is connected to the switching node, and the output end of the status monitoring signal conversion branch outputs a detection voltage, the detection voltage being used to characterize the operating status of the synchronous rectification and encapsulation chip in the freewheeling unit.

[0008] Preferably, the synchronous rectification packaged chip includes a synchronous rectification controller and a power transistor. The synchronous rectification controller is connected to the gate of the power transistor and is used to drive the power transistor to conduct in the third quadrant.

[0009] Preferably, the main circuit further includes: an open-loop controller connected to the gate of the main switching transistor for driving the main switching transistor at a fixed frequency and a fixed duty cycle; an energy storage inductor, the first end of which is connected to the switching node, and the second end of which outputs a DC output voltage; an output capacitor, the first end of which is connected to the second end of the energy storage inductor, and the second end of which is grounded; and a load resistor, the first end of which is connected to the second end of the energy storage inductor, and the second end of which is grounded.

[0010] Preferably, the on-state voltage drop sampling branch further includes: a first resistor, the first end of the first resistor being connected to a first DC power supply, the second end of the first resistor being connected to the anode of the light-emitting diode in the optocoupler, and the cathode of the light-emitting diode being connected to the switching node.

[0011] Preferably, the state monitoring signal conversion branch further includes: a second resistor, the first end of which is connected to a second DC power supply, and the second end of which is connected to the collector of the phototransistor in the optocoupler, the emitter of which is grounded; a filter capacitor, the first end of which, the collector of which, and the second end of which are connected to a common node, and the second end of which is grounded; and the detection voltage is output from the common node.

[0012] A method for detecting the operating status of a synchronous rectification and encapsulation chip, applied to a synchronous rectification and encapsulation chip operating status circuit as described above, includes: Step S1, powering on the detection circuit and detecting the DC output voltage after waiting for a first preset delay; Step S2, after the output voltage reaches a stable state, calculating and setting multiple threshold voltages, each threshold voltage corresponding to a number of abnormal chips, to form a synchronous rectification and encapsulation chip abnormal state threshold table; Step S3, acquiring the detected voltage and comparing and analyzing the detected voltage with each threshold voltage in the synchronous rectification and encapsulation chip abnormal state threshold table in sequence to obtain the number of abnormal chips; Step S4, recording and outputting the judgment result, the judgment result including abnormal alarm information and the number of abnormal chips.

[0013] Preferably, in step S2, the formula for calculating the threshold voltage is: Vth(n)=Vdd2-(CTR*Rup2 / Rup1)*[Vdd1-Vfled+n*Vsdth], n≥1, Where Vth(n) is the nth threshold voltage; Vdd2 is the second DC power supply voltage; CTR is the ratio of the optocoupler output current to the optocoupler input current; Rup2 is the second resistance value; Rup1 is the first resistance value; Vdd1 is the first DC power supply voltage; Vfled=1 is the forward conduction voltage drop of the light-emitting diode in the optocoupler device; Vsdth=0.5 is the judgment threshold used to distinguish the conduction state of the power transistor; n is a positive integer.

[0014] Preferably, in step S3, the formula for calculating the detection voltage is: Vc=Vdd2-IC*Rup2=Vdd2-(CTR*IF)*Rup2=Vdd2-[CTR*(Vdd1-Vfled-VSW) / Rup1]*Rup2, Where Vc is the detection voltage; IC is the collector current of the phototransistor in the optocoupler; IF is the forward current of the light-emitting diode in the optocoupler; Vfled is the forward voltage drop of the light-emitting diode in the optocoupler; and VSW is the forward voltage drop at the switching node.

[0015] Preferably, in step S3, the detected voltage is compared and analyzed sequentially with each threshold voltage in the synchronous rectification and encapsulation chip abnormal state threshold table. The specific analysis steps are as follows: Step S31, determine whether the detected voltage is less than the first threshold voltage, expressed by the formula: Vc < Vth(m), m=1; if yes, proceed to step S32; if no, the working state of all synchronous rectification and encapsulation chips is normal, and the abnormal chip quantity value m=0 is initialized; Step S32, increase the abnormal chip quantity value m by 1, and determine whether the detected voltage is greater than the (m+1)th threshold voltage and less than the mth threshold voltage, expressed by the formula: Vth(m+1) < Vc < Vth(m); if no, repeat step S32; if yes, determine that the abnormal chip quantity value is m, and stop the judgment.

[0016] Preferably, the first preset delay is 500ms.

[0017] Beneficial effects: By introducing a conduction voltage drop sampling branch that shares the same optocoupler with the state monitoring signal conversion branch, this invention can directly obtain the conduction status information of multiple series-connected synchronous rectification packaged chips in the freewheeling unit from the switching node without relying on external gate pins and overcoming strong interference from weak conduction voltage drops. This conduction status information is then converted into an easily discernible detection voltage output through optocoupler isolation. This provides an accurate and non-intrusive method for determining the internal MOSFET operating status for yield control in the production stage, long-term aging monitoring in the reliability verification stage, and multi-level redundancy protection design in power system applications. It effectively solves the industry problem that traditional solutions cannot monitor the actual conduction status of packaged chips online. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the main circuit in the detection circuit of the present invention; Figure 2 This is a schematic diagram of the state monitoring circuit in the detection circuit of the present invention; Figure 3 This is a schematic diagram of the detection method steps of the present invention; Figure 4 This is a flowchart of the detection method of the present invention; Figure 5 This is a linear relationship graph showing the measured value of the detection voltage in this invention as a function of the on-state voltage drop of the switching node; Figure 6 This is a diagram showing the correspondence between the specific number of chip anomalies in this invention; Figure 7 This is a schematic diagram showing the waveform changes of various signals in the circuit when the synchronous rectification and encapsulation chip changes from completely normal to only one abnormal chip in the present invention. Figure 8 This is a schematic diagram showing the waveform changes of various signals in the circuit when the synchronous rectification and encapsulation chip changes from having only one abnormal chip to having only two abnormal chips in this invention. Figure 9 This is a schematic diagram showing the waveform changes of various signals in the circuit when the synchronous rectification and encapsulation chip changes from having only two abnormal chips to having only three abnormal chips. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0021] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0022] Reference Figure 1 and Figure 2 This invention provides a synchronous rectification and encapsulation chip operating status detection circuit, comprising: a main circuit 1, the main circuit 1 including a main switch transistor QM and a freewheeling unit 11, the freewheeling unit 11 including multiple synchronous rectification and encapsulation chips connected in series, wherein: the drain of the main switch transistor QM is connected to a DC voltage source Vdc, the tail end of the freewheeling unit 11 and the source of the main switch transistor QM are connected to the same switching node SW, and the head end of the freewheeling unit 11 is grounded; and a status monitoring circuit 2, the status monitoring circuit 2 including a conduction voltage drop sampling branch 21 and a status monitoring signal conversion branch 22, wherein... The on-state voltage drop sampling branch 21 and the state monitoring signal conversion branch 22 share the same optocoupler U_OPTO. The input terminal of the optocoupler U_OPTO forms the output terminal of the on-state voltage drop sampling branch 21, and the output terminal of the optocoupler U_OPTO forms the input terminal of the state monitoring signal conversion branch 22. The input terminal of the on-state voltage drop sampling branch 21 is connected to the switching node SW, and the output terminal of the state monitoring signal conversion branch 22 outputs a detection voltage. The detection voltage is used to characterize the working state of the synchronous rectification and encapsulation chip in the freewheeling unit 11.

[0023] Specifically, in this embodiment of the invention, addressing the problem that the actual conduction state of the encapsulated synchronous rectifier chip cannot be directly monitored online due to the fact that the internal MOSFET gate is not brought out and the weak conduction voltage drop signal is easily interfered with by high voltage at the turn-off moment, the input terminal of the conduction voltage drop sampling branch 21 is connected to the switching node SW, and it shares the same optocoupler U_OPTO with the state monitoring signal conversion branch 22. By utilizing the isolation and level conversion characteristics of the optocoupler, the weak conduction voltage drop change is converted into an easily discernible detection voltage Vc output. This avoids the detection bottlenecks of traditional solutions that require external gate pins and weak signals being submerged by strong background noise. It achieves non-intrusive and highly reliable discrimination of the working state (normal conduction or failure) of multiple series-connected encapsulated synchronous rectifier chips, thereby providing accurate status information in production testing, long-term aging verification, and power system redundancy protection.

[0024] Specifically, refer to Figure 1 The main switch QM is an N-channel MOSFET that alternately performs turn-on and turn-off actions under the drive of the controller. The DC voltage source Vdc connected to the drain of the main switch QM provides a DC input voltage Vin, thereby generating a switching voltage waveform with an amplitude of Vin at the switching node SW, so that the subsequent energy storage element completes the charging and releasing process within the switching cycle.

[0025] Reference Figure 2 The optocoupler U_OPTO includes a light-emitting diode (LED) and a phototransistor. The anode of the LED serves as the input terminal of the optocoupler U_OPTO, and the cathode of the LED is connected to the switching node SW. The collector of the phototransistor serves as the output terminal of the optocoupler U_OPTO, and the emitter of the phototransistor is grounded. Electrical isolation between the LED and the phototransistor is achieved through optical signal coupling. The LED converts the input current signal into an optical signal, and the phototransistor receives the optical signal and converts it into a collector current signal at the output terminal.

[0026] In a preferred embodiment of the present invention, the synchronous rectification packaged chip includes a synchronous rectification controller and a power transistor. The synchronous rectification controller is connected to the gate of the power transistor and is used to drive the power transistor to conduct in the third quadrant.

[0027] Specifically, in order to eliminate the detection blind zone that makes it impossible to directly monitor the conduction state of the power transistor because the gate signal inside the encapsulated chip is not brought out to the outside, in this embodiment of the invention, multiple synchronous rectification encapsulated chips are connected in series to form a freewheeling unit 11, which amplifies the change in conduction voltage drop by using the series superposition method, and realizes the state discrimination through the subsequent optocoupler detection circuit.

[0028] Specifically, refer to Figure 1 The freewheeling unit 11 includes n synchronous rectification packaged chips connected in series, namely, the first synchronous rectification packaged chip U1, the second synchronous rectification packaged chip U2, the third synchronous rectification packaged chip U3... and the nth synchronous rectification packaged chip Un; wherein, the first synchronous rectification packaged chip U1 includes a first power transistor QSR1 and a first synchronous rectification controller VC1 connected to the gate of the first power transistor QSR1; the second synchronous rectification packaged chip U2 includes a second power transistor QSR2 and a second synchronous rectification controller VC2 connected to the gate of the second power transistor QSR2; the third synchronous rectification packaged chip U3 includes a third power transistor QSR3 and a third synchronous rectification controller VC3 connected to the gate of the third power transistor QSR3; and so on, the nth synchronous rectification packaged chip Un includes an nth power transistor QSRn and an nth synchronous rectification controller VCn connected to the gate of the nth power transistor QSRn.

[0029] More specifically, in this embodiment of the invention, the first power transistor QSR1, the second power transistor QSR2, the third power transistor QSR3, and so on up to the nth power transistor QSRn are all N-channel MOSFETs. The N-channel MOSFET operates in the third quadrant during the freewheeling phase, with current flowing from the source to the drain.

[0030] Through the above design, when multiple co-packaged chips are connected in series, when the power transistor inside any chip changes from normal channel conduction to abnormal body diode conduction, the total on-state voltage drop change of the series branch is amplified, so that the originally weak voltage drop change of a single chip is transformed into a significant voltage step that can be identified by the optocoupler detection circuit, thereby solving the technical problem of weak signal detection.

[0031] In a preferred embodiment of the present invention, the main circuit 1 further includes: an open-loop controller BC, which is connected to the gate of the main switch QM and is used to drive the main switch QM at a fixed frequency and a fixed duty cycle; an energy storage inductor L0, the first end of which is connected to the switching node SW, and the second end of which outputs a DC output voltage Vo; an output capacitor C0, the first end of which is connected to the second end of the energy storage inductor L0, and the second end of which is grounded; and a load resistor R0, the first end of which is connected to the second end of the energy storage inductor L0, and the second end of which is grounded.

[0032] Specifically, in the embodiments of the present invention, reference is made to... Figure 1 The output of the open-loop controller BC is connected to the gate of the main switch QM. The open-loop controller BC outputs rectangular pulses at a fixed frequency f and a fixed duty cycle D, thereby periodically turning the main switch QM on and off. This keeps the freewheeling phase duration of the switching node SW constant in each switching cycle, thus providing a stable on-state voltage drop sampling window for the series synchronous rectifier chip in the freewheeling unit 11. This avoids fluctuations in the detection voltage Vc caused by changes in the duty cycle and ensures the accuracy of state judgment. When the open-loop controller BC outputs a high level, the main switch QM is turned on, and the DC input source Vdc charges the energy storage inductor L0, raising the voltage of the switching node SW to Vdc. When the open-loop controller BC outputs a low level, the main switch QM is turned off, and the energy storage inductor L0 releases energy through the freewheeling unit 11, pulling the voltage of the switching node SW down to a negative value. The absolute value of this negative value is the sum of the on-state voltage drops of all the series synchronous rectifier chips in the freewheeling unit 11.

[0033] The first end of the energy storage inductor L0 is connected to the switching node SW, and the second end is connected to the first end of the output capacitor C0 and the first end of the load resistor R0 respectively. The energy storage inductor L0 stores energy from the DC input source Vdc during the conduction of the main switch QM, and releases energy to the output end through the freewheeling unit 11 during the turn-off of the main switch QM, thereby smoothing the pulse voltage at the input end into the DC voltage at the output end.

[0034] The first terminal of the output capacitor C0 is connected to the second terminal of the energy storage inductor L0, and the second terminal of the output capacitor C0 is grounded. This is used to filter out the switching frequency ripple component in the DC output voltage Vo and to provide a stable DC voltage to the load resistor R0.

[0035] The load resistor R0 is a power resistor. Its first end is connected to the second end of the energy storage inductor L0, and the second end is grounded. It is used to simulate the load conditions of the actual power system, consume the energy at the output end, and make the main circuit work in continuous or intermittent conduction mode.

[0036] Through the above design, the fixed frequency and fixed duty cycle drive mode of the open-loop controller BC ensures the stability of the freewheeling phase duration and avoids the interference of duty cycle changes on the on-state voltage drop sampling window in the closed-loop control. At the same time, the energy storage inductor L0, the output capacitor C0, and the load resistor R0 together form a standard Buck converter output filter network, providing a stable and repeatable switching node SW negative voltage waveform for the detection circuit, ensuring the consistent ability to distinguish the working state of the series synchronous rectifier packaged chip.

[0037] In a preferred embodiment of the present invention, the on-state voltage drop sampling branch 21 further includes: a first resistor R1, the first end of the first resistor R1 being connected to a first DC power supply V1, the second end of the first resistor R1 being connected to the anode of the light-emitting diode in the optocoupler U_OPTO, and the cathode of the light-emitting diode being connected to the switching node SW.

[0038] Specifically, in the embodiments of the present invention, reference is made to... Figure 2 The on-state voltage drop sampling branch 21 is composed of a first DC power supply V1, a first resistor R1, and a light-emitting diode (LED) inside the optocoupler U_OPTO connected in series. The first DC power supply V1 provides a forward bias voltage, and the first resistor R1 is used to limit the current amplitude flowing through the LED.

[0039] The cathode of the light-emitting diode is directly connected to the switching node SW. During the freewheeling phase of each switching cycle, when the voltage of the switching node SW is negative, the light-emitting diode is forward biased and turns on, generating a pulsed forward current proportional to the absolute value of the negative voltage of SW. When the main switch QM is turned on and the voltage of the SW node is positive, the light-emitting diode is reverse biased and turns off.

[0040] As can be seen, the conduction voltage drop sampling branch 21 converts the small negative voltage signal at the switching node SW into an optical pulse signal at the input of the optocoupler in real time, thereby completing the initial transformation from the weak signal on the high voltage side to the isolated optical signal.

[0041] In a preferred embodiment of the present invention, the state monitoring signal conversion branch 22 further includes: a second resistor R2, the first end of which is connected to a second DC power supply V2, and the second end of which is connected to the collector of the phototransistor in the optocoupler U_OPTO, wherein the emitter of the phototransistor is grounded; a filter capacitor Cs, the first end of which, the collector of the phototransistor, and the second end of the second resistor R2 are all connected to a common node, wherein the second end of which is grounded; and the detection voltage is output from the common node.

[0042] Specifically, in the embodiments of the present invention, reference is made to... Figure 2 The status monitoring signal conversion branch 22 consists of a second DC power supply V2, a second resistor R2, a phototransistor inside the optocoupler U_OPTO, and a filter capacitor Cs. The collector of the phototransistor is pulled up to the second DC power supply V2 through the second resistor R2, and the emitter is directly grounded, forming a common-emitter amplification structure.

[0043] When the light-emitting diode at the input of the optocoupler generates a light pulse, the phototransistor receives the corresponding light signal and generates a collector current. This current flows through the second resistor R2, generating a voltage drop across the second resistor R2.

[0044] The filter capacitor Cs is connected in parallel between the collector of the phototransistor and ground to smooth the pulsed collector voltage to a stable DC level, which is the detection voltage Vc output at the common node.

[0045] Since the current transfer ratio (CTR) of the optocoupler remains linear within the normal operating range, the amplitude of the detection voltage Vc is proportional to the average pulse current of the input-side LED, thus indirectly reflecting the negative voltage amplitude of the switching node SW during the freewheeling phase.

[0046] As can be seen, through the aforementioned state monitoring signal transformation branch 22, the pulsed optical signal at the input of the optocoupler is recovered and converted into a smooth DC detection voltage Vc. The filtering effect of the filter capacitor Cs is used to eliminate high-frequency switching ripple, so that the detection voltage Vc can be directly read by the analog-to-digital converter or comparator, thereby realizing the isolation transformation from a weak negative voltage signal to a stable DC level.

[0047] Specifically, through the combined action of the aforementioned on-state voltage drop sampling branch 21 and the state monitoring signal conversion branch 22, a strict linear relationship is achieved between the detection voltage Vc and the on-state voltage drop at the switching node SW. Specifically: when all the synchronous rectifier-encapsulated chips connected in series in the freewheeling unit 11 are operating normally and in the channel-on state, the absolute value of the negative voltage at the SW node is at its minimum, and the corresponding Vc output is at its maximum; when one chip malfunctions (i.e., 1 pcs NG, the internal MOSFET cannot conduct through the channel, only the body diode conducts), the absolute value of the negative voltage at the SW node increases by a fixed step, and Vc decreases by a fixed step accordingly; when two chips malfunction (2 pcs NG), the absolute value of the negative voltage at the SW node increases by another step, and Vc decreases by the same step again; when three chips malfunction (3 pcs NG), Vc continues to decrease by the same step.

[0048] like Figure 5 As shown, taking n=3 as an example, Vc decreases linearly with the increase of the absolute value of the negative pressure SW, showing a good proportional relationship; as Figure 6 As shown, by pre-calibrating the Vc threshold range corresponding to different numbers of abnormal chips (corresponding to the Vc judgment range of 1pcs NG, 2pcs NG, and 3pcs NG respectively), the specific number of abnormal chips in the freewheeling unit 11 can be accurately determined by looking up the table based on the measured Vc voltage value during actual testing, thereby realizing the quantitative judgment of the working status of multiple serially packaged chips.

[0049] Reference Figure 3 and Figure 4 The present invention also provides a method for detecting the working state of a synchronous rectification and encapsulation chip, applied to a synchronous rectification and encapsulation chip working state circuit as described above, comprising: step S1, powering on the detection circuit and detecting the DC output voltage Vo after waiting for a first preset delay; step S2, after the output voltage reaches a stable state, calculating and setting multiple threshold voltages, each threshold voltage corresponding to a number of abnormal chips, to form a synchronous rectification and encapsulation chip abnormal state threshold table; step S3, acquiring the detected voltage and comparing and analyzing the detected voltage with each threshold voltage in the synchronous rectification and encapsulation chip abnormal state threshold table in sequence to obtain the number of abnormal chips; step S4, recording and outputting the judgment result, the judgment result including abnormal alarm information and the number of abnormal chips.

[0050] Specifically, in order to achieve online and quantitative identification of the operating status of a packaged chip when it has no external gate pin and the on-state voltage drop is weak, in this embodiment of the invention, multiple synchronous rectified packaged chips are connected in series to form a freewheeling unit 11. The negative voltage signal of the sampling switch node SW is sampled by optocoupler isolation and linearly converted into a DC detection voltage Vc. Then, Vc is compared in stages by combining it with a pre-set abnormal state threshold table. This transforms the change of the MOSFET inside the chip from normal channel conduction to abnormal body diode conduction into a quantifiable voltage range difference, thereby achieving accurate identification of the number of abnormal chips and solving the problem that traditional solutions cannot directly monitor the internal state of packaged chips.

[0051] More specifically, in this embodiment of the invention, the first preset delay is preferably set to 500ms. This delay is used to wait for the DC input source Vdc to complete the power-on process and for each energy storage element of the main circuit 1 to enter the initial steady state, so as to avoid misjudgment caused by threshold comparison during the period when the DC output voltage Vo has not been established or fluctuates.

[0052] In a preferred embodiment of the present invention, the calculation formula for the threshold voltage in step S2 is as follows: Vth(n)=Vdd2-(CTR*Rup2 / Rup1)*[Vdd1-Vfled+n*Vsdth], n≥1, Where Vth(n) is the nth threshold voltage; Vdd2 is the second DC power supply voltage; CTR is the ratio of the optocoupler output current to the optocoupler input current; Rup2 is the second resistance value; Rup1 is the first resistance value; Vdd1 is the first DC power supply voltage; Vfled=1 is the forward voltage drop of the light-emitting diode in the optocoupler device U_OPTO; Vsdth=0.5 is the judgment threshold used to distinguish the conduction state of the power transistor; n is a positive integer.

[0053] Specifically, in this embodiment of the invention, the forward voltage drop Vfled of the light-emitting diode in the optocoupler U_OPTO is set to a typical value of 1V, and the judgment step size Vsdth is set to 0.5V. The threshold voltages from the 1st to the nth are calculated using the formula Vth(n)=Vdd2-(CTR*Rup2 / Rup1)*[Vdd1-1+n*0.5].

[0054] The formula embeds the number of abnormal chips n as a linear factor within square brackets. When n increases by 1, the value within the square brackets increases by 0.5, thus causing Vth(n) to decrease in step size.

[0055] Since the negative voltage increment of the switching node SW caused by each abnormal chip in the actual circuit corresponds exactly to the fixed decrease of the detection voltage Vc after the optocoupler linear transformation, these equally spaced threshold voltages can clearly separate the state intervals of completely normal, 1 abnormal, 2 abnormal, ..., n abnormal.

[0056] After calculating the threshold using this formula, the specific number of abnormal chips can be uniquely determined by simply comparing the actual measured Vc with these thresholds. This avoids misjudgment or missed judgment caused by uneven threshold intervals, and provides a reliable and repeatable quantitative criterion for mass production testing, reliability aging screening, and system-level fault location.

[0057] In a preferred embodiment of the present invention, the calculation formula for the detection voltage in step S3 is as follows: Vc=Vdd2-IC*Rup2=Vdd2-(CTR*IF)*Rup2=Vdd2-[CTR*(Vdd1-Vfled-VSW) / Rup1]*Rup2, Where Vc is the detection voltage; IC is the collector current of the phototransistor in the optocoupler U_OPTO; IF is the forward current of the light-emitting diode in the optocoupler U_OPTO; Vfled is the forward voltage drop of the light-emitting diode in the optocoupler U_OPTO; and VSW is the forward voltage drop at the switching node SW.

[0058] Specifically, in order to convert the conduction state change of the synchronous rectification and encapsulation chip in the series freewheeling unit 11 into a measurable DC level change, in this embodiment of the invention, the above formula is derived using the linear current transfer characteristics of the optocoupler U_OPTO and Ohm's law.

[0059] Specifically, when the switching node SW is under negative voltage during the freewheeling phase, the LED in the on-state voltage drop sampling branch 21 is forward biased, generating a forward current: IF = (Vdd1 - Vfled - VSW) / Rup1 Since VSW is negative, the forward current IF increases as |VSW| increases.

[0060] The forward current IF is linearly mapped to the output side through the optocoupler's current transfer ratio CTR, forming the collector current of the phototransistor: IC = CTR × IF.

[0061] In the state monitoring signal conversion branch 22, IC flows through the pull-up resistor Rup2, and according to Ohm's law, a voltage drop IC×Rup2 is generated. Therefore, the output detection voltage Vc = Vdd2 - IC×Rup2.

[0062] Substituting the expressions for IC and IF step by step, we obtain the final formula. This formula shows that there is a strict linear relationship between Vc and VSW, and because VSW is negative, Vc decreases linearly as |VSW| increases.

[0063] This quantitative relationship allows the increase in on-state voltage drop caused by the addition of a faulty chip in a series of chips to be linearly mapped to a fixed step decrease in Vc, thus providing a precise mathematical basis for subsequent threshold comparisons.

[0064] As a preferred embodiment of the present invention, refer to Figure 4 In step S3, the detected voltage is compared and analyzed sequentially with each threshold voltage in the abnormal state threshold table of the synchronous rectification and encapsulation chip. The specific analysis steps are as follows: Step S31, determine whether the detected voltage is less than the first threshold voltage, expressed by the formula: Vc < Vth(m), m=1; if yes, proceed to step S32; if no, the working state of all synchronous rectification and encapsulation chips is normal, and the abnormal chip quantity value m=0 is initialized; Step S32, increase the abnormal chip quantity value m by 1, and determine whether the detected voltage is greater than the (m+1)th threshold voltage and less than the mth threshold voltage, expressed by the formula: Vth(m+1) < Vc < Vth(m); if no, repeat step S32; if yes, determine that the abnormal chip quantity value is m, and stop the judgment.

[0065] Specifically, in order to automatically and accurately identify the number of abnormal chips in the series freewheeling unit without an external gate signal and only by detecting the DC level of the voltage Vc, this embodiment of the invention employs a step-by-step threshold comparison algorithm. This algorithm utilizes the monotonically decreasing stepwise relationship between the detection voltage Vc and the number of abnormal chips (the detection voltage Vc decreases by a fixed step for each additional abnormal chip). By comparing the measured detection voltage Vc with a preset threshold voltage sequence Vth(1), Vth(2), ..., Vth(n), the algorithm achieves a unique determination of the number of abnormal chips.

[0066] Specifically, the measured detection voltage Vc is first compared with the first threshold voltage Vth(1). Vth(1) corresponds to the upper limit of Vc when there is exactly one abnormal chip. If Vc is not lower than Vth(1), it means that the measured Vc value is within the Vc range of the completely normal region. Therefore, it is determined that all the series-connected synchronous rectification and encapsulation chips are working normally, the abnormal chip count m is initialized to 0, and the algorithm terminates.

[0067] Secondly, if the detected voltage Vc is less than Vth(1), it indicates that at least one abnormal chip exists. At this point, step S32 is entered, using a progressive comparison method. The number of abnormal chips m is incremented sequentially from 1. Each increment determines whether the current detected voltage Vc satisfies the condition of being "greater than the (m+1)th threshold voltage and less than the mth threshold voltage". This condition utilizes the interval characteristic of the threshold voltage sequence—Vth(m) is the upper limit of Vc when there are exactly m abnormal chips, and Vth(m+1) is the upper limit of Vc when there are exactly m+1 abnormal chips. The interval between the two uniquely corresponds to the number of abnormal chips m. When Vc falls within this interval, it can be determined that the number of abnormal chips equals the current value of m, and the judgment immediately stops.

[0068] Next, if the current m does not meet the interval condition, m is incremented by 1 and the comparison is repeated until m reaches the total number of series chips n. Since the detection voltage Vc decreases monotonically with the increase of abnormal chips, this progressive comparison process will inevitably make the condition true at some point m, thus completing the accurate location of the number of abnormalities.

[0069] Finally, after determining the number of abnormal chips, m, the warning information and the number of abnormalities are recorded and output.

[0070] With the above design, it is not necessary to test each chip individually. By using only one detection voltage Vc and a set of pre-calculated threshold voltages, the batch status identification of multiple synchronous rectified and packaged chips in series can be achieved. It can also quantitatively indicate how many chips have failed, providing clear digital criteria for yield analysis in production testing, degradation tracking in reliability aging, and redundancy protection in power supply systems.

[0071] As can be seen, the above detection circuit and detection method form a freewheeling unit 11 by connecting multiple synchronous rectified and packaged chips in series, and use the negative voltage signal of the optically isolated sampling switch node SW to linearly convert the weak on-state voltage drop change into a DC detection voltage Vc. Then, the number of abnormal chips is quantitatively determined by a preset equally spaced threshold sequence.

[0072] like Figures 7 to 9 Using three synchronous rectifier-encapsulated chips U1~U3 connected in series as an example, the waveform diagram illustrates the operation and function of the synchronous rectifier-encapsulated chip operating status monitoring circuit. Specifically: Figure 7 The diagram shows the changes from completely normal operation of U1 to U3, with only one component malfunctioning. The dashed line represents the case where U1 to U3 are all functioning normally, while the solid line represents the case where only one component of U1 to U3 malfunctions. As shown in the diagram, when only one component malfunctions, the DC voltage amplitude of Vc drops from 4.5V to 4.1V, and the Vc signal drops by 0.4V.

[0073] Figure 8The diagram shows the changes in voltage levels from only one U1 to only two U3 chips becoming abnormal. The dashed line represents the case where only one U1 to U3 chip is abnormal, and the solid line represents the case where both U1 to U3 chips are abnormal. As can be seen from the diagram, when the second chip becomes abnormal, the DC voltage amplitude of Vc drops from 4.1V to 3.7V, and the Vc signal drops by 0.4V.

[0074] Figure 9 The diagram shows the changes from only two faulty chips (U1-U3) to all three faulty chips. The dashed line represents the case where only two of U1-U3 are faulty, and the solid line represents the case where all three of U1-U3 are faulty. As can be seen from the diagram, when the third chip is faulty, the DC voltage amplitude of Vc drops from 3.7V to 3.3V, and the Vc signal drops by 0.4V.

[0075] The waveforms above verify that the detection voltage Vc decreases in equal steps with each additional abnormal chip, proving that the detection circuit can accurately map the conduction state changes of the series-connected chips into a step change of DC level, thus providing a reliable basis for the quantitative determination of the number of abnormalities.

[0076] In summary, this invention provides a synchronous rectification packaged chip operating status detection circuit and method. By connecting multiple synchronous rectification packaged chips in series to form a freewheeling unit 11, the freewheeling negative voltage signal at the sampling switch node SW using optocoupler isolation is used to linearly convert the weak on-state voltage drop change into a DC detection voltage Vc. Based on a preset equally spaced threshold sequence, Vc is compared in stages to quantitatively determine the specific number of abnormal chips in the series unit. This achieves non-invasive, high-reliability monitoring of the operating status of the MOSFET inside the packaged chip in production testing (FT), reliability verification (HTOL), and power system redundancy protection.

[0077] Compared with the prior art, the present invention has the following significant advantages: No external gate pin required: Direct sampling using negative voltage at the SW node avoids the detection blind zone where the gate signal inside the encapsulated chip is not brought out, making it suitable for various synchronous rectification encapsulated devices without a gate pin.

[0078] Weak signals can be detected: By accumulating the on-state voltage drop through multiple chips in series and combining it with optocoupler linear isolation conversion, the difference between the normal on-state voltage drop of only about 0.1V and the abnormal body diode voltage drop of 0.7V (about 0.6V) of each chip is mapped to a fixed step decrease of Vc (about 0.4V), which effectively solves the problem of weak signals being overwhelmed by high voltage interference.

[0079] Quantitative discrimination capability: By using an equally spaced threshold sequence and a progressive comparison algorithm, it can accurately identify the specific number of abnormal chips (such as 1, 2, ..., n abnormal chips), rather than just qualitatively judging whether they are good or bad, providing a quantitative basis for yield analysis, degradation tracking and system-level fault location.

[0080] Highly compatible and easy to integrate: The circuit structure is simple, requiring only one optocoupler, a small number of resistors and capacitors, and a DC power supply to achieve batch status monitoring of multiple chips. The detection signal Vc is at a DC level and can be directly connected to an ADC or comparator, facilitating rapid deployment in FT machines, aging test boards, and power system control circuits.

[0081] Improved system reliability: By monitoring the working status of the series freewheeling unit in real time, alarms can be triggered or redundant protection actions can be activated in time when the chip is abnormal, avoiding overheating or efficiency reduction of the whole machine due to synchronous rectification failure, thus significantly enhancing the long-term reliability of power supply products.

[0082] The above description is merely a preferred embodiment of the present invention and does not limit the implementation and protection scope of the present invention. Those skilled in the art should realize that any equivalent substitutions and obvious changes made based on the description and illustrations of the present invention should be included within the protection scope of the present invention.

Claims

1. A synchronous rectification and encapsulation chip operating status detection circuit, characterized in that, The detection circuit includes: a main circuit (1), which includes a main switch (QM) and a freewheeling unit (11), wherein the freewheeling unit (11) contains multiple series-connected synchronous rectification and encapsulation chips, wherein: the drain of the main switch (QM) is connected to a DC voltage source (Vdc), the tail end of the freewheeling unit (11) is connected to the source of the main switch (QM) at the same switching node (SW), and the head end of the freewheeling unit (11) is grounded; a state monitoring circuit (2), which includes a conduction voltage drop sampling branch (21) and a state monitoring signal conversion branch (22), wherein: the conduction voltage drop sampling branch (21) is connected to a DC voltage source (Vdc), wherein: the tail end of the freewheeling unit (11) is connected to the source of the main switch (QM) at the same switching node (SW), and the head end of the freewheeling unit (11) is grounded; and a state monitoring circuit (2), which includes a conduction voltage drop sampling branch (21) and a state monitoring signal conversion branch (22), wherein: the conduction voltage drop sampling branch (21) is connected to a DC voltage source (Vdc ... The downsampling branch (21) and the state monitoring signal conversion branch (22) share the same optocoupler (U_OPTO). The input terminal of the optocoupler (U_OPTO) constitutes the output terminal of the on-state voltage drop sampling branch (21), and the output terminal of the optocoupler (U_OPTO) constitutes the input terminal of the state monitoring signal conversion branch (22). The input terminal of the on-state voltage drop sampling branch (21) is connected to the switch node (SW), and the output terminal of the state monitoring signal conversion branch (22) outputs a detection voltage. The detection voltage is used to characterize the working state of the synchronous rectification and encapsulation chip in the freewheeling unit (11).

2. The synchronous rectification and encapsulation chip operating status detection circuit according to claim 1, characterized in that, The synchronous rectification packaged chip includes a synchronous rectification controller and a power transistor. The synchronous rectification controller is connected to the gate of the power transistor and is used to drive the power transistor to conduct in the third quadrant.

3. The synchronous rectification and encapsulation chip operating status detection circuit according to claim 1, characterized in that, The main circuit (1) further includes: an open-loop controller (BC), which is connected to the gate of the main switch (QM) and is used to drive the main switch (QM) at a fixed frequency and a fixed duty cycle; an energy storage inductor (L0), the first end of which is connected to the switching node (SW), and the second end of which outputs a DC output voltage; an output capacitor (C0), the first end of which is connected to the second end of the energy storage inductor (L0), and the second end of which is grounded; and a load resistor (R0), the first end of which is connected to the second end of the energy storage inductor (L0), and the second end of which is grounded.

4. The synchronous rectification and encapsulation chip operating status detection circuit according to claim 1, characterized in that, The on-state voltage drop sampling branch (21) further includes: a first resistor (R1), the first end of the first resistor (R1) is connected to a first DC power supply (V1), the second end of the first resistor (R1) is connected to the anode of the light-emitting diode in the optocoupler (U_OPTO), and the cathode of the light-emitting diode is connected to the switching node (SW).

5. The synchronous rectification and encapsulation chip operating status detection circuit according to claim 1, characterized in that, The state monitoring signal conversion branch (22) further includes: a second resistor (R2), the first end of which is connected to a second DC power supply (V2), the second end of which is connected to the collector of the phototransistor in the optocoupler (U_OPTO), and the emitter of the phototransistor is grounded; a filter capacitor (Cs), the first end of which, the collector of the phototransistor, and the second end of which are connected to a common node, and the second end of which is grounded; and the detection voltage is output from the common node.

6. A method for detecting the operating status of a synchronous rectified packaged chip, characterized in that, The detection method for a synchronous rectification and encapsulation chip operating status detection circuit as described in any one of claims 1-5 includes: step S1, powering on the detection circuit and detecting the DC output voltage after waiting for a first preset delay; step S2, after the output voltage reaches a stable state, calculating and setting multiple threshold voltages, each threshold voltage corresponding to a number of abnormal chips, to form a synchronous rectification and encapsulation chip abnormal state threshold table; step S3, acquiring the detected voltage and comparing it sequentially with each threshold voltage in the synchronous rectification and encapsulation chip abnormal state threshold table to obtain the number of abnormal chips; step S4, recording and outputting the judgment result, the judgment result including abnormal alarm information and the number of abnormal chips.

7. The method for detecting the working status of a synchronous rectified packaged chip according to claim 6, characterized in that, In step S2, the formula for calculating the threshold voltage is: Vth(n)=Vdd2−(CTR*Rup2 / Rup1)*[Vdd1−Vfled+n*Vsdth], n≥1， Where Vth(n) is the nth threshold voltage; Vdd2 is the second DC power supply voltage; CTR is the ratio of the optocoupler output current to the optocoupler input current; Rup2 is the second resistance value; Rup1 is the first resistance value; Vdd1 is the first DC power supply voltage; Vfled=1 is the forward conduction voltage drop of the light-emitting diode in the optocoupler device (U_OPTO); Vsdth=0.5 is the judgment threshold used to distinguish the conduction state of the power transistor; n is a positive integer.

8. The method for detecting the working status of a synchronous rectified packaged chip according to claim 7, characterized in that, In step S3, the formula for calculating the detection voltage is: Vc=Vdd2-IC*Rup2=Vdd2-(CTR*IF)*Rup2=Vdd2-[CTR*(Vdd1-Vfled-VSW) / Rup1]*Rup2, Where Vc is the detection voltage; IC is the collector current of the phototransistor in the optocoupler (U_OPTO); IF is the forward current of the light-emitting diode in the optocoupler (U_OPTO); Vfled is the forward voltage drop of the light-emitting diode in the optocoupler (U_OPTO); and VSW is the forward voltage drop at the switching node (SW).

9. A method for detecting the working status of a synchronous rectified packaged chip according to claim 7, characterized in that, In step S3, the detected voltage is compared and analyzed sequentially with each threshold voltage in the abnormal state threshold table of the synchronous rectification and encapsulation chip. The specific analysis steps are as follows: Step S31, determine whether the detected voltage is less than the first threshold voltage, expressed by the formula: Vc < Vth(m), m=1; if yes, proceed to step S32; if no, the working state of all synchronous rectification and encapsulation chips is normal, and the abnormal chip quantity value m=0 is initialized; Step S32, increase the abnormal chip quantity value m by 1, and determine whether the detected voltage is greater than the (m+1)th threshold voltage and less than the mth threshold voltage, expressed by the formula: Vth(m+1) < Vc < Vth(m); if no, repeat step S32; if yes, determine that the abnormal chip quantity value is m, and stop the judgment.

10. The method for detecting the working state of a synchronous rectified packaged chip according to claim 6, characterized in that, The first preset delay is 500ms.

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