Data processing apparatus, data processing method and device

Abstract

This application discloses a data processing apparatus, data processing method, and device, belonging to the field of computer technology. The data processing apparatus includes a processor, low-bandwidth memory, and a storage device. The processor includes a processing unit for data processing and high-bandwidth memory. During the response to a data processing request, the processing unit, in conjunction with the high-bandwidth memory and low-bandwidth memory, flexibly selects the target memory to load data based on the distribution of the data indicated by the data processing request in the low-bandwidth memory or storage device, and the access and transmission bandwidth of the high-bandwidth and low-bandwidth memory. This achieves reasonable allocation and efficient utilization of memory resources, avoiding slow data reading speeds due to over-reliance on low-bandwidth memory, minimizing the time required for the processing unit to acquire the data to be processed, ensuring data transmission efficiency, and thus ensuring efficient response to data processing requests.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data processing apparatus, data processing method and device. Background Technology

[0002] Computer devices typically include a processor, memory, and storage. Memory stores large amounts of data, while the processor, in response to a data processing request, instructs the memory to load the data to be processed corresponding to the data processing request from the storage into memory so that the processor can read the data to be processed from memory and process it. However, current data transmission methods are inefficient. Summary of the Invention

[0003] This application provides a data processing apparatus, data processing method, and device that can improve data transmission efficiency. The technical solution is as follows:

[0004] On one hand, a data processing device is provided, the data processing device including a processor, a first memory and a memory, the processor including a second memory and a processing unit, the processing unit being connected to the first memory and the second memory respectively, the first memory being connected to the second memory, the first memory and the second memory being connected to the memory respectively, and the access bandwidth of the first memory being less than the access bandwidth of the second memory;

[0005] The processing unit is configured to receive a data processing request and determine the distribution information of the data indicated by the data processing request, wherein the distribution information indicates the distribution of the data in the first memory or the memory.

[0006] The processing unit is further configured to determine the target memory from the first memory and the second memory based on the distribution information, the access bandwidth of the first memory, the access bandwidth of the second memory, and the transmission bandwidth between the first memory and the second memory;

[0007] The processing unit is also configured to control the target memory to load the data, read the data from the target memory, and process the data.

[0008] On the other hand, a data processing method is provided, which is executed by the data processing apparatus shown in the above aspect. The data processing apparatus includes a processor, a first memory, and a memory. The processor includes a second memory and a processing unit. The processing unit is connected to both the first memory and the second memory. The first memory and the second memory are connected to each other. The first memory and the second memory are both connected to the memory. The access bandwidth of the first memory is less than the access bandwidth of the second memory. The method includes:

[0009] The processing unit receives a data processing request and determines the distribution information of the data indicated by the data processing request, wherein the distribution information indicates the distribution of the data in the first memory or the memory.

[0010] The processing unit determines the target memory from the first memory and the second memory based on the distribution information, the access bandwidth of the first memory, the access bandwidth of the second memory, and the transmission bandwidth between the first memory and the second memory.

[0011] The processing unit controls the target memory to load the data, reads the data from the target memory, and processes the data.

[0012] On the other hand, a computer device is provided, which includes the data processing apparatus described in the above aspects.

[0013] In the solution provided in this application embodiment, the data processing device includes a processor, low-bandwidth memory, and a memory. The processor includes a processing unit for data processing and high-bandwidth memory. During the process of responding to a data processing request, the processing unit combines the high-bandwidth memory and the low-bandwidth memory, and flexibly selects the target memory to load data based on the distribution of the data indicated by the data processing request in the low-bandwidth memory or the memory, the access bandwidth of the high-bandwidth memory, the access bandwidth of the low-bandwidth memory, and the transmission bandwidth between the high-bandwidth memory and the low-bandwidth memory. This achieves reasonable allocation and efficient utilization of memory resources, avoids the situation where data is concentrated in the high-bandwidth memory, resulting in wasted low-bandwidth memory space, and also avoids the situation where the data reading speed is too slow due to over-reliance on low-bandwidth memory. It minimizes the time required for the processing unit to obtain the data to be processed, ensures the data transmission efficiency during the process of the processing unit responding to the data processing request, and thus ensures the response efficiency to the data processing request. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application;

[0016] Figure 2 This is a schematic diagram of data transmission in a data processing device provided in an embodiment of this application;

[0017] Figure 3 This is a schematic diagram of data transmission in another data processing device provided in an embodiment of this application;

[0018] Figure 4 This is a schematic diagram of data transmission in another data processing device provided in an embodiment of this application;

[0019] Figure 5 This is a schematic diagram of another data processing device provided in an embodiment of this application;

[0020] Figure 6 This is a schematic diagram of another data processing device provided in an embodiment of this application;

[0021] Figure 7 This is a schematic diagram illustrating the interaction between a terminal and a server, provided in an embodiment of this application.

[0022] Figure 8 This is a schematic diagram of the structure of a terminal provided in an embodiment of this application;

[0023] Figure 9 This is a schematic diagram of the structure of a server provided in an embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0025] The terms “first,” “second,” “third,” “fourth,” “fifth,” etc., used in this application may be used to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are used only to distinguish one concept from another. For example, without departing from the scope of this application, first data may be referred to as second data, and similarly, second data may be referred to as first data.

[0026] As used in this application, the terms "at least one," "multiple," "each," and "any" mean that at least one includes one, two, or more; multiple includes two or more; each refers to each of the corresponding multiple; and any means refers to any one of the multiple. For example, multiple data processing requests include three data processing requests, where each refers to each of the three data processing requests, and any means refers to any one of the three data processing requests, which could be the first data processing request, the second data processing request, or the third data processing request.

[0027] It should be noted that all information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application have been authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the data processing requests and data involved in this application were obtained with full authorization.

[0028] Figure 1 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application, as shown below. Figure 1 As shown, the data processing device includes a processor 101, a first memory 102, and a memory 103. The processor 101 includes a second memory 111 and a processing unit 112. The processing unit 112 is connected to the first memory 102 and the second memory 111 respectively. The first memory 102 is connected to the second memory 111. The first memory 102 and the second memory 111 are connected to the memory 103 respectively. The access bandwidth of the first memory 102 is less than the access bandwidth of the second memory 111.

[0029] The memory 103 is a device for long-term data storage, such as a hard disk drive (HDD), solid-state drive (SSD), or magnetic disk. The first memory 102 is a device for temporary data storage, such as DRAM (Dynamic Random Access Memory). DRAM interface standards have undergone multiple generations of development, improving data transfer speed, reducing power consumption, and increasing bandwidth. The processing unit 112 in the processor 101 (CPU) is used for data processing. The second memory 111 in the processor 101 is also a device for temporary data storage. The second memory 111 is a high-bandwidth memory, such as HBM (High Bandwidth Memory). HBM is a high-performance DRAM based on 3D stacking technology, suitable for applications with high bandwidth requirements, such as high-performance computing, graphics processing, and artificial intelligence. The access bandwidth of the first memory 102 refers to the amount of data that the processing unit 112 can read from the first memory 102 per unit time, or the amount of data that the processing unit 112 can store in the first memory 102 per unit time; the access bandwidth of the second memory 111 refers to the amount of data that the processing unit 112 can read from the second memory 111 per unit time, or the amount of data that the processing unit 112 can store in the second memory 111 per unit time. The connection between the processing unit 112, the second memory 111, the first memory 102, and the memory 103 can be implemented in any way. For example, the processing unit 112, the second memory 111, the first memory 102, and the memory 103 can all be connected electrically or wirelessly.

[0030] In this embodiment of the application, the processor 101 in the data processing device includes not only a processing unit 112 for performing data processing, but also high-bandwidth memory (i.e., second memory 111) and low-bandwidth memory (i.e., first memory 102). During the process of responding to a data processing request, the processing unit 112 can load the data indicated by the data processing request into the high-bandwidth memory or the low-bandwidth memory so that the processing unit 112 can read the data from it for processing.

[0031] The data processing device will now be described based on the above-mentioned components.

[0032] (1) Processing unit 112: used to receive data processing requests and determine the distribution information of the data indicated by the data processing request, the distribution information indicating the distribution of data in the first memory 102 or memory 103.

[0033] In this embodiment of the application, the processing unit 112 can receive a data processing request. The data processing request is used to indicate the processing of the indicated data. Considering that the data indicated by the data processing request may exist in the first memory 102 or the memory 103, the distribution of the data to be processed indicated by the data processing request can be determined based on the data processing request, so as to ensure that the subsequent processing unit 112 can obtain the data indicated by the data processing request.

[0034] In this context, a data processing request indicates the processing of indicated data. For example, a data processing request might indicate the computation of indicated data. For instance, if the indicated data is Table 1 and Table 2, the request might indicate a join operation on Table 1 and Table 2. A join operation is a fundamental operation in relational databases, used to combine data from two or more tables based on certain conditions for querying and analysis. Different join operations include inner joins, outer joins, and cross joins. Alternatively, a data processing request might indicate the computation of indicated data based on a specified algorithm. This algorithm can be of any type, such as a join algorithm, which could include nested loop joins, hash joins, or sort-merge joins.

[0035] The distribution information can reflect whether the data to be processed (the data indicated by the data processing request) is stored in the first memory 102 or the memory 103; or, it can reflect which part of the data to be processed is stored in the first memory 102 and which part is stored in the memory 103. Optionally, the distribution information can reflect the total amount of data to be processed and the amount of data to be processed stored in the first memory 102 or the memory 103.

[0036] (2) Processing unit 112: is also used to determine the target memory from the first memory 102 and the second memory 111 based on distribution information, the access bandwidth of the first memory 102, the access bandwidth of the second memory 111 and the transmission bandwidth between the first memory 102 and the second memory 111.

[0037] In the implementation of this application, if the processing unit 112 wants to obtain the data indicated by the data processing request, it needs to load the data into the first memory 102 or the second memory 111 so that the processing unit 112 can read the data from the first memory 102 or the second memory 111 and then process the read data. Since the distribution information can reflect the distribution of data in the first memory 102 or the memory 103, the access bandwidth of the first memory 102 and the access bandwidth of the second memory 111 can reflect the time required for the processor 101 to read the same amount of data from the first memory 102 or the second memory 111 respectively, and the transmission bandwidth can reflect the time required to move the data located in the first memory 102 to the second memory 111 in the data processing request indication, therefore, based on the distribution information, the access bandwidth of the first memory 102, the access bandwidth of the second memory 111 and the transmission bandwidth between the first memory 102 and the second memory 111, the target memory is determined from the first memory 102 and the second memory 111 to ensure that the data to be processed can be loaded from the target memory so that the processing unit 112 can obtain the data to be processed, and to ensure that the time required for the processing unit 112 to obtain the data to be processed is short enough as much as possible.

[0038] The target memory is at least one of the first memory 102 and the second memory 111. For example, the target memory is the first memory 102; or, it is the second memory 111; or, it is both the first memory 102 and the second memory 111. The transmission bandwidth between the first memory 102 and the second memory 111 refers to the amount of data that can be transmitted between the first memory 102 and the second memory 111 per unit time. The transmission bandwidth from the first memory 102 to the second memory 111 may be the same as or different from the transmission bandwidth from the second memory 111 to the first memory 102. The transmission bandwidth from the first memory 102 to the second memory 111 refers to the amount of data that can be transmitted per unit time when data is transmitted from the first memory 102 to the second memory 111, and the transmission bandwidth from the second memory 111 to the first memory 102 refers to the amount of data that can be transmitted per unit time when data is transmitted from the second memory 111 to the first memory 102.

[0039] (3) Processing unit 112: It is also used to control the loading of data from the target memory, read data from the target memory, and process the data.

[0040] In this embodiment of the application, the processor 101 can control the target memory to load the data indicated by the data processing request, so as to be able to read the data indicated by the data processing request from the target memory, and then process the read data according to the data processing request.

[0041] In the solution provided in this application embodiment, the data processing device includes a processor, low-bandwidth memory, and a memory. The processor includes a processing unit for data processing and high-bandwidth memory. During the process of responding to a data processing request, the processing unit combines the high-bandwidth memory and the low-bandwidth memory, and flexibly selects the target memory to load data based on the distribution of the data indicated by the data processing request in the low-bandwidth memory or the memory, the access bandwidth of the high-bandwidth memory, the access bandwidth of the low-bandwidth memory, and the transmission bandwidth between the high-bandwidth memory and the low-bandwidth memory. This achieves reasonable allocation and efficient utilization of memory resources, avoids the situation where data is concentrated in the high-bandwidth memory, resulting in wasted low-bandwidth memory space, and also avoids the situation where the data reading speed is too slow due to over-reliance on low-bandwidth memory. It minimizes the time required for the processing unit to obtain the data to be processed, ensures the data transmission efficiency during the process of the processing unit responding to the data processing request, and thus ensures the response efficiency to the data processing request.

[0042] In the above Figure 1 Based on the embodiments shown, in this application embodiment, the processing unit 112 can select a target memory from the first memory 102 and the second memory 111 by considering the difference between the time required to obtain data from the first memory 102 and the second memory 111. The data processing device will be described below.

[0043] (1) Processing unit 112: is used to determine a first duration and a second duration based on distribution information, access bandwidth of first memory 102, access bandwidth of second memory 111 and transmission bandwidth between first memory 102 and second memory 111. The first duration is the difference between the time required for processing unit 112 to read a first amount of data from first memory 102 or second memory 111 respectively. The first amount of data is the amount of data corresponding to the data indicated by the data processing request. The second duration is the time required for the data located in first memory 102 in the data indicated by the data processing request to be transmitted from first memory 102 to second memory 111.

[0044] In this embodiment, if the data processing request indication data is stored in the first memory 102, the processing unit 112 can read the data processing request indication data from the first memory 102; if the data processing request indication data is stored in the second memory 111, the processing unit 112 can read the data processing request indication data from the second memory 111. To ensure that the processing unit 112 can obtain the data processing request indication data as quickly as possible, the time required to obtain the data processing request indication data from different memory locations needs to be considered. Since the access bandwidth of the first memory 102 is less than the access bandwidth of the second memory 111, the processing unit 112 requires less time to read the same amount of data from the second memory 111 compared to the first memory 102. This first time reflects the data transmission time saved by reading the data processing request indication data from the second memory 111. Considering that at least some of the data indicated by the data processing request may be stored in the first memory 102, if the data indicated by the data processing request is stored in the second memory 111, then during data transmission, the data in the second memory 111 also needs to be transmitted to the second memory 111. Therefore, the second duration is determined in combination with the transmission bandwidth. The second duration can reflect the additional time required to store the data indicated by the data processing request in the second memory 111 compared to storing the data indicated by the data processing request in the first memory 102.

[0045] In one possible implementation, the data processing request comes from other modules or other devices.

[0046] For example, other modules located on the same device as the data processing unit can perform tasks that process data through a network model. When other modules perform this task, data processing is involved, and they will send data processing requests to the processing unit in the processor.

[0047] For example, the data processing device is located in the server, which provides data query services. In response to a query operation for certain data, the terminal sends a data query request to the server. Upon receiving the data query request, since the server does not directly store the data indicated by the data query request, the server generates a data processing request based on the data query request and sends the data processing request to the processor's processing unit. This allows the processor to respond to the data processing request and generate the data indicated by the data query request, so that the server can subsequently provide the queried data to the terminal.

[0048] In one possible implementation, the distribution information includes a first data volume and a second data volume, wherein the second data volume is the data volume corresponding to the data located in the first memory 102 in the data indicated by the data processing request; the processing unit 112 is used to determine a first ratio of the first data volume to the access bandwidth of the first memory 102 and a second ratio of the first data volume to the access bandwidth of the first memory 102; the difference between the first ratio and the second ratio is determined as a first duration; and the ratio of the second data volume to the transmission bandwidth is determined as a second duration.

[0049] In this embodiment, since the access bandwidth of the first memory 102 reflects the amount of data that the processing unit 112 can access per unit time, if the data processing request indication data is stored in the first memory 102, the first ratio reflects the time required for the processing unit 112 to read the data processing request indication data from the first memory 102. Similarly, since the access bandwidth of the second memory 111 reflects the amount of data that the processing unit 112 can access per unit time, if the data processing request indication data is stored in the second memory 111, the second ratio reflects the time required for the processing unit 112 to read the data processing request indication data from the second memory 111.

[0050] In this embodiment, the distribution information includes a first data volume and a second data volume, which can reflect the amount of data distributed in the first memory 102 or the storage 103 according to the data processing request indication. By combining the first data volume, the second data volume, the access bandwidth of the first memory 102, the access bandwidth of the second memory 111, and the transmission bandwidth between the first memory 102 and the second memory 111, the first duration and the second duration can be determined. The determined first duration can accurately reflect the data transmission time saved by reading the data processing request indication from the second memory 111, while the second duration can reflect the additional time required to store the data processing request indication in the second memory 111 compared to storing the data processing request indication in the first memory 102, thus ensuring the accuracy of the first duration and the second duration.

[0051] Optionally, the processing unit 112 is used to read first storage information from the first memory 102 and determine distribution information based on the first storage information and the data identifier carried by the data processing request.

[0052] In this embodiment, the data identifier is used to represent the data indicated by the data processing request. The first storage information can reflect the data storage situation in the first memory 102 and the data storage situation in the memory 103. The processing unit 112 reads the first storage information from the first memory 102, and then, based on the first storage information and the data identifier, can determine the amount of data indicated by the data processing request in the first memory 102 or the memory 103, and thus determine the distribution information.

[0053] The first storage information can be represented in any form. For example, the first storage information includes metadata in the first memory 102 and metadata of the database table. The metadata in the first memory 102 indicates which data is stored in the first memory 102, and the metadata of the database table can indicate the amount of data for each data item, such as rows or columns of the database table, which can reflect the amount of data in the database table.

[0054] Optionally, the data processing device includes a first controller and a controller corresponding to the memory 103. Processing unit 112: Used to send an information read request to the first controller, the information read request being used to request first stored information. First controller: Used to receive the information read request, and based on the information read request, query the first stored information indicated by the information read request from the first memory 102. If the first stored information is not found in the first memory 102, it sends an information read request to the controller corresponding to the memory 103. The controller corresponding to the memory 103: In response to the information read request, reads the first stored information from the memory 103 and sends the first stored information to the first controller. The first controller receives the first stored information, writes the first stored information into the first memory 102, and sends the first stored information to the processing unit 112. Wherein, the first controller is the controller corresponding to the first memory 102.

[0055] Optionally, the first duration and the second duration satisfy the following relationship:

[0056] Benefit = P / DRAM banduidth -P / HBM banduidth

[0057] Cost = a * P / Tranfer bandwidth

[0058] Where Benefit represents the first duration, P represents the first data volume, and DRAM bandwidth Used to represent the access bandwidth of the first memory 102, P / DRAM bandwidth Used to represent the first ratio, HBM bandwidth Used to represent the access bandwidth of the second memory 111, P / HBM bandwidthUsed to represent the second ratio; Cost is used to represent the second duration, a is used to represent the proportion of data located in the first memory 102 in the data indicated by the data processing request, a*P is used to represent the second data volume, Transfer bandwidth This is used to represent the transmission bandwidth between the first memory 102 and the second memory 111, and is also equivalent to the transmission bandwidth from the first memory 102 to the second memory 111.

[0059] (2) Processing unit 112: When the first duration is greater than the second duration, it determines the second memory 111 as the target memory; or, when the first duration is not greater than the second duration, it determines the first memory 102 as the target memory.

[0060] In this embodiment, if the first duration is greater than the second duration, it indicates that the time required to load the data indicated by the data processing request into the second memory 111 and then for the processing unit 112 to read the data indicated by the data processing request from the second memory 111 is shorter. Therefore, the second memory 111 is determined as the target memory. If the first duration is less than the second duration, it indicates that the time required to load the data indicated by the data processing request into the first memory 102 and then for the processing unit 112 to read the data indicated by the data processing request from the first memory 102 is shorter. Therefore, the first memory 102 is determined as the target memory. If the first duration equals the second duration, it means that the time required to load the data indicated by the data processing request into the first memory 102 and then for the processing unit 112 to read the data indicated by the data processing request from the first memory 102 is equal to the time required to load the data indicated by the data processing request into the second memory 111 and then for the processing unit 112 to read the data indicated by the data processing request from the second memory 111. However, considering that loading the data indicated by the data processing request into the first memory 102 would cause unnecessary data transfer, the first memory 102 is determined as the target memory.

[0061] In this embodiment, since the distribution information can reflect the distribution of the data indicated by the data processing request in the first memory 102 or the memory 103, the first duration and the second duration can be determined by combining the access bandwidth of the first memory 102, the access bandwidth of the second memory 111, and the transmission bandwidth between the first memory 102 and the second memory 111. By comparing the first duration and the second duration, the memory involved in the short data transmission process can be determined as the target memory, so as to ensure that the processing unit 112 can obtain the data indicated by the data processing request as soon as possible and ensure data transmission efficiency.

[0062] Based on the embodiments shown above, let P be the amount of data corresponding to the data indicated by the data processing request, where a proportion of the data is located in the first memory 102 and 1-a proportion of the data is located in the memory 103. Regardless of whether the determined target memory is the first memory 102 or the second memory 111, the time required to transfer the 1-a proportion of data from the memory 103 to the target memory is the same, and this time satisfies the following relationship:

[0063] I / O = (1-a)*P / IO bandwidth

[0064] Wherein, I / O represents the time required to transfer a proportion of 1-a in memory 103 to the target memory, P represents the amount of data corresponding to the data indicated by the data processing request, and 1-a represents the proportion of data in memory 103 within the data indicated by the data processing request. bandwidth This is used to represent the access bandwidth of memory 103, which is also equivalent to the amount of data that can be transferred from memory 103 to first memory 102 or second memory 111 per unit time.

[0065] The data processing device provided in this application embodiment can be applied to different scenarios, such as pure memory scenarios, i.e., a=1, in which case no additional I / O overhead is required; it is also applicable to external memory scenarios, i.e., a≠1, and has strong versatility.

[0066] Based on the embodiments shown above, when determining the target memory from the first memory 102 and the second memory 111 in this application embodiment, not only is the time consumed in the data transmission process considered, but also whether the remaining space of the second memory 111 is sufficient. Therefore, the processing unit 112 will also take the following measures to determine the target memory, which will be described below. Processing unit 112: used to determine the second memory 111 as the target memory when the first duration is greater than the second duration and the remaining space of the second memory 111 meets the storage requirements of the data processing request.

[0067] In this embodiment, when the first duration is longer than the second duration, the time required for loading the data indicated by the data processing request into the second memory 111 and for the processing unit 112 to read the data indicated by the data processing request from the second memory 111 is short. However, it also considers whether the remaining space of the second memory 111 can meet the storage requirements of the data processing request. Only when the first duration is longer than the second duration and the remaining space of the second memory 111 meets the storage requirements of the data processing request is the second memory 111 determined as the target memory. This is to take into account both the time required for the processing unit 112 to obtain the data indicated by the data processing request and the storage status of each memory, so as to ensure that the processing unit 112 obtains the data indicated by the data processing request in a short time and that the determined target memory has enough space to meet the storage requirements of the data processing request. This ensures the efficiency of subsequent data transmission while also considering the feasibility of the data transmission scheme.

[0068] The storage requirement for the data processing request refers to the memory space required by the processing unit 112 in responding to the data processing request. The remaining space of the second memory 111 is also equivalent to the free space of the second memory 111. The remaining space of the second memory 111 can be represented in any form, for example, the remaining space of the second memory 111 can be represented in the form of the amount of data that can be stored.

[0069] For example, the remaining space of the second memory 111 may be empty or not empty; when the remaining space of the second memory 111 is empty, it means that there is no remaining space in the second memory 111, that is, the second memory 111 has been filled; when the remaining space of the second memory 111 is not empty, it means that there is remaining space in the second memory 111, that is, the second memory 111 has not been filled; the remaining space of the second memory 111 meeting the storage requirements of data processing requests means that there is remaining space in the second memory 111 and that the remaining space can meet the storage requirements.

[0070] In one possible implementation, the first memory 102 is used to store the second storage information corresponding to the second memory 111; the processing unit 112 is used to read the second storage information from the first memory 102 and determine the remaining space of the second memory 111 based on the second storage information.

[0071] In this embodiment of the application, the first memory 102 stores second storage information corresponding to the second memory 111. The second storage information indicates the data storage situation in the second memory 111 and can reflect what data is stored in the second memory 111 and how much space is left in the second memory 111. Therefore, the processing unit 112 reads the second storage information from the first memory 102 so as to determine the remaining space of the second memory 111 based on the second storage information, so as to ensure the accuracy of the determined remaining space.

[0072] Optionally, the processing unit 112 can update the second storage information in the first memory 102.

[0073] In this embodiment, the storage or deletion of data in the second memory 111 is controlled by the processing unit 112. During the process of controlling the storage or deletion of data in the second memory 111, the processing unit 112 can obtain the data storage status in the second memory 111, so as to update the second storage information in the first memory 102 based on the data storage status of the second memory 111, so that the second storage information can accurately reflect the data storage status in the second memory 111, thereby ensuring the accuracy of the second storage information.

[0074] Optionally, the data processing device includes a first controller, and a processing unit 112 for sending an information update instruction to the first controller; the first controller for updating the second stored information in the first memory 102 based on the information update instruction. The first controller is the controller corresponding to the first memory 102.

[0075] In this embodiment of the application, the memory in the data processing device corresponds to a controller. The controller can be used to manage the reading and writing of data in the corresponding memory. When the processing unit 112 needs to update the second storage information, it will send an information update instruction to the first controller to instruct the first controller to update the second storage information in the first memory 102 based on the information update instruction.

[0076] In one possible implementation, the storage requirements of the data processing request are used to represent the space required for the data indicated by the data processing request and the space required for the data processing method corresponding to the data processing request.

[0077] In this embodiment of the application, during the process of responding to the data processing request, the processing unit 112 not only needs to load the data indicated by the data processing request, but also needs other space to process the data according to the data processing method. Therefore, the target memory needs to have enough space to store the data indicated by the data processing request and enough space to store the data processing method.

[0078] For example, if the data processing method indicates that the data to be processed must be grouped before the grouped data can be stored, then the space corresponding to the data processing method is used to store the grouped data. That is, in the process of responding to the data processing request, the memory not only needs to have enough space to store the data indicated by the data processing request, but also needs to have enough space to store the grouped data.

[0079] For example, if the data processing method indicates that after processing the data to be processed, there is also enough space to store the processing result, then in the process of responding to the data processing request, the memory not only needs enough space to store the data indicated by the data processing request, but also needs enough space to store the processing result.

[0080] Optionally, the processing unit 112 is used to obtain the amount of data corresponding to the data identifier carried in the data processing request from the first memory 102, determine the amount of data required by the algorithm indicated by the data processing request, and determine the storage requirement of the data processing request by summing the amount of data corresponding to the data identifier and the amount of data required by the algorithm.

[0081] In this embodiment, the data volume corresponding to the data identifier is equivalent to the first data volume mentioned above. The process of obtaining the data volume corresponding to the data identifier is the same as the process of obtaining the first data volume, and will not be repeated here. Different algorithms require different amounts of space. Based on the algorithm indicated by the data processing request, the amount of data required by the algorithm can be determined.

[0082] Based on the embodiments shown above, when determining the target memory from the first memory 102 and the second memory 111 in this application embodiment, not only is the time consumed in the data transmission process taken into account, but also whether the remaining space of the second memory 111 is sufficient. Therefore, the processing unit 112 will also determine the target memory in the following manner. Processing unit 112: is further configured to determine the first memory 102 as the target memory when the first duration is greater than the second duration and the remaining space of the second memory 111 does not meet the storage requirements of the data processing request.

[0083] In this embodiment, when the first duration is longer than the second duration, the time required to load the data indicated by the data processing request into the second memory 111 and then for the processing unit 112 to read the data indicated by the data processing request from the second memory 111 is short. However, the remaining space of the second memory 111 does not meet the storage requirements of the data processing request. Thus, even though the time required to load the data indicated by the data processing request into the second memory 111 and then for the processing unit 112 to read the data indicated by the data processing request from the second memory 111 is short, the second memory 111 will not be determined as the target memory because the remaining space of the second memory 111 does not meet the storage requirements of the data processing request. Instead, the first memory 102 will be determined as the target memory to ensure that the determined target memory can meet the storage requirements of the data processing request, so as to ensure that the subsequent processing unit 112 can respond to the data processing request smoothly and ensure the feasibility of the data transmission scheme.

[0084] In this embodiment, memory with high access bandwidth requires high cost, while memory with low access bandwidth requires low cost. From a cost perspective, the storage space of the first memory 102 in the data processing device is greater than the storage space of the second memory 111. Even if the remaining space of the second memory 111 does not meet the storage requirements of the data processing request, the remaining space of the first memory 102 can meet the storage requirements of the data processing request because the storage space of the first memory 102 is large enough. Therefore, the first memory 102 can be directly determined as the target memory.

[0085] It should be noted that the above embodiment determines the first memory 102 as the target memory when the first duration is greater than the second duration and the remaining space of the second memory 111 is insufficient. In another embodiment, under such circumstances, the processing unit 112 can also determine the first memory 102 and the second memory 111 as the target memory to ensure data transmission efficiency as much as possible. The data processing device will be described below.

[0086] (1) Processing unit 112: When the first duration is longer than the second duration and the second memory 111 still has remaining space but does not meet the storage requirements, it determines the first memory 102 and the second memory 111 as the target memory.

[0087] In this embodiment, when the first duration is longer than the second duration, the time required to load the data indicated by the data processing request into the second memory 111 and then for the processing unit 112 to read the data indicated by the data processing request from the second memory 111 is short. However, since the remaining space in the second memory 111 does not meet the storage requirements of the data processing request, the first memory 102 and the second memory 111 are determined as target memory in order to make the most of the remaining space in the second memory 111 and improve the data transmission efficiency as much as possible.

[0088] The statement that there is still remaining space in the second memory 111 means that the second memory 111 is not fully occupied, that is, data can still be added to the second memory 111.

[0089] (2) Processing unit 112: used to control the first memory 102 to load the first data in the data indicated by the data processing request from the memory 103, and to control the second memory 111 to load the second data in the data indicated by the data processing request from the memory 103.

[0090] In this embodiment, a portion of the data indicative of the data processing request is stored in memory 103, while the remainder is stored in first memory 102. When first memory 102 and second memory 111 are designated as target memories, a portion of the data indicative of the data processing request is subsequently stored in first memory 102, and the remainder in second memory 111. The subsequent processing unit 112 can then read data from both first memory 102 and second memory 111 to obtain the data indicative of the data processing request. To minimize unnecessary data transfer, a portion of the original data indicative of the data processing request is still stored in first memory 102. Instead, the first data indicative of the data processing request is loaded from memory 103 into first memory 102, and the second data indicative of the data processing request is loaded from memory 103 into second memory 111, thus distributing the data indicative of the data processing request across either first memory 102 or second memory 111.

[0091] The amount of the second data is equal to the amount of data that can be stored in the remaining space of the second memory 111, and the data located in the memory 103 in the data processing request indication includes the first data and the second data.

[0092] For example, if the data processing request indicates 100 megabytes of data, of which 20 megabytes are stored in the first memory 102 and the remaining 80 megabytes are stored in the memory 103, and the remaining space in the second memory 111 can store 30 megabytes of data, then 30 megabytes of data (equivalent to the second data) from the 80 megabytes in the memory 103 are loaded into the second memory 111, and the remaining 50 megabytes of data (equivalent to the first data) from the 80 megabytes in the memory 103 are loaded into the first memory 102. Thus, the first memory 102 stores 70 megabytes of data from the data processing request, and the second memory 111 stores 30 megabytes of data from the data processing request.

[0093] In one possible implementation, the data processing device includes a first controller and a second controller. The first controller corresponds to the first memory 102, and the second controller corresponds to the second memory 111. Processing unit 112 is used to send a first load instruction to the first controller and a second load instruction to the second controller. The first controller is used to receive the first load instruction and load first data from memory 103 into the first memory 102. The second controller is used to receive the second load instruction and load second data from memory 103 into the second memory 111.

[0094] The first load instruction instructs the first controller to load the first data from the memory 103 into the first memory 102, and the second load instruction instructs the second controller to load the second data from the memory 103 into the second memory 111.

[0095] In this embodiment of the application, the data processing device includes a controller corresponding to the memory. The controller can be used to manage the reading and writing of data in the corresponding memory. Therefore, the processing unit 112 sends a first loading instruction to the first controller and a second loading instruction to the second controller, so that the first controller and the second controller can read the corresponding data from the memory 103 and write it into the corresponding memory, so that all the data indicated by the data processing request is stored in the first memory 102 or the second memory 111.

[0096] (3) Processing unit 112: It is also used to read the first data and the third data in the original data in the first memory 102 and the data processing request indicated therein, and to read the second data from the second memory 111.

[0097] In this embodiment of the application, the data indicated by the data processing request includes first data, second data and third data. The third data is data that was originally stored in the first memory 102. The processing unit 112 reads the first data and the third data from the first memory 102 and reads the second data from the second memory 111, which is equivalent to the processing unit 112 reading the data indicated by the data processing request.

[0098] In this embodiment, when the first duration is longer than the second duration, the time required to load the data indicated by the data processing request into the second memory 111 and then for the processing unit 112 to read the data indicated by the data processing request from the second memory 111 is short. However, since the remaining space in the second memory 111 does not meet the storage requirements of the data processing request, the first memory 102 and the second memory 111 are determined as target memory. The second data is loaded from the memory 103 into the second memory 111, and the first data is loaded from the memory 103 into the first memory 102, so as to make the most of the remaining space in the second memory 111 and minimize the time required for the processing unit 112 to obtain the data indicated by the data processing request, thereby ensuring data transmission efficiency.

[0099] It should be noted that the above embodiments are illustrated using the example of data processing request indicating data including first data, second data, and third data. In another embodiment, all data indicated by the data processing request is stored in memory 103; or, if part of the data indicated by the data processing request is stored in the first memory 102, part of the data is stored in memory 103, and the amount of data that can be stored in the remaining space of the second memory 111 is greater than the amount of data corresponding to the data in memory 103, then other methods will be used for data transmission.

[0100] In one possible implementation, the data indicated by the data processing request includes the sixth data and the seventh data, and all the data indicated by the data processing request is stored in the memory 103; the processing unit 112 is used to control the first memory 102 to load the sixth data from the data indicated by the data processing request from the memory 103, control the second memory 111 to load the seventh data from the data indicated by the data processing request from the memory 103, and subsequently read the sixth data from the first memory 102 and the seventh data from the second memory 111.

[0101] In this embodiment, the amount of data corresponding to the seventh data is equal to the amount of data that the remaining space of the second memory 111 can store, and the sixth data is the data other than the seventh data in the data indicated by the data processing request. After the processing unit 112 reads the sixth data and the seventh data, it is equivalent to reading the data indicated by the data processing request. All the data indicated by the data processing request is stored in the memory 103. Since there is still remaining space in the second memory 111 but it does not meet the storage requirements of the data processing request, a portion of the data in the memory 103 is loaded into the first memory 102, and the remaining portion of the data is loaded into the second memory 111, so as to make the best use of the remaining space of the second memory 111, so as to minimize the time required for the processing unit 112 to obtain the data indicated by the data processing request, thereby ensuring data transmission efficiency.

[0102] In one possible implementation, a portion of the data indicated by the data processing request is stored in the first memory 102, a portion is stored in the memory 103, and the remaining space in the second memory 111 can store more data than the data corresponding to the data in the memory 103 in the data processing request. Processing unit 112: controls the second memory 111 to load the eighth data from the data indicated by the data processing request from the memory 103; controls the second memory 111 to load the ninth data from the data indicated by the data processing request from the first memory 102; reads the tenth data from the original data indicated by the data processing request in the first memory 102; and reads the eighth and ninth data from the second memory 111.

[0103] In this embodiment of the application, the data indicated by the data processing request includes the eighth data, the ninth data, and the tenth data. The eighth data is a portion of the original data indicated by the data processing request in the memory 103, while the ninth data and the tenth data are portions of the original data indicated by the data processing request in the first memory 102. The amount of data corresponding to the eighth data is less than the amount of data that the remaining space of the second memory 111 can store. The sum of the amounts of data corresponding to the eighth data and the ninth data is equal to the amount of data that the remaining space of the second memory 111 can store.

[0104] In this embodiment, since the second memory 111 still has remaining space but does not meet the storage requirements of the data processing request, and the amount of data corresponding to the eighth data stored in the memory 103 is less than the amount of data that the remaining space of the second memory 111 can store, the second memory 111 is controlled to load the eighth data from the data indicated by the data processing request from the memory 103, and the second memory 111 is controlled to load the ninth data from the data indicated by the data processing request from the first memory 102, so as to make the best use of the remaining space of the second memory 111, so as to minimize the time required for the processing unit 112 to obtain the data indicated by the data processing request, thereby ensuring data transmission efficiency.

[0105] Based on the embodiments shown above, in this application embodiment, different levels correspond to preset ratios to reflect the maximum space occupancy ratio of data processing requests of different levels on the second memory 111, so as to ensure that the second memory 111 can provide services for data processing requests of different levels. The data processing device is described below. Processing unit 112: used to determine the second memory 111 as the target memory when the first duration is greater than the second duration and the space occupancy ratio of the data processing request of the same level as the data processing request on the second memory 111 is less than the preset ratio corresponding to the level.

[0106] In this embodiment, when the first duration is longer than the second duration, the time required to load the data indicated by the data processing request into the second memory 111 and then for the processing unit 112 to read the data indicated by the data processing request from the second memory 111 is short. However, since different levels correspond to preset ratios, when the space occupancy ratio of the data processing request of the same level as the data processing request in the second memory 111 is less than the preset ratio corresponding to the level, the second memory 111 is determined as the target memory so that the data indicated by the data processing request can be loaded using the target memory, thereby reducing the time required for the processing unit 112 to obtain the data indicated by the data processing request, thus ensuring data transmission efficiency. At the same time, it also enables the second memory 111 to provide services for data processing requests of different levels, enabling the second memory 111 to cope with various complex situations, ensuring the performance of the data processing device and the utilization rate of the second memory 111.

[0107] The data processing request level reflects the importance of the requested procedure and can also be expressed as a priority. The preset proportions for different levels may be the same or different.

[0108] Optionally, the preset ratio corresponding to the level is positively correlated with the level.

[0109] In this embodiment, the higher the level, the larger the preset ratio, and the lower the level, the smaller the preset ratio. The sum of the preset ratios for multiple levels is 1. This ensures the efficiency of processing important data processing requests and thus guarantees the performance of the data processing device.

[0110] In one possible implementation, the processing unit 112 is used to determine the first memory 102 as the target memory when the first duration is greater than the second duration and the proportion of space occupied by the data processing request of the same level as the data processing request in the second memory 111 is not less than the preset proportion corresponding to the level.

[0111] In this embodiment, since different levels correspond to preset ratios, if the space occupancy ratio of the data processing request of the same level as the data processing request in the second memory 111 is not less than the preset ratio corresponding to the level, the first memory 102 is determined as the target memory. This is to avoid the situation where the space occupancy ratio of the data processing request corresponding to a certain level in the second memory 111 exceeds the preset ratio, thereby avoiding affecting the processing efficiency of data processing requests of other levels and ensuring the performance of the data processing device.

[0112] In the above Figure 1 Based on the embodiments shown, in the embodiments of this application, the target memory may be the first memory 102 or the second memory 111. The process of controlling the target memory to load the data indicated by the data processing request includes the following three methods.

[0113] First method: Processing unit 112: Used to control the target memory to load data processing request indication data from memory 103.

[0114] In this embodiment of the application, all the data indicated by the data processing request is located in the memory 103. Regardless of whether the target memory is the first memory 102 or the second memory 111, the processing unit 112 controls the target memory to load the data indicated by the data processing request from the memory 103 so that the target memory stores the data indicated by the data processing request.

[0115] The second method: Processing unit 112: When the target memory is the second memory 111, it controls the target memory to load the fourth data from the data indicated by the data processing request from the memory 103, and load the fifth data from the data indicated by the data processing request from the first memory 102.

[0116] In this embodiment, the target memory is the second memory 111, and part of the data indicated by the data processing request is located in the first memory 102, while the remaining data is located in the memory 103. The data indicated by the data processing request includes fourth data and fifth data. Therefore, the processing unit 112 controls the second memory 111 to load the fourth data from the memory 103 and controls the target memory to load the fifth data from the first memory 102, so that the second memory 111 stores both the fourth and fifth data, i.e., the second memory 111 stores the data indicated by the data processing request.

[0117] The third method: Processing unit 112: When the target memory is the first memory 102, it controls the target memory to load the fourth data from the memory 103.

[0118] In this embodiment of the application, the target memory is the first memory 102, and the data indicated by the data processing request includes the fourth data and the fifth data. The first memory 102 stores part of the data indicated by the data processing request. That is, the fifth data is already located in the first memory 102. Therefore, it is possible to control the first memory 102 to load the fourth data from the memory 103, so that the first memory 102 stores all the data indicated by the data processing request.

[0119] The fourth method: When the target memory is the first memory 102 and the first memory 102 stores the data indicating the data processing request, the processing unit 112 can directly read the data indicating the data processing request from the first memory 102 in the manner described above.

[0120] In this embodiment of the application, since the first memory 102 has already stored all the data of the data processing request indication, there is no need to control the first memory 102 to load data. Therefore, the processing unit 112 can directly read the data of the data processing request indication from the first memory 102.

[0121] In this embodiment of the application, regardless of how the data indicated by the data processing request is stored, and regardless of whether the target memory is the first memory 102 or the first memory 102, the data processing request can be transmitted in any of the above methods so that the target memory stores the data indicated by the data processing request, so that the subsequent processing unit 112 can read the data from the target memory and process it, ensuring data transmission efficiency and data processing feasibility.

[0122] Based on the embodiments shown above, in this embodiment, when the target memory stores data indicating a data processing request, the processing unit 112 reads the data indicating the data processing request from the target memory in multiple batches. The target memory then gradually releases the space occupied by the data indicating the data processing request. The data processing device will be described below. The processing unit 112 is further configured to control the target memory to delete data already read by the processing unit 112 based on the reading progress of the data indicating the data processing request by the processing unit 112.

[0123] In this embodiment, when the target memory stores data indicating a data processing request, the processing unit 112 reads a portion of the data from the target memory in multiple batches, processes the read portion of the data, and then reads a portion of the data from the target memory and processes it again. Thus, the data indicating the data processing request in the target memory includes the portion of data already read by the processing unit 112 and the portion of data not yet read by the processor 101. Therefore, based on the reading progress of the data indicating the data processing request by the processing unit 112, the target memory is controlled to delete the data already read by the processing unit 112, so as to release the space occupied by the target memory as quickly as possible and improve the utilization rate of the target memory.

[0124] In one possible implementation, the data processing request indicates that the data includes i sets of data, where i is an integer greater than 1; the processing unit 112 is used to read the j-th set of data from the target memory, process the j-th set of data, and control the target memory to delete the j-th set of data; read the (j+1)-th set of data from the second memory 111, process the (j+1)-th set of data, and control the target memory to delete the (j+1)-th set of data, where j is an integer greater than 0 and less than i.

[0125] In this embodiment of the application, the data indicated by the data processing request is divided into multiple groups of data. The processing unit 112 reads one group of data from the target memory each time and processes it, and controls the target memory to delete the read data. In this way, it can ensure that the processing unit 112 can respond to the data processing request accurately, ensure the processing efficiency of the processing unit 112 in processing the data processing request, and minimize the space occupation of the target memory, thus saving the space of the target memory.

[0126] It should be noted that the above-mentioned multiple optional embodiments can be combined in any way, and this application will not elaborate on them one by one here.

[0127] Based on the embodiments shown above, this application also provides a schematic diagram of data transmission in a data processing device, such as... Figures 2 to 4 As shown.

[0128] Taking a scenario where some data in the data processing request is located in the first memory 102 and some data is located in the storage 103 as an example, in this case, the fourth data in the data processing request is located in the storage 103, and the fifth data in the data processing request is located in the first memory 102. The processing unit 112 determines the second memory 111 as the target memory. The data transmission process in the data processing device is as follows: Figure 2 As shown. Processing unit 112 sends a third load instruction to second memory 111; second memory 111 receives the third load instruction, loads fourth data from memory 103, and loads fifth data from first memory 102; then, processing unit 112 reads the fourth and fifth data from second memory 111 and processes them.

[0129] Taking a scenario where some data in the data processing request is located in the first memory 102 and some data is located in the memory 103 as an example, in this case, the fourth data in the data processing request is located in the memory 103, and the fifth data in the data processing request is located in the first memory 102. The processing unit 112 determines the first memory 102 as the target memory, and the data transmission process in the data processing device is as follows: Figure 3 As shown, the processing unit 112 sends a fourth load instruction to the first memory 102; the second memory 111 receives the fourth load instruction and loads the fourth data from the memory 103; then, the processing unit 112 reads the fourth data and the fifth data from the first memory 102 and processes them.

[0130] Taking a data processing request indicating that some data is located in the first memory 102 and some data is located in the memory 103 as an example, in this case, the first and second data in the data processing request indicating that the data is located in the memory 103, and the third data in the data processing request indicating that the data is located in the first memory 102. The processing unit 112 determines the first memory 102 and the second memory 111 as the target memory. Then the data transmission process in the data processing device is as follows: Figure 4 As shown, the processing unit 112 sends a first load instruction to the first memory 102 and a second load instruction to the second memory 111; the first memory 102 receives the first load instruction and loads the first data from the memory 103; the second memory 111 receives the second load instruction and loads the second data from the memory 103; then, the processing unit 112 reads the first data and the third data from the first memory 102 and reads the second data from the second memory 111, and processes the read first data, second data and third data.

[0131] Based on the embodiments shown above, this application also provides a schematic diagram of the structure of a data processing device, such as... Figure 5As shown, taking DRAM as the first memory, HBM as the second memory, and Disk (external storage device) as the storage device as an example, DRAM and HBM can transmit data with Disk via I / O (Input / Output), and data can be transferred between DRAM and HBM. DRAM includes a memory buffer, a connection request scheduler, and a first memory space management. The memory buffer is used to store cached data. The connection request scheduler includes a circular queue, which includes at least one piece of information, each piece of information corresponding to a data processing request in the above embodiment. Through the circular queue, the pipelined execution of multiple parallel data processing requests can be controlled. After any data processing request is processed, the piece of information corresponding to that data processing request is deleted from the circular queue. The first memory space management is used to record the second storage information of HBM to indicate the data storage status in the second memory. The first memory space management can also record the transmission status from DRAM to HBM and the transmission status from Disk to HBM, so as to reflect the data storage status in the second memory.

[0132] In this embodiment, taking a data processing request corresponding to a join operation as an example, the data processing request instructs the execution of a join operation on two data tables, which are the data indicated by the data processing request. For any data processing request, as shown in the above embodiment, before responding to the data processing request, the processing unit determines a first duration and a second duration based on the metadata maintained in the memory buffer, the metadata of the database tables, and the hardware parameters used. The first duration is equivalent to the benefit, and the second duration is equivalent to the cost. If the benefit is greater than the cost, and the data indicated by the data processing request can be entirely stored on HBM, then the data indicated by the data processing request is executed on HBM; if the benefit is not greater than the cost, and the data indicated by the data processing request can be entirely stored on DRAM, then the data indicated by the data processing request is executed on DRAM. In this way, the performance benefit of HBM is maximized for this data processing request, ensuring that the time required from the processing unit receiving the data processing request to the data processing unit reading the data indicated by the data processing request is sufficiently short, guaranteeing data transmission efficiency, and thus guaranteeing the processing efficiency of the data processing request.

[0133] Furthermore, in cases where a portion of the data in the data processing request is located in the first memory and the remainder is located in the second memory, taking the execution of the data processing request on HBM as an example, according to the above... Figure 2The data processing apparatus shown can transfer a portion of the data in a data processing request indication located in DRAM to the HBM via a connection between the HBM and DRAM; and transfer a portion of the data in a data processing request indication located on the Disk to the HBM via a connection between the HBM and the Disk. These two transfer processes can be executed synchronously, thus the I / O access process can mask part of the DRAM-to-HBM transfer time, minimizing the time required for these two transfer processes.

[0134] It should be noted that when a processing unit receives multiple data processing requests, it can process these requests in a pipelined manner, enabling parallel responses to multiple requests. The processing unit can maintain a connection request scheduler in DRAM to record information for each data processing request in a circular queue. This information includes the execution status of the data processing request, its HBM usage, its DRAM usage, its transmission status, and other necessary metadata. The execution status includes not started, executing, and completed. HBM usage refers to the amount of data used to access the HBM during the processing unit's response to the request; DRAM usage refers to the amount of data used to access the DRAM during the processing unit's response to the request. The transmission status refers to the transmission status between DRAM and HBM, and the I / O transmission status between DRAM and HBM and the Disk, respectively, during the processing unit's response to the request. Other necessary metadata refers to other information about the data processing request, such as the time the data processing request was received and its priority.

[0135] In this embodiment, upon receiving any data processing request, the processing unit controls the DRAM to store an item corresponding to that data processing request in the circular queue. Subsequently, it also controls the DRAM to update the information corresponding to the data processing request in the circular queue, such as updating the execution status of the data processing request, the HBM usage, the DRAM usage, and the transmission status. If the execution status of any data processing request is "completed," the processing unit controls the DRAM to remove the information corresponding to that data processing request from the circular queue.

[0136] Furthermore, during the process of the processing unit responding to data processing requests, the HBM space occupied by the read data can be gradually released based on the progress of the data read from the HBM indicated by the data processing request. This eliminates the need to wait until the data processing request is completed before releasing the HBM space occupied by the data indicated by the request, ensuring maximum utilization of the HBM and guaranteeing its efficiency. Moreover, the processor manages the free space of the HBM through the first memory space management on DRAM, recording the data recording status in the HBM and the remaining free space.

[0137] Furthermore, when the processing unit receives multiple data processing requests, it can execute a preset number of data processing requests in parallel. When starting to execute any data processing request, it reads the information corresponding to each data processing request in the circular queue, selects the data processing request with the earliest reception time or the data processing request with the highest priority from the data processing requests that have not yet started to be executed, according to the reception time or priority of the data processing requests that have not yet started to be executed, and starts to execute the selected data processing request.

[0138] It should be noted that the above embodiment is illustrated using the example where the benefits outweigh the costs, and all the data indicated by the data processing request can be stored on HBM. In another embodiment, if the benefits outweigh the costs, and the data processing request cannot be fully stored on HBM, a hybrid mode is adopted. That is, part of the data indicated by the data processing request is placed on DRAM, and part of the data is placed on HBM. In this way, HBM space can be allocated to a portion of the data indicated by the data processing request. This allocation of HBM space is no longer based on the data processing request, but on a more granular approach such as data structure, which can make the most of HBM's high bandwidth characteristics and improve HBM utilization.

[0139] Furthermore, during the response to data processing requests, the processing unit can prefetch HBM access using methods such as group prefetching, asynchronous memory-chained access (AMAC), and coroutines. This allows for switching between different data processing requests, masking some of HBM's memory access latency. In HBM access scenarios, due to HBM's high bandwidth, it accesses adjacent or related data while accessing any other data. This reduces data access latency, making data processing smoother and reducing the time spent waiting for data to be transferred from HBM to the processing unit. Multiple access requests can be processed simultaneously in HBM access scenarios. Asynchronous memory-chained access allows the next memory access request to be initiated without waiting for the current memory access to complete. Through asynchronous memory-chained access, HBM's high bandwidth and parallel processing capabilities can be fully utilized, improving overall memory throughput and ensuring continuous data transfer from HBM to the processing unit. A coroutine is a lightweight thread that can pause and resume execution within a program. In HBM access, coroutines can be used to manage different access tasks. For example, when a coroutine is responsible for reading data from HBM to indicate a data processing request, it can pause its execution while waiting for data transmission, handing over execution to other coroutines. This allows for more efficient use of processing unit time and avoids idle processing units due to waiting for data. Furthermore, because coroutines have lower overhead than traditional threads and can be scheduled more flexibly, concurrent execution of multiple data accesses can be achieved, improving system responsiveness.

[0140] Furthermore, the algorithms involved in the data processing requests provided in this application embodiment can be join algorithms or other algorithms. Different data processing requests may involve different algorithms. By responding to multiple data processing requests in the above manner, HBM resources can be reasonably allocated among different algorithms, thereby improving the end-to-end performance of the system in processing queries. For different join algorithms, although the specific operations on the data tables to be joined are different, they all require scanning the entire table for partition probing or sorting and merging.

[0141] Furthermore, HBM boasts advantages such as high bandwidth and low latency, significantly improving data access speed. However, HBM's hardware costs are relatively high. In cloud storage environments, using HBM requires a trade-off between its performance advantages and cost to maximize economic benefits. Therefore, by prioritizing different data processing requests and allocating a preset proportion of HBM resources according to priority, the resource consumption of each priority level of data processing requests can be limited, thus meeting the quality standards and performance indicators of different SLA (Service-Level Agreement) service levels.

[0142] It should be noted that the data processing device provided in this application embodiment can be applied to any scenario. Taking the application in the database scenario as an example, in the database system, two relational tables are usually joined, especially in analytical workloads (OLAP, On-Line Analytical Processing).

[0143] Taking the interaction between a user and the server 602 corresponding to the database system via terminal 601 as an example, server 602 includes a data processing device, which includes a processor 621, a first memory 622, and a memory 623. Processor 621 includes a second memory 6211 and a processing unit 6212. Figure 6As shown, a user can access the database system through terminal 601, which displays the corresponding interface of the database system. The user can trigger a query operation for any data within the display interface through terminal 601. For example, to query the name and description information of various objects, terminal 601 sends a data query request to server 602 via a network connection. The data query request requests the name and description information of the objects. The processing unit 6212 in server 602 receives the data query request and determines that the name data table corresponding to the data query request is located in the first memory 622, and the description information table corresponding to the data query request is located in the memory 623. The name data table represents the name of each object, and the description information table represents the description information of each object. Taking the second memory 6211 as the target memory as an example, the processing unit 6212 sends a fifth load instruction to the second memory 6211; the second memory 6211 receives the fifth load instruction, loads the description information table from the memory 623, and loads the name data table from the first memory 622; then, the processing unit 6212 reads the name data table and the description information table from the second memory 6211, and combines the contents of the same object identifier field in the description information table and the description information table to obtain the result data table. The processing unit 6212 outputs the result data table, and the server 602 returns the result data table to the terminal 601. The terminal 601 can display the result data table in the display interface to display each object identifier, the name and description information corresponding to each object identifier.

[0144] In the embodiments of this application, a data processing request is equivalent to a connection operation. For connection operations, the method provided in the embodiments of this application can ensure that the data involved in the connection operation is quickly transmitted to the processing unit, thereby ensuring the response efficiency of the processing unit to the connection operation.

[0145] The data processing apparatus provided in this application embodiment is equivalent to a connection operator optimization scheme oriented towards HBM. It models the cost and benefit of using HBM, selects connection operations that can obtain performance benefits to accelerate using HBM, and pipelines multiple connection operations to improve the overall throughput and ensure reasonable performance benefits.

[0146] For multiple connection requests, the execution status of connection operations is tracked, and some transmission overhead is masked through pipelined execution.

[0147] This solution has strong adaptability and is suitable for different memory buffer ratios. It is not only suitable for memory OLAP processing, but also takes into account the buffer interaction between internal and external memory, making it equally suitable for external memory scenarios.

[0148] This solution is highly versatile, not targeting specific join algorithms, memory buffer management methods, or I / O methods, and provides a general optimization framework and strategies. It also boasts strong scalability, allowing for further performance improvements in practical systems by combining prefetching, multiple operators, and priority-based orthogonal optimization techniques. By fully leveraging the high bandwidth characteristics of HBM, it enhances memory access efficiency during join operations.

[0149] Figure 7 This is a flowchart of a data processing method provided in an embodiment of this application. The method is executed by the data processing device shown in the above embodiment. The data processing device includes a processor, a first memory, and a memory. The processor includes a second memory and a processing unit. The processing unit is connected to both the first memory and the second memory. The first memory and the second memory are connected to each other. The first memory and the second memory are connected to the memory. The access bandwidth of the first memory is less than the access bandwidth of the second memory. Figure 7 As shown, the method includes:

[0150] 701. The processing unit receives a data processing request and determines the distribution information of the data indicated by the data processing request. The distribution information indicates the distribution of the data in the first memory or storage.

[0151] 702. The processing unit determines the target memory from the first memory and the second memory based on the distribution information, the access bandwidth of the first memory, the access bandwidth of the second memory, and the transmission bandwidth between the first memory and the second memory.

[0152] 703. The processing unit controls the loading of data from the target memory, reads data from the target memory, and processes the data.

[0153] In the solution provided in this application embodiment, the data processing device includes a processor, low-bandwidth memory, and a memory. The processor includes a processing unit for data processing and high-bandwidth memory. During the process of responding to a data processing request, the processing unit combines the high-bandwidth memory and the low-bandwidth memory, and flexibly selects the target memory to load data based on the distribution of the data indicated by the data processing request in the low-bandwidth memory or the memory, the access bandwidth of the high-bandwidth memory, the access bandwidth of the low-bandwidth memory, and the transmission bandwidth between the high-bandwidth memory and the low-bandwidth memory. This achieves reasonable allocation and efficient utilization of memory resources, avoids the situation where data is concentrated in the high-bandwidth memory, resulting in wasted low-bandwidth memory space, and also avoids the situation where the data reading speed is too slow due to over-reliance on low-bandwidth memory. It minimizes the time required for the processing unit to obtain the data to be processed, ensures the data transmission efficiency during the process of the processing unit responding to the data processing request, and thus ensures the response efficiency to the data processing request.

[0154] In one possible implementation, the processing unit determines the target memory from the first memory and the second memory based on distribution information, the access bandwidth of the first memory, the access bandwidth of the second memory, and the transmission bandwidth between the first memory and the second memory, including:

[0155] Based on distribution information, access bandwidth of the first memory, access bandwidth of the second memory, and transmission bandwidth, the processing unit determines a first duration and a second duration. The first duration is the difference between the time required for the processing unit to read a first amount of data from the first memory or the second memory, respectively. The first amount of data is the amount of data corresponding to the data indicated by the data processing request. The second duration is the time required for the data located in the first memory in the data indicated by the data processing request to be transmitted from the first memory to the second memory.

[0156] If the processing unit determines the second memory as the target memory when the first duration is greater than the second duration; or, if the processing unit determines the first memory as the target memory when the first duration is not greater than the second duration.

[0157] In another possible implementation, the distribution information includes a first data volume and a second data volume, where the second data volume is the data volume corresponding to the data located in the first memory within the data indicated by the data processing request; the processing unit determines the first duration and the second duration based on the distribution information, the access bandwidth of the first memory, the access bandwidth of the second memory, and the transmission bandwidth, including:

[0158] The processing unit determines a first ratio of the first data volume to the access bandwidth of the first memory and a second ratio of the first data volume to the access bandwidth of the second memory; the difference between the first ratio and the second ratio is determined as a first duration; and the ratio of the second data volume to the transmission bandwidth is determined as a second duration.

[0159] In another possible implementation, if the processing unit determines the second memory as the target memory when the first duration is longer than the second duration, including:

[0160] If the processing unit determines the second memory as the target memory when the first duration is greater than the second duration and the remaining space of the second memory meets the storage requirements of the data processing request.

[0161] In another possible implementation, the method also includes:

[0162] If the processing unit determines the first memory as the target memory when the first duration is longer than the second duration and the remaining space in the second memory is insufficient to meet the storage requirements of the data processing request.

[0163] In another possible implementation, when the processing unit determines the first memory as the target memory if the first duration is longer than the second duration and the remaining space in the second memory is insufficient to meet the storage requirements of the data processing request, including:

[0164] If the processing unit determines the first memory and the second memory as the target memory when the first duration is longer than the second duration and there is still remaining space in the second memory but it does not meet the storage requirements;

[0165] The processing unit controls the loading of data from the target memory and reads data from the target memory, including:

[0166] The processing unit controls the first memory to load the first data from the data processing request indicated by the memory, and controls the second memory to load the second data from the data processing request indicated by the memory.

[0167] The processing unit reads first data from the first memory and third data from the existing data in the first memory that is indicated by the data processing request, and reads second data from the second memory.

[0168] In another possible implementation, if the processing unit determines the second memory as the target memory when the first duration is longer than the second duration, including:

[0169] If the processing unit determines the second memory as the target memory when the first duration is greater than the second duration and the proportion of space occupied by the data processing request of the same level as the data processing request in the second memory is less than the preset proportion corresponding to the level.

[0170] In another possible implementation, the processing unit controls the loading of data into the target memory, including:

[0171] The processing unit controls the target memory to load the data indicated by the data processing request from the memory; or,

[0172] If the target memory is the second memory, control the target memory to load the fourth data from the data processing request indicated by the memory, and load the fifth data from the data processing request indicated by the first memory; or...

[0173] If the target memory is the first memory, control the target memory to load the fourth data from the memory.

[0174] In another possible implementation, the method also includes:

[0175] Based on the progress of reading the data indicated by the data processing request, the processing unit controls the target memory to delete the data already read by the processing unit.

[0176] It should be noted that the data processing device and data processing method provided in the above embodiments belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0177] This application also provides a computer device, which includes a data processing apparatus.

[0178] Optionally, the computer device is provided as a terminal. Figure 8 This diagram illustrates a structural block diagram of a terminal provided in an exemplary embodiment of this application. The terminal 800 is a smartphone, tablet computer, laptop computer, desktop computer, smart speaker, smartwatch, smart voice interaction device, smart home appliance, or in-vehicle terminal, etc. The terminal 800 includes a data processing device, which includes a processor 801, a first memory 803, and a memory 802. The processor 801 includes a second memory 8011 and a processing unit 8012.

[0179] Processor 801 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 801 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). Processor 801 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 801 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed on the screen. In some embodiments, processor 801 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0180] The memory 802 may include one or more computer-readable storage media, which may be non-transitory. The memory 802 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 802 are used to store at least one computer program, which is executed by the processor 801 to implement the data processing method provided in the method embodiments of this application.

[0181] In some embodiments, the terminal 800 may also optionally include a peripheral device interface 804 and at least one peripheral device. The processor 801, memory 802, and peripheral device interface 804 can be connected via a bus or signal line. Each peripheral device can be connected to the peripheral device interface 804 via a bus, signal line, or circuit board. Specifically, the peripheral device includes at least one of the following: radio frequency circuitry 805, display screen 806, camera assembly 807, audio circuitry 808, and power supply 809.

[0182] Peripheral device interface 804 can be used to connect at least one I / O (Input / Output) related peripheral device to processor 801 and memory 802. In some embodiments, processor 801, memory 802 and peripheral device interface 804 are integrated on the same chip or circuit board; in some other embodiments, any one or two of processor 801, memory 802 and peripheral device interface 804 can be implemented on separate chips or circuit boards, which is not limited in this embodiment.

[0183] The radio frequency (RF) circuit 805 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The RF circuit 805 communicates with communication networks and other communication devices via electromagnetic signals. The RF circuit 805 converts electrical signals into electromagnetic signals for transmission, or converts received electromagnetic signals back into electrical signals. Optionally, the RF circuit 805 includes: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a user identity module card, etc. The RF circuit 805 can communicate with other terminals through at least one wireless communication protocol. This wireless communication protocol includes, but is not limited to: the World Wide Web, metropolitan area networks, intranets, various generations of mobile communication networks (2G, 3G, 4G, and 5G), wireless local area networks, and / or WiFi (Wireless Fidelity) networks. In some embodiments, the RF circuit 805 may also include circuitry related to NFC (Near Field Communication), which is not limited in this application.

[0184] Display screen 806 is used to display a UI (User Interface). This UI may include graphics, text, icons, videos, and any combination thereof. When display screen 806 is a touch display screen, it also has the ability to collect touch signals on or above its surface. These touch signals can be input as control signals to processor 801 for processing. In this case, display screen 806 can also be used to provide virtual buttons and / or a virtual keyboard, also known as soft buttons and / or a soft keyboard. In some embodiments, there may be one display screen 806, disposed on the front panel of terminal 800; in other embodiments, there may be at least two display screens, disposed on different surfaces of terminal 800 or in a folded design; in other embodiments, display screen 806 may be a flexible display screen, disposed on a curved or folded surface of terminal 800. Furthermore, display screen 806 may be configured as a non-rectangular irregular shape, i.e., a non-rectangular screen. Display screen 806 may be made of materials such as LCD (Liquid Crystal Display) or OLED (Organic Light-Emitting Diode).

[0185] The camera assembly 807 is used to acquire images or videos. Optionally, the camera assembly 807 includes a front-facing camera and a rear-facing camera. The front-facing camera is disposed on the front panel of the terminal, and the rear-facing camera is disposed on the back of the terminal. In some embodiments, there are at least two rear-facing cameras, which are any one of a main camera, a depth-sensing camera, a wide-angle camera, and a telephoto camera, to achieve background blurring by fusion of the main camera and the depth-sensing camera, panoramic shooting by fusion of the main camera and the wide-angle camera, VR (Virtual Reality) shooting, or other fusion shooting functions. In some embodiments, the camera assembly 807 may also include a flash. The flash may be a single-color temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm light flash and a cool light flash, which can be used for light compensation at different color temperatures.

[0186] The audio circuit 808 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, converting the sound waves into electrical signals that are input to the processor 801 for processing, or input to the radio frequency circuit 805 for voice communication. For stereo sound acquisition or noise reduction purposes, multiple microphones may be used, each located at a different part of the terminal 800. The microphone may also be an array microphone or an omnidirectional microphone. The speaker is used to convert the electrical signals from the processor 801 or the radio frequency circuit 805 into sound waves. The speaker may be a conventional diaphragm speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can convert electrical signals not only into audible sound waves but also into inaudible sound waves for purposes such as distance measurement. In some embodiments, the audio circuit 808 may also include a headphone jack.

[0187] Power supply 809 is used to supply power to the various components in terminal 800. Power supply 809 can be AC ​​power, DC power, a disposable battery, or a rechargeable battery. When power supply 809 includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery that is charged via a wired line, and a wireless rechargeable battery is a battery that is charged via a wireless coil. The rechargeable battery can also be used to support fast charging technology.

[0188] Those skilled in the art will understand that Figure 8 The structure shown does not constitute a limitation on terminal 800 and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0189] Optionally, the computer equipment is provided as a server. Figure 9 This is a schematic diagram of a server structure provided in an embodiment of this application. The server 900 can vary significantly due to different configurations or performance, and may include one or more data processing devices. The data processing devices include a processor 901, a first memory 903, and a memory 902. The processor 901 includes a second memory 9011 and a processing unit 9012. The memory 902 stores at least one computer program, which is loaded and executed by the processor 901 to implement the data processing methods provided in the above-described method embodiments. Of course, the server may also have wired or wireless network interfaces, a keyboard, and input / output interfaces for input and output. The server may also include other components for implementing device functions, which will not be elaborated here.

[0190] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0191] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present application should be included within the protection scope of the present application.

Claims

1. A data processing apparatus, characterized in that, The data processing device includes a processor (101), a first memory (102), and a memory (103). The processor (101) includes a second memory (111) and a processing unit (112). The processing unit (112) is connected to the first memory (102) and the second memory (111) respectively. The first memory (102) is connected to the second memory (111). The first memory (102) and the second memory (111) are connected to the memory (103) respectively. The access bandwidth of the first memory (102) is less than the access bandwidth of the second memory (111). The processing unit (112) is configured to receive a data processing request and determine the distribution information of the data indicated by the data processing request, wherein the distribution information indicates the distribution of the data in the first memory (102) or the memory (103); The processing unit (112) is further configured to determine the target memory from the first memory (102) and the second memory (111) based on the distribution information, the access bandwidth of the first memory (102), the access bandwidth of the second memory (111), and the transmission bandwidth between the first memory (102) and the second memory (111). The processing unit (112) is also used to control the target memory to load the data, read the data from the target memory, and process the data.

2. The apparatus according to claim 1, characterized in that, The processing unit (112) is used to determine a first duration and a second duration based on the distribution information, the access bandwidth of the first memory (102), the access bandwidth of the second memory (111), and the transmission bandwidth. The first duration is the difference between the time required for the processing unit (112) to read a first amount of data from the first memory (102) or the second memory (111), respectively. The first amount of data is the amount of data corresponding to the data indicated by the data processing request. The second duration is the time required for the data located in the first memory (102) in the data indicated by the data processing request to be transmitted from the first memory (102) to the second memory (111). The processing unit (112) is configured to determine the second memory (111) as the target memory when the first duration is greater than the second duration; or, when the first duration is not greater than the second duration, determine the first memory (102) as the target memory.

3. The apparatus according to claim 2, characterized in that, The distribution information includes the first data volume and the second data volume, wherein the second data volume is the data volume corresponding to the data located in the first memory (102) in the data indicated by the data processing request; The processing unit (112) is used to determine a first ratio of the first data volume to the access bandwidth of the first memory (102) and a second ratio of the first data volume to the access bandwidth of the second memory (111); to determine the difference between the first ratio and the second ratio as the first duration; and to determine the ratio of the second data volume to the transmission bandwidth as the second duration.

4. The apparatus according to claim 2, characterized in that, The processing unit (112) is configured to determine the second memory (111) as the target memory when the first duration is greater than the second duration and the remaining space of the second memory (111) meets the storage requirements of the data processing request.

5. The apparatus according to claim 2, characterized in that, The processing unit (112) is further configured to determine the first memory (102) as the target memory when the first duration is greater than the second duration and the remaining space of the second memory (111) does not meet the storage requirements of the data processing request.

6. The apparatus according to claim 5, characterized in that, The processing unit (112) is used to determine the first memory (102) and the second memory (111) as the target memory when the first duration is greater than the second duration and the second memory (111) still has remaining space but does not meet the storage requirements. The processing unit (112) is configured to control the first memory (102) to load the first data from the data indicated by the data processing request from the memory (103), and to control the second memory (111) to load the second data from the data indicated by the data processing request from the memory (103); The processing unit (112) is further configured to read the first data and the third data in the first memory (102) that are originally in the first memory (102) and indicated by the data processing request, and to read the second data from the second memory (111).

7. The apparatus according to claim 2, characterized in that, The processing unit (112) is used to determine the second memory (111) as the target memory when the first duration is greater than the second duration and the space occupancy ratio of the data processing request of the same level as the data processing request in the second memory (111) is less than the preset ratio corresponding to the level.

8. The apparatus according to any one of claims 1 to 7, characterized in that, The processing unit (112) is configured to control the target memory to load the data indicated by the data processing request from the memory (103); or, When the target memory is the second memory (111), the target memory is controlled to load the fourth data from the data indicated by the data processing request from the memory (103), and to load the fifth data from the data indicated by the data processing request from the first memory (102); or, If the target memory is the first memory (102), the target memory is controlled to load the fourth data from the memory (103).

9. The apparatus according to any one of claims 1 to 7, characterized in that, The processing unit (112) is also configured to control the target memory to delete the data already read by the processing unit (112) based on the reading progress of the data indicated by the data processing request by the processing unit (112).

10. A data processing method, characterized in that, The method is executed by the data processing apparatus according to any one of claims 1 to 9, the data processing apparatus comprising a processor, a first memory, and a memory, the processor comprising a second memory and a processing unit, the processing unit being connected to the first memory and the second memory respectively, the first memory being connected to the second memory, the first memory and the second memory being connected to the memory respectively, and the access bandwidth of the first memory being less than the access bandwidth of the second memory; the method comprises: The processing unit receives a data processing request and determines the distribution information of the data indicated by the data processing request, wherein the distribution information indicates the distribution of the data in the first memory or the memory. The processing unit determines the target memory from the first memory and the second memory based on the distribution information, the access bandwidth of the first memory, the access bandwidth of the second memory, and the transmission bandwidth between the first memory and the second memory. The processing unit controls the target memory to load the data, reads the data from the target memory, and processes the data.

11. The method according to claim 10, characterized in that, The processing unit determines the target memory from the first memory and the second memory based on the distribution information, the access bandwidth of the first memory, the access bandwidth of the second memory, and the transmission bandwidth between the first memory and the second memory, including: The processing unit determines a first duration and a second duration based on the distribution information, the access bandwidth of the first memory, the access bandwidth of the second memory, and the transmission bandwidth. The first duration is the difference between the time required for the processing unit to read a first amount of data from the first memory and the second memory respectively. The first amount of data is the amount of data corresponding to the data indicated by the data processing request. The second duration is the time required for the data located in the first memory in the data indicated by the data processing request to be transmitted from the first memory to the second memory. The processing unit determines the second memory as the target memory when the first duration is greater than the second duration; or, the processing unit determines the first memory as the target memory when the first duration is not greater than the second duration.

12. The method according to claim 11, characterized in that, The distribution information includes the first data volume and the second data volume, wherein the second data volume is the data volume corresponding to the data located in the first memory in the data indicated by the data processing request; the processing unit determines the first duration and the second duration based on the distribution information, the access bandwidth of the first memory, the access bandwidth of the second memory, and the transmission bandwidth, including: The processing unit determines a first ratio of the first data volume to the access bandwidth of the first memory and a second ratio of the first data volume to the access bandwidth of the second memory; the difference between the first ratio and the second ratio is determined as the first duration; and the ratio of the second data volume to the transmission bandwidth is determined as the second duration.

13. The method according to claim 11, characterized in that, When the processing unit determines the second memory as the target memory when the first duration is greater than the second duration, the following steps are included: The processing unit determines the second memory as the target memory when the first duration is greater than the second duration and the remaining space of the second memory meets the storage requirements of the data processing request.

14. The method according to claim 11, characterized in that, The method further includes: If the first duration is greater than the second duration and the remaining space in the second memory does not meet the storage requirements of the data processing request, the processing unit determines the first memory as the target memory.

15. The method according to claim 14, characterized in that, When the processing unit determines the first memory as the target memory when the first duration is greater than the second duration and the remaining space in the second memory does not meet the storage requirements of the data processing request, the following steps are taken: When the first duration is greater than the second duration and there is still remaining space in the second memory but it does not meet the storage requirements, the processing unit determines the first memory and the second memory as the target memory. The processing unit controls the target memory to load the data and reads the data from the target memory, including: The processing unit controls the first memory to load the first data from the data indicated by the data processing request from the memory, and controls the second memory to load the second data from the data indicated by the data processing request from the memory; The processing unit reads the first data and the third data from the data already present in the first memory and indicated by the data processing request from the first memory, and reads the second data from the second memory.

16. The method according to claim 11, characterized in that, When the processing unit determines the second memory as the target memory when the first duration is greater than the second duration, the following steps are included: The processing unit determines the second memory as the target memory when the first duration is greater than the second duration and the proportion of space occupied by the data processing request of the same level as the data processing request in the second memory is less than the preset proportion corresponding to the level.

17. The method according to any one of claims 10 to 16, characterized in that, The processing unit controls the target memory to load the data, including: The processing unit controls the target memory to load the data indicated by the data processing request from the memory; or... If the target memory is the second memory, control the target memory to load the fourth data from the data indicated by the data processing request from the memory, and load the fifth data from the data indicated by the data processing request from the first memory; or... If the target memory is the first memory, control the target memory to load the fourth data from the memory.

18. The method according to any one of claims 10 to 16, wherein the method further comprises: Based on the reading progress of the data indicated by the data processing request, the processing unit controls the target memory to delete the data already read by the processing unit.

19. A computer device, characterized in that, The computer device includes the data processing apparatus as described in any one of claims 1 to 9.

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