A serial communication data error correction method, device and electronic device

Abstract

This application provides a serial communication data error correction method, apparatus, and electronic device, relating to the field of computer technology. The method includes: before the serial port controller initialization is complete, sampling the serial port receiving data based on the system clock and storing the sampled data in a first buffer; in response to the serial port controller initialization completion, sampling the serial port receiving data based on a preset baud rate clock and storing the sampled data in a third buffer; resampling the first data in the first buffer based on the preset baud rate clock and storing the resampled data in a second buffer; in response to detecting that the stop bit position of the third data does not meet the set position condition, analyzing the second and third data to determine the correct stop bit position of the third data; and shift-sampling the second and third data based on the correct stop bit position, storing the shift-sampled data in a fourth buffer. This improves data stability.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a serial communication data error correction method, apparatus and electronic device. Background Technology

[0002] Current serial communication data error correction methods often use idle frame synchronization to confirm the correct start bit position. When there is a long idle state bit in a frame, the correct position can be restored. Alternatively, a fixed protocol transmission format can be adopted. If the fixed frame header cannot be identified, the data of this frame will not be received and processed. This ensures that if the correct frame header is identified, the subsequent data will definitely be correct.

[0003] Current serial communication data error correction methods suffer from limitations in timely error correction and inability to handle continuous data reception. Protocol-based methods require the BMC and peripherals to pre-agree on a fixed protocol frame format, significantly reducing communication flexibility. Therefore, current serial communication data error correction methods cannot correct errors in serial communication data promptly, and the data stability of serial communication is relatively low. Summary of the Invention

[0004] This application provides a serial communication data error correction method, apparatus, and electronic device.

[0005] This application provides a serial communication data error correction method, the method comprising: before the serial port controller initialization is completed, sampling the serial port receiving data based on the system clock, and storing the sampled first data into a first buffer; in response to the serial port controller initialization being completed, sampling the serial port receiving data based on a preset baud rate clock, and storing the sampled third data into a third buffer; resampling the first data in the first buffer based on the preset baud rate clock, and storing the resampled second data into a second buffer; in response to detecting that the stop bit position of the third data does not meet the set position condition, analyzing the second data and the third data to determine the correct stop bit position of the third data; and shift sampling the second data and the third data based on the correct stop bit position, and storing the shifted sampled data into a fourth buffer.

[0006] According to one embodiment of this application, storing the sampled first data into a first buffer includes: storing the sampled first data into the first buffer in response to the remaining storage area of ​​the first buffer being able to store the first data; and overwriting the earliest first data stored in the first buffer with the newly sampled first data in response to the remaining storage area of ​​the first buffer being unable to store the first data.

[0007] According to one embodiment of this application, the method further includes: determining the current stop position of the third data based on the bit width of each data frame in the third data and the current start position; detecting the serial port level state corresponding to the current stop position; determining that the stop position does not meet the set position condition in response to the serial port level state being low; and determining that the stop position meets the set position condition in response to the serial port level state being high.

[0008] According to one embodiment of this application, the step of analyzing the second data and the third data to determine the correct stop bit position of the third data includes: determining a first stop bit position where the serial port level is high between the current start bit position and the current stop bit position of the data frame; and determining the first stop bit position as the correct stop bit position in response to the fact that the number of the first stop bit positions is one.

[0009] According to one embodiment of this application, the method further includes: responding to the fact that there are multiple first stop bit positions, based on the second data, tracing back from each first stop bit position to the corresponding candidate start bit position according to the bit width of the data frame; detecting the serial port level state of each candidate start bit position and the previous bit of the candidate start bit position; determining the first stop bit position corresponding to the candidate start bit position where the previous serial port level state is high and the current serial port level state is low as the candidate stop bit position; and performing shift sampling on the second data and the third data based on the candidate stop bit position to determine the correct stop bit position.

[0010] According to one embodiment of this application, the step of shifting and sampling the second data and the third data based on the candidate stop bit positions to determine the correct stop bit position includes: in response to the existence of multiple candidate stop bit positions, shifting and sampling the second data and the third data based on each candidate stop bit position to obtain shifted sampled data; inputting each shifted sampled data into a corresponding error detection unit; detecting each data frame of the shifted sampled data through each error detection unit to determine whether the serial port level state corresponding to each stop bit position is high; and in response to the error detection unit detecting that the serial port level state corresponding to the stop bit position of the corresponding shifted sampled data is high, determining the corresponding candidate stop bit position as the correct stop bit position.

[0011] According to one embodiment of this application, the method further includes: monitoring the serial port receiving data to determine the number of consecutive high-level bits in the serial port level state; resetting the serial port receiving end in response to the number of consecutive high-level bits being greater than a preset idle bit threshold, and re-detecting the serial port level state corresponding to the serial port receiving data, taking the first detected low level as the correct start bit position; sampling the serial port receiving data based on the correct start bit position, and storing the sampled data in a fourth buffer; the preset idle bit threshold is determined based on the bit width corresponding to each data frame.

[0012] This application also provides a serial communication data error correction device, the device comprising: a data sampling control module, configured to sample serial port receiving data based on a system clock before the serial port controller initialization is completed, and store the sampled first data in a first buffer; and configured to sample serial port receiving data based on a preset baud rate clock in response to the completion of the serial port controller initialization, and store the sampled third data in a third buffer; a resampling module, configured to resample the first data in the first buffer based on the preset baud rate clock, and store the resampled second data in a second buffer; an error detection analysis module, configured to analyze the second data and the third data in response to detecting that the stop bit position of the third data does not meet a set position condition, and determine the correct stop bit position of the third data; and a shift sampling module, configured to shift sample the second data and the third data based on the correct stop bit position, and store the shift sampled data in a fourth buffer.

[0013] According to one embodiment of this application, the data sampling control module is further configured to: in response to the remaining storage area of ​​the first buffer being able to store the first data, store the sampled first data into the first buffer; in response to the remaining storage area of ​​the first buffer being unable to store the first data, overwrite the earliest first data stored in the first buffer with the newly sampled first data.

[0014] According to one embodiment of this application, the device further includes a stop bit detection module, which is configured to: determine the current stop bit position of the third data based on the bit width of each data frame in the third data and the current start bit position; detect the serial port level state corresponding to the current stop bit position; determine that the stop bit position does not meet the set position condition in response to the serial port level state being low; and determine that the stop bit position meets the set position condition in response to the serial port level state being high.

[0015] According to one embodiment of this application, the error detection analysis module is used to: determine a first stop bit position where the serial port level is high between the current start bit position and the current stop bit position of the data frame; and determine the first stop bit position as the correct stop bit position in response to the fact that the number of the first stop bit positions is one.

[0016] According to one embodiment of this application, the error detection analysis module is further configured to: respond to the fact that there are multiple first stop bit positions, based on the second data, trace backward from each first stop bit position to the corresponding candidate start bit position according to the bit width of the data frame; detect the serial port level state of each candidate start bit position and the previous bit of the candidate start bit position; determine the first stop bit position corresponding to the candidate start bit position where the serial port level state of the previous bit is high and the serial port level state of the current bit is low as the candidate stop bit position; and perform shift sampling on the second data and the third data based on the candidate stop bit position to determine the correct stop bit position.

[0017] According to one embodiment of this application, the error detection analysis module is configured to: in response to the existence of multiple candidate stop bit positions, perform shift sampling on the second data and the third data based on each candidate stop bit position to obtain shift sampling data; input each shift sampling data into a corresponding error detection unit; detect each data frame of the shift sampling data through each error detection unit to determine whether the serial port level state corresponding to each stop bit position is high; and in response to the error detection unit detecting that the serial port level state corresponding to the stop bit position of the corresponding shift sampling data is high, determine the corresponding candidate stop bit position as the correct stop bit position.

[0018] According to one embodiment of this application, the device further includes a reset control module, which is configured to: monitor the serial port receiving data and determine the number of consecutive high-level bits in the serial port level state; in response to the number of consecutive high-level bits being greater than a preset idle bit threshold, reset the serial port receiving end and re-detect the serial port level state corresponding to the serial port receiving data, taking the first detected low level as the correct start bit position; sample the serial port receiving data based on the correct start bit position, and store the sampled data in a fourth buffer; the preset idle bit threshold is determined based on the bit width corresponding to each data frame.

[0019] This application also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method of the above-described embodiments.

[0020] The method of this application embodiment, before the serial port controller initialization is completed, samples the serial port receiving data based on the system clock and stores the sampled first data in a first buffer; in response to the completion of the serial port controller initialization, samples the serial port receiving data based on a preset baud rate clock and stores the sampled third data in a third buffer; resamples the first data in the first buffer based on the preset baud rate clock and stores the resampled second data in a second buffer; in response to detecting that the stop bit position of the third data does not meet the set position condition, analyzes the second data and the third data to determine the correct stop bit position of the third data; based on the correct stop bit position, shifts and samples the second data and the third data, and stores the shifted and sampled data in a fourth buffer. In this way, errors in serial communication data can be corrected in a timely manner, and the data stability of serial communication is improved.

[0021] It should be understood that the teachings of this application are not required to achieve all the beneficial effects described above, but rather that a specific technical solution can achieve a specific technical effect, and other embodiments of this application can also achieve beneficial effects not mentioned above. Attached Figure Description

[0022] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, in which: In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0023] Figure 1 A schematic diagram of the processing flow of the serial communication data error correction method provided in the embodiments of this application is shown; Figure 2 This illustration shows a data waveform when a serial communication data error occurs, as provided in an embodiment of this application. Figure 1 ; Figure 3 This illustration shows a data waveform when a serial communication data error occurs, as provided in an embodiment of this application. Figure 2 ; Figure 4 This illustration shows a data waveform when a serial communication data error occurs, as provided in an embodiment of this application. Figure 3 ; Figure 5 This paper illustrates an application scenario diagram of the serial communication data error correction method provided in an embodiment of this application. Figure 6This illustration shows an optional schematic diagram of the serial communication data error correction device provided in an embodiment of this application; Figure 7 An optional schematic diagram of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0024] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0026] In the following description, the terms "first" and "second" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first" and "second" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0028] The processing flow of the serial communication data error correction method provided in the embodiments of this application is described below. See also... Figure 1 , Figure 1 This is a schematic diagram of the processing flow of the serial communication data error correction method provided in the embodiments of this application, which will be combined with... Figure 1 Steps S101-S105 are explained below.

[0029] Step S101: Before the serial port controller is initialized, the serial port receiving data is sampled based on the system clock, and the sampled first data is stored in the first buffer.

[0030] In some embodiments, the serial port controller may include a UART (Universal Asynchronous Receiver / Transmitter) controller. The system clock may include the internal system clock of the serial port controller. The system clock can be used to sample the received data at a clock frequency higher than the baud rate before serial port initialization is complete. The serial port received data may include a serial bitstream level signal on the RX (receive) pin. The serial port received data may be asynchronous communication data sent by a peripheral to the BMC (Baseboard Management Controller). The first data may include sampled data obtained based on the system clock sampling. A first buffer can be used to continuously store the received data before serial port initialization is complete.

[0031] In step S102, in response to the completion of serial port controller initialization, the serial port receiving data is sampled based on a preset baud rate clock, and the sampled third data is stored in the third buffer.

[0032] In some embodiments, the baud rate clock may include a sampling clock corresponding to the serial communication baud rate. The serial controller's baud rate clock (uart_baud) and the serial controller's system clock (uart_sys) have the following relationship.

[0033] uart_baud = uart_sys / (div×16) Here, div represents frequency division. The system clock of the serial port controller is greater than the baud rate clock, so the RX data of the serial port controller is oversampled before the serial port is initialized. The data is first buffered in the internal first buffer to store the data. It can be seen that the clock frequency is much greater than the baud rate; this sampling method ensures the correctness of the sampled data. The third data can be the data sampled based on the baud rate clock after the serial port initialization is completed. The third buffer can be used to store the sampled data after the serial port initialization is completed.

[0034] Step S103: Resample the first data in the first buffer based on a preset baud rate clock, and store the resampled second data into the second buffer.

[0035] In some embodiments, the second data may include data obtained by resampling the data in the first buffer based on a baud rate clock. The second buffer may be used to store communication data restored from the first buffer.

[0036] Step S104: In response to the detection that the stop position of the third data does not meet the set position condition, the second data and the third data are analyzed to determine the correct stop position of the third data.

[0037] Step S105: Based on the correct stop bit position, shift sampling is performed on the second and third data, and the shifted data is stored in the fourth buffer.

[0038] In some embodiments, the stop bit position may include the bit position of the stop bit in the data frame. The set position condition can be used to determine whether the data frame has a stop bit anomaly due to a misidentification of the start bit. The fourth buffer can be used to provide the CPU with the recovered correct serial communication data. Shift sampling may include adjusting the sampling time based on the re-determined correct stop bit position and re-extracting data. Shift sampling can be used to correct the sampling offset of subsequent data frames caused by a misidentification of the start bit. Specifically, shift sampling, based on the re-determined correct stop bit position, shifts the serial data sampling time forward or backward relative to the original erroneous sampling time, and resamples subsequent data sequentially according to the bit time interval corresponding to the configured baud rate to restore the correct data frame timing.

[0039] As an example, after the BMC powers on but before the serial port controller has finished initializing, the data on the RX pin is sampled based on the system clock. The first sampled data is then cyclically stored in the first buffer according to the first-in-first-out (FIFO) principle. After the serial port controller has finished initializing and the baud rate has been configured, the data on the RX pin is sampled normally based on the baud rate clock, and the third data is stored in the third buffer. At the same time, the first data stored in the first buffer is resampled based on the baud rate clock, and the resampled second data is stored in the second buffer. Subsequently, the stop bit position of the data frame in the third buffer is detected. When a stop bit is detected as low and does not meet the set high-level position condition, the second and third data are analyzed to determine the correct stop bit position. Finally, based on the correct stop bit position, the second and third data are shifted and sampled, and the final correct data sample is input into the fourth buffer. The data in the fourth buffer is the complete serial port receiving data, and the CPU inside the BMC uses the data in the fourth buffer for processing.

[0040] The method described in this application embodiment can achieve the following technical effects: By caching the system clock oversampling data and baud rate clock sampling data before and after serial port controller initialization, a complete sampling record of the initial communication phase of the peripheral is retained. This allows for automatic detection and correction of stop bit anomalies caused by start bit misidentification based on the joint analysis of the second and third data, even when there are differences in the power-on timing between the BMC and the peripheral. This avoids the continuous accumulation of erroneous data frames in subsequent transmissions, improves the robustness and data stability of serial communication, and enhances the performance and robustness of the BMC product.

[0041] By using the circular overwrite mechanism of the first buffer, the oldest historical data is overwritten with new data when the remaining storage area is insufficient. This enables the serial port controller to continuously receive oversampled data sent by peripherals before initialization, ensuring that the buffer always saves the sampling records of the most recent period, and providing a usable historical data basis for resampling and error correction analysis after the serial port initialization is completed.

[0042] By calculating the current stop bit position based on the data frame width and the current start bit position, and detecting the corresponding serial port level status, it is possible to accurately distinguish between a normal high-level stop bit state and an abnormal stop bit missing state. When a first stop bit position with only one high level is detected between the erroneous start bit position and the abnormal stop bit position, this position is directly determined as the correct stop bit position. This allows for timely error correction of abnormal serial port data, avoids the propagation of erroneous data, and shortens data recovery latency.

[0043] When multiple candidate stop bits exist, the algorithm traces back from each first stop bit position according to the bit width based on the second data and verifies the level characteristics of the candidate start bit (high before low). The algorithm then uses the historical complete data obtained by resampling the first buffer to filter the candidate positions, eliminating false candidates that do not conform to the start bit characteristics of the serial port protocol, thus improving the accuracy of error correction and localization.

[0044] By shifting and sampling the second and third data based on multiple candidate stop bit positions, and inputting each shifted sampled data into the corresponding error detection unit for parallel stop bit detection of subsequent data frames, the unique error-free correct channel is automatically identified, ensuring that the sampling timing of the data finally stored in the fourth buffer is the same as the correct stop bit position.

[0045] By continuously monitoring the number of consecutive high-level bits in the serial port receiver data and triggering a serial port receiver reset when the number of idle bits exceeds the threshold set based on the data frame bit width, the first low level detected again is used as the correct start bit position to restore sampling. This allows the correct data frame boundary synchronization reference to be quickly reconstructed after the bus enters an idle state, eliminating the impact of the accumulated sampling offset caused by the misidentification of the start bit on subsequent communication.

[0046] In some embodiments, storing the sampled first data into the first buffer in step S101 may include: storing the sampled first data into the first buffer in response to the remaining storage area of ​​the first buffer being able to store the first data; and overwriting the earliest first data stored in the first buffer with the newly sampled first data in response to the remaining storage area of ​​the first buffer being unable to store the first data.

[0047] In this embodiment, the remaining storage area may include: available storage space in the first buffer that has not yet been occupied by stored data. Overwriting may include: replacing the earliest historical data stored in the first buffer with newly sampled first data after the first buffer is full.

[0048] As an example, it is determined whether the data in the first buffer has overflowed. If it is determined that it has not overflowed, the sampled first data is stored in the first buffer. At this time, it indicates that the first buffer has completely saved all the sampled data of the peripheral device since the initial communication. After the serial port controller is initialized and the baud rate is configured, the first data in the first buffer is resampled according to the configured baud rate clock. The resampled second data is written to the second buffer. Since the data in the second buffer is extracted according to the standard bit width from the first low level sent by the peripheral device, the second buffer stores the first correct start bit position during the initial communication of the peripheral device. At this time, the third data sampled normally based on the baud rate clock in the third buffer may have missed the true first start bit position during BMC initialization, and the data bits of a subsequent frame of data may be misidentified as the start bit.

[0049] Conversely, if it is determined that the first buffer is full and overflowing, it indicates that the amount of data sent by the peripheral device exceeds the capacity of the first buffer. The first buffer adopts a cyclic sampling and writing method, replacing the earliest historical data stored in the first buffer with the first sampled data. After the serial port controller is initialized and the baud rate is configured, the stop bit position of the data frame in the third buffer can be detected. When an abnormal stop bit position is detected, since the first and second buffers can only store part of the historical data before the current erroneous frame, the relevant data of the previous frame stored in the first and second buffers can be retrieved and analyzed in combination with the sampling information of the current frame to restore the correct stop bit position and correct subsequent data, ensuring that the error does not continue to accumulate and propagate.

[0050] In some embodiments, the method further includes: determining the current stop position of the third data based on the bit width of each data frame in the third data and the current start position; detecting the serial port level state corresponding to the current stop position; determining that the stop position does not meet the set position condition in response to the serial port level state being low; and determining that the stop position meets the set position condition in response to the serial port level state being high.

[0051] In this embodiment, a data frame may include a basic serial communication transmission unit consisting of a start bit, data bits, an optional parity bit, and a stop bit arranged in a fixed timing sequence. The bit width may include the total number of bits occupied by each of the start bit, data bits, parity bit, and stop bit in the serial data frame. Specifically, the data frame consists of a start bit, data bits, parity bit, and stop bit.

[0052] Start bit: occupies 1 bit, active low.

[0053] Data bits: can be 5 bits, 6 bits, 7 bits, or 8 bits, with 8 bits being the most common.

[0054] Parity bit: odd parity, even parity, no parity, occupies 1 bit, no parity bit is occupied when there is no parity bit. Even parity: the parity rule is that the number of 1s in the data bits and the parity bit is even. Odd parity: the parity rule is that the number of 1s in the data bits and the parity bit is odd. No parity: that is, there is no parity bit.

[0055] Stop bits: occupy 1 bit, 1.5 bits, or 2 bits, active high.

[0056] The current start bit position can include: the sampling time of the start bit of the data frame currently detected by the serial port receiver. The current stop bit position can include: the sampling time of the stop bit determined based on the current start bit position and the bit width of the data frame, i.e., the position where a stop bit anomaly is currently detected. The serial port level state can include: the voltage level signal state of the RX pin of the serial port receiver at the sampling time. A low level can include: a voltage level signal of the RX pin of the serial port receiver in a logic 0 state. A high level can include: a voltage level signal of the RX pin of the serial port receiver in a logic 1 state.

[0057] As an example, data is read frame by frame from the third buffer. Based on the currently identified start bit position and the bit width of the data frame, the current stop bit position is determined. Next, the serial port level corresponding to the current stop bit position is checked. If the serial port level is low, it is determined that the stop bit position does not meet the set position condition, indicating a sampling error in the current start bit identification. If the serial port level is high, it is determined that the stop bit position meets the set position condition, indicating that the current data frame has been sampled correctly and can be directly stored in the fourth buffer for the CPU to read.

[0058] In some embodiments, the analysis of the second data and the third data in step S104 to determine the correct stop bit position of the third data includes: determining a first stop bit position where the serial port level is high between the current start bit position and the current stop bit position of the data frame; and determining the first stop bit position as the correct stop bit position in response to the fact that the number of first stop bit positions is one.

[0059] In this embodiment, the correct stop bit position may include: the position of the actual stop bit in the data frame, uniquely determined after analysis. The correct stop bit position is the reference benchmark for subsequent shift sampling to recover the correct data frame. The first stop bit position may include: all candidate stop bit positions where the serial port level is high between the current start bit position and the current stop bit position. The number may be the total number of first stop bit positions.

[0060] As an example, such as Figure 2 As shown, when a data frame includes a 1-bit start bit, 8-bit data bits, and a 1-bit stop bit, the `right_start` position indicates the correct start bit position, the `stop_no` position indicates the current stop bit position, the `error_start` position indicates the current start bit position, and the `right_stop` position indicates the correct stop bit position. Bit 14 represents the current stop bit position. When no stop bit is detected at bit 14, there must be a `right_stop` position, an `error_start` position, and a `right_start` position before bit 14. Therefore, the `right_stop` position representing the correct stop bit position must exist between `error_start` and `stop_no`, while the `right_start` position representing the correct start bit position must exist before `error_start`. First, the data between `error_start` and `stop_no` needs to be analyzed to determine if a unique `right_stop` position can be found. If there is only one stop bit position with a high serial port level between `error_start` and `stop_no`, then the 11th bit corresponding to the high level must be the `right_stop` position.

[0061] In some embodiments, the method further includes: responding to the fact that there are multiple first stop bit positions, tracing back from each first stop bit position to the corresponding candidate start bit position according to the bit width of the data frame based on the second data; detecting the serial port level state of each candidate start bit position and the previous bit of the candidate start bit position; determining the first stop bit position corresponding to the candidate start bit position where the serial port level state of the previous bit is high and the serial port level state of the current bit is low as the candidate stop bit position; and performing shift sampling on the second data and the third data based on the candidate stop bit position to determine the correct stop bit position.

[0062] In this embodiment, tracing backwards can be used to determine the corresponding candidate start bit position from the candidate stop bit position in the reverse direction of the time axis according to the data frame bit width. The candidate start bit position can include: the theoretical start bit position obtained by tracing backwards from each first stop bit position according to the bit width. The previous bit can include: the sampling position of the bit preceding the candidate start bit position.

[0063] As an example, such as Figure 3 As shown, when there are multiple first stop bit positions with a high serial port level (such as bits 6, 7, 8, 9, 10, 11, 12, and 13) between the error_start position (current start bit position) and the stop_no position (current stop bit position), the accurate right_stop position (correct stop bit position) cannot be uniquely determined solely by a high level. In this case, based on the second data, the system traces backward from each first stop bit position to the corresponding candidate start bit position according to the bit width of the data frame. For example, tracing backward 9 positions from bit 13 to bit 4, the serial port level status of bit 4 and its preceding bit 3 is checked. Since bit 4 is not low, it does not meet the requirement of a low start bit, so bit 13 is excluded. Similarly, tracing backward 9 positions from bit 12 to bit 3, the serial port level status of bit 3 and its preceding bit 2 is checked. Since bit 3 is not low, bit 12 is excluded. Starting from bit 11, trace back 9 positions to bit 2, and check the serial port level status of bit 2 and its preceding bit 1. Since bit 1 is high and bit 2 is low, matching the start-bit high-to-low level characteristic, the position corresponding to bit 11 is determined as the candidate stop bit position. The determination process for other first stop bit positions is similar and will not be repeated here. Based on each candidate stop bit position, the second and third data are shifted and sampled, and each shifted sampled data is input into the corresponding error detection unit. The correct stop bit position is determined by the stop bit detection of subsequent data frames.

[0064] In some embodiments, shift sampling is performed on the second data and the third data based on the candidate stop bit positions to determine the correct stop bit position, including: in response to the existence of multiple candidate stop bit positions, shift sampling is performed on the second data and the third data based on each candidate stop bit position to obtain shift sampling data; each shift sampling data is input into a corresponding error detection unit; each error detection unit detects each data frame of the shift sampling data to determine whether the serial port level state corresponding to each stop bit position is high; in response to the error detection unit detecting that the serial port level state corresponding to the stop bit position of the corresponding shift sampling data is high, the corresponding candidate stop bit position is determined as the correct stop bit position.

[0065] In this embodiment, the shift sampling data may include channel data obtained by shifting and sampling the second and third data based on each candidate stop position. The shift sampling data can be input in parallel into the corresponding error detection unit for stop position detection in subsequent data frames. The error detection unit can be used as a verification channel for stop position detection in subsequent data frames of the shift sampling data. Specifically, the error detection unit can filter out candidate stop positions without anomalies in parallel.

[0066] As an example, such as Figure 4 As shown, although there are 8 high-level signals, there are at most 4 possible right_stop positions, i.e., candidate stop positions. When multiple candidate stop positions exist, the second and third data are shift-sampled based on each candidate stop position and the corresponding right_start position (correct start position), resulting in 4 channels of shift-sampled data. These 4 channels of shift-sampled data are input to the first, second, third, and fourth error detection units, respectively. Each error detection unit checks the serial port level corresponding to the stop position in each subsequent data frame of the corresponding shift-sampled data. In the 4 error detection channels, only the channel corresponding to the correct stop position has a continuously high stop position in subsequent data frames; the other 3 channels will show a low stop position in subsequent detections. When an error detection unit detects a high serial port level corresponding to the stop position of its corresponding shift-sampled data, the candidate stop position corresponding to that error detection unit is determined as the correct stop position. Furthermore, the error-free shift-sampled data from the 4 error detection channels can be output via a selector and stored in the fourth buffer.

[0067] In some embodiments, the method further includes: monitoring the serial port receiving data to determine the number of consecutive high-level bits in the serial port level state; resetting the serial port receiving end in response to the number of consecutive high-level bits being greater than a preset idle bit threshold, and re-detecting the serial port level state corresponding to the serial port receiving data, taking the first detected low level as the correct start bit position; sampling the serial port receiving data based on the correct start bit position, and storing the sampled data into a fourth buffer.

[0068] In this embodiment, the preset idle bit threshold is determined based on the bit width corresponding to each data frame. Monitoring can be a continuous monitoring of the level state of the third data corresponding to the serial port receiver data. Continuous high level can include: a continuous bit sequence in the serial port receiver data that is continuously in a logic 1 state. Continuous high level indicates that the serial bus is in an idle waiting state. Bit count can include: the number of bits continuously occupied by the continuous high level. The idle bit threshold can include: an upper limit of the number of consecutive high level bits preset based on the data frame bit width to determine the serial bus idle. Taking a data frame with a bit width of 10 bits as an example, the corresponding data bit width is 8 bits, so the idle bit threshold can be set to 8 bits. Reset can include: clearing and resetting the serial port receiver state machine and sampling timing. Reset can eliminate the accumulated sampling offset caused by the misidentification of the start bit. The correct start bit position can be the sampling position corresponding to the first low level detected after reset.

[0069] As an example, during continuous serial data reception, the error detection and analysis unit checks frame by frame whether the stop bit of the third data is at the stop_no position. If the stop_no position is not detected, it is determined that the current data frame is sampled correctly, and the data is directly stored normally into the fourth buffer for the CPU to read. If the data actually contains errors but the stop_no position is never triggered, the unit will continuously monitor the number of consecutive high-level bits in the third data corresponding to the serial port receiver. When it is determined that the number of consecutive high-level bits is greater than the preset idle bit threshold, it is confirmed that there is an idle bit in the serial bus. At this time, the serial port receiver is reset. After the reset, the serial port level status of the data at the serial port receiver is re-detected, and the first low level detected is taken as the correct start bit position. Sampling is restarted based on the correct start bit position, and the subsequently sampled data is stored into the fourth buffer.

[0070] Figure 5 The diagram illustrates an application scenario of the serial communication data error correction method provided in this application embodiment.

[0071] like Figure 5 The diagram illustrates the serial port adaptive synchronous error correction process applied in a BMC system. The BMC internally includes a data sampling control unit, a first buffer area, a second buffer, a third buffer, a data error detection and correction verification unit, a detection status register, a serial port control processing module, first to fourth error detection units, a selector, a fourth buffer, and a CPU. The BMC sends data via the TX pin and receives data via the RX pin.

[0072] The data sampling control unit is used to process the data from the system clock sampling and the baud rate clock sampling, and writes the corresponding data into the first buffer and the third buffer respectively.

[0073] The first buffer stores the system clock sampled data; the second buffer stores the data resampled from the first buffer according to the baud rate; the third buffer stores the sampled data after serial port initialization. The fourth buffer stores the final data after error correction.

[0074] The data error detection and correction verification unit is used to identify abnormal locations where stop bits are missing in the data frame, and to perform backtracking analysis and shift error detection based on the data in each buffer. At the same time, the candidate correct stop bit flags obtained from the analysis are stored in the detection status register.

[0075] The detection status register is a flag register used to store the candidate correct stop bit flags.

[0076] The first, second, third, and fourth error detection units perform stop bit detection on the shift sampling data channels corresponding to each candidate stop bit position in subsequent frames to determine the correct channel without errors.

[0077] The serial port control processing module is used to handle the logic of the entire serial port controller, including the sampling control of received data, the management of data flow between buffers, and the transition of the internal receiving state machine.

[0078] Understandable. Figure 5 The application scenarios of the serial communication data error correction method in this application are only some exemplary implementations in the embodiments of this application. The application scenarios of the serial communication data error correction method in the embodiments of this application include, but are not limited to, those of... Figure 5 The application scenarios of the serial communication data error correction method shown are illustrated.

[0079] The exemplary structure of the software modules included in the serial communication data error correction device 90 provided in this application embodiment will be further described below. In some embodiments, such as Figure 6 As shown, the serial communication data error correction device 90 may include: The data sampling control module 901 is used to sample the data of the serial port receiving end based on the system clock before the serial port controller initialization is completed, and to store the sampled first data into the first buffer; and to sample the data of the serial port receiving end based on the preset baud rate clock in response to the completion of the serial port controller initialization, and to store the sampled third data into the third buffer. The resampling module 902 is used to resample the first data in the first buffer based on a preset baud rate clock, and store the resampled second data into the second buffer. The error detection and analysis module 903 is used to analyze the second and third data in response to the detection that the stop position of the third data does not meet the set position conditions, and to determine the correct stop position of the third data. The shift sampling module 904 is used to shift and sample the second and third data based on the correct stop bit position, and store the shifted and sampled data into the fourth buffer.

[0080] In some embodiments, the data sampling control module 901 is further configured to: store the sampled first data into the first buffer in response to the remaining storage area of ​​the first buffer being able to store the first data; and overwrite the earliest first data stored in the first buffer with the newly sampled first data in response to the remaining storage area of ​​the first buffer being unable to store the first data.

[0081] In some embodiments, the serial communication data error correction device 90 further includes a stop bit detection module, which is used to: determine the current stop bit position of the third data based on the bit width of each data frame in the third data and the current start bit position; detect the serial port level state corresponding to the current stop bit position; determine that the stop bit position does not meet the set position condition in response to the serial port level state being low; and determine that the stop bit position meets the set position condition in response to the serial port level state being high.

[0082] In some embodiments, the error detection analysis module 903 is configured to: determine a first stop bit position where the serial port level is high between the current start bit position and the current stop bit position of the data frame; and determine the first stop bit position as the correct stop bit position in response to the fact that the number of first stop bit positions is one.

[0083] In some embodiments, the error detection analysis module 903 is further configured to: respond to the fact that there are multiple first stop bit positions, trace backward from each first stop bit position to the corresponding candidate start bit position based on the second data according to the bit width of the data frame; detect the serial port level state of each candidate start bit position and the previous bit of the candidate start bit position; determine the first stop bit position corresponding to the candidate start bit position where the serial port level state of the previous bit is high and the serial port level state of the current bit is low as the candidate stop bit position; and perform shift sampling on the second data and the third data based on the candidate stop bit position to determine the correct stop bit position.

[0084] In some embodiments, the error detection and analysis module 903 is configured to: in response to the existence of multiple candidate stop bit positions, shift and sample the second data and the third data based on each candidate stop bit position to obtain shift sampled data; input each shift sampled data into the corresponding error detection unit; detect each data frame of the shift sampled data through each error detection unit to determine whether the serial port level state corresponding to each stop bit position is high; and in response to the error detection unit detecting that the serial port level state corresponding to the stop bit position of the corresponding shift sampled data is high, determine the corresponding candidate stop bit position as the correct stop bit position.

[0085] In some embodiments, the serial communication data error correction device 90 further includes a reset control module, which is configured to: monitor the serial port receiving data and determine the number of consecutive high-level bits in the serial port level state; in response to the number of consecutive high-level bits being greater than a preset idle bit threshold, reset the serial port receiving end and re-detect the serial port level state corresponding to the serial port receiving data, taking the first detected low level as the correct start bit position; sample the serial port receiving data based on the correct start bit position and store the sampled data in a fourth buffer; the preset idle bit threshold is determined based on the bit width corresponding to each data frame.

[0086] It should be noted that the description of the device in this application embodiment is similar to the description of the method embodiment above, and has similar beneficial effects as the method embodiment, therefore it will not be repeated. For any technical details not covered in the serial communication data error correction device provided in this application embodiment, please refer to... Figures 1 to 5 The meaning is understood in accordance with the description of any of the accompanying drawings.

[0087] According to embodiments of this application, this application also provides an electronic device and a non-transitory computer-readable storage medium.

[0088] Figure 7 A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of this application is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the application described and / or claimed herein.

[0089] like Figure 7 As shown, the electronic device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in ROM 802 or a computer program loaded into RAM 803 from storage unit 808. RAM 803 can also store various programs and data required for the operation of the electronic device 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via bus 804. I / O interface 805 is also connected to bus 804.

[0090] Multiple components in electronic device 800 are connected to I / O interface 805, including: input unit 806, such as keyboard, mouse, etc.; output unit 807, such as various types of displays, speakers, etc.; storage unit 808, such as hard disk, optical disk, etc.; and communication unit 809, such as network card, modem, wireless transceiver, etc. Communication unit 809 allows electronic device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0091] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as the serial communication data error correction method. For example, in some embodiments, the serial communication data error correction method can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the serial communication data error correction method described above can be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform a serial communication data error correction method by any other suitable means (e.g., by means of firmware).

[0092] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0093] The program code used to implement the methods of this application may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0094] In the context of this application, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0095] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0096] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0097] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0098] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0099] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0100] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for error correction of serial communication data, characterized in that, The method comprises: Before the initialization of the serial port controller is completed, sampling serial port receiving end data based on a system clock, and storing first data obtained by sampling into a first buffer; in response to the initialization of the serial port controller being completed, sampling serial port receiving end data based on a preset baud rate clock, and storing third data obtained by sampling into a third buffer; resampling first data in the first buffer based on the preset baud rate clock, and storing second data obtained by resampling into a second buffer; in response to detecting that a stop bit position of the third data does not satisfy a set position condition, analyzing the second data and the third data to determine a correct stop bit position of the third data; based on the correct stop bit position, shift sampling the second data and the third data, and storing data obtained by shift sampling into a fourth buffer.

2. The method of claim 1, wherein, The first data obtained by sampling is stored into the first buffer, comprising: in response to the remaining storage area of the first buffer being able to store first data, storing the first data obtained by sampling into the first buffer; in response to the remaining storage area of the first buffer being unable to store first data, overwriting the first data obtained by new sampling with the first data stored in the first buffer for the longest time.

3. The method of claim 1, wherein, The method further comprises: based on the bit width of each data frame in the third data and the current start bit position, determining the current stop bit position of the third data; detecting a serial port level state corresponding to the current stop bit position; in response to the serial port level state being a low level, determining that the stop bit position does not satisfy the set position condition; in response to the serial port level state being a high level, determining that the stop bit position satisfies the set position condition.

4. The method of claim 3, wherein, The analysis of the second data and the third data to determine the correct stop bit position of the third data comprises: determining a first stop bit position at which the serial port level state is a high level between the current start bit position and the current stop bit position of the data frame; in response to the number of the first stop bit positions being one, determining the first stop bit position as the correct stop bit position.

5. The method of claim 4, wherein, The method further comprises: in response to the number of the first stop bit positions being multiple, based on the second data, tracing back from each first stop bit position to a corresponding candidate start bit position according to the bit width of the data frame; detecting the serial port level state of each candidate start bit position and the previous bit of the candidate start bit position; determining a first stop bit position corresponding to a candidate start bit position as a candidate stop bit position, where the serial port level state of the previous bit is a high level and the serial port level state of the current bit is a low level; based on the candidate stop bit position, shift sampling the second data and the third data to determine the correct stop bit position.

6. The method of claim 5, wherein, The shift sampling of the second data and the third data based on the candidate stop bit position to determine the correct stop bit position comprises: in response to there being multiple candidate stop bit positions, respectively shift sampling the second data and the third data based on each candidate stop bit position to obtain shift sampling data; The respective shift sample data is input into a corresponding error detection unit; The error detection unit detects each data frame of the shift sample data to determine whether the stop bit position corresponds to a high level state of the serial port; In response to the error detection unit detecting that the stop bit position of the corresponding shift sample data corresponds to a high level state of the serial port, the corresponding candidate stop bit position is determined as the correct stop bit position.

7. The method of claim 1, wherein, The method further comprises: monitoring the serial port receiving end data to determine the number of consecutive high level bits; in response to the number of consecutive high level bits being greater than a preset idle bit threshold, resetting the serial port receiving end and re-detecting the serial port receiving end data to determine the first low level bit as the correct start bit position; based on the correct start bit position, sampling the serial port receiving end data and storing the sampled data in a fourth buffer; the preset idle bit threshold is determined based on the bit width corresponding to each data frame.

8. A serial communication data error correction apparatus, characterized by comprising: The device comprises: a data sampling control module configured to sample serial port receiving end data based on a system clock before initialization of a serial port controller is completed, and store first data obtained by sampling in a first buffer; and in response to the initialization of the serial port controller being completed, sample serial port receiving end data based on a preset baud rate clock, and store third data obtained by sampling in a third buffer; a resampling module configured to resample the first data in the first buffer based on the preset baud rate clock, and store second data obtained by resampling in a second buffer; an error detection analysis module configured to, in response to detecting that a stop bit position of the third data does not satisfy a set position condition, analyze the second data and the third data to determine a correct stop bit position of the third data; a shift sampling module configured to, based on the correct stop bit position, shift sample the second data and the third data, and store the data obtained by shift sampling in a fourth buffer.

9. The apparatus of claim 8, wherein, The data sampling control module is further configured to: in response to the remaining storage area of the first buffer being able to store the first data, store the first data obtained by sampling in the first buffer; in response to the remaining storage area of the first buffer being unable to store the first data, overwrite the first data stored in the first buffer earliest with newly sampled first data.

10. The apparatus of claim 8, wherein, The device further comprises a stop bit detection module configured to: determine a current stop bit position of the third data based on the bit width of each data frame in the third data and a current start bit position; detect a serial port level state corresponding to the current stop bit position; in response to the serial port level state being a low level, determine that the stop bit position does not satisfy the set position condition; in response to the serial port level state being a high level, determine that the stop bit position satisfies the set position condition.

11. The apparatus of claim 10, wherein, The error detection analysis module is configured to: determine a first stop bit position between the current start bit position and the current stop bit position of the data frame, at which the serial port level state is a high level; In response to the fact that the number of the first stop position is one, the first stop position is determined as the correct stop position.

12. The apparatus of claim 11, wherein, The error detection and analysis module is also used for: In response to the fact that there are multiple first stop bit positions, based on the second data, each first stop bit position is traced backward to the corresponding candidate start bit position according to the bit width of the data frame; Detect the serial port level status of each candidate start bit position and the bit preceding the candidate start bit position; The first stop position corresponding to the candidate start position where the serial port level of the previous bit is high and the serial port level of the current bit is low is determined as the candidate stop position. Based on the candidate stop position, the second data and the third data are shifted and sampled to determine the correct stop position.

13. The apparatus of claim 12, wherein, The error detection and analysis module is used for: In response to the existence of multiple candidate stop bit positions, the second data and the third data are shifted and sampled based on each candidate stop bit position to obtain shifted sampled data; Each shifted sample data is input into the corresponding error detection unit; Each error detection unit detects each data frame of the shifted sampling data to determine whether the serial port level corresponding to each stop bit position is high. In response to the error detection unit detecting that the serial port level corresponding to the stop position of the corresponding shift sampling data is high, the corresponding candidate stop position is determined as the correct stop position.

14. The apparatus of claim 8, wherein, The device further includes a reset control module, the reset control module being used for: The serial port receiving end data is monitored to determine the number of bits where the serial port level is continuously high. In response to the number of consecutive high-level bits being greater than a preset idle bit threshold, the serial port receiver is reset, and the serial port level status corresponding to the data received at the serial port receiver is re-detected, with the first detected low level being taken as the correct start bit position. Based on the correct start bit position, the serial port receiving data is sampled, and the sampled data is stored in the fourth buffer. The preset idle bit threshold is determined based on the bit width corresponding to each data frame.

15. An electronic device, comprising: include: At least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.

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