Hot plug detection circuit, control chip and electronic device

Abstract

This disclosure relates to the field of integrated circuit technology, and more particularly to a hot-plug detection circuit, a control chip, and an electronic device. The input terminal of the hot-plug detection circuit is connected to the transmitting end of a signal transmission link. The signal transmission link includes a transmitting end, a transmission line, and a receiving end. The transmission line is pluggable to both the transmitting end and the receiving end. The hot-plug detection circuit is used to: determine a second differential positive voltage based on the difference between a first differential positive voltage and a first preset voltage at the transmitting end; determine a second differential negative voltage based on the difference between a first differential negative voltage and a second preset voltage; and generate a hot-plug flag signal based on the second differential positive voltage and the second differential negative voltage. The hot-plug detection circuit of this disclosure does not occupy additional port resources, is compatible with both DC-coupled and AC-coupled transmission, and can detect both insertion and removal of the transmission line at the transmitting end and at the receiving end.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a hot-plug detection circuit, a control chip, and an electronic device. Background Technology

[0002] The core necessity of SerDes Transmitter (TX) hot-plug detection lies in its ability to enable proactive source control and early shutdown of TX to protect both the peer chip and its own chip. It can also reduce design costs through pin reuse. At the same time, this function can be linked with high-speed protocols such as Peripheral Component Interconnect Express (PCIe), High Definition Multimedia Interface (HDMI), and Non-Volatile Memory Express (NVMe) to achieve 24 / 7 operation and maintenance and reliable switching of high-speed links. It is a key design feature for application scenarios such as host → Add-in card and source → display / backplane.

[0003] In existing technologies, such as HDMI's TX-side hot-plug detection (HPD) function, additional pins are required to implement the HPD function, consuming interface resources. When implementing HPD functionality on the TX side, it is sometimes necessary to simultaneously ensure compatibility with DC coupling (such as...). Figure 1 (as shown) and AC coupling (such as) Figure 2 The transmission mode shown may also require the circuit to detect both the insertion and removal status of the cable at the TX end (e.g., ...). Figure 3 As shown), it can also detect the insertion / removal status of the cable at the receiving end (Receiver, RX) (e.g. Figure 4 (As shown).

[0004] In long-distance transmission scenarios, it is quite difficult to detect cable insertion and removal at the RX end from the TX end because the signal to be detected is severely attenuated and easily interfered with.

[0005] Therefore, it is necessary to propose a hot-plug detection scheme to reduce port resource consumption, be compatible with both DC-coupled and AC-coupled transmission modes, and simultaneously realize hot-plug detection at both the transmitting and receiving ends. Summary of the Invention

[0006] In view of this, this disclosure proposes a hot-plug detection circuit, the input terminal of which is connected to the transmitting end of a signal transmission link, wherein the signal transmission link includes a transmitting end, a transmission line, and a receiving end, and the transmission line is pluggable to both the transmitting end and the receiving end, wherein the hot-plug detection circuit is used for:

[0007] Receive the first differential positive voltage and the first differential negative voltage from the transmitting end;

[0008] A second differential positive voltage is determined based on the voltage difference between the first differential positive voltage and the first preset voltage, and a second differential negative voltage is determined based on the voltage difference between the first differential negative voltage and the second preset voltage, wherein the first preset voltage and the second preset voltage are related to the voltage swing of the transmitting end when the transmission link is normally connected;

[0009] A hot-plug flag signal is generated based on the second differential positive voltage and the second differential negative voltage. The hot-plug flag signal is used to determine whether a hot-plug has occurred between the transmission line and the transmitting end and / or the receiving end.

[0010] In one possible implementation, the hot-plug detection circuit includes an analog subtraction module, a reference voltage generation module, a first comparator, a second comparator, and / or logic circuitry, wherein...

[0011] The analog subtraction module is used to generate the second differential positive voltage, the second differential negative voltage, and the common-mode voltage of the second differential positive voltage and the second differential negative voltage.

[0012] The reference voltage generation module is used to generate a positive reference voltage and a negative reference voltage based on the common-mode voltage of the second differential positive voltage and the second differential negative voltage.

[0013] The first positive input terminal of the first comparator and the first positive input terminal of the second comparator are used to receive the second differential positive voltage.

[0014] The second positive input terminal of the first comparator and the second negative input terminal of the second comparator are used to receive the positive reference voltage.

[0015] The first negative input terminal of the first comparator and the first negative input terminal of the second comparator are used to receive the second differential negative voltage.

[0016] The second negative input terminal of the first comparator and the second positive input terminal of the second comparator are used to receive the negative reference voltage.

[0017] The outputs of the first comparator and the second comparator are respectively connected to the two inputs of the OR logic circuit.

[0018] The output terminal of the OR logic circuit is used to output the hot-plug flag signal.

[0019] In one possible implementation, the hot-plug detection circuit further includes a glitch elimination circuit for eliminating glitch signals in the hot-plug flag signal.

[0020] In one possible implementation, the analog subtraction module includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first current source, a second current source, a third current source, a fourth current source, a fifth current source, a first voltage source, a second voltage source, a first switch, a second switch, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein,

[0021] The first terminal of the first resistor and the first terminal of the second resistor are respectively used to receive the first differential positive voltage and the first differential negative voltage.

[0022] The second end of the first resistor is connected to the first end of the first switch, the first end of the first transistor, and the positive terminal of the first current source.

[0023] The second end of the second resistor is connected to the first end of the second switch, the first end of the second transistor, and the positive terminal of the second current source.

[0024] The second terminals of the first switch and the second switch are both connected to the negative terminal of the third current source, and the positive terminal of the third current source is grounded.

[0025] The gates of the first transistor and the second transistor are both connected to the positive terminal of the first voltage source, and the negative terminal of the first voltage source is grounded.

[0026] The negative terminal of the first current source, the negative terminal of the second current source, the first terminal of the third transistor, and the first terminal of the fourth transistor are connected.

[0027] The gates of the third transistor and the fourth transistor, the first terminal of the third resistor, and the first terminal of the fourth resistor are connected to output the common-mode voltage of the second differential positive voltage and the second differential negative voltage.

[0028] The second terminal of the third transistor, the second terminal of the third resistor, and the first terminal of the fifth transistor are connected to output the second differential negative voltage.

[0029] The second terminal of the fourth transistor, the second terminal of the fourth resistor, and the first terminal of the sixth transistor are connected to output the second differential positive voltage.

[0030] The gates of the fifth transistor and the sixth transistor are both connected to the positive terminal of the second voltage source, and the negative terminal of the second voltage source is grounded.

[0031] The second terminal of the fifth transistor is connected to the second terminal of the second transistor and the negative terminal of the fourth current source.

[0032] The second terminal of the sixth transistor is connected to the second terminal of the first transistor and the negative terminal of the fifth current source.

[0033] The positive terminals of the fourth current source and the fifth current source are both grounded.

[0034] In one possible implementation, the first transistor, the second transistor, the third transistor, and the fourth transistor are all PMOS transistors, and the fifth transistor and the sixth transistor are all NMOS transistors.

[0035] In one possible implementation, at least one of the first resistor, the second resistor, the third resistor, and the fourth resistor is an adjustable resistor.

[0036] In one possible implementation, the resistance values ​​of the first resistor and the second resistor are greater than the terminating resistance of the transmission line.

[0037] In one possible implementation, the switching control signal of the first switch is in phase with the first differential positive voltage, and the switching control signal of the second switch is in phase with the first differential negative voltage.

[0038] In one possible implementation, the signal transmission link is a high-speed serial link, the transmitting end includes a serializer, and the receiving end includes a deserializer.

[0039] According to one aspect of this disclosure, a control chip is provided, the control chip including the aforementioned hot-plug detection circuit.

[0040] According to one aspect of this disclosure, an electronic device is provided, the electronic device including the control chip described above.

[0041] The hot-plug detection circuit of this embodiment is directly connected to the transmitting end of the signal transmission link, without requiring additional port resources. By receiving the first differential positive voltage and the first differential negative voltage of the transmitting end, it determines the second differential positive voltage and the second differential negative voltage, and generates a hot-plug flag signal based on the second differential positive voltage and the second differential negative voltage to determine whether the transmission line has been hot-plugged with the transmitting end and / or the receiving end. The hot-plug detection circuit of this embodiment does not occupy additional port resources, is compatible with DC coupling and AC coupling transmission, and can detect both the insertion and removal of the transmission line at the transmitting end and the insertion and removal of the transmission line at the receiving end.

[0042] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0043] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0044] Figure 1 A schematic diagram of a DC-coupled transmission architecture in related technologies is shown.

[0045] Figure 2 A schematic diagram of the AC-coupled transmission architecture in related technologies is shown.

[0046] Figure 3 A schematic diagram of TX-end cable insertion and removal in related technologies is shown.

[0047] Figure 4 A schematic diagram of RX-end cable insertion and removal in related technologies is shown.

[0048] Figure 5 A schematic diagram of a hot-plug detection circuit according to an embodiment of the present disclosure is shown.

[0049] Figure 6 A schematic diagram of a hot-plug detection circuit according to an embodiment of the present disclosure is shown.

[0050] Figure 7 A schematic diagram of the circuit structure of an analog subtraction module according to an embodiment of the present disclosure is shown.

[0051] Figure 8 A waveform diagram of a relevant node is shown in the hot-plug detection circuit according to an embodiment of the present disclosure when a plugging or unplugging occurs at the transmitting end of a signal transmission link.

[0052] Figure 9 A waveform diagram of a relevant node is shown in the hot-plug detection circuit according to an embodiment of the present disclosure when a plugging or unplugging occurs at the receiving end of a signal transmission link. Detailed Implementation

[0053] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0054] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0055] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0056] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments without departing from the teachings of the inventive concept. The term "exemplary" as used herein means "serving as an example, embodiment, or illustration." Any embodiment illustrated herein as "exemplary" is not necessarily to be construed as superior to or better than other embodiments.

[0057] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0058] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.

[0059] Please see Figure 5 , Figure 5 A schematic diagram of a hot-plug detection circuit according to an embodiment of the present disclosure is shown.

[0060] like Figure 5As shown, the input terminal of the hot-plug detection circuit 20 is connected to the transmitting end 110 of the signal transmission link 10. The signal transmission link 10 includes a transmitting end 110, a transmission line 120, and a receiving end 130. The transmission line 120 is pluggable to both the transmitting end 110 and the receiving end 130. The hot-plug detection circuit 20 is used for:

[0061] Receive the first differential positive voltage TXP and the first differential negative voltage TXN from the transmitting end 110;

[0062] The second differential positive voltage is determined based on the difference between the first differential positive voltage TXP and the first preset voltage, and the second differential negative voltage is determined based on the difference between the first differential negative voltage TXN and the second preset voltage. The first preset voltage and the second preset voltage are related to the voltage swing of the transmitting end 110 when the transmission link is normally connected.

[0063] A hot-plug flag signal is generated based on the second differential positive voltage and the second differential negative voltage. The hot-plug flag signal is used to determine whether a hot-plug has occurred between the transmission line 120 and the transmitting end 110 and / or the receiving end 130.

[0064] The hot-plug detection circuit 20 of this embodiment is directly connected to the transmitting end 110 of the signal transmission link 10, without requiring additional port resources. By receiving the first differential positive voltage TXP and the first differential negative voltage TXN of the transmitting end 110, it determines the second differential positive voltage and the second differential negative voltage, and generates a hot-plug flag signal based on the second differential positive voltage and the second differential negative voltage to determine whether hot-plugging has occurred between the transmission line 120 and the transmitting end 110 and / or the receiving end 130. The hot-plug detection circuit 20 of this embodiment does not occupy additional port resources, is compatible with DC coupling and AC coupling transmission, and can detect both the insertion and removal of the transmission line 120 at the transmitting end 110 and the insertion and removal of the transmission line 120 at the receiving end 130.

[0065] For example, voltage swing can refer to the amplitude of signal voltage swing in a circuit, that is, the difference between the highest and lowest levels of the signal, and is a parameter for measuring the dynamic range of the circuit's output signal.

[0066] It should be noted that the specific magnitudes of the second differential positive voltage and the second differential negative voltage are not limited in the embodiments of this disclosure. Their specific magnitudes can be adaptively adjusted by the preset amplification factor in the hot-plug detection circuit. The hot-plug flag signal can be determined based on the magnitude relationship between the second differential positive voltage and the second differential negative voltage, or the magnitude relationship between the difference between the second differential positive voltage and the second differential negative voltage and the difference between the preset reference voltage pair.

[0067] This disclosure does not limit the specific type of transmission link, nor does it limit the specific implementation of the transmitting end 110, the receiving end 130, and the transmission line 120. Those skilled in the art can set them according to actual conditions and needs. For example, the transmission link includes a high-speed serial link, the transmitting end 110 includes a serializer, and the receiving end 130 includes a deserializer.

[0068] The embodiments disclosed herein do not limit the specific values ​​of the first preset voltage, the second preset voltage, and the preset amplification factor. Those skilled in the art can set them according to actual conditions and needs. For example, the first preset voltage and the second preset voltage can be V_det and -V_det, respectively, wherein V_det can be the voltage swing of the transmitting end when the transmission link is normally connected.

[0069] The specific implementation of the hot-plug detection circuit 20 in this embodiment is not limited. Those skilled in the art can implement it according to the actual situation and needs, referring to relevant technologies. As long as the second differential positive voltage can be determined based on the difference between the first differential positive voltage TXP and the first preset voltage (V_det), the second differential negative voltage can be determined based on the difference between the first differential negative voltage TXN and the second preset voltage (-V_det), and a hot-plug flag signal can be generated based on the second differential positive voltage and the second differential negative voltage.

[0070] For example, the hot-plug detection circuit 20 can be implemented by a general voltage processing component. After receiving the first differential positive voltage TXP and the first differential negative voltage TXN, the voltage processing component can obtain the first preset voltage and the second preset voltage to determine the hot-plug flag signal.

[0071] In one example, the voltage processing component includes, but is not limited to, a standalone processor, discrete components, or a combination of processors and discrete components. The processor may include a controller in an electronic device capable of executing instructions. The processor may be implemented in any suitable manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Within the processor, the executable instructions may be executed via hardware circuitry such as logic gates, switches, ASICs, programmable logic controllers, and embedded microcontrollers.

[0072] Of course, the hot-plug detection circuit 20 can also be implemented by a dedicated hardware circuit. The preferred implementation of the hot-plug detection circuit 20 will be described below.

[0073] The specific implementation of determining the second differential positive voltage based on the difference between the first differential positive voltage TXP and the first preset voltage, determining the second differential negative voltage based on the difference between the first differential negative voltage TXN and the second preset voltage, and generating a hot-plug flag signal based on the second differential positive voltage and the second differential negative voltage in this embodiment is not limited.

[0074] For example, such as Figure 5 As shown, R_term represents the resistance of the transmission line connected to the transmitter 110.

[0075] Please see Figure 6 , Figure 6 A schematic diagram of a hot-plug detection circuit 20 according to an embodiment of the present disclosure is shown.

[0076] In one possible implementation, such as Figure 6 As shown, the transmitting end 110 of the transmission link may include a serializer and a transmit amplifier (TX Driver), and the receiving end 130 may include a receive amplifier (RX Driver) and a deserializer. This disclosure does not limit the specific implementation of the serializer, deserializer, and amplifier. Those skilled in the art can implement them according to the actual situation and needs by referring to relevant technologies.

[0077] In one possible implementation, such as Figure 6 As shown, the hot-plug detection circuit 20 may include an analog subtraction module 210, a reference voltage generation module 220, a first comparator COMP1, a second comparator COMP2, and / or logic circuit OR, wherein...

[0078] The analog subtraction module 210 is used to generate the common-mode voltage (VCM) of the second differential positive voltage OUTP, the second differential negative voltage OUTN, and the second differential positive voltage OUTP and the second differential negative voltage OUTN.

[0079] The reference voltage generation module 220 is used to generate a positive reference voltage VREFP and a negative reference voltage VREFN based on the common-mode voltage of the second differential positive voltage OUTP and the second differential negative voltage OUTN.

[0080] The first positive input terminal of the first comparator COMP1 and the first positive input terminal of the second comparator COMP2 are used to receive the second differential positive voltage OUTP.

[0081] The second positive input terminal of the first comparator COMP1 and the second negative input terminal of the second comparator COMP2 are used to receive the positive reference voltage VREFP.

[0082] The first negative input terminal of the first comparator COMP1 and the first negative input terminal of the second comparator COMP2 are used to receive the second differential positive voltage OUTN.

[0083] The second negative input terminal of the first comparator COMP1 and the second positive input terminal of the second comparator COMP2 are used to receive the negative reference voltage VREFN.

[0084] The outputs of the first comparator COMP1 and the second comparator COMP2 are respectively connected to the two inputs of the OR logic circuit.

[0085] The output of the OR logic circuit is used to output the hot-plug flag signal (HPD_OUT).

[0086] The embodiments disclosed herein do not limit the specific implementation of the analog subtraction module 210 and the reference voltage generation module 220. Those skilled in the art can implement them according to the actual situation and needs, referring to relevant technologies.

[0087] Among them, the first comparator COMP1 and the second comparator COMP2 are both differential comparators. In a differential comparator, the difference between one pair of inputs is compared with the difference between another pair of inputs. For example, in the first comparator COMP1, the difference between TOUP and OUTN is compared with the difference between VREP and VREN.

[0088] For example, such as Figure 6 As shown, both pairs of differential inputs of the first comparator COMP1 are positively connected, that is, OUTP is connected to "+", OUTN is connected to "-", VREFP is connected to "+", and VREFN is connected to "-". When OUTP-OUTN>0 and OUTP-OUTN>VREFP-VREFN, the output of OUT1 is high, which indicates that a hot-plug event has occurred; otherwise, the output of OUT1 is low, which indicates that no hot-plug event has occurred.

[0089] For example, such as Figure 6As shown, the second comparator COMP2 has one pair of differential inputs connected positively and the other pair connected negatively, i.e., OUTP connected to "+", OUTN connected to "-", VREFP connected to "-", and VREFN connected to "+". When OUTN-OUTP>0 and OUTN-OUTP>VREFP-VREFN, OUT2 outputs high, indicating a hot-plug event has occurred; conversely, OUT2 outputs low, indicating no hot-plug event has occurred. Exemplarily, in this embodiment, performing an OR operation on OUT1 and OUT2 yields a hot-plug flag signal (HPD_OUT). A high level of the hot-plug flag signal (HPD_OUT) indicates a hot-plug event, such as the transmitter or receiver being unplugged. A low level of the hot-plug flag signal (HPD_OUT) indicates a normal transmission link connection.

[0090] For example, such as Figure 6 As shown, the reference voltage generation module 220 can be set according to actual conditions and needs. As long as half of the sum of the two reference voltages generated by the reference voltage generation module 220 is the same as the common-mode voltage output by the analog subtraction module, and the difference between the positive reference voltage VREFP and the negative reference voltage VREFN is less than the difference between the second differential positive voltage OUTP and the second differential negative voltage OUTN when the transmission link is switched from a normal connection (both ends of the transmission line are in a normal connection state with the transmitting end and the receiving end) to a state where either end is unplugged, that is, ((VREFP+VREFN) / 2=VCM) & (VREFP-VREFN<min(OUTOP-OUTN) (for example, the minimum value when the transmitting end or the receiving end is unplugged in multiple tests)). VCM represents the common-mode voltage of the second differential positive voltage OUTP and the second differential negative voltage OUTN, and VREFP and VREFN represent the positive reference voltage and the negative reference voltage, respectively. This disclosure describes the specific method by which the reference voltage generation module 220 generates the positive reference voltage VREFP and the negative reference voltage VREFN. The specific magnitudes of the positive reference voltage VREFP and the negative reference voltage VREFN are not limited, and those skilled in the art can set them according to actual conditions and needs.

[0091] For example, such as Figure 6 As shown, when OUTP-OUTN>0 and OUTP-OUTN>VREFP-VREFN, OUT1 outputs high.

[0092] In practical applications, the hot-plug flag signal (HPD_OUT) output by the OR logic circuit may contain glitch signals. Therefore, in one possible implementation, the embodiments of this disclosure may also include a glitch elimination circuit in the hot-plug detection circuit 20, which is used to eliminate glitch signals in the hot-plug flag signal.

[0093] Of course, the specific implementation of the glitch elimination circuit in this disclosure is not limited, and those skilled in the art can refer to relevant technologies to implement it according to actual conditions and needs.

[0094] Please see Figure 7 , Figure 7 A schematic diagram of the circuit structure of the analog subtraction module 210 according to an embodiment of the present disclosure is shown.

[0095] In one possible implementation, such as Figure 7 As shown, the analog subtraction module 210 may include a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first current source I1, a second current source I2, a third current source I3, a fourth current source I4, a fifth current source I5, a first voltage source V1, a second voltage source V2, a first switch S1, a second switch S2, a first transistor PM1, a second transistor PM2, a third transistor PM3, a fourth transistor PM4, a fifth transistor NM1, and a sixth transistor NM2, wherein...

[0096] The first terminal of the first resistor R1 and the first terminal of the second resistor R2 are respectively used to receive the first differential positive voltage TXP and the first differential negative voltage TXN.

[0097] The second end of the first resistor R1 is connected to the first end of the first switch S1, the first end (such as the drain) of the first transistor PM1, and the positive terminal of the first current source I1.

[0098] The second end of the second resistor R2 is connected to the first end of the second switch S2, the first end (such as the drain) of the second transistor PM2, and the positive terminal of the second current source I2.

[0099] The second terminal of the first switch S1 and the second terminal of the second switch S2 are both connected to the negative terminal of the third current source I3, and the positive terminal of the third current source I3 is grounded.

[0100] The gates of the first transistor PM1 and the second transistor PM2 are both connected to the positive terminal of the first voltage source V1, and the negative terminal of the first voltage source V1 is grounded.

[0101] The negative terminal of the first current source I1, the negative terminal of the second current source I2, the first terminal (e.g., drain) of the third transistor PM3, and the first terminal (e.g., drain) of the fourth transistor PM4 are connected.

[0102] The gate of the third transistor PM3, the gate of the fourth transistor PM4, the first terminal of the third resistor R3, and the first terminal of the fourth resistor R4 are connected to output the common-mode voltage (VCM) of the second differential positive voltage OUTP and the second differential negative voltage OUTN.

[0103] The second terminal (e.g., the source) of the third transistor PM3, the second terminal of the third resistor R3, and the first terminal (e.g., the source) of the fifth transistor NM1 are connected to output the second differential negative voltage OUTN.

[0104] The second terminal (e.g., the source) of the fourth transistor PM4, the second terminal of the fourth resistor R4, and the first terminal (e.g., the source) of the sixth transistor NM2 are connected to output the second differential positive voltage OUTP.

[0105] The gates of the fifth transistor NM1 and the sixth transistor NM2 are both connected to the positive terminal of the second voltage source V2, and the negative terminal of the second voltage source V2 is grounded.

[0106] The second terminal (e.g., drain) of the fifth transistor NM1 is connected to the second terminal (e.g., source) of the second transistor PM2 and the negative terminal of the fourth current source I4.

[0107] The second terminal (e.g., drain) of the sixth transistor NM2 is connected to the second terminal (e.g., source) of the first transistor PM1 and the negative terminal of the fifth current source I5.

[0108] The positive terminals of the fourth current source I4 and the fifth current source I5 are both grounded.

[0109] It should be understood that the source and drain of a transistor can be interchanged; therefore, the embodiments disclosed herein do not limit the specific types of the first terminal and the second terminal of a transistor.

[0110] The embodiments disclosed herein do not limit the types of the first switch S1 and the second switch S2. Those skilled in the art can set them according to actual conditions and needs. For example, the first switch S1 and the second switch S2 may include any one of the following: relay, reed switch, thyristor, switching diode, switching transistor, electronic bidirectional switch, optocoupler, transistor, etc. The transistor may be a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). The transistor may be based on silicon carbide (SiC) or gallium nitride (GaN) to improve performance.

[0111] The embodiments disclosed herein do not limit the specific type of each transistor. Those skilled in the art can set it according to actual conditions and needs. In one possible implementation, the first transistor PM1, the second transistor PM2, the third transistor PM3, and the fourth transistor PM4 are all PMOS transistors, and the fifth transistor NM1 and the sixth transistor NM2 are all NMOS transistors.

[0112] In one possible implementation, such as Figure 7 As shown, the preset amplification factor can be the ratio of the resistance value of the third resistor R3 or the fourth resistor R4 to the resistance value of the first resistor R1 or the second resistor R2.

[0113] The third resistor R3 and the fourth resistor R4 have the same resistance value, and the first resistor R1 and the second resistor R2 have the same resistance value.

[0114] In one possible implementation, at least one of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 is an adjustable resistor.

[0115] For example, in this embodiment of the present disclosure, the first resistor R1 and the second resistor R2 can be set as adjustable resistors. By adjusting the resistance values ​​of the first resistor R1 and the second resistor R2, the specific value of the preset amplification factor can be adjusted.

[0116] For example, in this embodiment of the present disclosure, the third resistor R3 and the fourth resistor R4 can be set as adjustable resistors. By adjusting the resistance values ​​of the third resistor R3 and the fourth resistor R4, the specific value of the preset amplification factor can be adjusted.

[0117] For example, in this embodiment of the present disclosure, the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 can be set as adjustable resistors. By adjusting the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4, the specific value of the preset amplification factor can be adjusted.

[0118] The embodiments disclosed herein do not limit the specific implementation of the adjustable resistor; those skilled in the art can set it according to actual conditions and needs.

[0119] In one possible implementation, the resistance values ​​of the first resistor R1 and the second resistor R2 are greater than the terminating resistance of the transmission line.

[0120] In one possible implementation, the switching control signal of the first switch S1 is in phase with the first differential positive voltage TXP, and the switching control signal of the second switch S2 is in phase with the first differential negative voltage.

[0121] For example, such as Figure 7 As shown, the third resistor R3, the fourth resistor R4, the first current source I1, the second current source I2, the fourth current source I4, the fifth current source I5, the first voltage source V1, the second voltage source V2, the first transistor PM1, the second transistor PM2, the third transistor PM3, the fourth transistor PM4, the fifth transistor NM1, and the sixth transistor NM2 are pseudo-differential folded cascode operational amplifiers.

[0122] For example, such as Figure 7 As shown, the first transistor PM1 and the second transistor PM2 are used as a pseudo-differential input pair, and the gate voltages of the first transistor PM1 and the second transistor PM2 are provided by the first voltage source V1.

[0123] For example, such as Figure 7 As shown, the fifth transistor NM1 and the sixth transistor NM2 are folded common gate transistors, responsible for the differential current steering. The gate voltages of the fifth transistor NM1 and the sixth transistor NM2 are generated by the second voltage source V2.

[0124] For example, such as Figure 7 As shown, the third transistor PM3, the fourth transistor PM4, the third resistor R3, and the fourth resistor R4 serve as the load of the operational amplifier.

[0125] For example, such as Figure 7 As shown, the second terminal of the third transistor PM3, the second terminal of the third resistor R3, and the first terminal of the fifth transistor NM1 are connected to form a negative differential voltage output terminal OUTN, used to output the second differential negative voltage OUTN; the second terminal of the fourth transistor PM4, the second terminal of the fourth resistor R4, and the first terminal of the sixth transistor NM2 are connected to form a positive differential voltage output terminal OUTP, used to output the second differential positive voltage OUTP; the gate of the third transistor PM3, the gate of the fourth transistor PM4, the first terminal of the third resistor R3, and the first terminal of the fourth resistor R4 are connected to output the common-mode voltage (VCM) of the second differential positive voltage OUTP and the second differential negative voltage OUTN.

[0126] For example, the first current source I1, the second current source I2, the third current source I3, the fourth current source I4, and the fifth current source I5 are all constant current sources.

[0127] For example, such as Figure 7As shown, the first resistor R1, the second resistor R2, the first switch S1, the second switch S2 and the third current source I3 form an analog subtraction circuit to realize the analog subtraction operation between the differential voltage signal (first differential positive voltage TXP, first differential negative voltage TXN) and the preset voltage signal (first preset voltage, second preset voltage).

[0128] For example, such as Figure 7 As shown, the control signal of the first switch S1 is in phase with the first differential positive voltage TXP output by the TX Driver, and the control signal of the second switch S2 is in phase with the first differential negative voltage TXN output by the TX Driver. That is, when TXP changes positive and TXN changes negative, the first switch S1 is turned on and the second switch S2 is turned off; when TXP changes negative and TXN changes positive, the first switch S1 is turned off and the second switch S2 is turned on.

[0129] The working principle of the analog subtraction module 210 is described below.

[0130] This embodiment of the disclosure can configure the current magnitude of each current source to be related to the current magnitude flowing through the first resistor R1 when the transmission link is normally connected (both ends of the transmission line are normally connected to the transmitting end and the receiving end), and set appropriate values ​​for the first resistor and the second resistor, thereby realizing the simulated subtraction operation between the differential voltage signal (first differential positive voltage TXP, first differential negative voltage TXN) and the preset voltage signal (first preset voltage, second preset voltage).

[0131] For example, such as Figure 7 As shown, we can set I1=I2=3 idet, I3=2 idet, where I1 represents the current magnitude of the first current source I1, I2 represents the current magnitude of the second current source I2, and idet represents the current flowing through the first resistor R1 when the signal transmission link is normally connected (both ends of the transmission line are normally connected to the transmitting and receiving ends). The resistance of the first resistor R1 is R_det, where idet × R_det = V_det, which is equivalent to setting a first preset voltage (V_det) and a second preset voltage (-V_det) under normal connection conditions. The control signal of the first switch S1 is in phase with the output TXP of the TX Driver, and the control signal of the second switch S2 is in phase with the output TXN of the TX Driver. That is, when TXP changes positively and TXN changes negatively, S1 is turned on and S2 is turned off; when TXP changes negatively and TXN changes positively, S1 is turned off and S2 is turned on.

[0132] Exemplarily, when the first differential positive voltage TXP and the first differential negative voltage TXN respectively jump by +V_det and -V_det, and the currents flowing through the first resistor R1 and the second resistor R2 are equal to idet, it is calculated from the KCL equations (Kirchhoff's current law equations) of nodes Vip and Vin that the currents flowing through the first transistor PM1 and the second transistor PM2 are both 2 idet. Therefore, the currents flowing through the third transistor PM3 and the fourth transistor PM4 are also equal, and the output voltages OUTP = OUTN = VCM; where V_det is the voltage swing of the first differential positive voltage TXP and the first differential negative voltage TXN.

[0133] Exemplarily, when the jump of TXP is greater than +V_det and the jump of TXN is less than -V_det (hot plug occurs), then the currents flowing through the first resistor R1 and the second resistor R2 are greater than idet. It is calculated from the KCL equations of nodes Vip and Vin that the current flowing through the first transistor PM1 is greater than 2 idet, and the current flowing through the second transistor PM2 is less than 2 idet. Therefore, the current flowing through the third transistor PM3 is greater than the current flowing through the fourth transistor PM4, and the output voltage OUTP > OUTN and VCM = (OUTP + OUTN) / 2. <00(...)​​​​​​​​​​​​Of course, due to the presence of noise during circuit operation, directly generating a hot-plugging flag signal based on the magnitude relationship between OUTP and OUTN may be affected by noise and have reliability issues. Therefore, in the embodiments of the present disclosure, OUTP, OUTN, reference voltages VREFP, and VREFN can be fed into a first comparator and a second comparator, and a glitch elimination circuit can be set up to further improve the accuracy of the determination.

[0139] Exemplarily, as Figure 7 shown, the preset amplification factor (the gain of the analog subtraction module 210) can be determined by the ratio of R_amp and R_det, where R_amp represents the resistance of the third resistor R3 or the fourth resistor R4, and R_det represents the resistance of the first resistor R1 or the second resistor R2.

[0140] Since the input of the analog subtractor needs to be connected to the differential output of the TX Driver, in order to minimize the impact on the transmitter 110 driver (TX Driver) as much as possible, R_det > R_term can be set. Preferably, in order to minimize the impact on the transmitter 110 driver as much as possible, R_det >> R_term can be set.

[0141] The scenarios of plugging and unplugging the transmission line 120 at the transmitter 110 and the scenarios of plugging and unplugging the transmission line 120 at the receiver 130 will be introduced separately below.

[0142] Please refer to Figure 8 , Figure 8 which shows a waveform schematic diagram of relevant nodes when the hot-plugging detection circuit 20 according to the embodiments of the present disclosure is plugged or unplugged at the transmitter 110 of the signal transmission link 10.

[0143] As Figure 8 shown, before t = t1, TX is connected to RX through a transmission line (cable), and the TX Driver outputs signals TXP and TXN with a frequency of 20 MHz and a differential swing (voltage swing) of V_det.

[0144] Since the swing of TXP and TXN is V_det, the output of the analog subtraction module 210, OUTP = OUTN = VCM. It can be obtained that OUTP - OUTN = 0 < VREFP - VREFN, and the outputs OUT1 and OUT2 of the first comparator COMP1 and the second comparator COMP2 are both at a low level, and HPD_OUT is also at a low level.

[0145] Exemplarily, as Figure 8As shown, after time t=t1, the TX transmission line is disconnected, and the transmission line and the RX R_term are disconnected together. The load resistance of the TX driver increases, and the differential swing between TXP and TXN increases, becoming greater than V_det. At this time, the analog subtractor output |OUTP-OUTN|>0. If |OUTP-OUTN| is greater than the differential threshold voltage VREFP-VREFN, the outputs OUT1 and OUT2 of the two comparators COMP1 and COMP2 will exhibit the following behavior: Figure 8 The transition shown indicates that the OUT output is high after the OR logic gate, which means that a glitch exists. After passing through the glitch elimination circuit, the glitch is eliminated, and HPD_OUT outputs a stable high level, indicating that the transmission line has been disconnected.

[0146] The embodiments disclosed herein do not limit the specific implementation of the burr elimination circuit. Those skilled in the art can refer to relevant technologies to implement it according to actual conditions and needs.

[0147] For example, glitches can be eliminated using digital circuits, such as synchronous sampling debouncing. This can be achieved by using a synchronous clock with a frequency much higher than the signal bandwidth to perform 2-3 levels of D register synchronization on the input signal, followed by logical voting on the multi-level outputs (AND for high-level active, OR for low-level active). Only when the input is at a stable level for several consecutive clock cycles will the corresponding level be output. Of course, narrow glitches in a single cycle will be directly filtered out. Alternatively, a synchronous counter can be used to count the duration of the input signal level. The output will only flip when the duration exceeds a preset threshold (greater than the maximum glitch width); glitches with insufficient duration will trigger the counter to reset, and the output will remain unchanged.

[0148] For example, the glitch elimination circuit can also be implemented using analog circuits. For instance, an RC low-pass circuit can be used to attenuate the amplitude of the glitch, and then the hysteresis characteristic (double-flip threshold) of a Schmitt trigger can be used to completely shield residual glitches whose amplitude does not reach the threshold, ultimately outputting a shaped and stable level. Alternatively, it can be implemented using a Schmitt trigger. For example, using the hysteresis window of a Schmitt trigger, glitches with amplitudes smaller than the hysteresis voltage cannot trigger the output flip and are directly filtered out. It can also be implemented using an integrator and comparator. The input signal controls the charging and discharging of the integrating capacitor. Only when the input level lasts long enough can the capacitor voltage reach the comparator flip threshold, triggering an output change; narrow glitches cannot make the capacitor voltage reach the threshold and are therefore shielded.

[0149] Please see Figure 9 , Figure 9 The diagram shows a waveform of a relevant node of the hot-plug detection circuit 20 according to an embodiment of the present disclosure when a plugging or unplugging occurs at the receiving end 130 of the signal transmission link 10.

[0150] like Figure 9 As shown, the operations before t=t1 are the same as plugging and unplugging the transmission line at the TX end.

[0151] like Figure 9 As shown, after time t=t1, the R_term at the RX end is disconnected, increasing the load resistance of the TX driver. However, due to the existence of the transmission line, the output signal of the TX driver continues to propagate through the transmission line. When it reaches the far end of the transmission line (i.e., the RX side), it will cause reflection. Due to the transmission delay of the transmission line, the reflected signal will appear at the TX end after a certain period of time. The reflected signal and the source signal are superimposed at the TX end, which may produce the following: Figure 9 The waveform shown.

[0152] The analog subtractor can extract the reflected signal from the TXP and TXN waveforms, meaning there exists a case where the output |OUTP-OUTN| > 0. If |OUTP-OUTN| is greater than the differential threshold voltage VREFP-VREFN, the outputs OUT1 and OUT2 of the two comparators COMP1 and COMP2 exhibit the following behavior: Figure 9 The transition shown indicates that the AND operation between the two outputs results in a glitch in OUT. After passing through the glitch elimination circuit, the glitch is eliminated, and HPD_OUT outputs a stable high level, indicating that the transmission line has been disconnected.

[0153] Because the transmission line experiences signal attenuation during transmission, and the attenuation increases with the signal frequency, a 20MHz frequency signal is used as an example during hot-plug detection.

[0154] Compared with the prior art, the beneficial effects of the technical solutions of the embodiments of this disclosure include:

[0155] (1) It is a hot-swappable technology implemented on the on-chip TX end, which does not occupy an additional pin port;

[0156] (2) It can detect both the insertion and removal of the transmission line at the TX end and the insertion and removal of the transmission line at the RX end;

[0157] (3) It is compatible with both AC-coupled and DC-coupled transmission;

[0158] (4) The RX end transmission line plug-in / plug-out detection function is realized by using reflection, so the transmission line that can be detected is longer.

[0159] According to one aspect of this disclosure, a control chip is provided, the control chip including the hot-plug detection circuit 20.

[0160] This disclosure does not limit the specific type of control chip. For example, the control chip may be located at the transmitting end of the signal transmission link. In this way, this disclosure can integrate the hot-plug detection circuit with the control chip at the transmitting end to achieve hot-plug detection on-chip. The control chip may include, for example, a processing component. In one example, the processing component includes, but is not limited to, a separate processor, discrete components, or a combination of a processor and discrete components. The processor may include a controller in an electronic device that has the function of executing instructions. The processor can be implemented in any suitable manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Inside the processor, the executable instructions can be executed by hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0161] According to one aspect of this disclosure, an electronic device is provided, the electronic device including the control chip described above.

[0162] This disclosure does not limit the type of electronic device. Those skilled in the art can configure it according to actual circumstances and needs. For example, the electronic device may include a terminal device and a server. The terminal device may be a user equipment (UE), mobile device, user terminal, terminal, handheld device, computing device, or in-vehicle device, etc. Examples of terminals include: mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and wireless terminals in vehicle-to-everything (V2X) networks, etc. For example, the server may be a local server or a cloud server.

[0163] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A hot-plug detection circuit, characterized in that, The input terminal of the hot-plug detection circuit is connected to the transmitting end of the signal transmission link, wherein the signal transmission link includes a transmitting end, a transmission line, and a receiving end, and the transmission line is pluggable to both the transmitting end and the receiving end. The hot-plug detection circuit is used for: Receive the first differential positive voltage and the first differential negative voltage from the transmitting end; A second differential positive voltage is determined based on the voltage difference between the first differential positive voltage and the first preset voltage, and a second differential negative voltage is determined based on the voltage difference between the first differential negative voltage and the second preset voltage, wherein the first preset voltage and the second preset voltage are related to the voltage swing of the transmitting end when the transmission link is normally connected; A hot-plug flag signal is generated based on the second differential positive voltage and the second differential negative voltage. The hot-plug flag signal is used to determine whether a hot-plug has occurred between the transmission line and the transmitting end and / or the receiving end.

2. The hot-plug detection circuit according to claim 1, characterized in that, The hot-plug detection circuit includes an analog subtraction module, a reference voltage generation module, a first comparator, a second comparator, and / or logic circuitry. The analog subtraction module is used to generate the second differential positive voltage, the second differential negative voltage, and the common-mode voltage of the second differential positive voltage and the second differential negative voltage. The reference voltage generation module is used to generate a positive reference voltage and a negative reference voltage based on the common-mode voltage of the second differential positive voltage and the second differential negative voltage. The first positive input terminal of the first comparator and the first positive input terminal of the second comparator are used to receive the second differential positive voltage. The second positive input terminal of the first comparator and the second negative input terminal of the second comparator are used to receive the positive reference voltage. The first negative input terminal of the first comparator and the first negative input terminal of the second comparator are used to receive the second differential negative voltage. The second negative input terminal of the first comparator and the second positive input terminal of the second comparator are used to receive the negative reference voltage. The outputs of the first comparator and the second comparator are respectively connected to the two inputs of the OR logic circuit. The output terminal of the OR logic circuit is used to output the hot-plug flag signal.

3. The hot-plug detection circuit according to claim 2, characterized in that, The hot-plug detection circuit also includes a glitch elimination circuit, which is used to eliminate glitch signals in the hot-plug indicator signal.

4. The hot-plug detection circuit according to claim 2, characterized in that, The analog subtraction module includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first current source, a second current source, a third current source, a fourth current source, a fifth current source, a first voltage source, a second voltage source, a first switch, a second switch, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein... The first terminal of the first resistor and the first terminal of the second resistor are respectively used to receive the first differential positive voltage and the first differential negative voltage. The second end of the first resistor is connected to the first end of the first switch, the first end of the first transistor, and the positive terminal of the first current source. The second end of the second resistor is connected to the first end of the second switch, the first end of the second transistor, and the positive terminal of the second current source. The second terminals of the first switch and the second switch are both connected to the negative terminal of the third current source, and the positive terminal of the third current source is grounded. The gates of the first transistor and the second transistor are both connected to the positive terminal of the first voltage source, and the negative terminal of the first voltage source is grounded. The negative terminal of the first current source, the negative terminal of the second current source, the first terminal of the third transistor, and the first terminal of the fourth transistor are connected. The gates of the third transistor and the fourth transistor, the first terminal of the third resistor, and the first terminal of the fourth resistor are connected to output the common-mode voltage of the second differential positive voltage and the second differential negative voltage. The second terminal of the third transistor, the second terminal of the third resistor, and the first terminal of the fifth transistor are connected to output the second differential negative voltage. The second terminal of the fourth transistor, the second terminal of the fourth resistor, and the first terminal of the sixth transistor are connected to output the second differential positive voltage. The gates of the fifth transistor and the sixth transistor are both connected to the positive terminal of the second voltage source, and the negative terminal of the second voltage source is grounded. The second terminal of the fifth transistor is connected to the second terminal of the second transistor and the negative terminal of the fourth current source. The second terminal of the sixth transistor is connected to the second terminal of the first transistor and the negative terminal of the fifth current source. The positive terminals of the fourth current source and the fifth current source are both grounded.

5. The hot-plug detection circuit according to claim 4, characterized in that, The first transistor, the second transistor, the third transistor, and the fourth transistor are all PMOS transistors, and the fifth transistor and the sixth transistor are all NMOS transistors.

6. The hot-plug detection circuit according to claim 4, characterized in that, At least one of the first resistor, the second resistor, the third resistor, and the fourth resistor is an adjustable resistor.

7. The hot-plug detection circuit according to claim 4, characterized in that, The resistance values ​​of the first resistor and the second resistor are greater than the terminating resistance of the transmission line.

8. The hot-plug detection circuit according to claim 4, characterized in that, The switching control signal of the first switch is in phase with the first differential positive voltage, and the switching control signal of the second switch is in phase with the first differential negative voltage.

9. The hot-plug detection circuit according to claim 1, characterized in that, The signal transmission link is a high-speed serial link, the transmitting end includes a serializer, and the receiving end includes a deserializer.

10. A control chip, characterized in that, The control chip includes a hot-plug detection circuit as described in any one of claims 1-19.

11. An electronic device, characterized in that, The electronic device includes the control chip as described in claim 10.

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