Method for data communication and device for implementing the method

Abstract

A method for data communication between a first processor and a second processor is proposed. The method includes: sending a data packet to the second processor; stopping data transmission for a first predetermined duration when it is determined that the transmission of the data packet is to be stopped; and sending one or more subsequent data packets to the second processor when the first predetermined duration expires.

Description

Technical Field

[0001] This disclosure relates to the field of data communication between processing devices, and more particularly to data communication between two processors in a computing environment. Background Technology

[0002] Electric motor drives (e.g., electric (e.g., induction) motor drives) are typically designed to operate with any electric (e.g., induction) motor based on drive parameters determined during a measurement phase, sometimes referred to as the “motor tuning” phase.

[0003] Motor drives are typically configured to generate setpoint signals based on electrical signals received from a power supply network (e.g., an energy supplier network), which are then fed to the motor to which the motor drive is coupled for controlling its operation.

[0004] An electric motor drive can be configured with multiple processing units (e.g., processors) and a data communication interface for sending data to / receiving data from another device. This configuration requires inter-processor data communication, whether between processors in the same device (e.g., the motor drive) or between processors in different devices, such as in an industrial network.

[0005] However, industrial networks have specific constraints, such as the enforcement of strict time attributes for data transmission, which may not be adequately addressed by conventional data communication protocols that can be used for inter-processor communication.

[0006] Therefore, there is a need to provide an improved inter-processor data communication scheme and an apparatus for implementing the scheme, in order to overcome the aforementioned shortcomings and deficiencies of conventional technologies in the field.

[0007] There is also a need to provide improved data communication schemes and devices for implementing these schemes, which can be used for inter-processor data communication, especially in industrial network environments. Summary of the Invention

[0008] The purpose of this disclosure is to provide an improved data communication scheme and an apparatus for implementing the scheme.

[0009] Another objective of this subject matter disclosure is to provide a data communication scheme and an apparatus for implementing the data communication scheme, so as to mitigate the aforementioned disadvantages and deficiencies of conventional inter-processor data communication schemes.

[0010] Another objective of this subject matter is to provide an inter-processor data communication scheme and an apparatus for implementing the scheme, so as to mitigate the aforementioned disadvantages and deficiencies of conventional inter-processor data communication schemes.

[0011] Another objective of this subject matter is to provide a data communication scheme and an apparatus for implementing the data communication scheme, which can be used for inter-processor data communication, particularly in industrial network environments.

[0012] To achieve these objectives and other advantages, and in accordance with the purposes disclosed herein, as embodied and broadly described herein, a method for data communication between a first (sender) processor and a third (receiver) processor is proposed according to one aspect of this disclosure. The method includes: the first (sender) processor sending data (packets) to the third (receiver) processor (via a second (intermediate) processor in a processor chain between the first and third processors); stopping data transmission (via the second (intermediate) processor) to the third (receiver) processor for a first predetermined duration when it is determined that the transmission of data (packets) should be stopped; and sending one or more subsequent data (packets) to the third (receiver) processor (via the second processor) upon the expiration of the first predetermined duration.

[0013] According to another aspect disclosed in this subject matter, a method for data communication between a first (transmitter) processor and a second processor is proposed. The method includes the first (transmitter) processor: transmitting data packets to the second processor; stopping data transmission for a first predetermined duration when it is determined that transmission of the data packets is to be stopped; and transmitting one or more subsequent data packets to the second processor upon the expiration of the first predetermined duration.

[0014] The proposed inter-processor data communication is advantageously suited for implementing data communication between a sending processor and a receiving processor through one or more intermediate processors, wherein at least one of the intermediate processors is limited in terms of resources and / or capabilities.

[0015] The proposed scheme is advantageously compatible with any suitable data communication protocol that the sending and receiving processors can use for data communication. Advantageously, the proposed method provides a scheme implemented by the sending processor (and therefore transparent to the receiving processor) that can be adapted for data communication with the receiving processor to transfer data from the sending processor to the receiving processor using a processor chain, where one or more intermediate processors may have very limited resources / capabilities. Specifically, the proposed scheme is advantageously applicable for inter-processor data communication, using a processor chain to communicate data from the sending processor to the receiving processor via one or more intermediate processors, particularly where at least one intermediate processor may not be configured to manage data reception and transmission according to the protocol used by the sending and receiving processors.

[0016] An embodiment of the proposed scheme can be implemented in a first processor configured to send data to another processor (a second processor), which can be any processor in a processor chain for data transfer from the first processor to the receiving processor.

[0017] In one or more embodiments, the proposed method may further include: suspending data transmission to a third (receiving) processor for a second predetermined duration while transmitting one or more subsequent data (packets).

[0018] In one or more embodiments, data transmission can be performed (substantially) continuously, such that data can be streamed from a first (sender) processor to a third (receiver) processor, for example at a streaming rate corresponding to the execution frequency of the (transmission) task performed by the first (sender) processor.

[0019] In one or more embodiments, sending data to a third (receiving) processor may include sending a stream of P data packets to a second processor, where P ≥ 1. In some embodiments, the P data packets of the stream may be streamed to the third (receiving) processor, for example at a streaming rate corresponding to the execution frequency of the (transmission) task performed by the first (sending) processor.

[0020] In some embodiments, determining that data transmission is to be stopped may include determining the completion of transmission of P data packets of the stream. In such embodiments, in addition to stopping data transmission to the third (receiving) processor for a first predetermined duration, the first (sendering) processor may send subsequent data to the third (receiving) processor including a transmission end signaling packet (e.g., to notify the third processor of the completion of transmission of the P data packets of the stream according to a data communication protocol used by the first (sendering) processor).

[0021] In some embodiments, the proposed method may further include: starting a transmitter stop timer when transmitting one or more subsequent data (packets). In some embodiments, the transmitter stop timer may be configured to expire at the end of a second predetermined duration. In some embodiments, data transmission to a third processor may be stopped (interrupted) while the transmitter stop timer is running.

[0022] In one or more embodiments, the proposed method may further include: starting a transmitter transmission end timer when it is determined that transmission of a data packet is to be stopped. In some embodiments, the transmitter transmission end timer may be configured to expire at the end of a first predetermined duration. In some embodiments, data transmission to a third processor may be stopped (interrupted) while the transmitter transmission end timer is running. In some embodiments, when the transmitter transmission end timer expires, a transmission end signaling packet (according to the data communication protocol used by the first (sender) processor and the third (receiver) processor) may be sent to the third processor.

[0023] In one or more embodiments, sending data to a third (receiving) processor may include writing the data to be sent to the third (receiving) processor into a memory shared between a first processor and a second processor (located between the first and third processors in a processor chain through which data is sent from the first processor to the third processor).

[0024] According to another aspect disclosed in this subject matter, a method for data processing is proposed, which is implemented by a second (intermediate) processor and includes: receiving data (e.g., one or more data packets) from a first (transmitter) processor, for example; storing the received data (e.g., one or more received data packets) in a memory coupled to the second processor; and transmitting the data stored in the memory (e.g., one or more data packets) to a third processor when it is determined that no further data (e.g., from the first processor) has been received for a third predetermined duration.

[0025] In one or more embodiments, the proposed method may further include, by a second processor, initiating a receiver transmission end timer upon determining that data is no longer being received (from the first processor). In some embodiments, the receiver transmission end timer may be configured to expire at the end of a third predetermined duration.

[0026] In one or more embodiments, the proposed method may further include, by a second processor, receiving subsequent data (e.g., one or more subsequent data packets) while transmitting data stored in memory to a third processor (e.g., from a first processor), and storing the received subsequent data (e.g., one or more received subsequent data packets) in memory. In some embodiments, the proposed method may further include, by the second processor, transmitting subsequent data (e.g., one or more subsequent data packets) stored in memory to a third processor when it is determined (based on) that no data has been received within a fourth predetermined duration (e.g., from the first processor).

[0027] In one or more embodiments, the proposed method may further include: a second processor, in addition to receiving data, initiating a first receiver stop transmission timer when it is determined that data will no longer be received by the second processor. In some embodiments, the first receiver stop transmission timer may be configured to expire at the end of a third predetermined duration.

[0028] In one or more embodiments, the proposed method may further include, by a second processor, in addition to receiving subsequent data, initiating a second receiver stop-transmission timer when it is determined that data will no longer be received by the second processor. In some embodiments, the second receiver stop-transmission timer may be configured to expire at the end of a fourth predetermined duration.

[0029] In some embodiments, receiving data (e.g., from a first processor) may include data read by a second processor from memory shared between the second processor and processors preceding the second processor in the processor chain (e.g., from the first processor).

[0030] In one or more embodiments, the proposed method may further include a second processor: receiving data (e.g., from a first processor), storing the received data (e.g., from the first processor) in a memory, and, upon determining that the memory is full to a predetermined level, transmitting the data stored in the memory to a third processor. In some embodiments, the second processor may apply a traffic management policy according to which the data stored in the memory may be transmitted upon the condition that the memory is full to a predetermined level. In such embodiments, the traffic management policy configured at the second processor may include additional rules according to which, upon determining that no further data has been received within a third predetermined duration, the data stored in the memory is transmitted to the third processor even if the memory is not full to a predetermined level. In some embodiments, determining that no further data has been received within a third predetermined duration may trigger (force) the transmission of the data stored in the memory, regardless of whether the memory is full to a predetermined level. For example, in some embodiments, the second (intermediate) processor may be configured with a traffic management policy that includes: a first data transmission rule, according to which the second processor waits for the memory to be filled to a predefined level before sending data stored in the memory; and a second data transmission rule, according to which, when it is determined that no further data has been received within a third predetermined duration (even if the memory may not be filled to the predetermined level), the data stored in the memory is sent.

[0031] In one or more embodiments, the first processor and the second processor may be processors in a processor chain for data transfer from a sending processor (the first processor in the chain) to a receiving processor (the last processor in the chain). In some embodiments, the second processor may be an intermediate processor in the processor chain through which data is sent from the sending processor to the receiving processor. In some embodiments, the first processor may be a processor that immediately precedes the second processor in the processor chain.

[0032] In one or more embodiments, the first processor and the second processor may be processors in a processor chain for data transmission from a first processor operating as a sending processor to a receiving processor operating as the last processor in the processor chain. In some embodiments, the second processor may be an intermediate processor in the processor chain through which data can be transmitted from the sending processor to the receiving processor.

[0033] In one or more embodiments, the first processor and the second processor may be processors in a processor chain for data transmission from the first processor operating as a sending processor (the first processor in the processor chain) to the second processor operating as a receiving processor (the last processor in the processor chain).

[0034] In one or more embodiments, the second processor and the third processor may be processors in a processor chain for data transmission from the sending processor to the receiving processor, and the second processor may be an intermediate processor in the processor chain through which data is sent from the sending processor to the receiving processor.

[0035] In one or more embodiments, the first processor and the third processor may be processors in a processor chain for data transmission from the first processor operating as a sending processor to the third processor operating as a receiving processor, the third processor being the last processor in the processor chain, and data sent from the first processor to the third processor may be sent through one or more intermediate processors in the processor chain.

[0036] According to another aspect of this subject matter disclosure, an apparatus includes a processor and a memory operatively coupled to the processor, wherein the apparatus is configured to perform the methods proposed in this subject matter disclosure.

[0037] According to another aspect of this subject matter disclosure, a computer-readable medium encoded with executable instructions (in some embodiments, non-transitory) is proposed, which, when executed, cause an apparatus including a processor operatively coupled to memory to perform the methods proposed in this subject matter disclosure.

[0038] According to another aspect of this disclosure, a computer program product is proposed, comprising computer program code tangibly embodied in a computer-readable medium, the computer program code including instructions that, when provided to and executed by a computer system, cause the computer to perform the methods proposed in this disclosure. According to another aspect of this disclosure, a dataset is proposed, which, for example, represents the computer program as proposed herein through compression or encoding.

[0039] It should be understood that the present invention can be implemented and utilized in a variety of ways, including but not limited to as a process, apparatus, system, device, and method for applications now known and later developed. These and other unique features of the systems disclosed herein will become more apparent from the following description and accompanying drawings. Attached Figure Description

[0040] This subject matter will be better understood by referring to the following figures and the accompanying description, and its numerous objects and advantages will become more apparent to those skilled in the art, wherein:

[0041] Figure 1a This is a schematic diagram illustrating an exemplary computing environment according to one or more embodiments;

[0042] Figure 1b This is a schematic diagram illustrating an exemplary computing environment according to one or more embodiments;

[0043] Figure 2 This is a block diagram illustrating exemplary data grouping according to one or more embodiments;

[0044] Figure 3a This is a block diagram illustrating exemplary initial data grouping according to one or more embodiments;

[0045] Figure 3b This is a block diagram illustrating an exemplary stop data grouping according to one or more embodiments;

[0046] Figure 4 This is a flowchart illustrating an exemplary transmission of a data stream from a sending processor to a receiving processor via an intermediate processor according to one or more embodiments;

[0047] Figure 5a This is a block diagram illustrating a proposed method for data communication by a sender processor in a processor chain according to one or more embodiments;

[0048] Figure 5b This is a block diagram illustrating a proposed method for data communication by an intermediate processor in a processor chain according to one or more embodiments;

[0049] Figure 6 This is a flowchart illustrating an exemplary transmission of a data stream from a sending processor to a receiving processor via an intermediate processor according to one or more embodiments; and

[0050] Figure 7 This is a diagram illustrating an exemplary architecture of a computer system for implementing the proposed method according to one or more embodiments. Detailed Implementation

[0051] The advantages and other features of the components disclosed herein will become more apparent to those skilled in the art. Representative embodiments of the subject matter are illustrated below with reference to the accompanying drawings, in which like reference numerals identify similar structural elements.

[0052] For simplicity and clarity, the accompanying drawings illustrate a general construction method, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the described embodiments of the invention. Furthermore, elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be enlarged relative to other elements to aid in understanding the embodiments of the invention. To aid understanding, some drawings may be shown in an idealized manner, such as when structures are shown as having straight lines, acute angles, and / or parallel planes, which may be significantly less symmetrical and ordered under real-world conditions. The same reference numerals in different drawings denote the same elements, while similar reference numerals may, but do not necessarily, denote similar elements.

[0053] Furthermore, it should be apparent that the teachings herein can be embodied in a variety of forms, and any particular structure and / or function disclosed herein is merely representative. In particular, those skilled in the art will understand that the aspects disclosed herein can be implemented independently of any other aspects, and that several aspects can be combined in various ways.

[0054] The present disclosure is described below with reference to block diagrams and flowcharts of apparatuses, devices, modules, units, functions, engines, methods, systems, and computer programs according to one or more exemplary embodiments. Each described apparatus, device, module, unit, function, engine, block diagram, and flowchart illustration can be implemented in hardware, software, firmware, middleware, microcode, or any suitable combination thereof. If implemented in software, the apparatus, device, module, unit, function, engine, block diagram, and / or flowchart illustration can be implemented by computer program instructions or software code that can be stored or transmitted on a computer-readable medium, or loaded onto a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to create a machine, such that the computer program instructions or software code, which executes on the computer or other programmable data processing apparatus, creates means for implementing the functions described herein.

[0055] Examples of computer-readable media include, but are not limited to, both computer storage media and communication media, with communication media encompassing any medium that facilitates the transfer of a computer program from one place to another. As used herein, “computer storage media” can be any physical medium accessible to a computer or processor. Furthermore, the terms “memory” and “computer storage media” include any type of data storage device, such as, but not limited to, hard disk drives, flash drives or other flash memory devices (e.g., memory keys, memory sticks, key drives), CD-ROMs or other optical storage, DVDs, disk storage or other magnetic storage devices, memory chips, random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), smart cards, or any other suitable medium that can be used to carry or store program code in the form of instructions or data structures readable by a computer processor, or combinations thereof. Additionally, various forms of computer-readable media can send or carry instructions to a computer, including routers, gateways, servers, or other wired (coaxial cable, fiber optic, twisted pair, DSL cable) or wireless (infrared, radio, cellular, microwave) transmission devices. Instructions can include code from any computer programming language, including but not limited to assembly, C, C++, Visual Basic, HTML, SQL, PHP, Java, Javascript, Python, and bash scripts.

[0056] Unless otherwise specifically stated, it should be understood that throughout the following description, discussions using terms such as processing, calculation, operation, determination refer to the actions or processes of a computer or computing system or similar electronic computing device that manipulate or convert data representing physical (e.g., electronic) quantities in the registers or memory of the computing system into other data representing physical quantities similarly represented in the memory, registers, or other such information storage, transmission, or display devices of the computing system.

[0057] The terms “comprising,” “including,” “having,” and any variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0058] Additionally, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0059] The terms “computing machine,” “computer,” “computing node,” “computing device,” “processing device,” “processing node,” or “core” as used in this subject matter disclosure are intended to cover, but not limited to, any computer, processor, calculator, computing system, computing node, computing task, computer job, processing, algorithm, and processing resources, processing, or computing operation configured to use or utilize mechanical phenomena.

[0060] In the following description and claims, the terms “coupled” and “connected” and their derivatives may be used. In certain embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact with each other. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0061] As used herein, the term "packet" can include data units that can be routed or transmitted between nodes or stations or across a network. As used herein, the term packet can include frames, protocol data units, or other data units. A packet can include a set of bits, which may include, for example, one or more address fields, control fields, and data. A data block can be any unit of data or information bits.

[0062] This subject matter disclosure can be advantageously implemented on any computing machine in a distributed computing environment comprising several computing machines (e.g., processors) operatively coupled to each other for data communication, such as via a data communication network (e.g., an Ethernet-based packet data communication network). Examples of computing machines on which embodiments of this subject matter disclosure can be advantageously implemented include, but are not limited to, processors, which can be any suitable microprocessor, microcontroller, processing core, central processing unit (CPU), quantum processing unit (QPU), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), digital signal processing chip and / or state machine or combination thereof.

[0063] It should be understood that the embodiments disclosed herein can be used in a variety of applications. While the invention is not limited thereto, the methods for data communication disclosed herein can be used in many devices, such as in any processor configured for inter-processor data communication, such as microcontrollers in network nodes in industrial networks, for example. However, the technical features of the invention are not limited thereto.

[0064] In the following description, the proposed methods according to embodiments disclosed in this subject matter are described in the context of a distributed computing environment that can be used for electric motor drives. However, those skilled in the art will understand that this context is merely exemplary and illustrative, and embodiments of the proposed methods can be used for data communication between two computing nodes (machines, processors) in a distributed computing environment in contexts other than electric motor drives.

[0065] Figure 1a An exemplary computing environment (10) in which the proposed method can be advantageously implemented is shown.

[0066] Figure 1a An exemplary computing environment (10) is shown, including a first data processing device (11), which in some embodiments, via, as Figure 1a The shared memory (13) shown is operatively coupled for data communication with the second data processing device (12).

[0067] In some embodiments, the computing environment (10) may include a third data processing device (14) operatively coupled to a second data processing device (12) for data communication.

[0068] In some embodiments, each of the first, second, and third data processing devices (11, 12, 14) may include a processor (the first processor, the second processor, and the third processor, respectively), which may be any suitable microprocessor, microcontroller, field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), digital signal processing chip, and / or state machine or combination thereof.

[0069] According to various embodiments, one or more of the first, second, and third data processing devices (11, 12, 14) may be configured as a multiprocessor computer having multiple processors for providing parallel computing. Each of the first, second, and third data processing devices (11, 12, 14) may also include a computer storage medium (such as, but not limited to, memory) capable of storing computer program instructions or software code, or capable of communicating with the computer storage medium, which, when executed by a processor of the first, second, 12, 14, causes the processor to execute the elements described herein. Additionally, the memory may be any type of data storage computer storage medium capable of storing data, such as data packets, for use according to one or more embodiments disclosed herein, and the memory may be coupled to the first, second, and third data processing devices (11, 12, 14) respectively to facilitate processing of the data stored therewith.

[0070] It should be understood, for reference Figure 1a Each of the first, second, and third data processing devices (11, 12, 14) shown and described is provided by way of example only. Many other architectures, operating environments, and configurations are possible.

[0071] In one or more embodiments, each of the first processor (11a) and the second processor (12a) of the first data processing device (11) and the second data processing device (12) may be configured to perform tasks asynchronously, performing real-time tasks or near real-time tasks in some embodiments.

[0072] For example, in some embodiments, the first processor (11a) may be configured to execute computer processing task 1 every millisecond, and the second processor (12a) may be configured to execute another computer processing task 2 every 3 milliseconds.

[0073] In some embodiments, as part of or while performing computer processing task 1, the first processor (11a) may be configured to transmit data (continuously in some embodiments) to the second processor (12a). In some embodiments, as part of or while performing computer processing task 1, the first processor (11a) may be configured to transmit data (continuously in some embodiments) to the third processor (14a), or in some embodiments via the second processor (12a).

[0074] therefore, Figure 1a The three processors shown can form a processor chain for transmitting data from the first processor (11a) (which may be referred to as the "sender processor") to the third processor (14a) (which may be referred to as the "receiver processor") via the second processor (12a) (which may be referred to as the "intermediate processor" herein).

[0075] In one or more embodiments, the first processor (11a) (sender processor) may be configured to send data as a data stream of data packets to the second processor (12a) as part of sending data to the third processor (14a) (receiver processor) via the second processor (12a) (intermediate processor).

[0076] This topic discloses data transmission schemes that can be advantageously used in computer environments, such as... Figure 1a The environment (10) shown depicts data being transmitted from a sending processor (11a) to a receiving processor (14a) via an intermediate processor (12a). The intermediate processor (12a) is configured to relay data received from the sending processor (11a) to the receiving processor (14a), and in some embodiments, performs little or no processing other than relaying the received data. Advantageously, the intermediate processor (12a) may have limited capabilities, such as limited processing and / or data communication capabilities (e.g., compared to the capabilities of the sending processor (11a) and the receiving processor (14a), and may not be configured to decode the received data to perform processing on such data. For example, in some embodiments, the intermediate processor (12a) may be a processor of a low-cost platform designed for a variety of devices, such as microcontrollers, industrial control systems, and wireless network systems. In some embodiments, the sending processor (11a) may have greater capabilities, including capabilities related to data processing, and may include, for example, a digital signal processor. Figure 1aIn the example shown, the sending processor (11a) may include a DSP core configured to control an electric motor, and the intermediate processor (12a) may be a microcontroller configured to execute application-level software (e.g., characterized by an application core), both processors being components of the motor drive platform (15). Additionally, in some embodiments, the receiving processor (14a) may be any suitable processor for data communication with the sending processor, according to any suitable data communication protocol. Figure 1a In the illustrative example, a suitable processor is used for an Ethernet server.

[0077] In some embodiments, the sending processor (11a) and the receiving processor (14a) may be configured to transmit and receive data respectively according to a data communication protocol. Advantageously, the intermediate processor (12a) may not be configured to fully implement the data communication protocol, and may only be configured to implement a portion of the data communication protocol that is compatible with its limited capabilities to a certain extent. In some embodiments, the intermediate processor (12a) may not be configured to implement the data communication protocol, such that it may not be configured to process (interpret) any messages (e.g., signaling messages) of the data communication protocol used by the sending processor and the receiving processor.

[0078] Figure 1a The exemplary architecture is advantageously compatible with the following use case: in which a first processor (11a) and a second processor (12a) are included in a first device (15) (e.g., mounted on an electronic board and operatively coupled to each other via a communication bus), and a third processor (14a) is included in a second device (16), the second device (16) being operatively coupled to the first device (15) via a data communication link, for example, a data communication network (17). In such a use case, the first processing device (11a) can be configured for tasks such as data collection and processing, and data transfer using the first processor (11a) to the third processing device (14a), the first processor (11a) sending data to the third processor (14a) via the second processor (12a), the second processor (12a) being used only to relay received data and send such received data to the third processor (14a) via the data communication interface of the first device (15) (which may be implemented (provided) by the second processor (12a)), the data communication network (17), and the data communication interface of the second device (16). Then, the data can be sent from the sender processor (11a) of the first device (15) to the receiver processor (14a) of the second device (16) via the intermediate processor (12a) of the first device (15). In some embodiments, the intermediate processor (12a) has limited capabilities (in terms of processing power or data communication capabilities).

[0079] Figure 1b Another exemplary computing environment (20) in which the proposed method can be advantageously implemented is shown.

[0080] Figure 1b Another exemplary computing environment (20) is shown, comprising a chain of N processors (20a_1 to 20a_N) included in respective data processing devices (20_1 to 20_N). In one or more embodiments, a processing device (20_1) including a first processor (20a_1) of the chain can be operatively coupled for data communication with a processing device (20_2) including a second processor (20a_2) of the chain. In one or more embodiments, a processing device (20_N) including the last processor (20a_N) of the chain (the receiving processor) can be operatively coupled for data communication with a processing device (20_N-1) including a processor preceding the last processor of the chain (20a_N-1).

[0081] In one or more embodiments, in addition to the sender processor (20) Processors other than the receiver processor (20a_N) and the receiver processor (20a_i) Each processing device (20_i, ) ) can be used as an intermediate processing device for the chain (20_i, Each intermediate processing unit includes an intermediate processor (20a_i, ).

[0082] In one or more embodiments, each intermediate processing device (20_i, ...) in the chain ... ( ) can be operatively coupled for data communication with both preceding and following processing units in the chain. In one or more embodiments, each intermediate processor (20a_i, ) can be operatively coupled to be used with the processor immediately preceding it in the chain (20a_i-1) (20a_i-1, respectively) ) and the processor immediately following it in the chain (20a_i +1) (20a_i +1, respectively, (to conduct data communication.)

[0083] In one or more embodiments, the sending processor (20a_1) of the chain can be configured to communicate with one or more (in some embodiments each) intermediate processors (20a_i, ...) of the chain. The data is sent to the receiver processor (20a_N) of the chain.

[0084] This topic publicly provides information that can be advantageous in areas such as Figure 1b The data transfer scheme used in the computer environment shown in environment (20) is such that data will pass through one or more intermediate processors (20a_i, ) forming a chain of intermediate processor sequences. The data is sent from the sender processor (20a_1) to the receiver processor (20a_N), where the sender processor (20a_1) is... The first processor in the processor chain, the receiver processor (20a_N), is... The last processor in the processor chain. In some embodiments, one or more intermediate processors (20a_i, ..., ...) are used to send data from the sending processor (20a_1) to the receiving processor (20a_N). One or more of the processors (in some embodiments, each) may have limited capabilities, such as limited processing and / or data communication capabilities (e.g., compared to the capabilities of the sender processor (20a_1) and receiver processor 20a_N), and may, for example, lack the ability to decode received data to perform processing on such data. In some embodiments, the sender processor (20a_1) and receiver processor (20a_N) may be configured for data sending and data receiving, respectively, according to a data communication protocol. In some embodiments, the sender processor (20a_1) and receiver processor (20a_N) may be the only two processors in the chain with data communication capabilities consistent with the implementation of a data communication protocol, such as an Internet data communication protocol (e.g., TCP / IP type). In some embodiments, the intermediate processor of the chain (20a_i, At least one of them may not have data communication capabilities consistent with the data communication protocol used for data communication by the sending processor (20a_1) and the receiving processor (20a_N). Advantageously, the intermediate processor of the chain (20a_i, At least one of them may not be configured to fully implement the data communication protocol used for data communication by the sending processor (20a_1) and the receiving processor (20a_N), and may only be configured to implement a portion of such a data communication protocol that is compatible (to a certain extent) with its limited capabilities (or not implemented in some embodiments).

[0085] Figure 1b The exemplary architecture is advantageously compatible with the following use case where: a first processor (20a_1) (sender processor) and a second processor (20a_2) (first intermediate processor of the chain) are included in a first device (21_1) (e.g., mounted on an electronic board and operably coupled to each other via a communication bus of the electronic board), while in some embodiments, the i-th intermediate processor (20a_i) is included in M ​​devices (21_j, In the intermediate devices (21_j) of the chain, these devices are coupled to each other for data communication through the chain of processors, and in some embodiments, the last processor (20a_N) (the receiving processor) and the processor before the last processor (20a_N-1) (the last intermediate processor of the chain) can be included in M ​​devices (21_j, In the last device (21_M) of the chain, these devices are coupled to each other for data communication through the processor chain.

[0086] In such a use case, the first processing unit (20_1) of the chain can be configured for tasks such as data collection and processing, and data transfer from the first processor (20a_1) of the chain to the last processing unit (20_N) of the chain, via the chain's intermediate processor (20a_i). ) sends data to the last processor (20a_N) in the chain, and the intermediate processor (20a_i, One or more of these can be used only for relaying slave chains in the preprocessor (20a_i-1, The data received by ) and via device (21_j, The corresponding data communication interface of the chain device may send such received data to the next (immediately following) processor (20a_i+1) of the chain via one or more communication networks (23_1, 23_2). Then, the data can be processed through one or more intermediate processors (20a_i, ...). The data is sent from the sender processor (20a_1) of the first device (21_1) to the receiver processor (20a_N) of the second device (21_M). In some embodiments, one or more of the intermediate processors (20a_i) have limited capabilities (in some embodiments, in terms of processing capabilities or data communication capabilities, relative to the capabilities of one or both of the sender processor (20a_1) and the receiver processor (20a_N).

[0087] Figure 2 Exemplary data packets are shown that can be used for transmission from a sending processor to a receiving processor via one or more intermediate processors in one or more embodiments.

[0088] Figure 2 The data group (20) is shown, which includes a header (21) followed by payload data, which is organized as follows: A sequence of data units, carrying, for example, so-called "variables," corresponding to payload data to be sent from the sending processor to the receiving processor. Depending on the embodiment, Data units can have a fixed size (e.g., bit size, byte size) or a variable size.

[0089] In some embodiments, the header (H) may include: a sequence number, for example, carried by a 3-bit field of the header (H); a data rate field, for example, 11-bit precision loss; and an enumeration value (for example, encoded on 2 bits) carrying the pulse width modulation (PWM) range.

[0090] In some embodiments, the PWM value may correspond to the frequency of data transmission used by the transmitter. For example, a 4 kHz PWM value may correspond to data transmitted at a data transmission frequency of 4 kHz.

[0091] In some embodiments, the PWM range may correspond to the range of data transmission frequency values ​​used by the sender of the data packets.

[0092] In some embodiments, the number of data units in a data packet is determined based on a known correspondence between the sender of the data packet (in some embodiments, a sender processor) and the receiver of the data packet (in some embodiments, a receiver processor). It can be based on the PWM range.

[0093] Refer again Figure 1a In some embodiments, the payload carried by each data unit may correspond to data related to a corresponding variable that needs to be transmitted from the first processor (sender processor) (11a) to the third processor (receiver processor) (14a).

[0094] In some embodiments, the number of variables for which the sending processor (11a) obtains its value can be dynamically adapted to the maximum data rate available for variable transfer via one or more intermediate processors to the receiving processor (14a).

[0095] For example, in some embodiments, one or more variables may be logged at each function call of a task executed by the sending processor, while other variables may be logged at each... Record once per function call. It is greater than or equal to 2. ) is a natural integer.

[0096] Refer again Figure 1a As part of executing Task 1, the first processor (sender processor) (11a) can write data to be sent to the third processor (receiver processor) (14a) via the second processor into a RAM memory shared by the first processor (sender processor) (11a) and the second processor (intermediate processor) (12a).

[0097] Using a shared RAM memory configured between the first processor (sender processor) (11a) and the second processor (intermediate processor) (12a) advantageously allows data to be transferred from the first processor (sender processor) (11a) to the second processor (intermediate processor) (12a) at a data rate consistent with the operation of the first processor (sender processor) (11a) and the operation of the second processor (intermediate processor) (12a).

[0098] Start and stop

[0099] In one or more embodiments, a transport protocol for transmitting a data stream comprising data packets between two processors (a sending processor and a receiving processor) may define start data packets and stop data packets for signaling the start and stop of transmission, respectively.

[0100] Figure 3a An exemplary starting data grouping is shown according to one or more embodiments.

[0101] In some embodiments, the starting data packet may include a predefined starting pattern, which may have a fixed length (e.g., several bytes) to distinguish it from other data transmitted by the sending processor. In some embodiments, the starting pattern may include one or more (predefined number) predefined starting bit patterns (in... Figure 3a In the example shown, the four bit patterns, “St1”, “St2”, “St3”, and “St4” (e.g., one or more predefined start bytes), can be repeated a predefined number of times in some embodiments (in some embodiments, the predefined number of times can be selected based on the corresponding length of the start pattern). In some embodiments, the start data packet may also include a CRC corresponding to the start pattern of the start data packet.

[0102] Figure 3b Exemplary stop data grouping is shown according to one or more embodiments.

[0103] In some embodiments, the stop data packet may include a predefined stop pattern, which may have a fixed length (e.g., several bytes) to distinguish it from other data transmitted by the sending processor. In some embodiments, the stop pattern may include one or more (predefined number) predefined stop bit patterns (in... Figure 3bIn the example shown, the four bit patterns, “Sp1”, “Sp2”, “Sp3”, and “Sp4” (e.g., one or more predefined stop bytes), can be repeated a predefined number of times in some embodiments (in some embodiments, the predefined number of times can be selected based on the corresponding length of the stop pattern). In some embodiments, the stop data packet may also include a CRC corresponding to the stop pattern of the stop data packet.

[0104] In some embodiments, one or more of the start data packet and stop data packet may be sent by the sending processor to the receiving processor to initiate or reset the transmission of the data stream. In some embodiments, the transmission of the reset data stream may be performed when a predefined data stream reset condition occurs, such as one or more of the following: a PWM change occurs, or data is not written to the shared RAM memory.

[0105] In one or more embodiments, the predefined stop pattern may be the same as the predefined start pattern, such that a single type of start / stop data packet can be used to signal the start and stop of transmission by the transmitter processor. In embodiments where data is continuously or substantially continuously streamed to a second processor for transmission to a third processor, using a single type of start / stop data packet may be advantageous.

[0106] Return to reference Figure 1a and Figure 1b In embodiments where data is sent from the first processor (11a) to the third processor (12a) via the second processor (12a), it is advantageous to select the second processor (12a) which has scarce resources and / or limited capabilities, so that the processor immediately preceding the processor in the processor chain (20a_i-1) (in Figure 1a In the example, the data received by the first processor (11a) is relayed to the next processor in the processor chain (20a_i + 1). Figure 1aIn the example, the second processor (12a) is the third processor (14a). In such an embodiment, the second processor (12a) may be a processor with limited capabilities, including regarding processing power, on-chip memory, etc. For example, in some embodiments, limitations associated with the operation of the second processor (12a) may include one or more of the following: a fixed task frequency (e.g., a low value of 4 kHz), a maximum data rate (e.g., a data rate less than or equal to 128 bytes / millisecond), a limited RAM size available to the second processor (12a), a limited ROM size available to the second processor (12a), and limited processing performance of the second processor (12a). However, advantageously, the limited resources and capabilities of the second processor (12a), operating as an intermediate processor in a processor chain, may be sufficient to implement the schemes proposed in this subject matter disclosure, as such schemes can be advantageously used in intermediate processors with strict constraints in terms of resources and capabilities.

[0107] In some embodiments, the second processor (12a, 20a_i, i = 2, ..., N-1) may not have decoding capability from the processor chain immediately preceding the processor (20a_i-1) (in... Figure 1a In the example, the first processor (11a) may not be configured to receive data from the processor immediately preceding the processor in the processor chain (20a_i-1). Figure 1a In the example, the data received by the first processor (11a) can be used solely to transfer the received data to the next processor in the processor chain (20a_i+1) by copying the received data from a first (e.g., smaller in some embodiments) (memory) buffer (e.g., shared RAM (13)) to a second (larger in some embodiments) (memory) buffer. Figure 1a In the example, the third processor (14a) is used. For example, in some embodiments, the second processor (12a, 20a_i, i = 2, ..., N-1) can be configured to read from the processor immediately preceding it in the processor chain (20a_i-1). Figure 1aIn the example, the first processor (11a) writes data to the shared RAM (13) and writes such data to a buffer (referred to as the "application buffer") operatively coupled to the second processor (12a, 20a_i, i = 2, ..., N-1) (or integrated in the same chip as the second processor (12a, 20a_i, i = 2, ..., N-1)), where there is no data processing between reading from the shared RAM and writing to the application buffer. In some embodiments, the second processor (12a, 20a_i, i = 2, ..., N-1) can be configured to only detect new data being written to the shared RAM (13), read the data written to the shared RAM (13), and write that data to its application buffer, without any data processing between reading from the shared RAM and writing to the application buffer. In some embodiments, the application buffer may have a predetermined fixed size, such as 512 bytes.

[0108] In some embodiments, the size of the memory buffer used by the processor (20a_i) in the processor chain can be selected based on one or more of the following: the execution frequency of the computer task performed by the processor (20a_i) (e.g., the task "Task_i" of the processor (20a_i)) and the minimum data transfer rate on the processor chain.

[0109] In one or more embodiments, the second processor (12a, 20a_i, where i = 2, ..., N-1) may be configured to read data stored in shared RAM memory and write such data to an application buffer during each task invocation of a task executed by the second processor (12a, 20a_i, i = 2, ..., N-1) (e.g., task "Task_i" of processor (20a_i)).

[0110] In some embodiments, the second processor (12a, 20a_i, where i = 2, ..., N-1) can be configured to send data stored in the application buffer to the next processor in the processor chain (20a_i + 1) when the application buffer is X% full (e.g., X = 100) – i.e., full to a predetermined degree. Figure 1a In the example, it is the third processor (14a).

[0111] In some embodiments, the second processor (12a, 20a_i, where i = 2, ..., N-1) can be configured to send data stored in the application buffer to the next processor in the processor chain (20a_i + 1) when it is determined that the application buffer is X% full (e.g., X = 100) – that is, full to a predetermined degree. Figure 1aIn the example, it is the third processor (14a).

[0112] In embodiments where data is transmitted from a second processor (12a, 20a_i, where i = 2, ..., N-1) to another processor via a data communication network, sending data stored in the application buffer conditionally when the application buffer is full to a predetermined level advantageously reduces the frequency of data transmission, thereby improving network load. Furthermore, sending data stored in the application buffer conditionally when the application buffer is full to a predetermined level allows for optimization of the CPU time usage of the second processor (by avoiding implementing schemes on the second processor that require decoding received data, such as detecting stop transmission messages (e.g., stop packets)), which can advantageously align with the limited capabilities of the second processor.

[0113] In such an embodiment, it is possible that the application buffer is X% full (e.g., X = 100), that is, full to a predetermined degree, and the last copied data in the application buffer does not correspond to the entire group, but rather to the processor immediately preceding it in the processor chain (20a_i-1). Figure 1a In the example, this is part of a data packet that is streamed from the first processor (11a) to the second processor (12a, 20a_i, where i = 2, ..., N-1). Therefore, the last data packet written to the application buffer may be incomplete.

[0114] Figure 4 This illustrates the transmission of a data stream from a first (sender) processor to a third (receiver) processor according to one or more embodiments disclosed in this subject matter.

[0115] This disclosure advantageously provides a scheme implemented by a sending processor that, in a manner transparent to the receiving processor (particularly to the data communication protocol that can be used for data communication by the sending and receiving processors), makes data transmission to the receiving processor suitable for the use of one or more intermediate processors between the sending and receiving processors, which may have limited resources and capabilities.

[0116] Figure 4 The exemplary system corresponds to Figure 1a The system shown will use the same reference numerals, and reference will be made to the relevant section. Figure 1a The description provided. However, those skilled in the art will understand that, regarding Figure 1a and Figure 4 The embodiments disclosed in this subject matter can be used in any suitable computing environment, such as, for example... Figure 1b The environment shown. Therefore, the term "environment" can also be used in the following text. Figure 1b Reference.

[0117] like Figure 4 As shown, in some embodiments, a first processor (11a, 20a_1) (“MotorControl”) operating as a sending processor can write data packets to a data stream to be sent to a third processor (“Ethernet Server Processor”) operating as a receiving processor, as part of executing a task (“TaskPwm”). In some embodiments, the first, second, and third processors can form a processor chain, wherein the first and second processors are included in a first device (such as, for example, a motor driver), and the third processor is included in a second device (such as, for example, a server). Given Figure 4 The illustrated exemplary system architecture includes a first device operatively coupled to a second device. In some embodiments, data sent from the first device to the second device during the execution of a task by a first processor (11a, 20a_1) can be sent to a third processor via a processor chain formed by the first, second, and third processors. Therefore, in some implementations, data sent by the first processor (11a, 20a_1) (included in the first device) operating as a sending processor to a third processor (included in the second device) operating as a receiving processor can be sent via one or more intermediate processors in the processor chain between the sending and receiving processors, for example in… Figure 1a and Figure 4 The second processor in the exemplary system (e.g., application microcontroller 12a).

[0118] In one or more embodiments, the first processor (11a, 20a_1) may be configured to write data packets of a data stream to be sent to a third processor into a memory shared between the first processor (11a, 20a_1) and the second processor, so as to send the data stream to the third processor (“Ethernet server processor”) via the second processor (e.g., application microcontroller 12a).

[0119] In one or more embodiments, the second processor may be configured to read data written to the shared memory when it is detected that data has been written to the shared memory. In some embodiments, the second processor may also be configured to write data read from the shared memory into a (memory) buffer.

[0120] Such as about Figure 2 As described, in some embodiments, data packets in a data stream transmitted from a first processor (11a, 20a_1) to a third processor via a second processor may include a header and one or more payload fields (“Vark”, ). ).

[0121] Such as about Figure 3a As described, in some embodiments, the start of transmission of P data packets of a data stream sent from the first processor (11a, 20a_1) to the third processor can be signaled to the third processor via a start data packet (examples of which are shown in...). Figure 3a (As shown above). In some embodiments, the second processor may not be configured to use signaling packets such as start data packets, and may write received start data packets as any other data read from shared memory into its (memory) buffer. In some embodiments, one or more intermediate processors located in the data communication chain between the sending processor and the receiving processor may not be configured (or have the capability) to perform processing (including reading and interpreting one or more signaling packets) on one or more signaling packets sent by the sending processor to the receiving processor.

[0122] like Figure 4 As shown, in one or more embodiments, the second processor may be configured to generate a header data unit to be written to its (memory) buffer first when it detects that data has been received and is to be written into its (late-stage) buffer for transmission to the next (immediately following) processor in the data communication chain of the processor.

[0123] In one or more embodiments, the (memory) buffers for data communication via the second processor can be configured as a set. The memory buffer has several memory segments, and the header data units can have a predefined (bit) length corresponding to the length of the (first) segment of the (memory) buffer. For example, in some embodiments, the (memory) buffer can have a storage capacity of 512 bytes and can include a fixed-size 4-byte segment. Each segment.

[0124] In one or more embodiments, the header data unit may include data related to the size of the (memory) buffer (e.g., in some embodiments, indicating the number of segments). Data, and in some embodiments where the segment size is fixed, data representing the size of each segment.

[0125] like Figure 4As shown, when its (memory) buffer is empty, the second processor can be configured to initiate a (first) data transfer cycle upon receiving new data (e.g., written to shared memory). In some embodiments, this may include: writing header data units into a first segment of its (memory) buffer, and writing received data into a segment of its (memory) buffer upon receiving data, until its (memory) buffer is X% full (e.g., X = 100), i.e., full to a predetermined degree. Once the first (memory) buffer (“TaskFast first buffer”) is X% full (e.g., X = 100), i.e., full to a predetermined degree, the second processor can send the contents of the first (memory) buffer (the data stored in the first (memory) buffer) to the next (immediately following) processor in the processor chain. Figure 4 In an exemplary case, a third processor (i.e., the receiving processor) is used to end the data transmission cycle.

[0126] In some embodiments, the header data unit may be used as a header for data stored in a (memory) buffer used by a second processor. In some embodiments, the header data unit may include a counter that counts the number of data packets stored in the (memory) buffer. For example, the counter may be initialized to a predetermined value and may be updated (e.g., incremented) each time a new data packet is written to the (memory) buffer of the second processor.

[0127] In one or more embodiments, when the (memory) buffer is cleared by sending the contents of the first (memory) buffer, the second processor may initiate another data transfer cycle, which may also include: writing header data units to a first segment of its (memory) buffer, writing received data to a segment of its (memory) buffer upon receiving data, until its (memory) buffer is X% full (e.g., X = 100), i.e., full to a predetermined degree, and once the (memory) buffer (“TaskFast next buffer”) is X% full (e.g., X = 100), i.e., full to a predetermined degree, sending the contents of the first (memory) buffer (the data stored in the first (memory) buffer) to the next (immediately following) processor in the processor chain (in... Figure 4 In an exemplary case, this is a third processor, namely the receiver processor.

[0128] In some embodiments, depending on the structure of the data stream sent by the first (transmitter) processor, a portion of a data packet or a packet header may be written into the last segment of a (memory) buffer during the data transmission cycle. For example, as Figure 4 As shown, in some embodiments, the (memory) buffer (in) Figure 4In the example, the last segment of the first and third (memory) buffers can be used to store variables grouped into data, and the other (memory) buffer (in...) Figure 4 In the example, the last segment of the second (memory) buffer can be used to store the header of the data packet.

[0129] Intermediate Processor Traffic Management Strategy

[0130] In one or more embodiments, the second processor may be configured with buffer management rules (traffic management policies) for managing the storage of received data into its buffer memory. In some embodiments, according to the buffer management rules (traffic management policies), data packets in a stream of data packets may be written into the buffer memory as they are received until the buffer memory is X% full (e.g., X = 100), that is, full to a predetermined degree (X%).

[0131] In one or more embodiments, according to the buffer management rule (flow management strategy), when it is determined that the buffer memory is X% full (e.g., X = 100) – that is, full to a predetermined degree – the received data packets of the stream of data packets written to the buffer memory can be sent to the third processor. Depending on the embodiment, the data can be sent to the third processor by the second processor using a data transmission message according to any suitable data communication protocol (consistent with the data communication capabilities of the second processor), or using shared memory where the data to be sent is written.

[0132] In one or more embodiments, the buffer management rules (flow management policies) used by the second processor may specify that data stored in the (memory) buffer can only be sent to the next (immediately following) processor in the processor chain when it is determined that the (memory) buffer is X% full (e.g., X = 100), that is, full to a predetermined level. Figure 4 In an exemplary case, this is a third processor (i.e., the receiving processor) to optimize the transmission flow of data packets through the second (intermediate) processor. In some embodiments, the second (intermediate) processor may be a processor with limited capabilities (particularly for data processing in data communication).

[0133] Operations at the first processor (sender processor):

[0134] Figure 5a A block diagram illustrating a proposed method (100a) for data communication for a sending processor according to an embodiment disclosed in this subject matter is shown.

[0135] One could consider the first processor in the computing environment, such as, for example Figure 1a or Figure 1bThe computing environment (10, 20) includes a first processor configured to operate as a sending processor (11a, 20a_1) in a processor chain for data transfer from the first processor to a third processor via one or more second processors, the third processor configured to operate as a receiving processor (14a, 20a_N), and one or more second processors configured to operate as intermediate processors (12a, 20a_i, where i = 2, ..., N-1). In one or more embodiments, the first processor may be operatively coupled to a subsequent processor in the chain for data communication, such as a second processor operating, for example, as an intermediate processor coupled to the first processor.

[0136] In one or more embodiments, the first processor and the second processor may be processors in a processor chain for data communication from the first processor operating as a sending processor—the first processor in the processor chain—to the third processor operating as a receiving processor—the last processor in the processor chain.

[0137] In one or more embodiments, the second processor may be an intermediate processor in a processor chain through which data is sent from a first (sender) processor to a third (receiver) processor.

[0138] In some embodiments, a processor chain for data transfer from a sending processor to a receiving processor can be used to send data from a first processor operating as a sending processor to a receiving processor, such that the data being sent can be transmitted via a second (intermediate) processor. Therefore, in some embodiments, data can be sent from the first (sending) processor to a third (receiving) processor via a second (intermediate) processor for transmission to the receiving processor at the end of the processor chain. From the perspective of the first processor, according to the proposed scheme, data can be sent to the third processor in a manner that considers the presence of one or more intermediate processors in the data transfer path from the first processor to the third processor.

[0139] In the following text, we will combine Figure 1a and 1b The proposed method for data communication for the sending processor is described. Figure 1a and 1b The illustration shows a non-limiting and exemplary case where the second processor is an intermediate processor for data transmission from the sending processor to the receiving processor. (See also: Regarding...) Figure 1aIn some embodiments (where the second (intermediate) processor immediately follows the first (sender) processor in the processor chain), data is sent by the first processor to the second processor using shared (RAM) memory coupled to the first and second processors, for transmission to the third (receiver) processor. In some embodiments, data may be sent by the first processor by writing the data to the shared memory, and the data may be read from the shared memory by the second processor (the intermediate processor immediately following the first processor in the processor chain formed by the first, second, and third processors).

[0140] In one or more embodiments, the first processor may send (101a) data (e.g., data packets) to the third processor, in some embodiments via shared memory coupled to the first and second processors. For example, in some embodiments, the first processor may send data to the third processor via the second processor. In some embodiments, the data packets are streamed via a shared memory coupled to a first processor and a second processor. In some embodiments, the first processor can send data packets to a third processor via the second processor, with the first processor operating as the first processor in a processor chain, the second processor operating as an intermediate processor in the processor chain, and the receiving processor being the last processor in the processor chain.

[0141] In some embodiments, Data packets can be streamed continuously or substantially continuously to a second processor (in some embodiments via shared memory) until the stream ends. Data packet transmission stops (e.g., when data packet transmission is completed, interrupted, or reset).

[0142] In one or more embodiments, when it is determined that the transmission of data (in the stream) packets should be stopped (e.g., when the transmission of data (packets) is complete, interrupted, or reset), the first processor may stop (102a) sending data (to the third processor) for a first predetermined duration. In some embodiments, when it is determined that the transmission of data packets in the stream should be stopped (e.g., when the transmission of data packets is complete, interrupted, or reset), the first processor may stop writing data to memory shared with the second processor for a first predetermined duration to stop data transmission (to the third processor) for the first predetermined duration.

[0143] In one or more embodiments, when the first predetermined duration expires, the first processor may send (103a) subsequent data (e.g., one or more subsequent data packets) to the third processor.

[0144] The first predetermined duration can be advantageously used to pause data transmission for a predetermined period of time. This data transmission pause—which can be transparent to the receiving processor—can be used by an intermediate processor in the processor chain between the sending and receiving processors, as described in further detail in this disclosure according to its embodiments.

[0145] In some embodiments, one or more subsequent data packets may include a transmission end signaling packet. In some embodiments, the transmission end signaling packet may be associated with... Figure 3b The described stop data packet corresponds to this. Advantageously, the end-of-transmission signaling packet may not be decoded by one or more intermediate processors in the processor chain between the sending and receiving processors, which can process their reception and send such an end-of-transmission signaling packet to the next processor in the chain without decoding (interpreting) the end-of-transmission signaling packet.

[0146] In one or more embodiments, the first processor may use a first timer to stop data transmission (to the third processor) for a first predetermined duration. In some embodiments, the first processor may be configured to start a transmitter transmission end timer when it is determined that transmission of a data packet is to stop. In some embodiments, the transmitter transmission end timer may be configured to expire at the end of the first predetermined duration.

[0147] In some embodiments, the first processor may be configured to stop data transmission (to the third processor) while the transmitter transmission end timer is running.

[0148] For example, in some embodiments, the first processor may be configured to send to the third processor. The stream of data packets, and once they have been sent The last packet of a data packet stream is interrupted from transmitting data to the third processor for a first predetermined duration. Specifically, once... Once the last packet of the data packet stream has been sent, the first processor can send any signaling messages that need to be sent, in accordance with the data communication protocol used by the first processor to send data to the third processor, only after a transmission pause of a first predetermined duration.

[0149] In one or more embodiments, the first processor may be configured to continue sending subsequent data (one or more subsequent data packets) (e.g., sending a transmission end signaling packet) to the third processor when it is determined that the transmitter transmission end timer has expired.

[0150] In one or more embodiments, the first processor may be configured to stop data transmission (to the third processor) for a second predetermined duration when sending subsequent data (e.g., one or more subsequent data packets) (e.g., sending a transmission end signaling packet) (to the third processor).

[0151] In one or more embodiments, the first processor may use a second timer to stop data transmission to the third processor for a second predetermined duration. In some embodiments, the first processor may be configured to start a transmitter stop transmission timer when sending subsequent data (e.g., one or more subsequent data packets) (e.g., sending a transmission end signaling packet) to the third processor. In some embodiments, the transmitter stop transmission timer may be configured to expire at the end of the second predetermined duration.

[0152] According to embodiments, the first predetermined duration and the second predetermined duration can be defined in relation to each other. In some embodiments, the first predetermined duration and the second predetermined duration can be defined as equal, such that the first processor can advantageously manage only one predetermined duration parameter.

[0153] Operations at the second processor (intermediate processor):

[0154] Figure 5b A block diagram illustrating a proposed method for data processing (100b) by an intermediate processor (of a processor chain) according to an embodiment disclosed in this subject matter is shown.

[0155] As mentioned above Figure 5a As mentioned above, a second processor in the computing environment can be considered, for example... Figure 1a or Figure 1b The computing environment (10, 20) includes a processor chain for data transfer from a first (sender) processor (11a, 20a_1) to a third (receiver) processor (14a, 20a_N) via one or more second (intermediate) processors configured to operate as intermediate processors (12a, 20a_i, i = 2, ..., N-1). In one or more embodiments, the second processors may be operatively coupled to the processor immediately preceding them in the chain (e.g., the first processor operating as a sender) and the processor immediately following them in the chain (e.g., the third processor operating as a receiver) for data communication.

[0156] In one or more embodiments, the first processor and the second processor may be processors in a processor chain for data transmission from the first processor, which operates as a sending processor, to a receiving processor, which is the last processor in the processor chain. The second processor may be an intermediate processor in the processor chain through which data is transmitted from the sending processor to the receiving processor. In some embodiments, a processor chain for data transmission from the sending processor to the receiving processor may be used to transmit data from the first processor, which operates as a sending processor, to the receiving processor, such that the transmitted data may be transmitted via the second (intermediate) processor. Therefore, in some embodiments, data may be transmitted from the first (sending) processor to the second (intermediate) processor for transmission to the receiving processor at the end of the processor chain. Therefore, in some embodiments, data transmitted by the first (sending) processor for transmission to the receiving processor at the end of the processor chain may be received by the second (intermediate) processor.

[0157] Such as about Figure 1a As described, in some embodiments, data can be sent by a first processor to a second processor using shared (RAM) memory coupled to both the first and second processors. In some embodiments, data can be sent by a first (transmitter) processor by writing the data to be sent into the shared memory, and the data to be sent can be read from the shared memory by a second (intermediate) processor.

[0158] In one or more embodiments, the second processor (12a, 20a_i, where i = 2, ..., N-1) may be configured to receive (101b) data (e.g., one or more data packets) from the first processor (11a, 20a_1). For example, in some embodiments, the second processor (12a, 20a_i, where i = 2, ..., N-1) may be configured to receive (101b) from the first processor (11a, 20a_1). A stream of data packets, where P is a natural integer greater than or equal to 10. ).

[0159] In one or more embodiments, a second processor (12a, 20a_i, where i = 2, ..., N-1) in a processor chain between a sending processor and a receiving processor can serve as an intermediate processor in the processor chain to receive data sent from the first (sending) processor to the third (receiving) processor.

[0160] In one or more embodiments, as an intermediate processor in a processor chain, a second processor (12a, 20a_i, where i = 2, ..., N-1) can be configured to receive data sent by the sending processor (11a, 20a_i-1, where i = 2, ..., N-1) to the receiving processor (14a, 20a_N) of the chain from the processor immediately preceding the second processor (12a, 20a_i, where i = 2, ..., N-1) in the chain.

[0161] In one or more embodiments, as an intermediate processor in a processor chain, a second processor (12a, 20a_i, where i = 2, ..., N-1) can be configured to send data received from a processor (11a, 20a_i-1, where i = 2, ..., N-1) preceding the second processor (12a, 20a_i, where i = 2, ..., N-1) in the chain (sent by the sending processor (11a, 20a_1) of the chain to the receiving processor (14a, 20a_N) of the chain) immediately following the second processor (12a, 20a_i, where i = 2, ..., N-1) in the chain (14a, 20a_i+1, where i = 2, ..., N-1).

[0162] In one or more embodiments, the second processor (12a, 20a_i, where i = 2, ..., N-1) may be configured to store the received data (102b) in a (memory) buffer. In some embodiments, the second processor (12a, 20a_i, where i = 2, ..., N-1) may be configured to store the received data (e.g., one or more received data packets) in a memory coupled to the second processor (12a, 20a_i, where i = 2, ..., N-1).

[0163] In one or more embodiments, the second processor (12a, 20a_i, where i = 2, ..., N-1) can be configured to read new data received in memory (e.g., shared with a processor (20a_i-1) immediately preceding the second processor (12a, 20a_i, where i = 2, ..., N-1) in the processor chain, such as the first processor (11a)) and write such newly received data into a (memory) buffer coupled to the second processor (12a, 20a_i, where i = 2, ..., N-1).

[0164] Such as about Figure 1a and Figure 1bAs described, in some embodiments, the second processor (12a, 20a_i, where i = 2, ..., N-1) may not have the capability to decode the received data (e.g., data received from the first processor (11a) (in some embodiments, via the first (sender) processor (11a, 20a_i) and the second (intermediate) processor (12a, 20a_i, where i = 2, ..., N-1) in the processor's data communication chain). The ability of one or more other intermediate processors (20a_2, ..., 20a_i-1) between i = 2, ..., N-1 (20a_i, ..., N-1) to decode the received data may be limited to sending the received data to a third processor (14a, 20a_N). Depending on the embodiment, the third processor may be any processor in a processor sub-chain between the second processor and the receiving processor in a processor chain for data transfer from the sending processor to the receiving processor via one or more intermediate processors (20a_2, ..., 20a_N-1). In some embodiments, data transfer by the second processor may include copying the received data from a first (memory) buffer (e.g., shared RAM (shared with the next processor in the processor chain (20a_i-1))) to a second (memory) buffer managed by the second (intermediate) processors (12a, 20a_i, where i = 2, ..., N-1). The data may be sent by the second (intermediate) processors (12a, 20a_i, where i = 2, ..., N-1). (2, ..., N-1) are sent to the third processor using any suitable data communication protocol consistent with the data communication capabilities of each of the second and third processors.

[0165] For example, in some embodiments, a second (intermediate) processor (12a, 20a_i, where i = 2, ..., N-1) may be configured to write received data (e.g., data from a received data stream) into a (memory) buffer operatively coupled to the second processor (12a, 20a_i, where i = 2, ..., N-1) (or integrated in the same chip as the second processor (12a, 20a_i, where i = 2, ..., N-1)). In some embodiments, the (memory) buffer may have a predetermined fixed size, such as 512 bytes. In some embodiments, according to embodiments disclosed herein, the second (intermediate) processor (12a, 20a_i, where i = 2, ..., N-1) may have only a limited capability to allow the writing of received data packets (e.g., data packets from a stream of data packets) into the (memory) buffer and to manage the transfer of data stored in the (memory) buffer according to certain specific buffer management rules.

[0166] For example, as mentioned above Figure 4In one or more embodiments, the second (intermediate) processor may have limited data processing capabilities, including the ability to perform data communication. In some embodiments, consistent with these limited capabilities, the second (intermediate) processor (12a, 20a_i, where i = 2, ..., N-1) may be configured to follow a flow management policy (which may also be referred to as a "buffer management rule"), according to which the second buffer sends data to the next (immediately following) processor in the processor chain when its buffer memory (containing the data to be sent) is X% full (e.g., X = 100). In some embodiments, the second (intermediate) processor (12a, 20a_i, where i = 2, ..., N-1) may be configured to follow a flow management policy, according to which the second (intermediate) processor (12a, 20a_i, where i = 2, ..., N-1) sends data to the next (immediately following) processor in the processor chain when its buffer memory (containing the data to be sent) is X% full (e.g., X = 100), that is, full to a predetermined degree.

[0167] In one or more embodiments, a second (intermediate) processor (12a, 20a_i, where i = 2, ..., N-1) may be configured to send (103b) data stored in a (memory) buffer to, for example, a third processor (14a, 20a_i+1, ..., 20a_N) when it is determined that no further data has been received from the first (sender) processor (11a, 20a_1) within a third predetermined duration. In some embodiments, the second (intermediate) processor (12a, 20a_i, where i = 2, ..., N-1) may be configured to send (103b) data stored in a (memory) buffer to the next (immediately following) processor (20a_i+1) in the processor chain when it is determined that no data has been received from a previous processor (20a_i-1) in the processor chain, for example, from the first (sender) processor (11a, 20a_1) within a third predetermined duration.

[0168] In an embodiment where the second (intermediate) processor (12a, 20a_i, where i = 2, ..., N-1) is configured to follow a flow management policy, according to which the second buffer sends data to the next (immediately following) processor (20a_i + 1) in the processor chain when its buffer memory (containing the data to be sent) is X% full (e.g., X = 100), this subject matter discloses that the second (intermediate) processor (12a, 20a_i, where i = 2, ..., N-1) can violate the flow management policy when it is determined that no new data has been received during a predetermined period. Advantageously, the data flow from the sending processor through the intermediate processor (in the processor chain, where the first processor (11a, 20a_1) is the sending processor and the last processor (14a, 20a_N) is the receiving processor) to the receiving processor (e.g., ... The termination of transmission of data packets can be managed in a manner compatible with resource- and / or capability-constrained intermediate processors. The proposed scheme advantageously provides management of data transmission (between the sending and receiving processors) by an intermediate processor with limited resources and / or capabilities; for example, the intermediate processor can be configured solely for relaying received data (by managing data stored in a (memory) buffer), and in some embodiments, no further processing of such received data is required.

[0169] In one or more embodiments, the third predetermined duration configured at the second processor (intermediate processor) and the first predetermined duration configured at the first (sender) processor (11a, 20a_1) (sender processor) may be selected to be related to each other.

[0170] For example, in some embodiments, a third predetermined duration may be defined (selected) first, for example based on the characteristics of the buffer memory used by the second (intermediate) processor (12a, 20a_i, where i = 2, ..., N-1) (e.g., the size of the buffer memory) and one or more of the capabilities of the second (intermediate) processor (12a, 20a_i, where i = 2, ..., N-1), and in such embodiments, a first predetermined duration may be defined based on the third predetermined duration.

[0171] As another example, in some embodiments, a first predetermined duration and a third predetermined duration may be defined (selected) based on the execution frequency of one or more (e.g., all) of the intermediate processors in a processor chain configured to implement schemes according to embodiments disclosed herein. For example, in... Figure 1bIn the chain of N processors shown, a first predetermined duration and a third predetermined duration can be defined (selected) based on one or more of the corresponding size of the corresponding (memory) buffer used by the intermediate processors of the chain and the corresponding execution frequency of the corresponding task executed by the intermediate processors of the chain, such that the transmission stop of the processor (of level i) can be recognized by the next (immediately following) processor (of level i+1) in the chain.

[0172] In one or more embodiments, a second (intermediate) processor (12a, 20a_i, where i = 2, ..., N-1) can be configured to monitor whether data is being received (e.g., in some embodiments, by monitoring whether new data is being written to its buffer). If no new data is being received (e.g., because the first (sender) processor has completed the transmission of all packets of the data stream to the receiver processor, or because the first (sender) processor has decided to reset the transmission of packets of the data stream to the receiver processor), no new data can be written to the buffer used by the second (intermediate) processor (12a, 20a_i, i = 2, ..., N-1), such that the second (intermediate) processor (12a, 20a_i, i = 2, ..., N-1) can monitor whether new data is being received by monitoring whether new data is being written to (and stored) in its buffer.

[0173] In one or more embodiments, a second (intermediate) processor (12a, 20a_i, where i = 2, ..., N-1) can be configured to monitor whether data is being received by monitoring whether new data is being written to memory (shared with the first (transmitter) processor (11a, 20a_1) in some embodiments), wherein new data is written to memory by the first (transmitter) processor (11a, 20a_1). If no new data is being received (e.g., because the first (transmitter) processor has completed the transmission of all packets of the data stream to the receiver processor, or because the first (transmitter) processor has decided to reset the transmission of packets of the data stream to the receiver processor), no new data can be written to the (shared) memory, such that the second (intermediate) processor (12a, 20a_i, i = 2, ..., N-1) can monitor whether new data is being received by monitoring whether new data is being written to the (shared) memory.

[0174] In one or more embodiments, the second (intermediate) processor (12a, 20a_i, where i = 2, ..., N-1) may not be configured to implement the data communication protocol used for data communication by the first (sender) processor and the receiver processor, or may only implement a portion of such a protocol. Therefore, data can be sent from the first (sender) processor to the receiver processor in a manner transparent to the second (intermediate) processor, which may be the last processor in a processor chain, wherein the second (intermediate) processor (12a, 20a_i, where i = 2, ..., N-1) is an intermediate processor, and the second (intermediate) processor may not be configured to interpret any signaling messages of the data communication protocol used by the sender and receiver processors (e.g., ...). Figure 3a The starting group shown, Figure 3b (See the stop packet shown). Specifically, the second (intermediate) processor may not be aware of whether data transmission between the sending and receiving processors has been completed, aborted, or reset. The proposed scheme can be advantageously implemented in intermediate processors with very limited resources and / or capabilities.

[0175] Figure 6 This illustrates the transmission of a data stream from a sending processor to a receiving processor via an intermediate processor, according to one or more embodiments disclosed in this subject matter.

[0176] Figure 6 Shown at the second (intermediate) processor for ending The operation of transferring a stream of data packets from the first processor (11a) (“MotorControl”) to the third processor (14a) via the second processor (12a, 20a_i, i = 2, ..., N-1). This relates to... Figure 4 Described The flow of data packets begins with the transfer of data packets from the first processor (11a) (“MotorControl”) to the third processor (14a) via the second processor (12a, 20a_i, where i = 2, ..., N-1).

[0177] Such as about Figure 4 As described, in one or more embodiments, the second processor may receive The last packet of a stream of data packets, and can generate a header data unit to be written into its (memory) buffer first, and can write the received data packets (and their corresponding headers) into its (memory) buffer.

[0178] like Figure 6As shown, after the last packet is written to the (memory) buffer, the (memory) buffer may not be X% full (where X is a predetermined level). In some embodiments, once the last data packet is written to the (memory) buffer, the second processor can determine that its (memory) buffer is not X% full (e.g., not 100% full). Based on its buffer management rules (flow management policy), further determining that its (memory) buffer is not X% full (e.g., not 100% full), the second processor may not send the data stored in its (memory) buffer to the next (immediately following) processor in the processor chain (in... Figure 6 In an exemplary case, a third processor, namely the receiver processor.

[0179] In one or more embodiments, while the last data packet is being written to the (memory) buffer, the second processor may begin monitoring whether further data is received within a third predetermined duration.

[0180] In one or more embodiments, when it is determined that no data has been received from the first processor within a third predetermined duration, the second processor (12a, 20a_i, where i = 2, ..., N-1) may, for example, send the remaining data packets stored in the memory to the third processor (14a) via a data communication network (17).

[0181] Therefore, in some embodiments, the buffer management rules of the second processor can stipulate that if the (memory) buffer contains data stored therein but is less than X% full, the data stored in the (memory) buffer can be sent to the (immediately following) processor in the processor chain. Figure 6 In an exemplary case, a third processor (i.e., the receiving processor) further determines that no additional data has been received (e.g., data already stored in a (memory) buffer) during a third predetermined duration.

[0182] In one or more embodiments, the value of a third predetermined duration may be predefined based on one or more of the size of the (memory) buffer used by the second processor, the execution frequency of the tasks performed by the second processor, and the size of the shared RAM that may be used for data transfer to the second processor in some embodiments.

[0183] In one or more embodiments, the value of the third predetermined duration may be predefined in relation to a value predefined for the first predetermined duration. Thus, the first and third predetermined durations may be predefined to be related to each other such that the first and third predetermined durations can be selected based on one or more corresponding data processing capabilities and corresponding data communication capabilities of the first processor and intermediate processors (such as the second processor), the first predetermined duration being used by the first processor to trigger the transmission of received data by the intermediate processors (such as the second processor), even if their transmission buffers are not full to a predetermined extent.

[0184] like Figure 6 As shown, in some embodiments, the second processor may send the contents of its (memory) buffer (“TaskFast penultimate buffer”) to the third processor (14a) even if such (memory) buffer is not full to a predetermined extent, in order to further determine that no further data has been received from the first processor within a third predetermined duration.

[0185] In one or more embodiments, the second processor may use a timer to monitor data reception over a third predetermined duration. For example, in some embodiments, the second processor may be monitored to initiate a receiver transmission end timer when it is determined that no more data is being received (from the first processor). This receiver transmission end timer may be configured to expire at the end of the third predetermined duration.

[0186] In one or more embodiments, the second processor may be configured, for example, to send data to the next (immediately following) processor in the processor chain (in accordance with buffer transfer rules, provided that its (memory) buffer is not empty, by a buffer management rule (flow management policy) executed by the second processor (task "TaskFast"). Figure 6 In an exemplary case, the third processor (i.e., the receiving processor). Depending on the embodiment, the condition that the (memory) buffer is not empty can be configured and enforced as a separate rule for data transfer to the next (immediately following) processor in the processor chain, or it can be integrated with one or more other data transfer rules, such as those proposed in this disclosure.

[0187] For example, in some embodiments, if data received from a preceding processor in the processor chain causes a second processor's (memory) buffer to fill to a predetermined extent, triggering the transfer of data contained in the (memory) buffer, the second processor may be configured to send the data contained in its (memory) buffer to the next processor. After the data is transferred to the next (immediately following) processor in the processor chain, the second processor's (memory) buffer may be empty, and the second processor may not receive further data from the preceding processor. In some embodiments, the second processor may monitor a third predetermined duration to determine whether further data is received during the third predetermined duration. If no further data is received during the third predetermined duration, the second processor may have a (memory) buffer that remains empty during the third predetermined duration. Depending on the embodiment, the second processor may be configured with a rule that does not perform data transfer when the (memory) buffer is empty. This rule may be integrated with a rule that further transmits data if no data is received within a third predetermined duration (in which case the second processor may not attempt to clear its (memory) buffer after the third predetermined duration), or it may not be integrated with a rule that further transmits data if no data is received within a third predetermined duration (in which case the second processor may attempt to clear its (memory) buffer after the third predetermined duration, and such an attempt may not be effective because data transfer may be conditional on the buffer not being empty).

[0188] In one or more embodiments, the second processor may be configured to further send data stored in its (memory) buffer to the (immediately following) processor in the processor chain. Figure 6 In an exemplary case, the third processor (i.e., the receiving processor) further determines that no further data has been received within a third predetermined duration (e.g., already stored in the (memory) buffer), resumes its monitoring of data reception, for example, in some embodiments, monitoring data writes in memory shared with the previous processor in the processor chain, and storing the received data in its (memory) buffer.

[0189] As described in one or more embodiments regarding the operation of a first processor (sender processor), the first processor may be configured to further halt data transmission from the second processor to the third processor for a first predetermined duration, and to transmit one or more subsequent data (e.g., data packets) from the second processor (possibly via one or more other intermediate processors) to the third processor upon the expiration of the first predetermined duration. In some embodiments, the first processor may be configured to halt data transmission to the second processor for a second predetermined duration while transmitting one or more subsequent data (packets). In some embodiments, the one or more subsequent data may include data indicating the end of data transmission to the third processor, such as, for example... Figure 3b The stop data packet is shown. Advantageously, the second predetermined duration can be used to trigger (force) data (which may include data indicating the end of data transmission to a third processor) through any intermediate processor in the transmission chain between the first processor (sender processor) and the receiver processor. The intermediate processor applies a buffer management rule according to which it should not send any received data if its (memory) buffer is not full to a predetermined level, so that data can be sent along the processor chain even if it is insufficient to fill the (memory) buffer of the intermediate processor in the chain to the predetermined level configured for that intermediate processor.

[0190] Therefore, in some embodiments, the second processor may receive one or more subsequent data sent by the first processor (sender processor). In some embodiments, receiving subsequent data sent by the first processor may include storing the received subsequent data in its (memory) buffer. In some embodiments, the received subsequent data may be insufficient to fill the (memory) buffer used by the second processor, such that the second processor may not trigger the transmission of the data stored in its (memory) buffer.

[0191] In some embodiments, corresponding to the first processor stopping data transmission to the third processor during a second predetermined duration, the second processor may not receive any further data other than the received subsequent data during the corresponding time period.

[0192] In one or more embodiments, the second processor may be configured to send subsequent received data stored in memory to the third processor when it is determined that no data has been received within a fourth predetermined duration (even if the subsequent received data does not fill the second processor's (memory) buffer to a predetermined extent configured for the second processor).

[0193] In some embodiments, a fourth predetermined duration can be configured in relation to a second predetermined duration. In some embodiments, the fourth predetermined duration can be configured to be the same as the third predetermined duration. In such embodiments, it is advantageous that the second processor can be configured with a data transmission triggering rule, according to which, upon determining that no further data has been received within the predetermined duration (corresponding to the third and fourth predetermined durations), a data transmission to the next processor in the processor chain can be triggered (forced), such that the second processor can apply the same rule when it is determined that no data has been received from the first processor within the (third) predetermined duration and when it is determined that no data has been received from the first processor within the (fourth) predetermined duration. Thus, as Figure 6 As illustrated in the example, a second processor can be configured to subsequently apply the same rules, resulting in receiving some data that has not yet filled its buffer to a predetermined level and storing this received data in its buffer. Upon determining that no further data has been received within a predetermined time period configured for the second processor (even if its buffer is not full to the predetermined level configured for the second processor), the data received from the previous processor in the chain (“TaskFast penultimate buffer”) is sent to the next processor in the processor chain. Then, it further receives subsequent data that also has not filled its buffer to a predetermined level (e.g., stop data packetization) and stores this received data in its buffer so that, upon determining that no further data has been received during the predetermined time period configured for the second processor (even if its buffer is not full to the predetermined level configured for the second processor), the subsequent data received from the previous processor in the chain (“TaskFast last buffer”) is sent to the next processor in the processor chain.

[0194] In some embodiments, the third predetermined duration and the fourth predetermined duration can be configured to be independent of each other, such that the second processor can be configured to apply two different data transmission triggering rules, one configured with the third predetermined duration and the other configured with the fourth predetermined duration.

[0195] In some embodiments, depending on the implementation, additional rules for resolving specific cases where the buffer used by the second processor is empty after the last data transfer to the next processor may be applied independently of the data transfer triggering rules (or more), or incorporated into such rules.

[0196] Advantageously, the second (intermediate) processor can be configured to send the last transmitted data from the sending processor to the receiving processor (e.g., The last data packet in the stream of data packets), and the sending processor uses it to indicate to the receiving processor that the transmission has ended (e.g., stop packet), without processing such data, while applying a general data transmission rule, according to which data is only sent to the next processor in the chain when it is determined that its (memory) buffer is full to a predetermined extent.

[0197] This general data transmission rule advantageously allows the use of a second processor with very limited data processing and communication capabilities, while optimizing the CPU utilization of the second processor. In particular, the proposed scheme avoids the need to implement any loops at the second processor for managing and processing received data (e.g., for detecting start and / or stop packets). Therefore, the messages of the data transmission protocol used for data communication between the sending and receiving processors (e.g., signaling messages, such as start and stop messages) can be completely transparent to the second (intermediate) processor.

[0198] Figure 7 An exemplary apparatus 1000 configured to use data communication features according to embodiments disclosed in this subject matter is illustrated. For example, depending on the embodiment, apparatus 1000 may be configured to use one or more of data communication features between a first processor and a second processor performed by a first processor and data communication features between a first processor and a second processor performed by a second processor. Depending on the embodiment, apparatus 1000 may be included in electronic circuitry, electronic boards, electronic components, chips, CPUs, or any other suitable data processing platform.

[0199] The device 1000, which may include one or more processors, includes a control engine 1001, a communication interface engine 1002, a data communication engine 1003, and a memory 1004.

[0200] exist Figure 7 In the architecture shown, the communication interface engine 1002, the data communication engine 1003, and the memory 1004 are all operably coupled to each other through the control engine 1001.

[0201] In one or more embodiments, the communication interface engine 1002 may be configured to perform various functions or embodiments provided in this subject matter disclosure, including providing a data interface to the device 1000, including for exchanging data with another device, including data communication between a first processor and a third processor, sending data (e.g., data packets) from the first processor to the third processor, and receiving data (e.g., one or more data packets) from the first processor by a second processor, for example. In some embodiments, the communication interface engine 1002 may be implemented in software and incorporated into a computing machine (e.g., a processor) configured according to embodiments of this subject matter disclosure.

[0202] In one or more embodiments, the data communication engine 1003 may be configured to perform various functions or embodiments provided in this subject matter disclosure, including with respect to one or more of the following: (1) by a first processor, stopping data transmission for a first predetermined duration when it is determined that the transmission of data packets should be stopped, and sending subsequent data (e.g., one or more subsequent data packets) to a third processor when the first predetermined duration expires; and (2) by a second processor, storing received data (e.g., one or more received data packets) in a memory coupled to the second processor; and sending the data stored in the memory to the third processor when it is determined that no further data has been received for a third predetermined duration. In some embodiments, the data communication engine 1003 may be implemented in software and incorporated into a computer machine (e.g., a processor) configured according to embodiments of this subject matter disclosure.

[0203] Control engine 1001 includes one or more processors, which may be any suitable microprocessor, microcontroller, field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), digital signal processing chip, and / or state machine, or a combination thereof. Control engine 1001 may also include or communicate with a computer storage medium (such as, but not limited to, memory 1004), capable of storing computer program instructions or software code that, when executed by a processor, causes the processor to perform the elements described herein. Additionally, memory 1004 may be any type of data storage computer storage medium capable of storing multimedia content data, service data, service list data, customized data, personalized data, and / or channel data for use according to one or more embodiments disclosed herein, coupled to control engine 1001, and operable with data communication engine 1003 and communication interface engine 1002 to facilitate processing of the data stored therewith.

[0204] In the embodiments disclosed in this subject matter, apparatus 1000 is configured to perform one or more methods described herein.

[0205] It should be understood, for reference Figure 7 The device 1000 shown and described is provided by way of example only. Many other architectures, operating environments, and configurations are possible. Other embodiments of the device may include fewer or more components and may be combined with [the following information is missing from the original text]. Figure 7 The device components shown describe some or all of the functions. Therefore, although control engine 1001, data communication engine 1003, communication interface engine 1002, and memory 1004 are shown as part of device 1000, there are no limitations on the location and control of components 1001-1004. In particular, in other embodiments, components 1001-1004 may be part of different entities or computing systems.

[0206] Although the invention has been described with reference to preferred embodiments, those skilled in the art will readily understand that various changes and / or modifications can be made to the invention without departing from the spirit or scope of the invention as defined in the appended claims.

[0207] Although the invention has been disclosed in the context of certain preferred embodiments, it should be understood that certain advantages, features, and aspects of the systems, devices, and methods can be implemented in various other embodiments. Furthermore, it is contemplated that the various aspects and features described herein can be practiced individually, combined together, or substituted for one another, and various combinations and sub-combinations of features and aspects can be made, all of which still fall within the scope of the invention. Moreover, the systems and devices described above need not include all the modules and functions described in the preferred embodiments.

[0208] The information and signals described herein can be represented using any of a wide variety of different techniques and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0209] Depending on the embodiment, certain actions, events, or functions of any method described herein may be performed in a different order, and may be added together, combined, or omitted (e.g., not all described actions or events are necessary for the practice of the method). Furthermore, in some embodiments, actions or events may be performed simultaneously rather than sequentially.

Claims

1. A method for data communication between a first processor and a third processor, the method comprising: the first processor: Send data to the third processor; When it is determined that data transmission should be stopped, data transmission to the third processor is stopped for a first predetermined duration; and Upon the expiration of the first predetermined duration, subsequent data is sent to the third processor.

2. The method according to claim 1, further comprising: When sending one or more subsequent data, data transmission to the third processor is stopped for a second predetermined duration.

3. The method according to any one of claims 1-2, wherein, Sending data to the third processor includes sending a stream of P data packets to the second processor, where P ≥ 1; and wherein determining that the transmission of data is to be stopped includes determining the completion of the transmission of the P data packets of the stream, and wherein subsequent data includes a transmission end signaling packet.

4. The method according to any one of claims 1-3, further comprising: When sending one or more subsequent packets, a transmitter stop transmission timer is started, wherein the transmitter stop transmission timer is configured to expire at the end of a second predetermined duration, wherein data transmission to the third processor is stopped while the transmitter stop transmission timer is running.

5. The method according to any one of claims 1-4, wherein, Sending data to the third processor includes writing the data to be sent to the third processor into a memory shared between the first and second processors.

6. A method for data processing, the method comprising: a second processor: Receive data; The received data is stored in a memory coupled to a second processor; as well as When it is determined that no further data has been received during the third predetermined duration, the data stored in the memory is sent to the third processor.

7. The method according to claim 6, further comprising: When sending data stored in memory to a third processor, it receives subsequent data and stores the received subsequent data in memory; And when it is determined that no further data has been received during the fourth predetermined duration, subsequent data stored in memory is sent to the third processor.

8. The method according to any one of claims 6 to 7, further comprising: Further data is received, and when it is determined that the second processor will no longer receive data, a first receiver stop transmission timer is started, wherein the first receiver stop transmission timer is configured to expire at the end of a third predetermined duration.

9. The method according to claim 8, further comprising: Further receiving of subsequent data, when it is determined that the second processor will no longer receive data, the second receiver stop transmission timer is started, wherein the second receiver stop transmission timer is configured to expire at the end of a fourth predetermined duration.

10. The method according to any one of claims 6-9, further comprising: Receive data; The received data is stored in the memory; And when it is determined that the memory is full to a predetermined extent, the data stored in the memory is sent to the third processor.

11. The method according to claim 10, wherein, If it is determined that no further data is received during the third predetermined duration, the data stored in the memory is sent to the third processor even if the memory is not full to a predetermined level.

12. The method according to any one of claims 6 to 11, wherein, The second and third processors are processors in a processor chain for data transmission from the sending processor to the receiving processor, wherein the second processor is an intermediate processor in the processor chain, through which data is sent from the sending processor to the receiving processor.

13. The method according to any one of claims 1 to 5, wherein, The first processor and the third processor are processors in a processor chain for data transmission from the first processor, which operates as a sending processor, to the third processor, which operates as a receiving processor. The third processor is the last processor in the processor chain, wherein data sent from the first processor to the third processor is transmitted through one or more intermediate processors in the processor chain.

14. An apparatus comprising a processor and a memory operatively coupled to the processor, wherein, The apparatus is configured to perform the method according to any one of claims 1 to 13.

15. A computer program product comprising computer program code tangibly embodied in a computer-readable medium, the computer program code including instructions that, when provided to and executed by a computer system, cause the computer to perform the method according to any one of claims 1 to 13.

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