A master-slave switching method for a dual-CPU architecture

Abstract

This invention relates to a master-slave switching method for a dual-CPU architecture. The method includes: establishing two unidirectional GPIO lines and one bidirectional data transmission line between the two CPUs, and setting two configuration files; customizing unidirectional signal rules, message exchange rules, and communication message protocols; and after power-on, each CPU checks its STATUS status. loc Perform initialization; and according to the one-way signal rules and STATUS loc It interacts with the CPU on the other side via GPIO signals and sets state Y based on the signal transmission and reception status. GPIO ; and according to the communication message protocol and STATUS loc It exchanges communication messages with the CPU on the other side and sets the STATUS status based on the message exchange status. in Z COMM ; and based on STATUS loc STATUS in Z COMM and Y GPIO Configure master-slave switching. This invention can reduce the risk of misjudgment or loss of control.

Description

Technical Field

[0001] This invention relates to the field of rail transit technology, and in particular to a master-slave switching method for a dual-CPU architecture. Background Technology

[0002] In the rail transit industry, to enhance equipment reliability, a dual-CPU architecture is typically built on the same equipment. The two CPUs act as master and slave, respectively, and perform control processing simultaneously. If the master CPU fails, the slave CPU can take over the master's tasks within a specified time and continue to complete the relevant control functions. The core of this architecture lies in the master-slave switching mechanism, and its design directly determines the overall availability and security of the system.

[0003] Current conventional master-slave failover schemes are mostly based on bidirectional handshake protocols. These methods typically rely on a single bidirectional data bus (such as a serial port or Ethernet) for periodic exchange of status messages. When the communication link itself fails, the CPUs on both sides may misjudge the other's failure due to their inability to receive or correctly parse the other's messages, leading to a simultaneous switch to master and triggering a "dual-master" risk. Conversely, if the other CPU has crashed but the link remains normal, both sides may remain in a "dual-slave" state for an extended period, causing the entire system to lose its external control capabilities.

[0004] To address the aforementioned issues, we propose an improved solution: adding two independent unidirectional General Purpose Input / Output (GPIO) lines for master-slave transmission and slave-master transmission respectively. Combined with dedicated unidirectional signal rules, the health status of both transmitting and receiving channels can be accurately determined, decoupling link anomalies from CPU failures. A customized message exchange protocol with a sequence number acknowledgment mechanism is implemented through bidirectional COMM lines to quantitatively assess the integrity of the communication link and the operating status of the remote CPU. Based on this, and using persistent configuration files in non-volatile storage, a comprehensive analysis of four dimensions—local role status, remote role status, GPIO status, and COMM status—is performed to accurately switch between master and slave based on pre-defined decision logic. This improved solution reduces the risk of "dual master" or loss of control due to misjudgment, reduces the oscillation risk caused by frequent switching, and provides highly robust master-slave redundancy for rail transit equipment. How to implement this improved solution is the technical problem this invention aims to solve. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of existing technologies by providing a master-slave switching method for a dual-CPU architecture. This invention establishes two unidirectional GPIO signal lines, denoted as GPIO-A and GPIO-B, and a bidirectional data transmission line, denoted as the COMM line, between the two CPUs in the dual-CPU architecture. Two corresponding configuration files are stored on non-volatile storage media connected to each CPU via a data bus. Unidirectional signal rules are customized for the GPIO-A / B lines, and message exchange rules and communication message protocols are customized for the COMM line. After the dual-CPU architecture is powered on, either CPU initializes its STATUS state according to the configuration file. loc ; and according to the one-way signal rules and status STATUS loc The system monitors the real-time status of the CPU, interacts with it via GPIO signals, and sets the status Y based on the signal transmission and reception status. GPIO ; and according to the communication message protocol and status STATUS loc The system monitors the real-time status of the CPU, exchanges communication messages with the CPU on the other side, and sets the STATUS status based on the message exchange status. in and state Z COMM And based on the STATUS loc STATUS in Z COMM and Y GPIO The real-time status combination is used for master-slave switching. This invention can reduce the risk of "dual master" or loss of control caused by misjudgment, reduce the oscillation risk caused by frequent switching, and provide highly robust master-slave redundancy protection for rail transit equipment.

[0006] In view of this, embodiments of the present invention provide a master-slave switching method for a dual-CPU architecture, the method comprising: In a dual-CPU architecture, two unidirectional GPIO signal lines, denoted as GPIO-A and GPIO-B, are established between the two CPUs. A bidirectional data transmission line, denoted as the COMM line, is also established. Two corresponding configuration files are stored on non-volatile storage media connected to the two CPUs via their respective data buses. Unidirectional signal rules are customized for the GPIO-A / B lines, and message exchange rules and communication message protocols are customized for the COMM line. The two CPUs include a first CPU and a second CPU. The unidirectional signal rules are as follows: only the master chip can periodically send a square wave signal S to the slave chip, and the duty cycle of the square wave signal S is determined by a preset duty cycle r. stdThe message exchange rules are as follows: after the dual-CPU architecture is powered on, the master chip first sends the first communication message to the slave chip, and then the slave chip and the master chip exchange communication messages in an alternating order. The data format of the communication messages follows the communication message protocol. The communication message protocol includes four protocol words, namely, sequence number SN, sequence number SB_FB, status STATUS, and checksum CRC. After the dual-CPU architecture is powered on, either CPU on one side creates a corresponding master-slave switching management variable; and adjusts the STATUS status in the management variable according to the corresponding configuration file. loc Perform initialization; and according to the unidirectional signal rules and the STATUS state. loc The system monitors the real-time status of the CPU, interacts with it via GPIO signals, and sets the status Y in the management variable based on the signal transmission and reception status. GPIO ; and according to the communication message protocol and the status STATUS loc The system monitors the real-time status of the CPU, exchanges communication messages with the CPU on the other side, and sets the STATUS status in the management variables based on the message exchange status. in and state Z COMM And based on the STATUS loc STATUS in Z COMM and Y GPIO The real-time state combination of the STATUS loc and the corresponding configuration file for master-slave switchover configuration; wherein, the STATUS status loc Used to record the real-time master-slave status of the local CPU, including the master chip and slave chip; the status STATUS in Used to record the real-time master-slave status of the opposite CPU, including the master chip and the slave chip; the status Y GPIO Used to record the real-time operating status of the GPIO lines on this side, including normal and abnormal; the status Z COMM Used to record the real-time operating status of the COMM line, including normal and abnormal conditions.

[0007] Preferably, the GPIO-A line is used for unidirectional signal transmission from the first CPU to the second CPU; The GPIO-B line is used for unidirectional signal transmission from the second CPU to the first CPU; The COMM lines include serial port data lines, Ethernet data lines, and CAN bus data lines; The two configuration files include a first configuration file corresponding to the first CPU and a second configuration file corresponding to the second CPU; the two configuration files have the same file fields, both including a chip identifier field and a master-slave type field; the chip identifier field is 1 to indicate that the corresponding CPU is the first CPU, and 2 to indicate that the corresponding CPU is the second CPU; the master-slave type field includes two types: master chip and slave chip; The sequence number SN is the counting sequence number on the transmitting side; The sequence number SB_FB is the counting sequence number carried in the previous message sent by the receiving side; The STATUS status is used to characterize the master-slave status of the transmitting device, including two types: master chip and slave chip. The CRC checksum is calculated using the CRC algorithm based on the continuous data SN+SB_FB+STATUS. The master-slave switching management variable includes the serial number SN. in Serial Number SN_FB in The STATUS in CRC checksum in Serial Number SN loc Serial Number SN_FB loc The STATUS loc CRC checksum loc Serial Number X pre The state Y GPIO The state Z COMM ; The serial number SN in The serial number SN_FB in The STATUS in The CRC checksum in Used to record the protocol words of communication messages received by the CPU on this side; the sequence number SN loc The serial number SN_FB loc The STATUS loc The CRC checksum loc Used to record the communication message protocol words sent by the CPU on this side; the sequence number X pre The sequence number SN_FB is used to determine the most recently parsed message. in Record it; the serial number SN in The serial number SN_FB in The serial number SN loc The serial number SN_FB loc The serial number X pre All are initially set to 0 upon creation; the STATUS state is... inThe CRC checksum in The STATUS loc The CRC checksum loc All are initially set to empty upon creation; the state Y GPIO The state Z COMM All are initially set to normal during creation.

[0008] Preferably, the step of managing the STATUS variable according to the corresponding configuration file... loc Initialization is performed, specifically including: The single-sided CPU uses the corresponding first configuration file or second configuration file as the current configuration file; And read the master-slave type field from the current configuration file as the corresponding initial state STATUS. ini ; And the initial state STATUS ini Check if it is empty; If the initial state STATUS ini If it is empty, then the state STATUS will be... loc Set it as the master piece and synchronize the master-slave type field in the current configuration file; If the initial state STATUS ini If it is not empty, then the initial state STATUS is... ini Is the main image being identified? If so, then the STATUS status will be entered into the system. loc If set as a slave, then synchronize and update the master-slave type field in the current configuration file; otherwise, set the status STATUS. loc Set it as the master piece and synchronize the master-slave type field of the current configuration file.

[0009] Preferably, the step of acting according to the one-way signal rule and the state STATUS loc The system monitors the real-time status of the CPU, interacts with it via GPIO signals, and sets the status Y in the management variable based on the signal transmission and reception status. GPIO Specifically, it includes: The single-sided CPU uses the GPIO-A line or the GPIO-B line used for sending unidirectional signals on this side as the current sending line, and uses the GPIO-B line or the GPIO-A line used for receiving unidirectional signals on this side as the current receiving line. And in the state STATUS loc When the real-time status is the master chip, the transmitting end of the current transmitting line on this side is taken as the corresponding master transmitting port PO. MThe receiving end of the current receiving line on this side is designated as the corresponding main receiving port PI. M The current transmitting line is used as the corresponding receiving port PI at the receiving end of the CPU on the other side. S The current receiving line is designated as the corresponding slave port PO at the transmitting end of the CPU on the opposite side. S Based on the preset duty cycle r std The periodic square wave signal S is generated from the main transmitting port PO. M To the receiving port PI S Send, and to the main sending port PO M The signal transmission status is monitored in real time; and the main receiving port PI is monitored. M Has the PO from the sending port been received? S The transmitted square wave signal S is monitored in real time; and the main transmitting port PO is monitored. M During the monitoring process, if the signal is successfully sent, the state Y is set. GPIO If the signal transmission fails, then state Y is set. GPIO This is abnormal; and in response to the main receiving port PI M During the monitoring process, if the square wave signal S is received, then the state Y is set. GPIO If the square wave signal S is not received, then the state Y is set to an abnormal state. GPIO This is normal; And in the state STATUS loc When the real-time status is set to slave time, the transmitting end of the current transmitting line on this side is taken as the corresponding slave transmitting port PO. S The receiving end of the current receiving line on this side is taken as the corresponding receiving port PI. S The current transmitting line is used as the corresponding main receiving port PI at the receiving end of the CPU on the other side. M The current receiving line is used as the transmitting end of the CPU on the opposite side as the corresponding main transmitting port PO. M ; and for the receiving port PI S Has the main port PO been received? M The transmitted square wave signal S is monitored in real time; and the transmitting port PO is monitored. S The signal transmission status is monitored in real time; and the signal transmission status of the receiving port PI is monitored in real time. S During the monitoring process, if the square wave signal S can be received normally, then the state Y is set. GPIO If the square wave signal S is not received normally, then state Y is set. GPIO This is an anomaly; and in the case of the slave port PO S During the monitoring process, if the slave port POS To send a signal outward, the state Y is set. GPIO If the above is an anomaly, and the source port PO is abnormal. S If no signal is sent out, then state Y is set. GPIO This is normal.

[0010] Preferably, the step of following the communication message protocol and the status STATUS... loc The system monitors the real-time status of the CPU, exchanges communication messages with the CPU on the other side, and sets the STATUS status in the management variables based on the message exchange status. in and state Z COMM Specifically, it includes: Step 5-1, the single-sided CPU is in the STATUS state. loc After initialization is complete, the STATUS state is... loc Is it the main image identification? If yes, proceed to step 5-2; if no, proceed to step 5-4. Step 5-2, according to the communication message protocol, based on the current sequence number SN loc The serial number SN_FB loc and the state STATUS loc Calculate the corresponding check code CRC. loc ; Step 5-3, according to the communication message protocol, based on the current sequence number SN loc The serial number SN_FB loc The STATUS loc The CRC checksum loc Generate a communication message and send it to the CPU on the other side; Step 5-4, for the serial number SN loc Add 1; Step 5-5: Start the local timer to perform periodic timing according to the preset period T; Steps 5-6: Every cycle T, confirm whether a communication message sent by the CPU on the other side has been received; if received, proceed to step 5-7; if not received, proceed to step 5-12. Steps 5-7: Parse the currently received communication message according to the communication message protocol, and set the sequence number SN based on the parsing result. in The serial number SN_FB in The STATUS in The CRC checksum in ; Steps 5-8: According to the communication message protocol, check the CRC checksum. inPerform verification; and identify the verification result; if the verification is successful, proceed to step 5-9; if the verification fails, proceed to step 5-11. Steps 5-9, for the judgment condition (SN) loc -SN_FB in ≤2 and SN_FB in >X pre If the condition is met, proceed to step 5-10; otherwise, proceed to step 5-11. Steps 5-10, based on the sequence number SN_FB in For the serial number X pre Configure settings; Step 5-11, based on the serial number SN in For the serial number SN_FB loc Configure settings; Step 5-12, according to the communication message protocol, based on the current sequence number SN loc The serial number SN_FB loc and the state STATUS loc Calculate the corresponding check code CRC. loc ; Step 5-13, according to the communication message protocol, based on the current sequence number SN loc The serial number SN_FB loc The STATUS loc The CRC checksum loc Generate a communication message and send it to the CPU on the other side; Step 5-14, for the serial number SN loc Add 1; Steps 5-15, based on the serial number SN loc and the serial number X pre Calculate the difference between the serial numbers E=SN loc -X pre ; Step 5-16: Check whether the sequence number difference E is greater than the preset sequence number difference threshold E. hold Perform identification; if yes, proceed to step 5-17; if no, proceed to step 5-18. Step 5-17, set the state Z COMM Set it as an exception and proceed to steps 5-6; Step 5-18, set the state Z COMM Set it to normal and proceed to steps 5-6.

[0011] Preferably, the state-based STATUS loc STATUS in ZCOMM and Y GPIO The real-time state combination of the STATUS loc And the corresponding configuration file for master-slave switching configuration, specifically including: Step 61: After the single-sided CPU starts its local timer and runs for a preset specified duration L1, it periodically scans the state Z at a preset scanning frequency. COMM Identify the real-time status; Wherein, the specified duration L1 is an integer multiple of the preset period T, L1=N1×T, the multiple N1 is a preset positive integer, N1>1; Step 62, if the state Z COMM If it is normal, then the state STATUS is... loc and the STATUS in The system identifies whether the states are the same; if so, it applies the mandatory rule that the first CPU is the master and the second CPU is the slave to the STATUS status. loc And configure master-slave switching in the corresponding configuration file; otherwise, do not configure the STATUS status. loc And the corresponding configuration files for master-slave switching; Step 63, if the state Z COMM If it is abnormal, then for the state Y GPIO Is it normal to identify? If so, then do not perform the STATUS status check. loc And perform master-slave switching according to the corresponding configuration file; otherwise, further check the current STATUS status. loc Whether to identify the master CPU; if so, then apply the mandatory rule of the first CPU as master and the second CPU as slave to the STATUS status. loc And configure the master-slave switch according to the corresponding configuration file; otherwise, switch the local side to the master side and configure the STATUS status accordingly. loc And the corresponding configuration file for master-slave switching configuration.

[0012] Furthermore, the mandatory rule of assigning the first CPU as master and the second CPU as slave to the STATUS state is further applied. loc And the corresponding configuration file for master-slave switching configuration, specifically including: Step 71: The single-sided CPU uses the corresponding first configuration file or second configuration file as the current configuration file; Step 72, and read the chip identifier field of the current configuration file as the corresponding chip identifier ID. chip ; Step 73, and assign an ID to the chip. chip Whether it is 1 is used for identification; Step 74, if the chip identifier ID chip If the value is 1, then the state STATUS will be set to 1. loc Set it as the master and synchronously update the master-slave type field in the current configuration file; after this update, continue to wait for a preset specified time L2; and when this wait ends, set the state Y. GPIO To determine if it is still an anomaly, identify the status STATUS. If so, change the status STATUS. loc Set it as a slave segment and synchronously update the master-slave type field in the current configuration file; Wherein, the specified duration L2 is an integer multiple of the preset period T, L2=N2×T, the multiple N2 is a preset positive integer, N2>1; Step 75, if the chip identifier ID chip If the value is not 1, then the state STATUS will be set to 1. loc Set it as a slave segment and synchronously update the master-slave type field in the current configuration file.

[0013] Furthermore, the state STATUS is changed by switching the local side to the master side. loc And the corresponding configuration file for master-slave switching configuration, specifically including: The single-sided CPU will record the STATUS status. loc Set it as the master piece and synchronize the master-slave type field of the current configuration file.

[0014] This invention provides a master-slave switching method for a dual-CPU architecture. As described above, this invention establishes two unidirectional GPIO signal lines, denoted as GPIO-A and GPIO-B, and a bidirectional data transmission line, denoted as the COMM line, between the two CPUs in the dual-CPU architecture. Two corresponding configuration files are stored on non-volatile storage media connected to each CPU via a data bus. Unidirectional signal rules are customized for the GPIO-A / B lines, and message exchange rules and communication message protocols are customized for the COMM line. After power-on, either CPU initializes its STATUS state according to the configuration file. loc ; and according to the one-way signal rules and status STATUS loc The system monitors the real-time status of the CPU, interacts with it via GPIO signals, and sets the status Y based on the signal transmission and reception status. GPIO ; and according to the communication message protocol and status STATUS loc The system monitors the real-time status of the CPU, exchanges communication messages with the CPU on the other side, and sets the STATUS status based on the message exchange status. in and state ZCOMM And based on the STATUS loc STATUS in Z COMM and Y GPIO The real-time state combination is used for master-slave switching. This embodiment of the invention reduces the risk of "dual master" or loss of control caused by misjudgment and reduces the oscillation risk caused by frequent switching, providing highly robust master-slave redundancy protection for rail transit equipment. Attached Figure Description

[0015] Figure 1 A schematic diagram of a master-slave switching method for a dual-CPU architecture provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a dual-CPU architecture provided in an embodiment of the present invention; Figure 3 STATUS provided for embodiments of the present invention loc A schematic diagram of the initialization process; Figure 4 The master-slave GPIO signal transmit / receive state and state Y provided in the embodiments of the present invention GPIO A diagram illustrating the correspondence between the two relationships; Figure 5 This is a schematic diagram of a one-sided communication message processing flow provided in an embodiment of the present invention; Figure 6 STATUS provided for embodiments of the present invention loc STATUS in Z COMM Y GPIO A diagram illustrating the correspondence between the master-slave switching strategy; Figure 7 This is a schematic diagram of the master-slave switching process with the first CPU as the master and the second CPU as the slave, provided for an embodiment of the present invention. Detailed Implementation

[0016] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0017] Figure 1 This is a schematic diagram of a master-slave switching method for a dual-CPU architecture provided in an embodiment of the present invention, as shown below. Figure 1 As shown, this method includes the following steps: Step 1: In the dual-CPU architecture, establish two unidirectional GPIO signal lines between the two CPUs, denoted as GPIO-A and GPIO-B, and establish one bidirectional data transmission line, denoted as COMM. Store the corresponding two configuration files on the non-volatile storage media connected to the two CPUs via their respective data buses. Customize unidirectional signal rules for GPIO-A / B lines and customize message exchange rules and communication message protocols for COMM lines.

[0018] Here, as Figure 2 As shown in the schematic diagram of the dual-CPU architecture provided in this embodiment of the invention, the two CPUs in the dual-CPU architecture of this embodiment include a first CPU and a second CPU. GPIO-A lines are used for unidirectional signal transmission from the first CPU to the second CPU. GPIO-B lines are used for unidirectional signal transmission from the second CPU to the first CPU.

[0019] The COMM line in this embodiment of the invention includes at least a serial port data line, an Ethernet data line, and a Controller Area Network (CAN) bus data line. In addition, it can be any type of data line that supports bidirectional data transmission.

[0020] like Figure 2 As shown, the two configuration files in this embodiment of the invention include a first configuration file corresponding to a first CPU and a second configuration file corresponding to a second CPU. It should be noted that the two configuration files have the same file fields, both including a chip identifier field and a master-slave type field; a chip identifier field of 1 indicates that the corresponding CPU is the first CPU, and a field of 2 indicates that the corresponding CPU is the second CPU; the master-slave type field includes two types: master chip and slave chip.

[0021] The unidirectional signal rule in this embodiment of the invention is as follows: only the master chip can periodically send a square wave signal S to the slave chip, and the duty cycle of the square wave signal S is determined by a preset duty cycle r. std Decision. Here, the preset duty cycle r in this embodiment of the invention is... std This is a pre-set duty cycle parameter, such as 50%.

[0022] The message exchange rules in this embodiment of the invention are as follows: after the dual-CPU architecture is powered on, the master chip first sends the first communication message to the slave chip, and then the slave chip and the master chip exchange communication messages in an alternating order. The data format of the communication messages follows the communication message protocol.

[0023] like Figure 2As shown, the communication message protocol of this embodiment includes four protocol words: sequence number SN, sequence number SB_FB, status STATUS, and checksum CRC. SN is the sequence number on the sending side. SB_FB is the sequence number carried in the previous message sent by the receiving side. STATUS is used to characterize the master-slave status of the sending side, including master and slave segments. CRC is a checksum calculated using the CRC algorithm based on the continuous data SN + SB_FB + STATUS.

[0024] Step 2: After the dual-CPU architecture is powered on, any one of the two CPUs creates a set of corresponding master-slave switching management variables; and adjusts the STATUS status in the management variables according to the corresponding configuration file. loc Perform initialization; and according to the one-way signal rules and the STATUS status. loc The system monitors the real-time status of the CPU, interacts with it via GPIO signals, and sets the status Y in the management variable based on the signal transmission and reception status. GPIO ; and according to the communication message protocol and status STATUS loc The system monitors the real-time status of the CPU, exchanges communication messages with the CPU on the other side, and sets the STATUS status in the management variables based on the message exchange status. in and state Z COMM And based on the STATUS loc STATUS in Z COMM and Y GPIO Real-time state combination of state STATUS loc And the corresponding configuration file for master-slave switching configuration.

[0025] Step 2 specifically includes: Step 21: After the dual-CPU architecture is powered on, any one of the two CPUs creates a set of corresponding master-slave switching management variables.

[0026] Here, the master-slave switching management variable in this embodiment of the invention includes the sequence number SN. in Serial Number SN_FB in Status in CRC checksum in Serial Number SN loc Serial Number SN_FB loc Status loc CRC checksum loc Serial Number X pre State Y GPIO State Z COMM .

[0027] Serial Number SN inSerial Number SN_FB in Status in CRC checksum in Used to record the protocol words of communication messages received by the CPU on this side. Serial Number SN loc Serial Number SN_FB loc Status loc CRC checksum loc Used to record the protocol words of communication messages sent by the CPU on this side.

[0028] It should be noted that the STATUS loc Used to record the real-time master-slave status of the local CPU, including the master chip and slave chip. Status STATUS in Used to record the real-time master-slave status of the opposite CPU, including the master chip and slave chip. Status Y GPIO Used to record the real-time operating status of the GPIO lines on this side, including normal and abnormal states. Status Z COMM Used to record the real-time operating status of the COMM line, including normal and abnormal conditions. Serial Number X pre The sequence number SN_FB is used to determine the most recent message that meets all parsing criteria. in Record it.

[0029] It should also be noted that the serial number SN in Serial Number SN_FB in Serial Number SN loc Serial Number SN_FB loc Serial Number X pre All are initially set to 0 upon creation; Status in CRC checksum in Status loc CRC checksum loc All are initially set to empty upon creation; state Y GPIO State Z COMM All are initially set to normal during creation.

[0030] Step 22, and adjust the status STATUS in the management variables according to the corresponding configuration file. loc Perform initialization.

[0031] Specifically, it includes: Step 221: The single-sided CPU uses the corresponding first configuration file or second configuration file as the current configuration file.

[0032] Step 222, and read the master-slave type field of the current configuration file as the corresponding initial state STATUS. ini .

[0033] Step 223, and check the initial state STATUS. ini It identifies whether the value is empty.

[0034] Step 224, if the initial state STATUS ini If it is empty, then set the status to STATUS. loc Set it as the master and synchronize the master-slave type field of the current configuration file.

[0035] Step 225, if the initial state STATUS ini If it is not empty, then the initial state STATUS is... ini Is the primary image being identified? If so, then set the status to STATUS. loc Set it as a slave and synchronize the master / slave type field in the current configuration file; otherwise, set the status to STATUS. loc Set it as the master and synchronize the master-slave type field of the current configuration file.

[0036] Specifically, this includes: Step 225-1, if the initial state STATUS ini If it is not empty, then the initial state STATUS is... ini Whether to identify the main image.

[0037] Step 225-2, if yes, then change the status STATUS. loc Set it as a slave and synchronize the master-slave type field of the current configuration file.

[0038] Step 225-3, if not, then change the status STATUS. loc Set it as the master and synchronize the master-slave type field of the current configuration file.

[0039] The processing flow for steps 222-225 above can be referenced. Figure 3 STATUS provided for embodiments of the present invention loc To understand the initialization process, refer to the diagram below.

[0040] Step 23, and according to the one-way signal rules and status STATUS loc The system monitors the real-time status of the CPU, interacts with it via GPIO signals, and sets the status Y in the management variable based on the signal transmission and reception status. GPIO .

[0041] Specifically, it includes: Step 231: The single-sided CPU uses the GPIO-A line or GPIO-B line used for transmitting unidirectional signals on its own side as the current transmitting line, and uses the GPIO-B line or GPIO-A line used for receiving unidirectional signals on its own side as the current receiving line.

[0042] Step 232, and in the STATUS state loc When the real-time status is the master chip, the transmitting end of the current transmitting line on this side is taken as the corresponding master transmitting port PO. M 1. Designate the receiving end of the current receiving line on this side as the corresponding main receiving port PI. M The current transmitting line is used as the corresponding receiving port PI at the receiving end of the CPU on the other side. S The current receiving line is designated as the corresponding slave port PO at the transmitting end of the CPU on the other side. S Based on the preset duty cycle r std A periodic square wave signal S is generated from the main transmitter port PO. M To the receiving port PI S Send, and to the main sending port PO M Real-time monitoring of signal transmission status; and monitoring of the main receiving port PI M Did you receive the PO from the sending port? S The transmitted square wave signal S is monitored in real time; and the main transmitting port PO is monitored. M During the monitoring process, if the signal is successfully sent, the status Y is set. GPIO Normal; if signal transmission fails, set status Y. GPIO This is abnormal; and it is also abnormal on the main receiving port PI. M During the monitoring process, if a square wave signal S is received, the state Y is set. GPIO If an abnormality is detected and no square wave signal S is received, then the state is set to Y. GPIO This is normal.

[0043] Step 233, and in the STATUS state loc The real-time status is set to slave time, and the current transmitting line's transmitting end on this side is taken as the corresponding slave port PO. S 1. Designate the receiving end of the current receiving line on this side as the corresponding slave receiving port PI. S The current transmitting line is used as the corresponding main receiving port PI at the receiving end of the CPU on the other side. M The current receiving line is designated as the corresponding master transmitting port PO at the transmitting end of the CPU on the other side. M ; and for the PI from the receiving port S Has the PO from the main port been received? M The transmitted square wave signal S is monitored in real time; and the transmission port PO is monitored. S Real-time monitoring of signal transmission status; and monitoring of the receiving port PI S During the monitoring process, if the square wave signal S can be received normally, then the state Y is set. GPIO If the square wave signal S is not received normally, then set the state to Y. GPIO This is an anomaly; and it occurs on the sender port PO.S During the monitoring process, if the output port PO is... S To send a signal outward, set state Y. GPIO This is an error; if it originates from port PO... S If no signal is sent out, set state Y. GPIO This is normal.

[0044] Here, in the current step 23, state Y is... GPIO For the configuration logic, please refer to Figure 4 The master-slave GPIO signal transmit / receive state and state Y provided in the embodiments of the present invention GPIO Use the corresponding diagram to understand.

[0045] Step 24, and according to the communication message protocol and status STATUS loc The system monitors the real-time status of the CPU, exchanges communication messages with the CPU on the other side, and sets the STATUS status in the management variables based on the message exchange status. in and state Z COMM .

[0046] Specifically, it includes: Step 24-1, single-sided CPU in STATUS state loc After initialization is complete, check the STATUS status. loc Is it the main image identification? If yes, proceed to step 24-2; if no, proceed to step 24-4.

[0047] Step 24-2, according to the communication message protocol, based on the current sequence number SN loc Serial Number SN_FB loc and status STATUS loc Calculate the corresponding CRC checksum. loc .

[0048] Step 24-3, according to the communication message protocol, based on the current sequence number SN loc Serial Number SN_FB loc Status loc CRC checksum loc Generate a communication message and send it to the CPU on the other side.

[0049] Step 24-4, for serial number SN loc Add 1.

[0050] Step 24-5: Start the local timer to perform periodic timing according to the preset period T.

[0051] Here, the period T in this embodiment of the invention is a preset time period or time length parameter.

[0052] Step 24-6: Every cycle T, confirm whether a communication message sent by the CPU on the other side has been received; if received, proceed to step 24-7; if not received, proceed to step 24-12.

[0053] Step 24-7: Parse the currently received communication message according to the communication message protocol, and set the sequence number SN based on the parsing result. in Serial Number SN_FB in Status in CRC checksum in .

[0054] Step 24-8: According to the communication message protocol, check the CRC checksum. in Perform verification; and identify the verification result; if the verification is successful, proceed to step 24-9; if the verification fails, proceed to step 24-11.

[0055] Step 24-9, for the judgment condition (SN) loc -SN_FB in ≤2 and SN_FB in >X pre If the condition is met, proceed to step 24-10; otherwise, proceed to step 24-11.

[0056] Here, the judgment condition (SN) of the embodiments of the present invention loc -SN_FB in ≤2 and SN_FB in >X pre The conditional branches of ) include SN loc -SN_FB in ≤2、SN_FB in >X pre .

[0057] 1) Branch SN loc -SN_FB in ≤2; SN under ideal conditions loc -SN_FB in The difference is 0 or 1. However, considering that in actual working conditions, bidirectional data lines, i.e., COMM lines, may cause one side of the CPU to retransmit data due to brief line jitter, this embodiment of the invention will use SN. loc -SN_FB in The difference threshold is raised to 2. A difference threshold of 2 means that the local CPU allows the remote CPU to perform operations on a single raw data packet. o If transmission fails, a retransmission can be performed within the next period T, and the retransmitted message must satisfy SN_FB. in >X preUpdate the serial number X on this side in real time. pre However, if the CPU on the other side is in the original message data o If a packet is retransmitted continuously within multiple periods T (more than once T) after a failed transmission, the local CPU will treat the continuously retransmitted packet as an invalid exchange packet and will not update the sequence number X. pre It should be noted that, in the embodiment SN of the present invention... loc -SN_FB in The design rule for the difference threshold is: difference threshold = 1 + number of retransmission tolerances, and the number of retransmission tolerances ≥ 0. In this embodiment of the invention, the difference threshold is set to 2, so the corresponding number of retransmission tolerances is 1. However, in actual application scenarios, the number of retransmission tolerances can be customized based on actual application needs.

[0058] 2) Branch SN_FB in >X pre : Serial Number X pre The sequence number SN_FB is used to determine the most recent message that meets all parsing criteria. in Recording this information, where "meeting all message parsing criteria" means simultaneously satisfying the following conditions: successful reception of periodic messages, successful CRC check, and the judgment condition (SN). loc -SN_FB in ≤2 and SN_FB in >X pre ), serial number X pre The trend of change should be a monotonically increasing trend. Ideally, the local CPU extracts the sequence number SN_FB from each newly received message. in It must be greater than the previously saved sequence number X on this side. pre However, in actual operation, the local CPU may receive retransmitted or delayed messages from the remote CPU, which may result in SN_FB. in ≤X pre In order to ensure the sequence number X pre Because of the monotonicity and increasing nature of the expression, this embodiment of the invention sets the branch SN_FB. in >X pre To avoid serial number X pre A rollback error has occurred.

[0059] Step 24-10, based on sequence number SN_FB in For serial number X pre Configure the settings.

[0060] Step 24-11, based on the serial number SN in For serial number SN_FB loc Configure the settings.

[0061] Step 24-12, according to the communication message protocol, based on the current sequence number SN loc Serial Number SN_FB loc and status STATUS loc Calculate the corresponding CRC checksum. loc .

[0062] Step 24-13, according to the communication message protocol, based on the current sequence number SN loc Serial Number SN_FB loc Status loc CRC checksum loc Generate a communication message and send it to the CPU on the other side.

[0063] Step 24-14, for serial number SN loc Add 1.

[0064] Steps 24-15, based on the serial number SN loc and serial number X pre Calculate the difference between the serial numbers E=SN loc -X pre .

[0065] Steps 24-16: Check whether the sequence number difference E is greater than the preset sequence number difference threshold E. hold Perform identification; if yes, proceed to step 24-17; if no, proceed to step 24-18.

[0066] Here, the sequence number difference threshold E in this embodiment of the invention hold This is a pre-set positive integer, which can be set based on the actual needs of the application, but it is important to ensure that E... hold >2.

[0067] It should be noted that, under ideal conditions, the sequence number SN, incremented by 1 on this side during the first round of message exchange, is... loc With serial number X pre The difference is 1, and the subsequent serial number SN is increased by 1 each time. loc With serial number X pre The difference is always 2; however, in actual operation, abnormal conditions such as message loss, message retransmission, and message delay may occur. As mentioned above, these abnormal conditions occur when sequence number X... pre Neither will be updated, but the serial number SN loc The sequence number is automatically incremented by 1 on this side again; therefore, when the above abnormal operating condition occurs, the sequence number difference E=SN. loc -X pre It will continue to increase and will inevitably be greater than 2. This embodiment of the invention sets a threshold value E for the sequence number difference. hold This is to set a maximum tolerable number of exceptions = E hold-2. This maximum number of anomalies can be customized based on actual application needs. After customization, it will be based on E. hold The rule corresponding to the maximum number of anomalies + 2 can be used to determine the threshold E of the sequence number difference. hold Configure compatibility settings.

[0068] Step 24-17, set state Z COMM Set it as an exception and proceed to step 24-6.

[0069] Step 24-18, set state Z COMM Set it to normal and proceed to step 24-6.

[0070] Here, the communication message sending and receiving process in the current step 24 can be referred to Figure 5 This is a schematic diagram of the one-sided communication message processing flow provided in the embodiments of the present invention.

[0071] Step 25, and based on the status STATUS loc STATUS in Z COMM and Y GPIO Real-time state combination of state STATUS loc And the corresponding configuration file for master-slave switching configuration.

[0072] Specifically, it includes: Step 251: After the local timer is started and runs for a preset specified duration L1, the single-sided CPU periodically scans the state Z at a preset scanning frequency. COMM It identifies the real-time status.

[0073] Here, in this embodiment of the invention, the specified duration L1 is an integer multiple of the preset period T, L1 = N1 × T, where the multiple N1 is a preset positive integer, N1 > 1. The scanning frequency is a preset time frequency parameter.

[0074] Step 252, if state Z COMM If it is normal, then the status STATUS is... loc and STATUS in The system identifies whether the CPUs are the same; if so, it enforces the rule that the first CPU is the master and the second CPU is the slave, and then processes the STATUS status accordingly. loc And configure master-slave failover in the corresponding configuration file; otherwise, do not configure the STATUS status. loc And the corresponding configuration files for master-slave switching.

[0075] Step 253, if state Z COMM If it is abnormal, then for state Y GPIO Is it a normal identification? If so, then do not perform a status check on STATUS. locAnd perform master-slave switching according to the corresponding configuration file; otherwise, further check the current STATUS. loc Whether to identify the primary CPU; if so, then enforce the rule that the first CPU is primary and the second CPU is secondary to determine the STATUS status. loc Configure master-slave switching according to the corresponding configuration file; otherwise, switch the local side to master status. loc And the corresponding configuration file for master-slave switching configuration.

[0076] Here, the master-slave switching strategy selection mechanism in step 25 can be referenced. Figure 6 STATUS provided for embodiments of the present invention loc STATUS in Z COMM Y GPIO The diagram illustrates the correspondence between the master-slave switching strategy and the corresponding strategy.

[0077] In steps 252 and 253, the STATUS state is processed according to the mandatory rule that the first CPU is the master and the second CPU is the slave. loc And the corresponding configuration file for master-slave switching configuration, specifically including: Step A1: The single-sided CPU uses the corresponding first configuration file or second configuration file as the current configuration file.

[0078] Step A2, and read the chip identifier field of the current configuration file as the corresponding chip identifier ID. chip .

[0079] Step A3, and assign the chip identifier ID. chip Whether it is 1 or not is used for identification.

[0080] Step A4, if the chip identifier ID chip If the value is 1, then the status STATUS will be changed. loc Set it as the master and synchronize the master-slave type field of the current configuration file; after this update, continue to wait for the preset specified duration L2; and when this wait ends, change the status to Y. GPIO To determine if it is still an anomaly, check if so, and then change the status to STATUS. loc Set it as a slave and synchronize the master-slave type field of the current configuration file.

[0081] Here, the specified duration L2 in this embodiment of the invention is an integer multiple of the preset period T, L2=N2×T, the multiple N2 is a preset positive integer, N2>1.

[0082] The current step A4 specifically includes: Step A4-1, if the chip identifier ID chipIf the value is 1, then the status STATUS will be changed. loc Set it as the master and synchronize the master-slave type field of the current configuration file.

[0083] Step A4-2, and after this update, continue to wait for the preset specified duration L2.

[0084] Step A4-3, and at the end of this wait, check state Y. GPIO To determine if it is still an anomaly, check if so, and then change the status to STATUS. loc Set it as a slave and synchronize the master-slave type field of the current configuration file.

[0085] Step A5, if the chip identifier ID chip If the value is not 1, then the status STATUS will be changed. loc Set it as a slave and synchronize the master-slave type field of the current configuration file.

[0086] Here, the master-slave switchover configuration process for steps A1-A5 can be found here. Figure 7 The following is a schematic diagram of the master-slave switching process provided in the embodiments of the present invention, in which the first CPU is the master and the second CPU is the slave.

[0087] In step 253, the status STATUS is changed by switching this side to the master side. loc And the corresponding configuration file for master-slave failover configuration, specifically including: a single CPU changing the STATUS status. loc Set it as the master and synchronize the master-slave type field of the current configuration file.

[0088] This invention provides a technical solution for master-slave switching in a dual-CPU architecture. As described above, this invention establishes two unidirectional GPIO signal lines, denoted as GPIO-A and GPIO-B, and one bidirectional data transmission line, denoted as the COMM line, between the two CPUs in the dual-CPU architecture. Two corresponding configuration files are stored on non-volatile storage media connected to each CPU via a data bus. Unidirectional signal rules are customized for the GPIO-A / B lines, and message exchange rules and communication message protocols are customized for the COMM line. After power-on, either CPU initializes its STATUS state according to the configuration file. loc ; and according to the one-way signal rules and status STATUS loc The system monitors the real-time status of the CPU, interacts with it via GPIO signals, and sets the status Y based on the signal transmission and reception status. GPIO ; and according to the communication message protocol and status STATUS locThe system monitors the real-time status of the CPU, exchanges communication messages with the CPU on the other side, and sets the STATUS status based on the message exchange status. in and state Z COMM And based on the STATUS loc STATUS in Z COMM and Y GPIO The real-time state combination is used for master-slave switching. This embodiment of the invention reduces the risk of "dual master" or loss of control caused by misjudgment and reduces the oscillation risk caused by frequent switching, providing highly robust master-slave redundancy protection for rail transit equipment.

[0089] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented in hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0090] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A master-slave switching method for a dual-CPU architecture, characterized in that, The method includes: Two unidirectional GPIO signal lines are established between two CPUs in a dual-CPU architecture, denoted as corresponding GPIO-A line and GPIO-B line, a bidirectional data transmission line is established, denoted as COMM line, and corresponding two configuration files are stored on non-volatile storage media connected by data buses of the two CPUs respectively; unidirectional signal rules are customized for the GPIO-A / B line; and message mutual transmission rules and communication message protocol are customized for the COMM line; wherein the two CPUs include a first CPU and a second CPU; the unidirectional signal rules are that only the master chip can periodically send a square wave signal S to the slave chip, the duty cycle of the square wave signal S is determined by a preset duty cycle r std ; the message mutual transmission rules are that after the dual-CPU architecture is powered on, the master chip first sends a first communication message to the slave chip, then the slave chip and the master chip alternately send communication messages, and the data format of the communication message follows the communication message protocol; the communication message protocol includes four protocol words, namely sequence number SN, sequence number SB_FB, status STATUS, and check code CRC. After the dual-CPU architecture is powered on, either CPU on one side creates a corresponding master-slave switching management variable; and adjusts the STATUS status in the management variable according to the corresponding configuration file. loc Perform initialization; and according to the unidirectional signal rules and the STATUS state. loc The system monitors the real-time status of the CPU, interacts with it via GPIO signals, and sets the status Y in the management variable based on the signal transmission and reception status. GPIO ; and according to the communication message protocol and the status STATUS loc The system monitors the real-time status of the CPU, exchanges communication messages with the CPU on the other side, and sets the STATUS status in the management variables based on the message exchange status. in and state Z COMM And based on the STATUS loc STATUS in Z COMM and Y GPIO The real-time state combination of the STATUS loc and the corresponding configuration file for master-slave switchover configuration; wherein, the STATUS status loc Used to record the real-time master-slave status of the local CPU, including the master chip and slave chip; the status STATUS in Used to record the real-time master-slave status of the opposite CPU, including the master chip and the slave chip; the status Y GPIO Used to record the real-time operating status of the GPIO lines on this side, including normal and abnormal; the status Z COMM Used to record the real-time operating status of the COMM line, including normal and abnormal conditions.

2. The master-slave switching method for a dual-CPU architecture according to claim 1, characterized in that, The GPIO-A line is used for unidirectional signal transmission from the first CPU to the second CPU; The GPIO-B line is used for unidirectional signal transmission from the second CPU to the first CPU; The COMM lines include serial port data lines, Ethernet data lines, and CAN bus data lines; The two configuration files include a first configuration file corresponding to the first CPU and a second configuration file corresponding to the second CPU; the two configuration files have the same file fields, both including a chip identifier field and a master-slave type field; the chip identifier field is 1 to indicate that the corresponding CPU is the first CPU, and 2 to indicate that the corresponding CPU is the second CPU; the master-slave type field includes two types: master chip and slave chip; The sequence number SN is the counting sequence number on the transmitting side; The sequence number SB_FB is the counting sequence number carried in the previous message sent by the receiving side; The STATUS status is used to characterize the master-slave status of the transmitting device, including two types: master chip and slave chip. The CRC checksum is calculated using the CRC algorithm based on the continuous data SN+SB_FB+STATUS. The master-slave switching management variable includes the serial number SN. in Serial Number SN_FB in The STATUS in CRC checksum in Serial Number SN loc Serial Number SN_FB loc The STATUS loc CRC checksum loc Serial Number X pre The state Y GPIO The state Z COMM ; The serial number SN in The serial number SN_FB in The STATUS in The CRC checksum in Used to record the protocol words of communication messages received by the CPU on this side; the sequence number SN loc The serial number SN_FB loc The STATUS loc The CRC checksum loc Used to record the communication message protocol words sent by the CPU on this side; the sequence number X pre The sequence number SN_FB is used to determine the most recently parsed message. in Record it; the serial number SN in The serial number SN_FB in The serial number SN loc The serial number SN_FB loc The serial number X pre All are initially set to 0 upon creation; the STATUS state is... in The CRC checksum in The STATUS loc The CRC checksum loc All are initially set to empty upon creation; the state Y GPIO The state Z COMM All are initially set to normal during creation.

3. The master-slave switching method for a dual-CPU architecture according to claim 2, characterized in that, The status STATUS in the management variable is managed according to the corresponding configuration file. loc Initialization is performed, specifically including: The single-sided CPU uses the corresponding first configuration file or second configuration file as the current configuration file; And read the master-slave type field from the current configuration file as the corresponding initial state STATUS. ini ; And the initial state STATUS ini Check if it is empty; If the initial state STATUS ini If it is empty, then the state STATUS will be... loc Set it as the master piece and synchronously update the master-slave type field in the current configuration file; If the initial state STATUS ini If it is not empty, then the initial state STATUS is... ini Is the main image being identified? If so, then the STATUS status will be entered into the system. loc If set as a slave, then synchronize and update the master-slave type field in the current configuration file; otherwise, set the status STATUS. loc Set it as the master piece and synchronize the master-slave type field of the current configuration file.

4. The master-slave switching method for a dual-CPU architecture according to claim 2, characterized in that, According to the unidirectional signal rule and the STATUS loc The system monitors the real-time status of the CPU, interacts with it via GPIO signals, and sets the status Y in the management variable based on the signal transmission and reception status. GPIO Specifically, it includes: The single-sided CPU uses the GPIO-A line or the GPIO-B line used for sending unidirectional signals on this side as the current sending line, and uses the GPIO-B line or the GPIO-A line used for receiving unidirectional signals on this side as the current receiving line. And in the state STATUS loc When the real-time status is the master chip, the transmitting end of the current transmitting line on this side is taken as the corresponding master transmitting port PO. M The receiving end of the current receiving line on this side is designated as the corresponding main receiving port PI. M The current transmitting line is used as the corresponding receiving port PI at the receiving end of the CPU on the other side. S The current receiving line is designated as the corresponding slave port PO at the transmitting end of the CPU on the opposite side. S Based on the preset duty cycle r std The periodic square wave signal S is generated from the main transmitting port PO. M To the receiving port PI S Send, and to the main sending port PO M The signal transmission status is monitored in real time; and the main receiving port PI is monitored. M Has the PO from the sending port been received? S The transmitted square wave signal S is monitored in real time; and the main transmitting port PO is monitored. M During the monitoring process, if the signal is successfully sent, the state Y is set. GPIO If the signal transmission fails, then state Y is set. GPIO This is abnormal; and in response to the main receiving port PI M During the monitoring process, if the square wave signal S is received, then the state Y is set. GPIO If the square wave signal S is not received, then the state Y is set to an abnormal state. GPIO This is normal; And in the state STATUS loc When the real-time status is set to slave time, the transmitting end of the current transmitting line on this side is taken as the corresponding slave transmitting port PO. S The receiving end of the current receiving line on this side is taken as the corresponding receiving port PI. S The current transmitting line is used as the corresponding main receiving port PI at the receiving end of the CPU on the other side. M The current receiving line is used as the transmitting end of the CPU on the opposite side as the corresponding main transmitting port PO. M ; and for the receiving port PI S Has the main port PO been received? M The transmitted square wave signal S is monitored in real time; and the transmitting port PO is monitored. S The signal transmission status is monitored in real time; and the signal transmission status of the receiving port PI is monitored in real time. S During the monitoring process, if the square wave signal S can be received normally, then the state Y is set. GPIO If the square wave signal S is not received normally, then state Y is set. GPIO This is an anomaly; and in the case of the slave port PO S During the monitoring process, if the slave port PO S To send a signal outward, the state Y is set. GPIO If the above is an anomaly, and the source port PO is abnormal. S If no signal is sent out, then state Y is set. GPIO This is normal.

5. The master-slave switching method for a dual-CPU architecture according to claim 2, characterized in that, According to the communication message protocol and the STATUS loc The system monitors the real-time status of the CPU, exchanges communication messages with the CPU on the other side, and sets the STATUS status in the management variables based on the message exchange status. in and state Z COMM Specifically, it includes: Step 5-1, the single-sided CPU is in the STATUS state. loc After initialization is complete, the STATUS state is... loc Is it the main image identification? If yes, proceed to step 5-2; if no, proceed to step 5-4. Step 5-2, according to the communication message protocol, based on the current sequence number SN loc The serial number SN_FB loc and the state STATUS loc Calculate the corresponding check code CRC loc ; Step 5-3, according to the communication message protocol, based on the current sequence number SN loc The serial number SN_FB loc The STATUS loc The CRC checksum loc Generate a communication message and send it to the CPU on the other side; Step 5-4, for the serial number SN loc Add 1; Step 5-5: Start the local timer to perform periodic timing according to the preset period T; Steps 5-6: Every cycle T, confirm whether a communication message sent by the CPU on the other side has been received; if received, proceed to step 5-7; if not received, proceed to step 5-12. Steps 5-7: Parse the currently received communication message according to the communication message protocol, and set the sequence number SN based on the parsing result. in The serial number SN_FB in The STATUS in The CRC checksum in ; Steps 5-8: According to the communication message protocol, check the CRC checksum. in Perform verification; and identify the verification result; if the verification is successful, proceed to step 5-9; if the verification fails, proceed to step 5-11. Steps 5-9, for the judgment condition (SN) loc -SN_FB in ≤2 and SN_FB in >X pre If the condition is met, proceed to step 5-10; otherwise, proceed to step 5-11. Steps 5-10, based on the sequence number SN_FB in For the serial number X pre Configure settings; Step 5-11, based on the serial number SN in For the serial number SN_FB loc Configure settings; Step 5-12, according to the communication message protocol, based on the current sequence number SN loc The serial number SN_FB loc and the state STATUS loc Calculate the corresponding check code CRC loc ; Step 5-13, according to the communication message protocol, based on the current sequence number SN loc The serial number SN_FB loc The STATUS loc The CRC checksum loc Generate a communication message and send it to the CPU on the other side; Step 5-14, for the serial number SN loc Add 1; Step 5-15, based on the serial number SN loc and the serial number X pre Calculate the difference between the serial numbers E=SN loc -X pre ; Step 5-16: Check whether the sequence number difference E is greater than the preset sequence number difference threshold E. hold Perform identification; if yes, proceed to step 5-17; if no, proceed to step 5-18. Step 5-17, set the state Z COMM Set it as an exception and proceed to steps 5-6; Step 5-18, set the state Z COMM Set it to normal and proceed to steps 5-6.

6. The master-slave switching method for a dual-CPU architecture according to claim 2, characterized in that, The STATUS-based loc STATUS in Z COMM and Y GPIO The real-time state combination of the STATUS loc And the corresponding configuration file for master-slave switching configuration, specifically including: Step 61: After the single-sided CPU starts its local timer and runs for a preset specified duration L1, it periodically scans the state Z at a preset scanning frequency. COMM Identify the real-time status; Wherein, the specified duration L1 is an integer multiple of the preset period T, L1=N1×T, the multiple N1 is a preset positive integer, N1>1; Step 62, if the state Z COMM If it is normal, then the state STATUS is... loc and the STATUS in The system identifies whether the states are the same; if so, it applies the mandatory rule that the first CPU is the master and the second CPU is the slave to the STATUS status. loc And configure master-slave switching in the corresponding configuration file; otherwise, do not configure the STATUS status. loc And the corresponding configuration files for master-slave switching; Step 63, if the state Z COMM If it is abnormal, then for the state Y GPIO Is it normal to identify? If so, then do not perform the STATUS status check. loc And perform master-slave switching according to the corresponding configuration file; otherwise, further check the current STATUS status. loc Whether to identify the master CPU; if so, then apply the mandatory rule of the first CPU as master and the second CPU as slave to the STATUS status. loc And configure the master-slave switch according to the corresponding configuration file; otherwise, switch the local side to the master side and configure the STATUS status accordingly. loc And the corresponding configuration file for master-slave switching configuration.

7. The master-slave switching method for a dual-CPU architecture according to claim 6, characterized in that, The mandatory rule of assigning the first CPU as master and the second CPU as slave to the STATUS state. loc And the corresponding configuration file for master-slave switching configuration, specifically including: Step 71: The single-sided CPU uses the corresponding first configuration file or second configuration file as the current configuration file; Step 72, and read the chip identifier field of the current configuration file as the corresponding chip identifier ID. chip ; Step 73, and assign an ID to the chip. chip Whether it is 1 is used for identification; Step 74, if the chip identifier ID chip If the value is 1, then the state STATUS will be set to 1. loc Set it as the master and synchronously update the master-slave type field in the current configuration file; after this update, continue to wait for a preset specified time L2; and when this wait ends, set the state Y. GPIO To determine if it is still an anomaly, identify the status STATUS. If so, change the status STATUS. loc Set it as a slave segment and synchronously update the master-slave type field in the current configuration file; Wherein, the specified duration L2 is an integer multiple of the preset period T, L2=N2×T, the multiple N2 is a preset positive integer, N2>1; Step 75, if the chip identifier ID chip If the value is not 1, then the state STATUS will be... loc Set it as a slave segment and synchronously update the master-slave type field in the current configuration file.

8. The master-slave switching method for a dual-CPU architecture according to claim 6, characterized in that, The state STATUS is set by switching this side to the main screen. loc And the corresponding configuration file for master-slave switching configuration, specifically including: The single-sided CPU will record the STATUS status. loc Set it as the master piece and synchronize the master-slave type field of the current configuration file.

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