High-frequency high-voltage gate based on decoupling of source and drain functions and preparation method thereof

Abstract

This invention discloses a high-frequency, high-voltage gate structure based on source and drain functional decoupling and its fabrication method, belonging to the field of semiconductor device technology. The method includes: depositing a passivation layer on a substrate, then forming an asymmetric gate pin pattern with source and drain sidewalls on an electron beam resist using asymmetric progressive electron beam lithography; etching the passivation layer using this pattern as a mask to form asymmetric gate pin grooves; subsequently forming a gate neck region and a gate cap region with an undercut structure through multilayer photolithography; and finally fabricating a floating T-type gate through metal deposition and lift-off processes. This invention reduces gate capacitance through steep source sidewalls and modulates the electric field distribution through gentle drain sidewalls, achieving synergistic optimization of frequency characteristics and voltage withstand capability. It effectively solves the performance trade-off problem of traditional symmetrical structures in the millimeter-wave band and is suitable for high-frequency applications such as 5G / 6G communication and satellite communication.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, specifically relating to a high-frequency, high-voltage gate based on source and drain functional decoupling and its fabrication method. Background Technology

[0002] With the rapid development of 5G and 6G mobile communications, satellite communications, and high-resolution radar, increasingly stringent requirements are being placed on the power density, operating frequency, and conversion efficiency of core power devices in the radio frequency (RF) front-end. Gallium nitride (GaN), as a representative of third-generation wide-bandgap semiconductor materials, has become an ideal choice for millimeter-wave power amplifiers due to its high breakdown electric field, high electron saturation drift velocity, and excellent high-temperature operating characteristics. In W-band (75–110 GHz) and even higher frequency applications, to achieve sufficient RF gain, device size must be further reduced, with gate length typically needing to be reduced to below 100 nm. However, with the continuous shrinking of device feature sizes, the traditional field-plate T-gate structure faces severe challenges: extremely high electric field peaks are easily generated near the gate edge of the drain, limiting the device's breakdown voltage capability; at the same time, the impact of parasitic parameters on device performance increases dramatically.

[0003] To achieve both high power and high frequency characteristics in the millimeter-wave band, various gate structures have been proposed by those skilled in the art, such as T-gate structures with tilted sidewall field plates, floating T-gate structures with tilted groove structures, and Γ-gate structures. However, the T-gate structure with tilted sidewall field plates still adopts the traditional design method of the gate cap being tightly attached to the passivation layer, resulting in a large gate parasitic capacitance, which limits the gain performance of the device in the high-frequency band. In the floating T-gate structure with tilted groove structure, excessive tilting of the source gate pin introduces excess gate capacitance, which cannot fully utilize the high-frequency performance of the device. Due to the asymmetry of the gate cap, the gate cap region of the Γ-gate structure still requires passivation layer support, making it difficult to achieve lower parasitic capacitance in the W-band and above. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a high-frequency, high-voltage gate based on source-drain functional decoupling and its fabrication method. In a first aspect, the present invention provides a method for fabricating a high-frequency, high-voltage gate based on source-drain functional decoupling, comprising: A substrate is provided, and a passivation layer is deposited on the surface of the substrate; Electron beam resist is coated on the surface of the passivation layer, and the electron beam resist is subjected to asymmetric progressive electron beam exposure and development to form a gate pin pattern with asymmetric source sidewall and drain sidewall on the electron beam resist. Using the developed electron beam resist as a mask, the passivation layer is etched to transfer the gate pin pattern into the passivation layer, forming an asymmetric gate pin groove. Then, the remaining electron beam resist is removed. Electron beam resist is coated on the surface of the passivation layer with the asymmetric gate foot groove. After exposure and development, a gate neck region is defined above the asymmetric gate foot groove. A first layer of photoresist and a second layer of photoresist are sequentially coated on the electron beam resist. After exposure and development, a gate cap region is defined above the gate neck region and an undercut structure is formed. Gate metal is deposited on the sample surface and a stripping process is performed to remove the metal, electron beam resist, and each layer of photoresist above the second layer of photoresist, forming a floating T-type gate with asymmetric gate feet at the source and drain ends.

[0005] In one embodiment of the present invention, the angle between the source end sidewall and the horizontal direction is . The angle between the sidewall of the drain end and the horizontal direction is... ,in, and .

[0006] In one embodiment of the present invention, when the angle between the source end sidewall and the horizontal direction... The step of coating the passivation layer surface with electron beam resist and performing asymmetric progressive electron beam exposure and development on the electron beam resist to form a gate pin pattern with asymmetric source and drain sidewalls on the electron beam resist includes: Electron beam resist is spin-coated onto the surface of the passivation layer; Along the source-to-drain direction, the electron beam resist corresponding to the gate pin pattern is divided into... Sub-regions; At different exposure doses, the above Electron beam exposure and development are performed on each sub-region to form an asymmetrical gate pin pattern between the source and drain sidewalls; Wherein, when the angle between the source end sidewall and the horizontal direction At that time, the exposure dose of the first sub-region Make the ratio of the developed photoresist thickness to the initial photoresist thickness in the first sub-region 0, and the second sub-region... Exposure dose for each sub-region Decrease along the direction from source to drain, and make the first... The ratio of the developed photoresist thickness to the initial photoresist thickness in each sub-region is... The inner edge increases in the direction from the source end to the drain end.

[0007] In one embodiment of the present invention, when the angle between the source end sidewall and the horizontal direction... The step of coating the passivation layer surface with electron beam resist and performing asymmetric progressive electron beam exposure and development on the electron beam resist to form a gate pin pattern with asymmetric source and drain sidewalls on the electron beam resist includes: Electron beam resist is spin-coated onto the surface of the passivation layer; Starting from the middle position of the electron beam resist corresponding to the gate pin pattern, the electron beam resist on the side of the middle position closest to the source end is divided into... The electron beam resist at the middle position near the drain end is divided into sub-regions. Sub-regions; The exposure dose of the first sub-region located in the middle, near the source end. Make the ratio of the developed photoresist thickness to the initial photoresist thickness in this sub-region 0, the first... Exposure dose for each sub-region The direction from the intermediate position to the source end decreases, and the first... The ratio of the developed photoresist thickness to the initial photoresist thickness in each sub-region is... The exposure dose increases from the source end to the drain end; the first sub-region near the drain end in the middle position has an exposure dose that increases from the source end to the drain end. Make the ratio of the developed photoresist thickness to the initial photoresist thickness in this sub-region 0, the first... Exposure dose for each sub-region The direction decreases from the middle position to the drain end, and makes the first The ratio of the developed photoresist thickness to the initial photoresist thickness in each sub-region is... The inner edge increases in the direction from the source end to the drain end.

[0008] In one embodiment of the present invention, in a direction perpendicular to the plane of the substrate, the orthogonal projection of the gate metal in the asymmetric gate recess does not completely cover the drain sidewall and / or the source sidewall.

[0009] In one embodiment of the present invention, in a direction perpendicular to the plane of the substrate, the orthogonal projection of the gate metal in the asymmetric gate recess covers at least a portion of the passivation layer surrounding the asymmetric gate recess.

[0010] In one embodiment of the present invention, the material of the passivation layer includes , or .

[0011] In one embodiment of the present invention, the angle between the source end sidewall and the horizontal direction is... The range is The angle between the sidewall of the drain end and the horizontal direction The range is .

[0012] Secondly, the present invention also provides a high-frequency, high-voltage gate based on source-drain functional decoupling, which is prepared by the method described in the first aspect.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) This invention provides a high-frequency, high-voltage gate based on source and drain functional decoupling, which adopts an asymmetric gate pin structure: the source sidewall has a steep topography to minimize gate-source parasitic capacitance, and the drain sidewall has a gently sloping topography to effectively modulate the electric field distribution. This overcomes the performance trade-off between frequency characteristics and voltage withstand capability in traditional symmetric gate pin structures, and solves the problem that it is difficult to simultaneously achieve high-frequency characteristics and high voltage withstand level in the prior art. By controlling the tilt angle relationship between the source and drain sidewalls, the gate parasitic capacitance is significantly reduced while the electric field peak at the drain gate pin is effectively smoothed, thereby achieving higher power gain and breakdown voltage in millimeter-wave bands such as the W-band.

[0014] (2) This invention adopts a floating T-gate structure, which greatly weakens the capacitive coupling effect between the gate and the channel by increasing the vertical distance between the gate cap and the passivation layer. Combined with the asymmetric gate pin design, the gate-source capacitance and gate-drain capacitance are significantly reduced, which is beneficial to meeting the stringent requirements of device performance in high-frequency application scenarios such as 5G / 6G communication and satellite communication.

[0015] (3) The present invention adopts an asymmetric progressive electron beam exposure method. By dividing the grid pin pattern into multiple sub-regions and applying a gradient exposure dose, the morphological characteristics of the grid pin sidewall can be precisely controlled, realizing continuous control from the vertical sidewall to the sidewall with different tilt angles. The process has good repeatability and is suitable for large-scale production.

[0016] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0017] Figure 1 This is a schematic flowchart of a method for fabricating a high-frequency, high-voltage gate based on source-drain functional decoupling provided in an embodiment of the present invention. Figures 2-11 This is a schematic diagram of the fabrication process of a high-frequency, high-voltage gate based on source and drain functional decoupling provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of another high-frequency, high-voltage gate structure based on source and drain functional decoupling provided in an embodiment of the present invention; Figure 13 This is a schematic diagram illustrating the relationship between the gate-drain capacitance and the peak electric field at the drain gate pin as a function of the tilt angle of the drain gate pin, according to an embodiment of the present invention. Figure 14aThis is an electron beam exposure dose-film thickness curve provided in an embodiment of the present invention; Figure 14b This is a schematic diagram of the exposure dose of different sub-regions provided in the embodiments of the present invention; Figure 15 This is a schematic diagram of a high-frequency, high-voltage gate with a non-covered area provided in an embodiment of the present invention; Figure 16 This is a schematic diagram of another high-frequency, high-voltage gate with a non-covered area provided in an embodiment of the present invention; Figure 17 This is a graph showing the change of gate-drain capacitance with the non-covered area provided in an embodiment of the present invention; Figure 18 This is a curve showing the change of the peak electric field at the drain gate foot with the non-covered area, provided in an embodiment of the present invention. Detailed Implementation

[0018] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0019] Figure 1 This is a schematic flowchart of a method for fabricating a high-frequency, high-voltage gate based on source-drain functional decoupling provided in an embodiment of the present invention. Figures 2-11 This is a schematic diagram illustrating the fabrication process of a high-frequency, high-voltage gate based on source-drain functional decoupling, as provided in an embodiment of the present invention. Figures 1-11 As shown, this embodiment of the invention provides a method for fabricating a high-frequency, high-voltage gate based on source-drain functional decoupling, comprising: S1. Provide a substrate 1 and deposit a passivation layer 2 on the surface of the substrate 1.

[0020] like Figures 2-3 As shown, the substrate 1 was first cleaned: Substrate 1 was ultrasonically cleaned in acetone solution for 5 minutes; substrate 1 was then heated in a 60°C stripping solution in a water bath for 15 minutes; substrate 1 was then ultrasonically cleaned in acetone solution and isopropanol solution for 5 minutes each to remove surface organic contaminants and particulate impurities; the substrate was rinsed with ultrapure water for 2 minutes and dried with nitrogen. Next, the surface of substrate 1 was treated with ammonia: the cleaned substrate 1 was immersed in an ammonia solution and heated in a 55°C water bath for 5 minutes; the sample was rinsed with ultrapure water for 2 minutes and dried with nitrogen. Finally, a passivation layer 2 of a predetermined thickness, such as 100 nm, was deposited on the entire substrate using PECVD or other CVD processes. The material of the passivation layer 2 can be... SiN and Materials, etc.

[0021] S2. Electron beam resist is coated on the surface of passivation layer 2, and the electron beam resist is subjected to asymmetric progressive electron beam exposure and development to form asymmetric gate pin patterns on the source sidewall and drain sidewall on the electron beam resist.

[0022] After the passivation layer 2 is deposited, the asymmetric gate pin pattern is defined. (See [link to relevant documentation]). Figure 4 Electron beam resist is spin-coated onto the surface of passivation layer 2. The resist is patterned by asymmetric progressive electron beam exposure and development, thereby forming an asymmetric gate pin pattern between the source sidewall and the drain sidewall after development. Figure 12 This is another schematic diagram of a high-frequency, high-voltage gate structure based on source and drain functional decoupling provided in an embodiment of the present invention. It should be noted that... (Please refer to...) Figures 11-12 In this embodiment, the asymmetrical gate pin pattern between the source and drain sidewalls refers to the different tilt angles of the source and drain sidewalls. The angle between the source sidewall and the horizontal direction is defined as... The angle between the drain end sidewall and the horizontal direction is defined as ,in, and In other words, the source sidewall of the gate pin pattern can be a vertical sidewall and the drain sidewall can be an inclined sidewall, or both can be inclined sidewalls, but the inclination angle of the source sidewall is greater than that of the drain sidewall.

[0023] It should be noted that, compared with conventional symmetrical gate pins, this embodiment reduces the gate capacitance on the source side by making the tilt angle of the source sidewall greater than that of the drain sidewall, thereby improving the overall frequency characteristics of the device while ensuring the ability of the drain to modulate the electric field.

[0024] Figure 13 This is a schematic diagram illustrating the relationship between the gate-drain capacitance and the peak electric field at the drain gate pin as a function of the drain gate pin tilt angle, according to an embodiment of the present invention. Figure 13 As shown, with the increase of the drain-gate pin tilt angle, the gate-drain capacitance decreases, while the peak electric field at the drain-gate pin increases accordingly. The two trends are opposite, indicating a clear performance trade-off. To achieve the optimal balance between gate-drain capacitance and peak electric field, the angle between the source sidewall and the horizontal direction in this embodiment is... The range is The angle between the sidewall of the drain end and the horizontal direction The range is It can effectively control the peak electric field while ensuring a low gate-drain capacitance.

[0025] When the angle between the source end sidewall and the horizontal direction When, step S2 includes: S211. Spin-coat electron beam resist on the surface of passivation layer 2; S212. Along the source-to-drain direction, divide the electron beam resist corresponding to the gate pin pattern into... Sub-regions; S213. With different exposure doses, Electron beam exposure and development are performed on each sub-region to form an asymmetrical gate pin pattern between the source and drain sidewalls; Among them, when the angle between the source end sidewall and the horizontal direction hour, The exposure dose in each sub-region decreases from the source end to the drain end, when the angle between the drain end sidewall and the horizontal direction... hour, The exposure dose of each sub-region decreases from the drain end to the source end.

[0026] Figure 14a This is an electron beam exposure dose-resin thickness curve provided in an embodiment of the present invention. The horizontal axis represents the electron beam exposure dose, and the vertical axis represents the ratio of the resist thickness after development to the initial resist thickness. Figure 14a As shown, at low exposure doses (range 1), the ratio of the developed resist thickness to the initial resist thickness is close to 1, meaning the developed resist thickness is close to the initial resist thickness. Within range 2, as the exposure dose gradually increases, the ratio of the developed resist thickness to the initial resist thickness decreases accordingly. When the exposure dose reaches a high dose (range 3), the ratio of the developed resist thickness to the initial resist thickness approaches 0, meaning the developed resist thickness approaches 0. This indicates that the higher the exposure dose, the thinner the resist thickness after development. Clearly, the higher the exposure dose, the stronger the chemical reaction of the electron beam resist, and the thinner the remaining resist thickness after development; conversely, the lower the exposure dose, the thicker the remaining resist thickness.

[0027] In view of this, in this embodiment, after spin-coating electron beam resist on the surface of passivation layer 2, the electron beam resist corresponding to the gate pin pattern is divided in the direction from the source to the drain (i.e., the gate length direction) into... Sub-regions. Figure 14b This is a schematic diagram of the exposure dose for different sub-regions provided in an embodiment of the present invention, such as... Figure 14b As shown, the dimension of the first sub-region in the grid length direction is denoted as... , These represent the exposure doses of the 1st, 2nd, ..., Nth sub-regions, respectively, when the source-end sidewall is a vertical sidewall and the drain-end sidewall is an inclined sidewall. Make the ratio of the developed adhesive thickness to the initial adhesive thickness of the first sub-region 0, along the direction from the source end to the drain end. Decreasing, and making the first The ratio of the developed photoresist thickness to the initial photoresist thickness in each sub-region is... The exposure dose increases from the source end to the drain end. This exposure dose gradient design allows for differences in the resist thickness after development in different sub-regions (the resist thickness is thinner in areas with higher exposure doses and thicker in areas with lower exposure doses), ultimately achieving an asymmetric morphology of the grid foot sidewalls.

[0028] When the angle between the source end sidewall and the horizontal direction The step of coating an electron beam resist on the surface of passivation layer 2 and performing asymmetric progressive electron beam exposure and development on the electron beam resist to form a gate pin pattern with asymmetric source and drain sidewalls on the electron beam resist includes: S221. Spin-coat electron beam resist on the surface of passivation layer 2; S222. Starting from the middle position of the electron beam resist corresponding to the gate pin pattern, divide the electron beam resist on the side of the middle position closest to the source end into... The electron beam resist at the middle position near the drain end is divided into sub-regions. Sub-regions; in, The exposure dose of each sub-region decreases from the middle position to the source end. The exposure dose of each sub-region decreases from the middle position to the leak end.

[0029] Specifically, when the sidewalls of the gate pin pattern are all sloping sidewalls, an electron beam resist is spin-coated onto the surface of passivation layer 2. Starting from the middle position of the electron beam resist corresponding to the gate pin pattern, the electron beam resist near the source end at this middle position is divided into... The electron beam resist at the middle position near the drain end is divided into sub-regions. Each sub-region. Similarly, for the side of this intermediate position closer to the source end, along the direction from the intermediate position to the source end, respectively for the first sub-region. Apply exposure dose to each sub-region ,in, The ratio of the developed photoresist thickness to the initial photoresist thickness in the first sub-region closest to the source end is set to 0. Decreasing, and making the first The ratio of the developed photoresist thickness to the initial photoresist thickness in each sub-region is... Inside, that is to say, the first The ratio of the developed photoresist thickness to the initial photoresist thickness in each sub-region is also... The range increases incrementally. For the side of the middle position closest to the drain end, along the direction from the middle position to the source end, respectively, for the first... Apply exposure dose to each sub-region ,in, The ratio of the developed adhesive thickness to the initial adhesive thickness in the first sub-region, located near the drain end in the middle, is set to 0. Decreasing, and making the first The ratio of the developed photoresist thickness to the initial photoresist thickness in each sub-region is greater than 0 and less than 1, meaning that the ratio of the developed photoresist thickness to the initial photoresist thickness in each sub-region is greater than 0 and less than 1. The ratio of the developed photoresist thickness to the initial photoresist thickness in each sub-region is also... It increases within a certain range.

[0030] In this embodiment, different exposure doses are applied to multiple sub-regions on both sides of the middle position. By controlling the gradient change of the exposure dose, the two sidewalls of the grid pin pattern are asymmetrically distributed.

[0031] Finally, the exposed sample is placed in electron beam developer to remove the electron beam resist in the grid trench area. After drying with nitrogen, the sample is placed... The film forms on the hot plate for 1 minute.

[0032] It should be understood that, compared with the structure with the source sidewall perpendicular, when the passivation layer 2 is thicker and the gate foot groove is deeper, both the source sidewall and the drain sidewall have a certain tilt angle, which is beneficial for filling the gate metal during the evaporation process, avoiding the generation of obvious voids, and thus affecting the resistance of the gate metal.

[0033] S3. Using the developed electron beam resist as a mask, etch the passivation layer 2, transfer the gate pin pattern to the passivation layer 2, form an asymmetric gate pin groove, and then remove the remaining electron beam resist.

[0034] like Figure 5 As shown, in step S3, firstly, using the developed electron beam resist as a mask, the passivation layer 2 in the gate pin area is removed by plasma etching (ICP) to form an asymmetric gate pin groove. The etching conditions include: and As the reactant gas, the upper electrode power was set to 100W and the lower electrode power to 25W. The etching depth was controlled to be consistent with the thickness of passivation layer 2 to ensure complete removal of the passivation layer 2 material in the gate pin pattern area while maintaining the accuracy of pattern transfer. After ICP etching, the sample underwent post-etching cleaning, which included the following steps: ultrasonic cleaning in acetone solution for 3 minutes to remove most of the residue; then, the sample was heated in a 60°C stripping solution for 10 minutes to further remove etching residue; next, the sample was ultrasonically cleaned in acetone solution and isopropanol solution for 3 minutes each; finally, the sample was rinsed with ultrapure water for 2 minutes and the surface was dried with nitrogen.

[0035] S4. Electron beam resist is coated on the surface of passivation layer 2 with asymmetric gate foot grooves. After exposure and development, a gate neck region is defined above the asymmetric gate foot grooves.

[0036] Specifically, please see Figures 6-7 After spin-coating electron beam resist onto the surface of passivation layer 2 with asymmetric gate grooves, the sample is pre-baked on a hot plate at 200°C for 5 minutes to remove moisture. Then, electron beam resist is applied and spin-spinned, and the sample is baked on a hot plate. The electron beam resist can be selected from PMMA, ZEP520 or CSAR 62 series electron beam photoresist.

[0037] The electron beam resist in the neck region above the asymmetric grid foot groove is fully exposed with a preset exposure dose, i.e., the preset exposure dose needs to make the ratio of the resist thickness after development to the initial resist thickness 0; the exposed sample is placed in the electron beam developer to remove the electron beam resist in the grid neck and the asymmetric grid foot groove, and then dried with nitrogen; the sample is placed on a hot plate at 130°C for 1 min to harden the film.

[0038] S5. First and second layers of photoresist are sequentially coated on the electron beam resist. After exposure and development, a gate cap region is defined above the gate neck region, forming an undercut structure.

[0039] like Figures 8-9 As shown, in step S5, the first layer of photoresist is first spin-coated onto the electron beam resist surface: the sample is placed on a hot plate and pre-baked for 5 minutes to remove moisture; SF series photoresist such as SF6 photoresist is spin-coated to form an easily peelable undercut structure in subsequent steps, and then the resist is baked on a hot plate.

[0040] Next, a second layer of photoresist is spin-coated onto the surface of the first layer: a stepper photoresist such as EPI621 photoresist is spin-coated to define the size of the gate cap pattern, and then the photoresist is baked on a hot plate.

[0041] The photoresist was exposed using a Stepper lithography machine. After exposure, it was baked on a hot plate for 1 minute to eliminate the standing wave effect. Finally, the photoresist was developed using a developer such as TMAH to obtain the gate cap region with an undercut structure.

[0042] S6. Deposit gate metal on the sample surface and perform a stripping process to remove the metal, electron beam resist, and each layer of photoresist above the second layer of photoresist, forming a floating T-type gate with asymmetric gate feet at the source and drain ends.

[0043] Please see Figure 10 The sample with the complete grid pattern is placed in a plasma bottom film removal machine to remove any residual adhesive that may be present at the bottom; the sample is then placed in an electron beam evaporation stage, and the vacuum level in the reaction chamber of the electron beam evaporation stage is reached. After Torr, the gate metal is evaporated, such as a Ni / Au stacked metal or other metals that can be used to fabricate the gate.

[0044] See further Figure 11 The sample after the gate metal evaporation is completed is stripped to remove the metal, electron beam resist, and second and third layers of photoresist above the second layer of photoresist. The sample is then rinsed with ultrapure water and dried with nitrogen gas to finally form a floating T-shaped gate with source-drain asymmetric gate feet.

[0045] In this embodiment, by adjusting the range of the exposure gate neck, a certain non-covered area can be formed inside the asymmetric gate foot, thereby obtaining a high-frequency, high-voltage gate structure with a non-covered area. Figures 15-16 This is a schematic diagram of a high-frequency, high-voltage gate with a non-covered area provided in an embodiment of the present invention. (See diagram below.) Figures 15-16 As shown, in the direction perpendicular to the plane of substrate 1, when the orthogonal projection of the gate metal in the asymmetric gate recess does not completely cover the drain sidewall and / or source sidewall, the non-covered area is defined as greater than 0; when the orthogonal projection of the gate metal in the asymmetric gate recess covers at least part of the passivation layer 2 around the asymmetric gate recess, the non-covered area is defined as less than 0.

[0046] It should be understood that the gate-drain capacitance and the peak electric field at the drain gate pin will vary with the change in the uncovered area. Figure 17 This is a graph showing the change of gate-drain capacitance with the non-covered area provided in an embodiment of the present invention. Figure 18 This is a graph showing the peak electric field at the drain gate foot as a function of the uncovered area, provided in an embodiment of the present invention. Please refer to [link / reference]. Figure 17 When the tilt angle is constant, if the application requires higher frequency performance than voltage withstand capability, the non-covered area of ​​the gate metal can be increased (corresponding to a non-covered area greater than 0). The gate-drain capacitance will decrease as the non-covered area increases, thus improving the device's frequency performance. Figure 18 As shown, if the application scenario requires higher voltage withstand capability than frequency characteristics, the non-covered area can be reduced or even extended to the drain to form a field plate structure (or even extended to the drain to form a field plate structure, corresponding to the case where the non-covered area is less than 0). In this case, the peak electric field at the drain gate is reduced due to the reduction of the non-covered area, and the voltage withstand capability of the device is improved.

[0047] This invention also provides a high-frequency, high-voltage gate structure based on source and drain functional decoupling, which is prepared using the above method.

[0048] As can be seen from the above embodiments, the beneficial effects of the present invention are as follows: (1) This invention provides a high-frequency, high-voltage gate based on source and drain functional decoupling, which adopts an asymmetric gate pin structure: the source sidewall has a steep topography to minimize gate-source parasitic capacitance, and the drain sidewall has a gently sloping topography to effectively modulate the electric field distribution. This overcomes the performance trade-off between frequency characteristics and voltage withstand capability in traditional symmetric gate pin structures, and solves the problem that it is difficult to simultaneously achieve high-frequency characteristics and high voltage withstand level in the prior art. By controlling the tilt angle relationship between the source and drain sidewalls, the gate parasitic capacitance is significantly reduced while the electric field peak at the drain gate pin is effectively smoothed, thereby achieving higher power gain and breakdown voltage in millimeter-wave bands such as the W-band.

[0049] (2) This invention adopts a floating T-gate structure, which greatly weakens the capacitive coupling effect between the gate and the channel by increasing the vertical distance between the gate cap and the passivation layer. Combined with the asymmetric gate pin design, the gate-source capacitance and gate-drain capacitance are significantly reduced, which is beneficial to meeting the stringent requirements of device performance in high-frequency application scenarios such as 5G / 6G communication and satellite communication.

[0050] (3) The present invention adopts an asymmetric progressive electron beam exposure method. By dividing the grid pin pattern into multiple sub-regions and applying a gradient exposure dose, the morphological characteristics of the grid pin sidewall can be precisely controlled, realizing continuous control from the vertical sidewall to the sidewall with different tilt angles. The process has good repeatability and is suitable for large-scale production.

[0051] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0052] The use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples" indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0053] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for preparing a high-frequency high-voltage gate based on decoupling of source and drain functions, characterized in that, include: A substrate is provided, and a passivation layer is deposited on the surface of the substrate; Electron beam resist is coated on the surface of the passivation layer, and the electron beam resist is subjected to asymmetric progressive electron beam exposure and development to form a gate pin pattern with asymmetric source sidewall and drain sidewall on the electron beam resist. Using the developed electron beam resist as a mask, the passivation layer is etched to transfer the gate pin pattern into the passivation layer, forming an asymmetric gate pin groove. Then, the remaining electron beam resist is removed. Electron beam resist is coated on the surface of the passivation layer with the asymmetric gate foot groove. After exposure and development, a gate neck region is defined above the asymmetric gate foot groove. A first layer of photoresist and a second layer of photoresist are sequentially coated on the electron beam resist. After exposure and development, a gate cap region is defined above the gate neck region and an undercut structure is formed. Gate metal is deposited on the sample surface and a stripping process is performed to remove the metal, electron beam resist, and each layer of photoresist above the second layer of photoresist, forming a floating T-type gate with asymmetric gate feet at the source and drain ends.

2. The method for fabricating a high-frequency, high-voltage gate based on source-drain functional decoupling according to claim 1, characterized in that, The included angle between the source end side wall and the horizontal direction is The included angle between the drain end side wall and the horizontal direction is wherein, and .

3. The method for fabricating a high-frequency, high-voltage gate based on source-drain functional decoupling according to claim 2, characterized in that, When the included angle between the source end sidewall and the horizontal direction is When the included angle between the source end sidewall and the horizontal direction is When the included angle between the source end sidewall and the horizontal direction is Electron beam resist is spin-coated onto the surface of the passivation layer; In the source-to-drain direction, the electron beam resist corresponding to the gate foot pattern is divided into sub-areas. The source side and the drain side of the gate foot pattern are asymmetric. The source side and the drain side of the gate foot pattern are asymmetric. Wherein, when the angle between the source end sidewall and the horizontal direction At that time, the exposure dose of the first sub-region Make the ratio of the developed photoresist thickness to the initial photoresist thickness in the first sub-region 0, and the second sub-region... Exposure dose for each sub-region Decrease along the direction from source to drain, and make the first... The ratio of the developed photoresist thickness to the initial photoresist thickness in each sub-region is... The inner edge increases in the direction from the source end to the drain end.

4. The method for fabricating a high-frequency, high-voltage gate based on source-drain functional decoupling according to claim 2, characterized in that, When the angle between the source end sidewall and the horizontal direction The step of coating the passivation layer surface with electron beam resist and performing asymmetric progressive electron beam exposure and development on the electron beam resist to form a gate pin pattern with asymmetric source and drain sidewalls on the electron beam resist includes: Electron beam resist is spin-coated onto the surface of the passivation layer; Starting from the middle position of the electron beam resist corresponding to the gate pin pattern, the electron beam resist on the side of the middle position closest to the source end is divided into... The electron beam resist at the middle position near the drain end is divided into sub-regions. Sub-regions; The exposure dose of the first sub-region located in the middle, near the source end. Make the ratio of the developed photoresist thickness to the initial photoresist thickness in this sub-region 0, the first... Exposure dose for each sub-region The direction from the intermediate position to the source end decreases, and the first... The ratio of the developed photoresist thickness to the initial photoresist thickness in each sub-region is... The exposure dose increases from the source end to the drain end; the first sub-region near the drain end in the middle position has an exposure dose that increases from the source end to the drain end. Make the ratio of the developed photoresist thickness to the initial photoresist thickness in this sub-region 0, the first... Exposure dose for each sub-region The direction decreases from the middle position to the drain end, and makes the first The ratio of the developed photoresist thickness to the initial photoresist thickness in each sub-region is... The inner edge increases in the direction from the source end to the drain end.

5. The method for fabricating a high-frequency, high-voltage gate based on source-drain functional decoupling according to claim 3 or 4, characterized in that, In a direction perpendicular to the plane of the substrate, the orthogonal projection of the gate metal within the asymmetric gate foot recess does not completely cover the drain sidewall and / or source sidewall.

6. The method for fabricating a high-frequency, high-voltage gate based on source-drain functional decoupling according to claim 3 or 4, characterized in that, In a direction perpendicular to the plane of the substrate, the orthogonal projection of the gate metal within the asymmetric gate recess covers at least a portion of the passivation layer surrounding the asymmetric gate recess.

7. The method for fabricating a high-frequency, high-voltage gate based on source-drain functional decoupling according to claim 1, characterized in that, The material of the passivation layer includes , or .

8. The method for fabricating a high-frequency, high-voltage gate based on source-drain functional decoupling according to claim 2, characterized in that, The angle between the source end sidewall and the horizontal direction The range is The angle between the sidewall of the drain end and the horizontal direction The range is .

9. A high-frequency, high-voltage gate based on source-drain functional decoupling, characterized in that, It is prepared by any one of the methods described in claims 1 to 8.

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