A stacked package structure and a forming method thereof

Abstract

This invention provides a stacked packaging structure and its forming method, comprising: a substrate on which a first chip is mounted; a thermally conductive insulating layer disposed on the first chip, having a through-groove thereon, comprising a first insulating layer, a first thermally conductive layer, and a second insulating layer sequentially stacked away from the first chip, and a second thermally conductive layer disposed on the sidewall of the through-groove and connected to the first thermally conductive layer; a second chip having a conductive pad disposed in the through-groove and connected to both the second thermally conductive layer and the first chip; and an encapsulation layer covering the substrate, the first chip, the thermally conductive insulating layer, and the second chip. The first and second thermally conductive layers form a thermally conductive channel, improving the heat dissipation performance of the second chip; furthermore, the contact area between the conductive pad of the second chip and the second thermally conductive layer increases, further improving heat dissipation performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing equipment technology, and in particular to a stacked packaging structure and its formation method. Background Technology

[0002] In current multilayer chip stacking packaging products, chips are often bonded together using non-conductive film layers, or the spaces between chips are filled using bottom filler. Such stacking and bonding can lead to heat accumulation due to the weak heat dissipation capacity of the adhesive or the narrow gaps, thus affecting product performance.

[0003] Traditional heat dissipation solutions for packaged devices mostly rely on a top heat diffuser to evenly distribute hot spots, which are then dissipated by a heat dissipation module. However, the problem of hot spots is more severe in stacked chip packages, especially when heat-generating chips are stacked in the middle. Not only is heat difficult to dissipate, but it can also affect nearby chips, leading to reduced reliability. Summary of the Invention

[0004] This invention provides an innovative stacked packaging structure and its formation method, constructing a composite thermally conductive insulating layer that integrates vertical heat dissipation channels and electrical interconnection functions. This structure effectively solves the problems of heat dissipation difficulties and heat accumulation, especially in the middle layer chips, during stacked chip packaging.

[0005] The core of this invention lies in proposing a stacked packaging structure, comprising: A substrate on which a first chip is mounted; A thermally conductive insulating layer is disposed on the first chip and has a through groove thereon. It includes a first insulating layer, a first thermally conductive layer and a second insulating layer that are stacked sequentially in a direction away from the first chip, and a second thermally conductive layer disposed on the sidewall of the through groove and connected to the first thermally conductive layer. The second chip is provided with a conductive pad, which is disposed in the through groove and is connected to both the second thermal conductive layer and the first chip; An encapsulation layer is provided that covers the substrate, the first chip, the thermally conductive insulating layer, and the second chip.

[0006] Preferably, the thickness of the first insulating layer is 0.5-2 micrometers, the thickness of the first thermally conductive layer is 0.2-5 micrometers, and the thickness of the second insulating layer is 0.5-2 micrometers.

[0007] Preferably, the height of the second thermally conductive layer is equal to the sum of the thicknesses of the first insulating layer, the first thermally conductive layer, and the second insulating layer, and the thickness of the second thermally conductive layer is 0.2-1 micrometer.

[0008] Preferably, the first insulating layer and the second insulating layer are made of aluminum oxide, aluminum nitride, or silicon dioxide.

[0009] Preferably, the first and second thermal conductive layers are made of aluminum, copper, or doped thermal conductive film.

[0010] Preferably, the encapsulation layer includes a first molding compound layer disposed on the substrate and the sidewall of the first chip, and a first molding compound layer covering the first chip, the thermally conductive insulating layer and the second chip.

[0011] A method for forming a stacked package structure includes the following steps: The first chip is mounted on the substrate; A first insulating layer, a first thermally conductive layer, and a second insulating layer are sequentially stacked on the first chip; A through-groove is formed that penetrates the first insulating layer, the first thermally conductive layer, and the second insulating layer, and a second thermally conductive layer is formed that is disposed on the sidewall of the through-groove and connected to the first thermally conductive layer; A second chip with a conductive disk is installed, the conductive disk is placed in the through slot, and is connected to both the second thermal conductive layer and the first chip; An encapsulation layer is formed covering the substrate, the first chip, the thermally conductive insulating layer, and the second chip.

[0012] Preferably, the first insulating layer, the first thermally conductive layer, the second insulating layer, and the second thermally conductive layer are formed by a deposition process.

[0013] Preferably, the steps of forming the first insulating layer, the first thermally conductive layer, and the second insulating layer include: Deposit a layer of silicon dioxide material; A first implantation layer is formed by ion implantation of silicon dioxide material. The first implantation layer constitutes a first thermally conductive layer. A first insulating layer is formed below the implantation layer. A second insulating layer is formed by depositing silicon dioxide material on the first thermally conductive layer. The steps for forming the second thermally conductive layer include: A second implantation layer is formed by a second ion implantation through the sidewall of the tank, and the second implantation layer constitutes a second thermally conductive layer.

[0014] Preferably, the process conditions for the first and second ion implantations are as follows: The implanted ions are Cu⁺, Ag⁺, or Zn⁺, and the implantation dose is 1×10¹⁵ - 1×10¹⁵. 6 cm⁻², Injection energy: 30-100 keV, annealing at 200-400℃ under N2 atmosphere.

[0015] The present invention has the following beneficial effects: The present invention improves the heat dissipation performance of the second chip by setting a first insulating layer, a first thermally conductive layer and a second insulating layer, and a second thermally conductive layer stacked in sequence, with the first thermally conductive layer and the second thermally conductive layer forming a thermally conductive channel; moreover, the conductive pad of the second chip contacts the second thermally conductive layer, increasing the contact area and further improving the heat dissipation performance.

[0016] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings.

[0017] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0018] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the structure after mounting the first chip on the substrate in the method for forming the stacked packaging structure provided in the embodiment of the present invention. Figure 2 This is a schematic diagram of the structure after a first insulating layer, a first thermally conductive layer and a second insulating layer are sequentially stacked on a first chip in the method for forming a stacked packaging structure provided in an embodiment of the present invention. Figure 3 A schematic diagram of a through-groove forming a stacked packaging structure in an embodiment of the present invention, wherein a through-groove is formed through the first insulating layer, the first thermally conductive layer and the second insulating layer; Figure 4 This is a schematic diagram of the structure after forming a second heat-conducting layer disposed on the sidewall of the through slot and connected to the first heat-conducting layer in the method for forming a stacked packaging structure provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of the structure after the first molding layer is formed in the method for forming the stacked packaging structure provided in the embodiment of the present invention; Figure 6 This is a schematic diagram of the structure after the second molding layer is formed in the method for forming the stacked packaging structure provided in the embodiment of the present invention. Detailed Implementation

[0019] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in further detail below with reference to the accompanying drawings and specific embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it.

[0021] refer to Figure 6 The stacked packaging structure of the present invention mainly includes: a substrate 1, a first chip 2, a thermally conductive insulating layer 3, a second chip 6, and a packaging layer.

[0022] The thermally conductive insulating layer 3 is disposed on the first chip 2 and adopts a unique "sandwich + sidewall" composite structure, specifically including: First insulating layer 31: disposed on the surface of the first chip 2, serving as the bottom electrical insulating layer.

[0023] First thermally conductive layer 32: disposed on the first insulating layer 31, serving as a highly efficient thermally conductive channel in the horizontal direction.

[0024] The second insulating layer 33 is disposed on the first thermally conductive layer 32 as a top electrical insulating layer, protecting the first thermally conductive layer 32 and preventing unnecessary electrical contact with the second chip 6.

[0025] Through-slot 4: Vertically penetrates the first insulating layer 31, the first thermally conductive layer 32 and the second insulating layer 33, providing space for the electrical connection of the second chip 6.

[0026] The second heat-conducting layer 34 is disposed on the side wall of the through groove 4 and is directly connected to the first heat-conducting layer 32 to form a vertical heat-conducting channel.

[0027] The heat generated by the second chip 6 is first transferred to the second thermally conductive layer 34 in contact with it through its conductive pad 61. Since the second thermally conductive layer 34 is directly connected to the horizontal first thermally conductive layer 32, the heat can quickly change from the vertical direction to the horizontal direction, and then diffuse laterally through the first thermally conductive layer 32, and finally be conducted to the entire package structure or dissipated through subsequent heat dissipation structures such as the package layer or external heat sink.

[0028] By providing a first insulating layer 31 and a second insulating layer 33, the highly thermally conductive metal layer 32 is completely encased in insulating material. This ensures that even within the limited space of the chip stack, the highly thermally conductive channels will not short-circuit with chips 2, 6 or conductive pad 61.

[0029] The conductive pad 61 of the second chip 6 is not only used for electrical interconnection, but its side also has a large contact area with the second heat-conducting layer 34 on the side wall of the through slot 4, which increases the heat conduction area from the chip to the heat dissipation structure and further improves the heat dissipation efficiency.

[0030] In a preferred embodiment, the thickness of the first insulating layer 31 is 0.5-2 micrometers, the thickness of the first thermally conductive layer 32 is 0.2-5 micrometers, the thickness of the second insulating layer 33 is 0.5-2 micrometers, and the thickness of the second thermally conductive layer 34 is 0.2-1 micrometer. The first insulating layer 31 and the second insulating layer 33 are preferably made of high dielectric strength and high thermal conductivity ceramic materials such as alumina (Al2O3), aluminum nitride (AlN), or silicon dioxide (SiO2). The first thermally conductive layer 32 and the second thermally conductive layer 34 are preferably made of highly conductive and highly thermally conductive metals such as aluminum or copper, or doped thermally conductive films formed by ion implantation.

[0031] This invention also provides a method for forming the above-mentioned stacked packaging structure. The process steps will be described in detail below through a specific embodiment.

[0032] Example 1

[0033] Step 1, as follows Figure 1 As shown, a substrate 1 is provided, which can be a printed circuit board (PCB) with interconnect lines or a silicon interposer. A first chip 2 is mounted and electrically connected to the substrate 1 using a chip mounting process. This step can employ conventional flip-chip or wire bonding techniques to fix and interconnect the bottom chip.

[0034] Step 2, as follows Figure 2 As shown, it includes the following steps.

[0035] Step 2.1: Deposit the first insulating layer 31 A layer of silicon dioxide (SiO2) with a thickness of 0.5-2 micrometers is deposited on the surface of the first chip 2 using low-temperature deposition processes such as plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD). The deposition temperature is controlled at 200-400℃ to avoid thermal damage to the mounted first chip 2.

[0036] Step 2.2: Form the first thermally conductive layer 32 The SiO2 material deposited in step 2.1 underwent its first ion implantation. The implanted ions were copper (Cu⁺), silver (Ag⁺), or zinc (Zn⁺), with an implantation dose of 1 × 10¹. 5 Up to 1×10¹ 6 The implantation energy is 30-100 keV, with a diameter of cm⁻². In this step, high-energy metal ions are implanted to a specific depth in the SiO₂ layer, forming a highly doped "implanted layer". Subsequently, annealing is performed at 200-400℃ under a nitrogen (N₂) atmosphere. During annealing, the implanted metal ions diffuse, aggregate, and crystallize, forming metal or alloy nanoparticles with a diameter of several nanometers, such as Cu-Zn alloys, within the SiO₂ matrix.

[0037] Metal nanoparticles form a highly thermally conductive "nanohighway" within an insulating SiO2 matrix. Since the thermal conductivity of the metal nanoparticles is much higher than that of SiO2, a first thermally conductive layer 32 is formed. The unimplanted underlying SiO2 naturally forms the first insulating layer 31.

[0038] Step 2.3: Deposit the second insulating layer 33 On the first thermally conductive layer 32, a layer of SiO2 material with a thickness of 0.5-2 micrometers is deposited again by PECVD or ALD process to form a second insulating layer 33, which completely encapsulates the highly thermally conductive metal nanoparticle layer.

[0039] Step 3: Form the through groove 4 and the second heat-conducting layer 34 Step 3.1: Forming a through groove Using photolithography and dry etching processes, an opening perpendicular to the three layers, forming a through-hole 4, is etched into the multilayer structure consisting of a first insulating layer 31, a first thermally conductive layer 32, and a second insulating layer 33. The etching process needs to be precisely controlled to ensure that the sidewalls of the through-hole 4 are exposed to the end face of the first thermally conductive layer 32.

[0040] Step 3.2: Forming the second thermally conductive layer A second ion implantation was performed on the sidewall of through-hole 4. The implantation conditions were similar to the first, with Cu⁺, Ag⁺, or Zn⁺ ions implanted at a dose of 1 × 10¹. 5 Up to 1×10¹ 6 The ions are heated to cm⁻², with an energy of 30-100 keV, and annealed at 200-400℃ under a N₂ atmosphere. In this step, high-energy ions are injected in a direction perpendicular to the sidewall, forming a second thermally conductive layer 34 reinforced with nanoparticles in the SiO₂ of the sidewall of the through-groove 4.

[0041] Since the sidewall of the through groove 4 is in direct contact with the end face of the first thermally conductive layer 32, the second thermally conductive layer 34 formed by the second ion implantation will be seamlessly connected with the first thermally conductive layer 32 in terms of both physics and thermality, together forming a continuous, low thermal resistance thermally conductive network from the vertical direction to the horizontal direction.

[0042] Step 4: Install the second chip A second chip 6 with a conductive pad 61 is provided. The second chip 6 is mounted onto the thermally conductive insulating layer 3 using thermosetting bonding or reflow soldering. During mounting, precise alignment ensures that the conductive pad 61 of the second chip 6 is located within the through-groove 4. The conductive pad 61 forms a large-area physical contact with the second thermally conductive layer 34 on the sidewall of the through-groove 4, while the bottom of the conductive pad 61 is electrically connected to the corresponding pad on the first chip 2 via conductive adhesive or direct bonding. This step simultaneously completes the electrical interconnection of the second chip 6 and establishes an efficient heat conduction path.

[0043] Step 5: Forming the encapsulation layer Finally, an encapsulation layer is formed covering the entire structure to provide mechanical protection and environmental reliability. In a preferred embodiment, the encapsulation layer includes a first molding layer 5 and a second molding layer 7. First, the first molding layer 5 is formed by a molding process to fill the gap between the substrate 1 and the first chip 2, and to cover the sidewalls of the substrate 1 and the first chip 2. Then, the second molding layer 7 is formed to cover the first chip 2, the thermally conductive insulating layer 3, and the second chip 6, completing the overall encapsulation.

[0044] Example 2

[0045] Compared with Example 1, this example mainly forms a first insulating layer 31, a first thermally conductive layer 32, and a second insulating layer 33 through a deposition process, and then forms a through-groove 4 by etching, and then deposits a second thermally conductive layer 34.

[0046] In summary, the stacked packaging structure and its formation method provided by this invention, by designing a composite insulating structure including a horizontal thermal conductive layer and a vertical thermal conductive layer, and combining it with an innovative ion implantation process, constructs an efficient heat dissipation path for stacked chips within a limited space, effectively solving the thermal management problem in 3D packaging, and significantly improving the reliability and performance of the product.

[0047] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A stacked packaging structure, characterized in that, include: A substrate (1) on which a first chip (2) is mounted; A thermally conductive insulating layer (3) is disposed on the first chip (2) and has a through groove (4) thereon. It includes a first insulating layer (31), a first thermally conductive layer (32) and a second insulating layer (33) stacked sequentially in the direction away from the first chip (2), and a second thermally conductive layer (34) disposed on the side wall of the through groove (4) and connected to the first thermally conductive layer (32). The second chip (6) is provided with a conductive disk (61), which is disposed in the through groove (4) and is connected to both the second heat-conducting layer (34) and the first chip (2); An encapsulation layer is provided to cover the substrate (1), the first chip (2), the thermally conductive insulating layer (3), and the second chip (6).

2. The stacked packaging structure according to claim 1, characterized in that, The thickness of the first insulating layer (31) is 0.5-2 micrometers, the thickness of the first thermally conductive layer (32) is 0.2-5 micrometers, and the thickness of the second insulating layer (33) is 0.5-2 micrometers.

3. The stacked packaging structure according to claim 1, characterized in that, The height of the second thermally conductive layer (34) is equal to the sum of the thicknesses of the first insulating layer (31), the first thermally conductive layer (32), and the second insulating layer (33), and the thickness of the second thermally conductive layer (34) is 0.2-1 micrometer.

4. The stacked packaging structure according to claim 1, characterized in that, The first insulating layer (31) and the second insulating layer (33) are made of aluminum oxide, aluminum nitride or silicon dioxide.

5. The stacked packaging structure according to claim 1, characterized in that, The first thermal conductive layer (32) and the second thermal conductive layer (34) are made of aluminum or copper or doped thermal conductive film.

6. The stacked packaging structure according to claim 1, characterized in that, The encapsulation layer includes a first molding layer (5) disposed on the sidewalls of the substrate (1) and the first chip (2), and a first molding layer (7) covering the first chip (2), the thermally conductive insulating layer (3), and the second chip (6).

7. A method for forming a stacked packaging structure according to any one of claims 1-6, characterized in that, Includes the following steps: The first chip (2) is mounted on the substrate (1); A first insulating layer (31), a first thermally conductive layer (32), and a second insulating layer (33) are formed on the first chip (2) in sequence. A through groove (4) is formed that penetrates the first insulating layer (31), the first heat-conducting layer (32), and the second insulating layer (33), and a second heat-conducting layer (34) is formed on the side wall of the through groove (4) and connected to the first heat-conducting layer (32). The second chip (6) with a conductive disk (61) is installed, the conductive disk (61) is placed in the through groove (4), and is connected to both the second heat-conducting layer (34) and the first chip (2); An encapsulation layer is formed covering the substrate (1), the first chip (2), the thermally conductive insulating layer (3), and the second chip (6).

8. The forming method according to claim 7, characterized in that, A first insulating layer (31), a first thermally conductive layer (32), a second insulating layer (33), and a second thermally conductive layer (34) are formed by a deposition process.

9. The forming method according to claim 7, characterized in that, The steps of forming the first insulating layer (31), the first thermally conductive layer (32), and the second insulating layer (33) include: Deposit a layer of silicon dioxide material; A first implantation layer is formed by ion implantation of silicon dioxide material. The first implantation layer constitutes a first thermally conductive layer (32), and a first insulating layer (31) is formed below the implantation layer. A second insulating layer (33) is formed by depositing silicon dioxide material on the first thermally conductive layer (32). The steps for forming the second thermally conductive layer (34) include: A second ion implantation is performed through the sidewall of the through-groove (4) to form a second implantation layer, which constitutes a second thermally conductive layer (34).

10. The forming method according to claim 9, characterized in that, The process conditions for the first and second ion implantations are as follows: The implanted ions are Cu⁺, Ag⁺, or Zn⁺, and the implantation dose is 1×10¹⁵ - 1×10¹⁵. 6 cm⁻², Injection energy: 30-100 keV, annealing at 200-400℃ under N2 atmosphere.

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