An addressable sensitive amplifier test circuit based on voltage follower

Abstract

The application relates to a voltage follower-based addressable sensitive amplifier test circuit, which comprises: a sensitive amplifier array to be tested, the array comprising a plurality of sensitive amplifiers to be tested; an addressing circuit for providing an address signal to select a target sensitive amplifier; a switch selection circuit connected between the sensitive amplifier array to be tested and an external test node, controlled by the addressing circuit, for coupling the signal of the external test node to the selected sensitive amplifier; and a voltage follower module with an input end connected to the switch selection circuit, for transmitting the test voltage output by the switch selection circuit to the corresponding end of the selected sensitive amplifier. The application can realize efficient and accurate SA performance testing. The node voltage curve is only affected by the gain of the operational amplifier, and the design open-loop gain is above 60 dB, so that an error below 0.1% can be realized.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing, and in particular to a test circuit for an addressable sensitive amplifier based on a voltage follower. Background Technology

[0002] With the continuous advancement of semiconductor process technology, especially the shrinking of technology nodes, the impact of process variations on circuit performance has become increasingly significant. In the design of memory circuits such as DRAM and SRAM, the Sensing Amplifier (SA), as a core component, is responsible for amplifying the weak voltage signals in the memory cells. Its performance stability is crucial for the read and write operations of the memory circuit array. However, process variations, such as mask alignment errors, changes in doping concentration, and temperature fluctuations, can lead to problems such as inconsistent SA gain, increased distortion, and input bias voltage drift, severely affecting its performance in practical applications. To address these challenges, establishing statistical modeling of the SA is particularly important. By statistically modeling the performance of the SA under different process variation conditions, its performance fluctuations can be predicted more accurately, providing quantitative optimization schemes for the design. This model not only helps designers identify patterns in performance changes but also provides a theoretical basis for subsequent process adjustments and reliability assurance. As the impact of process variations on performance gradually increases, traditional circuit testing methods often struggle to comprehensively cover all possible process variations. Therefore, addressable test circuit technology can effectively integrate the SA into the test circuit and conduct systematic evaluation through large-scale experiments. This method can test the performance variations of the SA (Standard Instrument) under various process conditions, providing more reliable performance assurance for memory circuit design. By integrating the SA into the addressable test circuit, not only can testing efficiency be significantly improved, but the operating characteristics of the SA under different process fluctuations can also be analyzed in depth, providing data support for the optimization of future memory circuit designs. This ensures the performance and stability of the SA while improving the reliability of memory devices.

[0003] Traditional addressable test peripheral circuits can achieve high-throughput SA testing. However, the transmission gate is directly connected to the SA, and its equivalent resistance during conduction causes a drop in the SA's node voltage, resulting in a distorted butterfly curve. Consequently, the measured static noise margin (SNM) cannot accurately reflect the SA's true performance. A technique is urgently needed to address the inaccuracy of SNM caused by the voltage drop generated by the transmission gate during butterfly curve scanning. Summary of the Invention

[0004] This invention provides a voltage follower-based addressable sensitive amplifier test circuit. This addressable test circuit can significantly reduce the equivalent resistance of the transmission gate in the switching circuit, making voltage transmission virtually lossless, thereby ensuring the accuracy of the measured butterfly curve results.

[0005] To achieve the above objectives, the technical solution of the present invention includes:

[0006] A voltage follower-based addressable sensitive amplifier test circuit includes:

[0007] A sensitive amplifier array under test, the array comprising multiple sensitive amplifiers under test;

[0008] Addressing circuitry is used to provide an address signal to select the target sensitive amplifier;

[0009] A switch selection circuit, connected between the sensitive amplifier array under test and the external test node, is controlled by the addressing circuit and is used to couple the signal from the external test node to the selected sensitive amplifier.

[0010] A voltage follower module, whose input is connected to the switch selection circuit, is used to transmit the test voltage output by the switch selection circuit to the corresponding terminal of the selected sensitive amplifier.

[0011] A further improvement of the present invention is that the voltage follower module includes an operational amplifier, the output terminal of the operational amplifier is connected to its inverting input terminal to form a negative feedback structure, the non-inverting input terminal of the operational amplifier is used to receive the input test voltage, and its output terminal is used to connect to a sensitive amplifier.

[0012] A further improvement of the present invention is that the sensitive amplifier includes a bit line terminal BL, a complementary bit line terminal BLB, a high-potential side control terminal PCS, and a low-potential side control terminal NCS.

[0013] A further improvement of the present invention is that the number of switch selection circuits is three; wherein:

[0014] The output of the switching circuit used for coupling the BL signal couples the BL signal to the bit line terminal BL of the sensitive amplifier through the voltage follower module.

[0015] Each output terminal of the switching circuit used for coupling the BLB signal is connected to the corresponding complementary bit line terminal (BLB) of the sensitive amplifier.

[0016] Each output terminal of the switching circuit used to couple the PCS signal is connected to the corresponding high-potential side control terminal PCS of the sensitive amplifier.

[0017] A further improvement of the present invention is that the low-potential side control terminals (NCS) of all the sensitive amplifiers in the array of sensitive amplifiers under test are all connected together, and configured such that when the target sensitive amplifier is selected, the remaining unselected sensitive amplifiers are in a turned-off state.

[0018] A further improvement of the present invention is that the row address width of the addressing circuit is M and the column address width is N, and it is configured to be able to address multiple sensitive amplifiers for testing.

[0019] A further improvement of the present invention is that the array of sensitive amplifiers under test is composed of sensitive amplifiers of the same type or a mixture of sensitive amplifiers of different types.

[0020] Compared with the prior art, the beneficial effects of the present invention include:

[0021] 1) This invention enables efficient and accurate SA performance testing. The node voltage curve is only affected by the operational amplifier gain, and an error of less than 0.1% can be achieved by designing an open-loop gain of over 60dB.

[0022] 2) This invention provides a circuit that allows for large-scale testing of different types of SAs and supports direct performance comparison between different types of SAs. Attached Figure Description

[0023] Figure 1 This is an architecture diagram of a voltage follower-based addressable sensitive amplifier test circuit.

[0024] Figure 2 This is a schematic diagram showing the connection between the voltage follower module and the sensitive amplifier. Detailed Implementation

[0025] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are based on the technical solution of the present invention and provide detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0026] like Figure 1 As shown, an embodiment of the present invention provides a voltage follower-based addressable sensitive amplifier test circuit, which includes:

[0027] The array of sensitive amplifiers under test includes multiple sensitive amplifiers (SAs) under test; each sensitive amplifier (SA) has a bit line output (BL), a complementary bit line output (BLB), a high-level side drive control terminal (PCS) (P-channel Control Signal Output / Pull-up Control), and a low-level side drive control terminal (NCS) (N-channel Control Signal / Pull-down Control).

[0028] An addressing circuit is used to provide an address signal to select the target sensitive amplifier. In this embodiment, the row address width of the addressing circuit is M, and the column address width is N, configured to address multiple sensitive amplifiers for testing. The row addressing circuit and the column addressing circuit together generate an addressing strobe signal, the addressing strobe signal having a width of 2. N+M With the help of the switch selection circuit, it can select 2 N +M SA test.

[0029] A switch selection circuit, connected between the array of sensitive amplifiers under test and the external test node, is controlled by the addressing circuit and couples the external test signal to the selected sensitive amplifier (SA).

[0030] like Figure 2 As shown, the input of the voltage follower module is connected to the switch selection circuit to transmit the input test voltage to the input of the selected target sensitive amplifier. The voltage follower module includes an operational amplifier, the output of which is connected to its inverting input to form a negative feedback structure, and the non-inverting input of which receives the input test voltage.

[0031] The sensitive amplifier includes a bit line terminal BL, a complementary bit line terminal BLB, a high-potential side control terminal PCS, and a low-potential side control terminal NCS. In this embodiment, there are three switch selection circuits, all controlled by addressing gating signals. The output of the switch circuit used to couple the BL signal couples the BL signal to the bit line terminal BL of the sensitive amplifier through the voltage follower module; each output of the switch circuit used to couple the BLB signal is connected to the corresponding complementary bit line terminal BLB of the sensitive amplifier; each output of the switch circuit used to couple the PCS signal is connected to the corresponding high-potential side control terminal PCS of the sensitive amplifier.

[0032] The low-potential side control terminals (NCS) of all the sensitive amplifiers in the array under test are connected together, and configured such that when the target sensitive amplifier is selected, the remaining unselected sensitive amplifiers are in the off state.

[0033] Please see the appendix Figure 2 The voltage follower module's output voltage is essentially equal to its input voltage, with a very low output impedance and a very high input impedance. Let the open-loop gain of the operational amplifier be A. From the following formula, we can see that ΔV is independent of the DUT current, resulting in a more stable voltage. This ensures that despite a large current in the path, there is virtually no voltage drop. Because of the high input resistance, the transmission gate connected to the input of the voltage follower will not produce a voltage drop. Therefore, it can be ensured that regardless of the current of the unit under test, the transmitted signal will not experience a significant voltage drop, thus preventing distortion of the butterfly curve due to voltage drop.

[0034]

[0035]

[0036] The array of sensitive amplifiers under test (DUTs) consists of either the same type of sensitive amplifiers or a mixture of different types. Due to varying currents, different DUTs exhibit different voltage drops. Traditional connection methods are no longer suitable when testing multiple different types of sensitive amplifiers simultaneously. Addressable test circuits employing voltage follower structures ensure that the Q-drop is unaffected by the performance of the DUT, thus maintaining a relatively consistent voltage drop even when different DUTs are placed in the same array.

[0037] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A voltage follower based addressable sense amplifier test circuit, characterized by, include: A sensitive amplifier array under test, the array comprising multiple sensitive amplifiers under test; Addressing circuitry is used to provide an address signal to select the target sensitive amplifier; A switch selection circuit, connected between the sensitive amplifier array under test and the external test node, is controlled by the addressing circuit and is used to couple the signal from the external test node to the selected sensitive amplifier. A voltage follower module, whose input is connected to the switch selection circuit, is used to transmit the test voltage output by the switch selection circuit to the corresponding terminal of the selected sensitive amplifier.

2. The voltage follower based addressable sense amplifier test circuit of claim 1, wherein, The voltage follower module includes an operational amplifier, the output of which is connected to its inverting input to form a negative feedback structure, the non-inverting input of which is used to receive the input test voltage, and its output is used to connect to a sensitive amplifier.

3. The voltage follower based addressable sense amplifier test circuit of claim 1, wherein, The sensitive amplifier includes a bit line terminal BL, a complementary bit line terminal BLB, a high-potential side control terminal PCS, and a low-potential side control terminal NCS.

4. The voltage follower based addressable sense amplifier test circuit of claim 3, wherein, The number of switch selection circuits is three; among which: The output of the switching circuit used for coupling the BL signal couples the BL signal to the bit line terminal BL of the sensitive amplifier through the voltage follower module. Each output terminal of the switching circuit used for coupling the BLB signal is connected to the corresponding complementary bit line terminal (BLB) of the sensitive amplifier. Each output terminal of the switching circuit used to couple the PCS signal is connected to the corresponding high-potential side control terminal PCS of the sensitive amplifier.

5. The voltage follower based addressable sense amplifier test circuit of claim 3, wherein, The low-potential side control terminals (NCS) of all the sensitive amplifiers in the array under test are connected together, configured such that when the target sensitive amplifier is selected, the remaining unselected sensitive amplifiers are in a turned-off state.

6. The voltage follower based addressable sense amplifier test circuit of claim 1, wherein, The addressing circuit has a row address width of M and a column address width of N, and is configured to addressably connect to multiple sensitive amplifiers for testing.

7. The voltage follower based addressable sense amplifier test circuit of claim 1, wherein, The array of sensitive amplifiers under test consists of sensitive amplifiers of the same type or a mixture of sensitive amplifiers of different types.

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