Method, device, computer device, medium and product for distributing voltage bias of a josephson junction array

Abstract

The application relates to a voltage bias distribution method and device of a Josephson junction array, a computer device, a medium and a product. The method comprises the following steps: determining an equal ratio sub-sequence in a Josephson junction array sequence as a standard progress sequence, and determining a remaining sequence as a non-standard sequence; distributing the bias state of a standard Josephson junction in each Josephson junction array by a corresponding progress algorithm for the Josephson junction array belonging to the standard progress sequence; distributing the bias state of each non-standard Josephson junction in each Josephson junction array by an iterative greedy algorithm for the Josephson junction array belonging to the non-standard sequence; calculating a microwave frequency for compensating a residual error according to the bias state of the standard Josephson junction and the bias state of the non-standard Josephson junction; and driving the Josephson junction array by the microwave frequency, so that the output voltage of the Josephson junction array is equal to a preset target voltage. The application can improve the bias configuration efficiency of the Josephson junction.

Description

Technical Field

[0001] This application relates to the field of superconducting technology, and in particular to a method, apparatus, computer device, medium, and product for distributing voltage bias of a Josephson array. Background Technology

[0002] Quantum voltage synthesis technology is the core means of establishing and maintaining international voltage standards, and its physical basis is the Josephson effect. The Josephson effect is a macroscopic quantum effect that refers to the phenomenon where, when two superconductors are coupled through an extremely thin insulating layer, a normal metal, or a weak connection, superconducting electron pairs can undergo quantum tunneling, resulting in a special superconducting current. This effect occurs in a structure called a "Josephson junction," which typically consists of two superconductors connected by a thin insulating layer, a short section of normal metal, or other forms of weak connection.

[0003] In Josephson junctions, bias configuration refers to applying a DC current or voltage to the junction. Its core function is to control the operating state of the Josephson junction, placing it in a specific operating region where macroscopic quantum effects can be observed or utilized. Bias configuration is a necessary means to activate, control, and read out the macroscopic quantum behavior in Josephson junctions, and is widely used in quantum computing, quantum metrology, and fundamental physics research. Traditional bias state solutions mainly include three methods, each tailored to different junction structures and application requirements, but all have their limitations:

[0004] The first method is a deterministic fast algorithm based on specific number system mathematical principles. This method is specifically designed for cases where the array sequence contains strictly geometric subsequences (such as binary or ternary), and can efficiently calculate the bias state. Its drawback is that it heavily relies on the ideal mathematical structure of the sequence. When the actual array deviates from the perfect geometric relationship due to manufacturing or design factors, the algorithm will produce significant deviations and cannot guarantee obtaining the globally optimal solution.

[0005] The second method is a precise optimization algorithm based on global search, which aims to theoretically find the globally optimal bias combination without requiring the sequence to have a regular structure. The simplest and most commonly used method is the enumeration-indexing algorithm, which traverses all 3m (m represents the number of arrays, m>30) possible bias combinations and selects the one with the smallest error. This method has a high computational cost, and for large-scale arrays, its worst-case computational complexity is very high, making it difficult to meet the requirements of real-time, high-frequency voltage synthesis.

[0006] The third method is a heuristic approximation algorithm for non-ideal, irregular array sequences, aiming to balance computational efficiency and synthesis accuracy in engineering practice. This algorithm does not presuppose the sequence structure and can quickly obtain an approximately optimal bias configuration. Its disadvantage is that, as a general method, it fails to automatically identify and utilize the characteristics of standard geometric subsequences that may exist in the sequence, and therefore cannot achieve the theoretically highest efficiency on arrays with regular structures.

[0007] Therefore, there is an urgent need to propose a voltage bias allocation method for Josephson arrays, which can meet the configuration requirements of different types of Josephson arrays and improve applicability, while also improving the configuration efficiency of the bias. Summary of the Invention

[0008] Therefore, it is necessary to provide a method, apparatus, computer equipment, medium, and product for distributing the voltage bias of a Josephson array that has broad applicability and can improve the bias configuration efficiency of Josephson junctions, in order to address the above-mentioned technical problems.

[0009] In a first aspect, this application provides a method for allocating the voltage bias of a Josephson array, the method comprising:

[0010] The geometric subsequences in the Josephson array sequence are identified as standard base sequences, and the remaining sequences in the Josephson array sequence are identified as non-standard sequences.

[0011] For Josephson junction matrices belonging to the standard base sequence, the bias state of the standard Josephson junctions in each Josephson junction matrix is ​​allocated by the corresponding base algorithm;

[0012] For Josephson node matrices that belong to non-standard sequences, the bias state of each non-standard Josephson node in each Josephson node matrix is ​​allocated by an iterative greedy algorithm.

[0013] Calculate the microwave frequency used to compensate for the residual based on the bias states of the standard Josephson junction and the non-standard Josephson junction.

[0014] The Josephson array is driven by the microwave frequency so that the output voltage of the Josephson array is equal to the preset target voltage.

[0015] In one embodiment, the standard radix sequence includes a standard binary sequence and a standard ternary sequence; the pair of Josephson junction matrices belonging to the standard radix sequence are assigned the bias state of the standard Josephson junctions in each Josephson junction matrix using a corresponding radix algorithm, including:

[0016] For standard Josephson nodes belonging to the standard binary sequence, the bias state of the standard Josephson nodes in each Josephson node matrix is ​​assigned using a binary algorithm;

[0017] For standard Josephson nodes belonging to the standard ternary sequence, the bias state of the standard Josephson nodes in each Josephson node matrix is ​​allocated by the balanced ternary algorithm.

[0018] In one embodiment, the calculation of the microwave frequency for compensating the residual based on the bias states of the standard Josephson junction and the non-standard Josephson junction includes:

[0019] The residual of the Josephson node array sequence is determined based on the number of Josephson nodes that have been assigned the bias state.

[0020] The microwave frequency used to compensate for this residual is calculated using the following formula:

[0021]

[0022] in, This represents the summation number of the Josephson array. This represents the residual. This indicates the initial drive frequency.

[0023] In one embodiment, the pair of Josephson node matrices belonging to a non-standard sequence is configured with an iterative greedy algorithm to allocate the bias state of each non-standard Josephson node in each Josephson node matrix, including:

[0024] Based on the number of non-standard Josephson nodes in each Josephson node array, the Josephson node arrays belonging to the non-standard sequence are sorted in descending order;

[0025] Following the descending order, each Josephson node in the non-standard sequence is traversed sequentially, and the non-standard Josephson nodes in the corresponding Josephson node array are biased according to the preset rules.

[0026] In one embodiment, the biasing of non-standard Josephson nodes in the corresponding Josephson node array according to a preset rule includes:

[0027] Calculate the summation number of non-standard Josephson nodes in the Josephson node array, and determine this summation number as the initial residual error;

[0028] If the absolute value of the remaining error is greater than or equal to half the number of nodes in the current Josephson array, assign an offset with the same sign as the current remaining error to each non-standard Josephson node in the current Josephson array; otherwise, assign a 0 offset to each non-standard Josephson node in the current Josephson array.

[0029] In one embodiment, the method further includes:

[0030] The remaining error is updated using the following formula:

[0031]

[0032] in, This represents the remaining error from the previous iteration update. This is represented by the bias of the non-standard Josephson nodes assigned in the current Josephson node array. This represents the current node segment.

[0033] Secondly, this application also provides a voltage biasing distribution device for a Josephson array, the device comprising:

[0034] The classification module is used to identify the geometric subsequences in the Josephson array sequence as standard base sequences and the remaining sequences in the Josephson array sequence as non-standard base sequences.

[0035] The first allocation module is used to allocate the bias state of the standard Josephson nodes in each Josephson node matrix that belongs to the standard base sequence, using the corresponding base algorithm.

[0036] The second allocation module is used to allocate the bias state of each non-standard Josephson node in each Josephson node matrix to the non-standard sequence through an iterative greedy algorithm.

[0037] The calculation module is used to calculate the microwave frequency for compensating the residual based on the bias state of the standard Josephson junction and the bias state of the non-standard Josephson junction.

[0038] The driving module is used to drive the Josephson array at the microwave frequency so that the output voltage of the Josephson array is equal to the preset target voltage.

[0039] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0040] The geometric subsequences in the Josephson array sequence are identified as standard base sequences, and the remaining sequences in the Josephson array sequence are identified as non-standard sequences.

[0041] For Josephson junction matrices belonging to the standard base sequence, the bias state of the standard Josephson junctions in each Josephson junction matrix is ​​allocated by the corresponding base algorithm;

[0042] For Josephson node matrices that belong to non-standard sequences, the bias state of each non-standard Josephson node in each Josephson node matrix is ​​allocated by an iterative greedy algorithm.

[0043] Calculate the microwave frequency used to compensate for the residual based on the bias states of the standard Josephson junction and the non-standard Josephson junction.

[0044] The Josephson array is driven by the microwave frequency so that the output voltage of the Josephson array is equal to the preset target voltage.

[0045] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0046] The geometric subsequences in the Josephson array sequence are identified as standard base sequences, and the remaining sequences in the Josephson array sequence are identified as non-standard sequences.

[0047] For Josephson junction matrices belonging to the standard base sequence, the bias state of the standard Josephson junctions in each Josephson junction matrix is ​​allocated by the corresponding base algorithm;

[0048] For Josephson node matrices that belong to non-standard sequences, the bias state of each non-standard Josephson node in each Josephson node matrix is ​​allocated by an iterative greedy algorithm.

[0049] Calculate the microwave frequency used to compensate for the residual based on the bias states of the standard Josephson junction and the non-standard Josephson junction.

[0050] The Josephson array is driven by the microwave frequency so that the output voltage of the Josephson array is equal to the preset target voltage.

[0051] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, performs the following steps:

[0052] The geometric subsequences in the Josephson array sequence are identified as standard base sequences, and the remaining sequences in the Josephson array sequence are identified as non-standard sequences.

[0053] For Josephson junction matrices belonging to the standard base sequence, the bias state of the standard Josephson junctions in each Josephson junction matrix is ​​allocated by the corresponding base algorithm;

[0054] For Josephson node matrices that belong to non-standard sequences, the bias state of each non-standard Josephson node in each Josephson node matrix is ​​allocated by an iterative greedy algorithm.

[0055] Calculate the microwave frequency used to compensate for the residual based on the bias states of the standard Josephson junction and the non-standard Josephson junction.

[0056] The Josephson array is driven by the microwave frequency so that the output voltage of the Josephson array is equal to the preset target voltage.

[0057] The aforementioned method, apparatus, computer equipment, medium, and product for allocating voltage bias in Josephson arrays divide the Josephson array sequence into standard radix and non-standard radix sequences. For Josephson arrays belonging to the standard radix sequence, the bias state of the standard Josephson junctions in each Josephson array is allocated using the corresponding radix algorithm. For Josephson arrays belonging to the non-standard radix sequence, the bias state of each non-standard Josephson junction in each Josephson array is allocated using an iterative greedy algorithm. This ensures that the Josephson array sequence, regardless of the number of junctions it contains, can achieve optimal bias matching. The algorithm assigns the bias state of each Josephson junction in each Josephson junction array, which can improve the applicability of this application to the voltage bias assignment of Josephson junctions. On the other hand, the corresponding base algorithm selected in this application is the fastest configuration method for the voltage bias assignment of Josephson junction arrays in standard base sequences. At the same time, the iterative greedy algorithm selected in this application is also the fastest configuration method for the voltage bias assignment of Josephson junction arrays in non-standard base sequences. Under the premise that the output voltage of the Josephson junction array is equal to the preset target voltage, the voltage bias assignment efficiency of the Josephson junction array can be improved. Attached Figure Description

[0058] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 This is a flowchart illustrating the voltage bias allocation method for a Josephson array in one embodiment.

[0060] Figure 2 This is a flowchart illustrating step 102 in one embodiment;

[0061] Figure 3 This is a flowchart illustrating step 103 in one embodiment;

[0062] Figure 4 This is a structural block diagram of the voltage bias distribution device for a Josephson array in one embodiment;

[0063] Figure 5 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0064] In order to make the objectives, technical solutions and advantages of the present application more clear and understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0065] It should be noted that the terms "first", "second", etc. used in the present application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having" used in the present application and any variations thereof are intended to cover non-exclusive inclusion. The term "plurality" used in the present application refers to two or more.

[0066] In one embodiment, as Figure 1 shown, a method for distributing voltage bias of a Josephson junction array is provided. In this embodiment, this method is exemplified by being applied to a terminal. It can be understood that this method can also be applied to a server, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server. In this embodiment, the method includes the following steps 101 to step 105, where:

[0067] Step 101, determine the geometric subsequence in the Josephson junction array sequence as the standard radix sequence, and determine the remaining sequence in the Josephson junction array sequence as the non-standard sequence.

[0068] It can be understood that the "geometric subsequence" refers to a new sequence formed by extracting several items (not necessarily consecutive) in the original order from a geometric sequence, and this new sequence still maintains the properties of a geometric sequence.

[0069] The purpose of this step is to automatically and accurately analyze the mathematical structure of the Josephson junction array sequence N, identify whether there is a dominant standard geometric subsequence hidden therein, and provide a basis for subsequent algorithm selection. This step is strictly based on the mathematical definition of a geometric sequence: the necessary and sufficient condition for three numbers a, b, c to form a geometric sequence is b 2 = a × c. Specifically, it can be achieved through the following three steps to determine whether the Josephson junction array sequence contains a geometric subsequence:

[0070] The first step is to sort the input Josephson junction array sequence N in ascending order to obtain an ordered sequence S. On this basis, systematically scan all possible number pairs (a, b) in S (where a < b). For each number pair, calculate the theoretical value of the middle term :

[0071]

[0072] Then verify Is it an integer and also present in sequence S? If the verification passes, then confirm (a, b, ...) This forms a geometric triplet with a common ratio of r = b / a. This process records all the "predecessor-successor" relationships found (i.e., "a is the predecessor of b with a common ratio of r").

[0073] The second step, based on the above records, employs a priority search strategy to reconstruct the complete geometric subsequence: starting from the larger numerical nodes in the records, backtracking along the edges with the same common ratio until no predecessor is found, thus determining the starting term of the geometric chain; then, starting from the end of the constructed chain, theoretical calculations are performed and its existence verified based on the common ratio r, thereby expanding the terminating term of the chain. In this way, all mathematically rigorous and as long as possible geometric subsequences G and their common ratio r can be extracted from the sequence.

[0074] The third step is to select the longest subsequence from the generated subsequences as the dominant subsequence G. dominant And calculate its "capacity contribution" η:

[0075]

[0076] The contribution η reflects the proportion of the total number of nodes in the equal-ratio subsequence to the total number of nodes in the entire sequence. A threshold θ is set to 0.2. If η ≥ θ and the common ratio r = 3, the current sequence is classified as a "standard ternary sequence"; if η ≥ θ and r = 2, it is classified as a "standard binary sequence"; if neither of these conditions is met, it is classified as a "non-standard sequence". This type is crucial for driving subsequent algorithm routing.

[0077] This embodiment utilizes the necessary and sufficient condition for a geometric sequence, b 2 =a×c, prioritizes searching and reconstructing the longest geometric subsequence. This method can extract the subsequence of the dominant sequence from physically discontinuous and irregular practical sequences, providing a reliable basis for intelligent routing.

[0078] Step 102: For Josephson nodes belonging to the standard base sequence, the bias state of the standard Josephson nodes in each Josephson node matrix is ​​allocated by the corresponding base algorithm.

[0079] This step acts as an intelligent decision-making layer, automatically matching the sequence with the algorithm based on the sequence type produced in the first stage.

[0080] If the type is "standard ternary sequence", then the routing is to the balanced ternary algorithm to allocate the bias states of the standard Josephson nodes in each Josephson node matrix. Since the sequence has already been sorted in the first stage, it does not need to be re-sorted. Furthermore, since the ternary group has been found through the above steps, it can be directly used in the balanced ternary algorithm without needing to search again. The same applies to binary sequences. If the type is "standard binary sequence", then the routing is to the signed binary algorithm to allocate the bias states of the standard Josephson nodes in each Josephson node matrix.

[0081] Figure 2 This is a flowchart illustrating step 102 in one embodiment. The standard base sequence includes a standard binary sequence and a standard ternary sequence, such as... Figure 2 As shown, the pair of Josephson nodes belonging to the standard base sequence allocates the bias state of the standard Josephson nodes in each Josephson node matrix through the corresponding base algorithm, including the following steps 201 and 202:

[0082] Step 201: For standard Josephson nodes belonging to the standard binary sequence, allocate the bias state of the standard Josephson nodes in each Josephson node array using a binary algorithm.

[0083] Step 202: For standard Josephson nodes belonging to the standard ternary sequence, allocate the bias state of the standard Josephson nodes in each Josephson node matrix using the balanced ternary algorithm.

[0084] Step 103: For Josephson nodes belonging to non-standard sequences, the bias state of each non-standard Josephson node in each Josephson node matrix is ​​assigned by an iterative greedy algorithm.

[0085] In this step, the input includes the target summary number N. target And the entire array sequence N.

[0086] This implementation analyzes the intrinsic structure of the array sequence through preliminary mathematical feature analysis, and dynamically selects and calls the optimal core algorithm that matches it based on the quantization decision results, thereby achieving adaptive optimization of the solution strategy.

[0087] Figure 3 This is a flowchart illustrating step 103 in one embodiment. In this embodiment, as shown... Figure 3 As shown, for this pair of Josephson node matrices belonging to a non-standard sequence, the bias state of each non-standard Josephson node in each Josephson node matrix is ​​allocated through an iterative greedy algorithm, including the following steps 301 and 302:

[0088] Step 301: Arrange the Josephson arrays belonging to the non-standard sequence in descending order according to the number of non-standard Josephson nodes in each Josephson array.

[0089] Specifically, the array sequence N can be sorted in descending order of the number of nodes in each segment to obtain N. desc =[a1,a2,…,a m ].

[0090] Step 302: In descending order, traverse each Josephson node array in the non-standard sequence and assign biases to the non-standard Josephson nodes in the corresponding Josephson node array according to the preset rules.

[0091] In one embodiment, the biasing of non-standard Josephson nodes in the corresponding Josephson node array according to a preset rule includes:

[0092] Calculate the summation number of non-standard Josephson nodes in the Josephson node array, and determine this summation number as the initial residual error;

[0093] If the absolute value of the remaining error is greater than or equal to half the number of nodes in the current Josephson array, assign an offset with the same sign as the current remaining error to each non-standard Josephson node in the current Josephson array; otherwise, assign a 0 offset to each non-standard Josephson node in the current Josephson array.

[0094] Specifically, initialize the residual error R=N target Process N sequentially desc Each node segment a in i The decision rule is: if the absolute value of the current remaining error is not less than a... i If the value is 2, then assign a bias (+1 or -1) with the same sign as R to that segment and update the remaining error R; otherwise, assign a zero bias to that segment. This step allows the algorithm to make a locally optimal choice in each iteration, thereby continuously optimizing the deviation between the current solution and the objective.

[0095] It is understood that in this embodiment, when processing the sorted array of nodes from largest to smallest, the process will proceed if and only if the absolute value of the remaining target value R is not less than the current segment node number a. i When it is half of the value, assign it a non-zero bias.

[0096] Furthermore, the method for allocating the voltage bias of the Josephson array also includes:

[0097] The remaining error is updated using the following formula:

[0098]

[0099] in, This represents the remaining error from the previous iteration update. This is represented by the bias of the non-standard Josephson nodes assigned in the current Josephson node array. This represents the current node segment.

[0100] Step 104: Calculate the microwave frequency used to compensate for the residual based on the bias state of the standard Josephson junction and the bias state of the non-standard Josephson junction.

[0101] In one embodiment, the calculation of the microwave frequency for compensating the residual based on the bias states of the standard Josephson junction and the non-standard Josephson junction includes:

[0102] The residual of the Josephson node array sequence is determined based on the number of Josephson nodes that have been assigned the bias state.

[0103] The microwave frequency used to compensate for this residual is calculated using the following formula:

[0104]

[0105] in, This represents the summation number of the Josephson array. This represents the residual. This indicates the initial drive frequency.

[0106] It is understandable that the algorithm outputs a bias vector s and a final residual error Δ=R. According to the Josephson effect, the array output voltage is proportional to the driving frequency f. Therefore, the residual error of the algorithm can be completely compensated by fine-tuning the microwave frequency.

[0107] Step 105: Drive the Josephson array using the microwave frequency so that the output voltage of the Josephson array is equal to the preset target voltage.

[0108] This step involves using this microwave frequency. Driven by this, the actual output of the array will be exactly equal to the target voltage V. target This enables low-error voltage synthesis.

[0109] The voltage bias allocation method for Josephson arrays proposed in this embodiment divides the Josephson array sequence into standard radix and non-standard radix sequences. For Josephson arrays belonging to the standard radix sequence, the bias state of the standard Josephson junctions in each Josephson array is allocated using the corresponding radix algorithm. For Josephson arrays belonging to the non-standard radix sequence, the bias state of each non-standard Josephson junction in each Josephson array is allocated using an iterative greedy algorithm. This ensures that regardless of the number of junctions in the Josephson array sequence, the optimal algorithm can be matched to allocate the bias state of each junction. The bias state of each Josephson junction in the Josephson array can improve the applicability of the voltage bias allocation of Josephson junctions in this application. On the other hand, the corresponding base algorithm selected in this application is the fastest configuration method for voltage bias allocation of Josephson array in standard base sequence. At the same time, the iterative greedy algorithm selected in this application is also the fastest configuration method for voltage bias allocation of Josephson array in non-standard base sequence. Under the premise that the output voltage of Josephson array is equal to the preset target voltage, the allocation efficiency of voltage bias of Josephson array can be improved.

[0110] The following section provides an achievable scenario based on the voltage bias allocation method for the Josephson array proposed in this embodiment. Combining specific data, a complete bias state solution example is calculated step by step to illustrate the implementation method and effect of this algorithm.

[0111] Input the target voltage and parameters. For ease of comparison, the same target summary number N as the one used in the literature on the 2V Josephson array sequence from the National Institute of Metrology of China is adopted. target =45999. Let Josephson's constant K be... J Given that the initial driving frequency f is known, the following conditions are met:

[0112]

[0113] in, This represents the target total number, and the target voltage can be calculated using this formula. .

[0114] Array Sequence: The Josephson array sequence m in the document "2V Josephson Array Sequence of the National Institute of Metrology of China" includes 16 sub-arrays, and its array N is:

[0115] N=[4,8748,2916,5832,972,7828,8476,324,108,8748,8748,36,12,8748,8748,4].

[0116] After obtaining the Josephson junction array sequence N, automatically analyze the mathematical structure of the sequence N to identify whether it contains a standard geometric subsequence. The specific analysis method includes the following steps S1.1 and step S1.2, where:

[0117] Step S1.1: Sorting and scanning.

[0118] First, arrange the sequence N in ascending order of the junction values to obtain an ordered sequence S:

[0119] S = [4, 4, 12, 36, 108, 324, 972, 2916, 5832, 7828, 8476, 8748, 8748, 8748, 8748, 8748]

[0120] Subsequently, systematically scan all pairs of numbers (a, b) in S (where a < b), and according to the necessary and sufficient condition of the geometric sequence b 2 = a × c, find whether the integer c is also in S.

[0121] For example, take a = 4, b = 12, and calculate c theory = b 2 / a = 144 / 4 = 36. Checking reveals that 36 ∈ S, so it is confirmed that (4, 12, 36) forms a geometric triple with a common ratio r = b / a = 3. Record "4 is the predecessor of 12 with a common ratio of 3".

[0122] Continuing the scan, it can be found that (12, 36, 108), (36, 108, 324), (108, 324, 972), (324, 972, 2916), (972, 2916, 8748) all meet the conditions, and the common ratio is 3.

[0123] Step S1.2: Reconstruct the geometric subsequence.

[0124] Based on the relationships recorded in step S1.1, start backtracking from the maximum value node and expand forward. Starting from "8748", according to the record, its predecessor is "2916", and then tracing the predecessor of "2916" is "972", until backtracking to the starting term "4". Then starting from the end "8748" of this chain "4, 12, 36, 108, 324, 972, 2916, 8748", calculate 8748 × 3 = 26244, but 26244 ∉ S, so the chain terminates.

[0125] Thus, extract the longest geometric subsequence G dominant as:

[0126] G dominant = [4, 12, 36, 108, 324, 972, 2916, 8748]

[0127] Its common ratio r = 3.

[0128] Then, the algorithm's intelligent dynamic routing is solved. Since the Josephson node array sequence contains a ternary sequence, it automatically routes to the bias state of the standard Josephson nodes in each Josephson node array allocated by the balanced ternary method.

[0129] For the remaining sequences in sequence N, the bias state of each non-standard Josephson node in each Josephson node array is allocated by the improved greedy algorithm in this embodiment.

[0130] Specifically, for the target number N received in this stage target Given 45999 and the original sequence N, perform the following steps: S3.1, S3.2, and S3.3. Where:

[0131] Step S3.1: Preprocessing and sorting.

[0132] Sort the array sequence N in descending order of the number of nodes to obtain N desc :

[0133] N desc =[8748,8748,8748,8748,8748,8476,7828,5832,2916,972,324,108,36,12,4,4]

[0134] It is understandable that N desc The value of each element in the array represents the number of Josephson nodes included in the Josephson node array. It is important to note that this sorting is only used for the order of greedy decision-making and does not change the physical numbering of the subarrays.

[0135] Step S3.2: Iterative greedy allocation.

[0136] Initialize residual error R=N target =45999. Iterate through N sequentially. desc Each element a in i Bias allocation is performed according to the rules:

[0137] a1=8748: |R|=45999≥8748 / 2=4374, therefore, the bias s1=sign(R)=+1 is assigned. Update R=R-s1·a1=45999-8748=37251.

[0138] a2=8748: |R|=37251≥4374, assign s2=+1. Update R=37251-8748=28503.

[0139] a3=8748: |R|=28503≥4374, allocate s3=+1. Update R=28503-8748=19755.

[0140] a4=8748: |R|=19755≥4374, allocate s4=+1. Update R=19755-8748=8307.

[0141] a5=8748: |R|=8307≥4374, allocate s5=+1. Update R=8307-8748=-441.

[0142] a6=8476: |R|=441<8476 / 2=4238, assign s6=0. R remains unchanged, still -441.

[0143] a7=7828: |R|=441<7828 / 2=3914, allocate s7=0.

[0144] a8=5832: |R|=441<5832 / 2=2916, allocate s8=0.

[0145] a9=2916: |R|=441<2916 / 2=1458, allocate s9=0.

[0146] a 10 =972: |R|=441<972 / 2=486, allocate s 10 =0.

[0147] a 11 =324:|R|=441≥324 / 2=162,Distribute s 11 =sign(R)=-1. Update R=-441-(-1)×324=-117.

[0148] a 12 =108: |R|=117≥108 / 2=54, allocate s 12 =-1. Update R=-117-(-1)×108=-9.

[0149] a 13 =36: |R|=9<36 / 2=18, allocate s 13 =0.

[0150] a 14 =12: |R|=9<12 / 2=6, allocate s 14 =0.

[0151] a 15 =4: |R|=9≥4 / 2=2, allocate s 15=-1. Update R=-9-(-1)×4=-5.

[0152] a 16 =4: |R|=5≥2, allocate s 16 =-1. Update R=-5-(-1)×4=-1.

[0153] The iteration ends, and the final residual error Δ = R = -1.

[0154] Step S3.3: Generate bias vector and physical compensation.

[0155] The assigned bias state s i Mapping back to the original order of the atomic array yields the optimal bias state vector s. The summation number N of the array output is then calculated. out =N target -Δ=45999-(-1)=46000.

[0156] The algorithm output includes a bias vector and a residual Δ = -1. According to the Josephson voltage formula, this residual can be precisely compensated by fine-tuning the microwave frequency f, achieving zero-error voltage output. The compensated frequency f′ is:

[0157] =f·(N target / (N target -Δ))=f·(45999 / (45999-(-1)))=f·(45999 / 46000)

[0158] At this frequency Driven by this, the voltage output by the Josephson array sequence will be exactly equal to the target voltage V. target .

[0159] The voltage bias allocation method for Josephson arrays proposed in this embodiment is based on intelligently selecting and executing the optimal bias state solution strategy according to the inherent mathematical characteristics of the array sequence. The entire method flow is clear, consisting of three core stages: intelligent identification of sequence features, dynamic routing of the solution algorithm, and calculation of the optimal bias state. The input to the method is the target summation number N. target and the Josephson array sequence N=[N1,N2,…,N] m The output is the optimal bias state vector s=[s1,s2,…,s…]. m ], where s i ∈{–1,0,+1}.

[0160] The purpose of this embodiment is to propose an innovative adaptive hierarchical driving method, which enables the driving system to have the intelligence of "perception-decision-optimization". It designs a front-end intelligent module that can automatically analyze the mathematical characteristics of any given Josephson array sequence. This module needs to accurately determine whether the sequence contains a dominant standard binary or ternary geometric subsequence and quantify its contribution.

[0161] Then, based on the feature recognition results, a dynamic intelligent algorithm routing mechanism is constructed. This mechanism can automatically and seamlessly allocate the solution task to the optimal core algorithm according to the "identity label" of the sequence: a fast base conversion algorithm is called for the identified standard sequences, and an efficient and robust general greedy algorithm is called for non-standard sequences. This ensures that the statistical average computational efficiency of the entire adaptive system is higher than that of always using a single general algorithm when processing any sequence. That is, by statistically analyzing the driving process of a large number of actual arrays, the time saved by this method through intelligent routing is greater than the additional time overhead introduced by the feature recognition module itself, thereby improving the overall performance. Regardless of which core algorithm is used, the tiny residual error of its output can be physically compensated by precise and linear microwave frequency fine-tuning, ultimately achieving zero-error quantum voltage output in physical implementation, so that the voltage synthesis accuracy is no longer limited by the approximation degree of the algorithm.

[0162] Compared with existing technologies, the advantages of this application are as follows: through intelligent feature recognition and adaptive routing mechanism, it fundamentally solves the contradiction between efficiency and universality in traditional methods. For arrays containing standard subsequences, this invention can automatically call a dedicated base algorithm with extremely low computational complexity, thereby achieving an average solution efficiency that is statistically superior to a single general algorithm. For completely non-standard sequences, universality is ensured through an efficient improved greedy algorithm.

[0163] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0164] Based on the same inventive concept, this application also provides a voltage biasing device for Josephson arrays to implement the voltage biasing distribution method for Josephson arrays described above. The solution provided by this device is similar to the solution described in the above method. Therefore, the specific limitations of one or more embodiments of the voltage biasing device for Josephson arrays provided below can be found in the limitations of the voltage biasing distribution method for Josephson arrays described above, and will not be repeated here.

[0165] In one exemplary embodiment, such as Figure 4 As shown, a voltage bias distribution device 100 for a Josephson array is provided, comprising: a classification module 11, a first distribution module 12, a second distribution module 13, a calculation module 14, and a driving module 15, wherein:

[0166] Classification module 11 is used to identify the equal-geometric subsequences in the Josephson array sequence as standard base sequences and the remaining sequences in the Josephson array sequence as non-standard sequences;

[0167] The first allocation module 12 is used to allocate the bias state of the standard Josephson nodes in each Josephson node matrix to the standard radix matrix using the corresponding radix algorithm.

[0168] The second allocation module 13 is used to allocate the bias state of each non-standard Josephson node in each Josephson node matrix to the Josephson node matrix belonging to the non-standard sequence through an iterative greedy algorithm.

[0169] The calculation module 14 is used to calculate the microwave frequency for compensating the residual based on the bias state of the standard Josephson junction and the bias state of the non-standard Josephson junction.

[0170] The driving module 15 is used to drive the Josephson array by the microwave frequency, so that the output voltage of the Josephson array is equal to the preset target voltage.

[0171] In one embodiment, the standard base sequence includes a standard binary sequence and a standard ternary sequence, and the first allocation module 12 further includes a first allocation unit and a second allocation unit, wherein:

[0172] The first allocation unit is used to allocate the bias state of the standard Josephson nodes in each Josephson node array to the standard Josephson nodes belonging to the standard binary sequence using a binary algorithm.

[0173] The second allocation unit is used to allocate the bias state of the standard Josephson nodes in each Josephson node array to the standard Josephson nodes belonging to the standard ternary sequence using a balanced ternary algorithm.

[0174] In one embodiment, the calculation module 14 further includes a residual determination unit and a first calculation unit, wherein:

[0175] The residual determination unit is used to determine the residual of the Josephson node array sequence based on the number of Josephson nodes that have been assigned the bias state.

[0176] The first calculation unit is used to calculate the microwave frequency used to compensate for the residual using the following formula:

[0177]

[0178] in, This represents the summation number of the Josephson array. This represents the residual. This indicates the initial drive frequency.

[0179] In one embodiment, the second allocation module 13 further includes a sorting unit and a traversal unit, wherein:

[0180] The sorting unit is used to sort the Josephson nodes belonging to the non-standard sequence in descending order based on the number of non-standard Josephson nodes in each Josephson node array.

[0181] The traversal unit is used to traverse each Josephson node array in the non-standard sequence in descending order, and to assign biases to the non-standard Josephson nodes in the corresponding Josephson node array according to preset rules.

[0182] In one embodiment, the traversal unit further includes a first calculation subunit and an allocation subunit, wherein:

[0183] The first calculation subunit is used to calculate the summation number of non-standard Josephson nodes in the Josephson node array, and the summation number is determined as the initial residual error;

[0184] The allocation sub-unit is used to allocate an offset with the same sign as the current residual error to each non-standard Josephson node in the current Josephson node array if the absolute value of the residual error is greater than or equal to half the number of nodes in the current Josephson node array; otherwise, it allocates a 0 offset to each non-standard Josephson node in the current Josephson node array.

[0185] In one embodiment, the voltage bias distribution device of the Josephson array further includes an update module for updating the remaining error using the following formula:

[0186]

[0187] in, This represents the remaining error from the previous iteration update. This is represented by the bias of the non-standard Josephson nodes assigned in the current Josephson node array. This represents the current node segment.

[0188] Each module in the voltage bias distribution device of the aforementioned Josephson array can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in a computer device, or stored in software within the memory of the computer device, so that the processor can call and execute the operations corresponding to each module.

[0189] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 5 As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When executed by the processor, the computer program implements a method for distributing the voltage bias of a Josephson array. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0190] Those skilled in the art will understand that Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0191] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0192] The geometric subsequences in the Josephson array sequence are identified as standard base sequences, and the remaining sequences in the Josephson array sequence are identified as non-standard sequences.

[0193] For Josephson junction matrices belonging to the standard base sequence, the bias state of the standard Josephson junctions in each Josephson junction matrix is ​​allocated by the corresponding base algorithm;

[0194] For Josephson node matrices that belong to non-standard sequences, the bias state of each non-standard Josephson node in each Josephson node matrix is ​​allocated by an iterative greedy algorithm.

[0195] Calculate the microwave frequency used to compensate for the residual based on the bias states of the standard Josephson junction and the non-standard Josephson junction.

[0196] The Josephson array is driven by the microwave frequency so that the output voltage of the Josephson array is equal to the preset target voltage.

[0197] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0198] The geometric subsequences in the Josephson array sequence are identified as standard base sequences, and the remaining sequences in the Josephson array sequence are identified as non-standard sequences.

[0199] For Josephson junction matrices belonging to the standard base sequence, the bias state of the standard Josephson junctions in each Josephson junction matrix is ​​allocated by the corresponding base algorithm;

[0200] For Josephson node matrices that belong to non-standard sequences, the bias state of each non-standard Josephson node in each Josephson node matrix is ​​allocated by an iterative greedy algorithm.

[0201] Calculate the microwave frequency used to compensate for the residual based on the bias states of the standard Josephson junction and the non-standard Josephson junction.

[0202] The Josephson array is driven by the microwave frequency so that the output voltage of the Josephson array is equal to the preset target voltage.

[0203] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, performs the following steps:

[0204] The geometric subsequences in the Josephson array sequence are identified as standard base sequences, and the remaining sequences in the Josephson array sequence are identified as non-standard sequences.

[0205] For Josephson junction matrices belonging to the standard base sequence, the bias state of the standard Josephson junctions in each Josephson junction matrix is ​​allocated by the corresponding base algorithm;

[0206] For Josephson node matrices that belong to non-standard sequences, the bias state of each non-standard Josephson node in each Josephson node matrix is ​​allocated by an iterative greedy algorithm.

[0207] Calculate the microwave frequency used to compensate for the residual based on the bias states of the standard Josephson junction and the non-standard Josephson junction.

[0208] The Josephson array is driven by the microwave frequency so that the output voltage of the Josephson array is equal to the preset target voltage.

[0209] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0210] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0211] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0212] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method of distributing voltage bias to an array of Josephson junctions, characterized by, The method includes: The equal-ratio subsequences in the Josephson array sequence are determined as standard base sequences, and the remaining sequences in the Josephson array sequence are determined as non-standard sequences; For Josephson junction matrices belonging to the standard base sequence, the bias state of the standard Josephson junctions in each Josephson junction matrix is ​​allocated by the corresponding base algorithm; For Josephson node matrices that belong to non-standard sequences, the bias state of each non-standard Josephson node in each Josephson node matrix is ​​allocated by an iterative greedy algorithm. The microwave frequency used to compensate for the residual is calculated based on the bias state of the standard Josephson junction and the bias state of the non-standard Josephson junction. The Josephson array is driven by the microwave frequency so that the output voltage of the Josephson array is equal to the preset target voltage.

2. The method of claim 1, wherein, The standard base sequence includes a standard binary sequence and a standard ternary sequence; the allocation of the bias state of the standard Josephson nodes in each Josephson node matrix belonging to the standard base sequence, using the corresponding base algorithm, includes: For standard Josephson nodes belonging to the standard binary sequence, the bias state of each standard Josephson node in the Josephson node array is allocated by a binary algorithm; For standard Josephson nodes belonging to the standard ternary sequence, the bias state of each standard Josephson node in the Josephson node matrix is ​​allocated by the balanced ternary algorithm.

3. The method of claim 1, wherein, The step of calculating the microwave frequency for residual compensation based on the bias states of the standard Josephson junction and the non-standard Josephson junction includes: The residual of the Josephson node array sequence is determined based on the number of Josephson nodes that have been assigned the bias state. The microwave frequency used to compensate for the residual is calculated using the following formula: wherein, represents a total number of junctions of the array of Josephson junctions, represents the residual error, represents an initial drive frequency.

4. The method according to claim 1, characterized in that, The process of allocating the bias states of each non-standard Josephson node in a Josephson node matrix belonging to a non-standard sequence using an iterative greedy algorithm includes: Based on the number of non-standard Josephson nodes in each Josephson node array, the Josephson node arrays belonging to the non-standard sequence are sorted in descending order; Following the descending order, each Josephson node in the non-standard sequence is traversed sequentially, and the non-standard Josephson nodes in the corresponding Josephson node array are biased according to a preset rule.

5. The method according to claim 4, characterized in that, The step of assigning biases to non-standard Josephson nodes in the corresponding Josephson node array according to preset rules includes: Calculate the summation number of non-standard Josephson nodes in the Josephson node array, and determine the summation number as the initial residual error; If the absolute value of the remaining error is greater than or equal to half the number of nodes in the current Josephson array, assign a bias with the same sign as the current remaining error to each of the non-standard Josephson nodes in the current Josephson array; otherwise, assign a 0 bias to each of the non-standard Josephson nodes in the current Josephson array.

6. The method according to claim 5, characterized in that, The method further includes: The remaining error is updated using the following formula: in, This represents the remaining error from the previous iteration. This is represented by the bias of the non-standard Josephson nodes assigned in the current Josephson node array. This represents the current node segment.

7. A voltage biasing distribution device for a Josephson array, characterized in that, The device includes: The classification module is used to identify the equal-geometric subsequences in the Josephson array sequence as standard base sequences and the remaining sequences in the Josephson array sequence as non-standard sequences. The first allocation module is used to allocate the bias state of the standard Josephson nodes in each Josephson node matrix that belongs to the standard base sequence by means of the corresponding base algorithm. The second allocation module is used to allocate the bias state of each non-standard Josephson node in each Josephson node matrix that belongs to a non-standard sequence using an iterative greedy algorithm. The calculation module is used to calculate the microwave frequency for compensating the residual based on the bias state of the standard Josephson junction and the bias state of the non-standard Josephson junction. The driving module is used to drive the Josephson array using the microwave frequency, so that the output voltage of the Josephson array is equal to the preset target voltage.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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