Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

A semiconductor structure and a method for fabricating the semiconductor structure are disclosed. The semiconductor structure includes: a substrate; a plurality of bit line structures located on the surface of the substrate, the plurality of bit line structures extending along a first direction and spaced apart along a second direction, the first direction and the second direction being perpendicular to each other and both parallel to the substrate surface; and a memory node contact structure located between adjacent bit line structures. The memory node contact structure includes a lower contact portion and an upper contact portion stacked thereon, the bottom surface of the lower contact portion contacting the substrate, the bottom surface of the upper contact portion contacting the top surface of the lower contact portion, the upper contact portion comprising a metallic conductive material, and the lower contact portion comprising a semiconductor conductive material; wherein, in the first direction, the width of the upper contact portion located between adjacent bit line structures is greater than the width of the lower contact portion; the sidewalls of the bit line structures adjacent to the memory node contact structure comprising a low dielectric constant material. This semiconductor structure exhibits high reliability and stability.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure and a method for fabricating the semiconductor structure. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of volatile memory. A DRAM device typically includes a memory array region consisting of memory cells and a peripheral region consisting of logic control circuitry. A typical memory cell includes a switching structure (such as a transistor) and a storage structure (such as a capacitor). The logic control circuitry in the peripheral region addresses each memory cell in the memory array region via multiple word lines and bit lines passing through it, and activates the switching structure to electrically connect to the storage structure, thereby performing data reads, writes, or accesses.

[0003] However, as the integration of the memory array area becomes higher, the space for memory node contacts and the spacing between adjacent memory node contacts and bit lines are becoming smaller and smaller, which introduces huge challenges to device reliability and process difficulty, especially in the fabrication process where there are many technical problems that urgently need to be solved. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising: a substrate; a plurality of bit line structures located on the surface of the substrate, the plurality of bit line structures extending along a first direction and spaced apart along a second direction, the first direction and the second direction being perpendicular to each other and both parallel to the surface of the substrate; a memory node contact structure located between adjacent bit line structures, the memory node contact structure including a lower contact portion and an upper contact portion stacked thereon, the bottom surface of the lower contact portion contacting the substrate, the bottom surface of the upper contact portion contacting the top surface of the lower contact portion, the upper contact portion comprising a metallic conductive material, and the lower contact portion comprising a semiconductor conductive material; wherein, in the first direction, the width dimension of the upper contact portion located between adjacent bit line structures is greater than the width dimension of the lower contact portion; the sidewalls of the bit line structures adjacent to the memory node contact structures comprise a low dielectric constant material.

[0005] In some embodiments, the semiconductor structure includes: a plurality of memory node contact structures located between adjacent bit line structures and spaced apart along the first direction.

[0006] In some embodiments, the semiconductor structure further includes a gate layer located between adjacent bit line structures and also between adjacent memory node contact structures, the gate layer comprising a material including silicon nitride.

[0007] In some embodiments, the storage node contact structure further includes a protective layer that covers only the sidewall of the lower contact portion adjacent to the fence layer, and the material of the protective layer includes silicon oxide.

[0008] In some embodiments, the bitline structure includes a bitline body and a spacer layer that at least covers the sidewalls of the bitline body; the bitline body includes a bitline contact layer, a bitline conductive layer, and a bitline capping layer stacked together, a portion of the bottom surface of the bitline contact layer contacts the substrate, the bottom surface of the bitline conductive layer contacts the top surface of the bitline contact layer, and the bottom surface of the bitline capping layer contacts the top surface of the bitline conductive layer; the spacer layer includes a first spacer layer stacked together and a second spacer layer located outside the first spacer layer, the first spacer layer at least covers the sidewalls of the bitline body, and the second spacer layer at least covers the sidewalls of the first spacer layer.

[0009] In some embodiments, the material of the first spacer layer includes silicon oxide, and the material of the second spacer layer includes silicon oxide and the low dielectric constant material spaced apart in the first direction.

[0010] In some embodiments, the material of the portion of the second spacer layer adjacent to the fence layer is silicon oxide, and the material of the portion of the second spacer layer adjacent to the storage node contact structure is the low dielectric constant material.

[0011] In some embodiments, the low dielectric constant material includes silicon oxide.

[0012] In some embodiments, the semiconductor structure further includes: a storage transistor structure located on the surface of the substrate, the storage transistor structure including a first source and drain that are in contact with and electrically connected to a bit line structure and a second source and drain that are in contact with and electrically connected to a storage node contact structure; a word line structure located in the substrate, the word line structure extending along the second direction, serving as the gate of the storage transistor structure or electrically connected to the gate of the storage transistor structure; and a storage node structure located on the substrate, in contact with and electrically connected to the top surface of the storage node contact structure.

[0013] According to a second aspect of the present disclosure, a method for fabricating a semiconductor structure is provided, comprising: providing a substrate; forming a plurality of bit line structures on the surface of the substrate, the plurality of bit line structures extending along a first direction and spaced apart along a second direction, the first direction and the second direction being perpendicular to each other and both parallel to the surface of the substrate; forming a memory node contact structure between adjacent bit line structures, the memory node contact structure including a lower contact portion and an upper contact portion stacked thereon, the bottom surface of the lower contact portion contacting the substrate, the bottom surface of the upper contact portion contacting the top surface of the lower contact portion, the upper contact portion comprising a metallic conductive material, and the lower contact portion comprising a semiconductor conductive material; wherein, in the first direction, the width dimension of the upper contact portion located between adjacent bit line structures is greater than the width dimension of the lower contact portion; the sidewalls of the bit line structures adjacent to the memory node contact structures comprise a low dielectric constant material.

[0014] In some embodiments, forming a plurality of bit line structures on the substrate surface includes: forming a plurality of bit line bodies and a spacer layer at least covering the sidewalls of each bit line body on the substrate surface; forming the bit line body includes sequentially forming a stacked bit line contact layer, a bit line conductive layer and a bit line capping layer on the substrate surface, wherein a portion of the bottom surface of the bit line contact layer contacts the substrate, the bottom surface of the bit line conductive layer contacts the top surface of the bit line contact layer, and the bottom surface of the bit line capping layer contacts the top surface of the bit line conductive layer; forming the spacer layer includes sequentially forming a first spacer layer and a second spacer layer located outside the first spacer layer, wherein the first spacer layer at least covers the sidewalls of the bit line bodies, the second spacer layer at least covers the sidewalls of the first spacer layer, and the material of the second spacer layer includes the low dielectric constant material, wherein the low dielectric constant material includes silicon oxycarbide.

[0015] In some embodiments, forming a memory node contact structure between adjacent bit line structures includes forming a lower contact portion and an upper contact portion stacked sequentially on the substrate surface between adjacent bit line structures.

[0016] In some embodiments, forming sequentially stacked lower and upper contacts on the substrate surface between adjacent bit line structures includes: forming an initial lower contact material layer between adjacent bit line structures, the initial lower contact material layer filling the gap between adjacent bit line structures; performing a first etching on the initial lower contact material layer to separate the initial lower contact material layer into a plurality of initial lower contact layers spaced apart along a first direction; performing an ashing process, including: oxidizing the sidewalls of the initial lower contact layers facing the first direction and opposite thereto to form an initial protective layer; performing a second etching on the initial lower contact layers and the initial protective layer to reduce the height of the initial lower contact layers and the initial protective layer, wherein the remaining initial protective layer serves as a protective layer, the remaining initial lower contact layers serve as the lower contacts, the protective layer covering the sidewalls of the lower contacts facing the first direction and opposite thereto; and forming the upper contact on the lower contacts.

[0017] In some embodiments, performing the ashing process further includes oxidizing the second spacer layer exposed by the portion of the initial lower contact material layer removed by the first etching.

[0018] In some embodiments, after performing the ashing process and before performing the second etching, the method further includes forming a fence layer between adjacent bit line structures, the fence layer filling the gap between adjacent initial lower contact layers.

[0019] In some embodiments, the method further includes: forming a storage transistor structure on the surface of the substrate, the storage transistor structure including a first source and drain that are in contact with and electrically connected to a bit line structure and a second source and drain that are in contact with and electrically connected to a storage node contact structure; forming a word line structure in the substrate, the word line structure extending along the second direction and serving as the gate of the storage transistor structure or electrically connected to the gate of the storage transistor structure; and forming a storage node structure on the substrate, the storage node structure being in contact with and electrically connected to the top surface of the storage node contact structure. Attached Figure Description

[0020] Figure 1 This is a schematic diagram illustrating the formation of a substrate according to an exemplary embodiment;

[0021] Figure 2 This is a schematic diagram illustrating the formation of an active region and a shallow trench isolation structure according to an exemplary embodiment;

[0022] Figure 3 This is a schematic diagram illustrating the formation of a word line structure according to an exemplary embodiment;

[0023] Figure 4This is a schematic diagram illustrating the formation of a bitline structure according to an exemplary embodiment;

[0024] Figure 5 This is a schematic diagram illustrating the formation of an initial lower contact material layer according to an exemplary embodiment;

[0025] Figure 6 This is a schematic diagram illustrating the first etching process according to an exemplary embodiment;

[0026] Figure 7 This is a schematic diagram illustrating the execution of an ashing process according to an exemplary embodiment;

[0027] Figure 8 This is a schematic diagram illustrating the formation of a fence layer according to an exemplary embodiment;

[0028] Figure 9 This is a schematic diagram illustrating a second etching process according to an exemplary embodiment;

[0029] Figure 10 This is a schematic diagram illustrating the formation of an upper contact material layer according to an exemplary embodiment;

[0030] Figure 11 This is a schematic diagram illustrating the formation of an upper contact portion according to an exemplary embodiment;

[0031] Figure 12 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment. Detailed Implementation

[0032] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0033] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0034] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0035] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0036] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0037] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0038] In related technologies, the fabrication process of Dynamic Random Access Memory (DRAM) structures typically requires the formation of memory cell-related structures, such as memory transistors, memory capacitors, bit lines, and word lines, in the memory array region, while peripheral transistors and metal interconnects are formed in the peripheral region. The inventors of this application have discovered that after fabricating the bit line structures, it is necessary to form memory node contacts and isolation barriers between adjacent bit line structures. However, the space between adjacent bit line structures is small, and voids and other defects easily occur when filling the conductive material of the memory node contacts, leading to poor conductivity of the memory node contacts and severely affecting device yield. Furthermore, after forming the memory node contacts, the distance between adjacent memory node contacts and bit lines, as well as between adjacent bit lines, is too small, easily causing mutual interference and coupling problems during memory cell operation, resulting in poor performance and reliability of the memory device.

[0039] To address the aforementioned technical problems, this disclosure provides a semiconductor structure and a method for fabricating the semiconductor structure, which will be described below in conjunction with... Figures 1 to 12 This disclosure provides a specific example of a semiconductor structure and a method for fabricating the semiconductor structure. Figures 1 to 11 This is a schematic diagram illustrating the formation of a semiconductor structure according to an exemplary embodiment of the present disclosure. Figure 12 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment of the present disclosure.

[0040] In an exemplary embodiment of this disclosure, a semiconductor structure is provided, with reference to Figure 11 As shown, where Figure 11 (a) is a top view of the semiconductor structure in the opposite direction of the third direction Z. Figure 11 (b) is Figure 11 (a) is a schematic diagram of the cross section along the B-B' direction. Figure 11 (c) is Figure 11 (a) shows a cross-sectional schematic diagram along the D-D' direction. The semiconductor structure includes: a substrate 10; a plurality of bit line structures 11 located on the surface of the substrate 10, the plurality of bit line structures 11 extending along a first direction Y and spaced apart along a second direction X, the first direction Y and the second direction X being perpendicular to each other and both parallel to the surface of the substrate 10; a memory node contact structure 12 located between adjacent bit line structures 11, the memory node contact structure 12 including a lower contact portion 121 and an upper contact portion 123 stacked together, the bottom surface of the lower contact portion 121 contacting the substrate 10, the bottom surface of the upper contact portion 123 contacting the top surface of the lower contact portion 121, the upper contact portion 123 comprising a metallic conductive material, and the lower contact portion 121 comprising a semiconductor conductive material; wherein, in the first direction, the width dimension of the upper contact portion 123 located between adjacent bit line structures 11 is greater than the width dimension of the lower contact portion 121; the sidewalls of the bit line structures 11 adjacent to the memory node contact structure 12 comprising a low dielectric constant material.

[0041] The substrate 10 may be made of at least one of the following semiconductor materials or group III-V materials: silicon, germanium, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). In an exemplary embodiment of this disclosure, the substrate 10 is made of single-crystal silicon. The semiconductor conductive material of the lower contact 121 may be doped polycrystalline silicon, doped polycrystalline germanium, doped polycrystalline silicon-germanium, or group III-V compound semiconductor materials. In an exemplary embodiment of this disclosure, the semiconductor conductive material of the lower contact 121 is doped polycrystalline silicon. The metallic conductive material of the upper contact 123 may be a combination of tungsten, aluminum, nickel, platinum, titanium, tantalum, molybdenum, ruthenium as the main body and their nitrides as the barrier layer. In an exemplary embodiment of this disclosure, the metallic conductive material of the upper contact 123 is a combination of tungsten and titanium nitride.

[0042] Continue to refer to Figure 11 As shown, in some embodiments, the upper contact portion 123 includes a first sub-portion 123a located between adjacent bit line structures 11 and a second sub-portion 123b located outside the adjacent bit line structures 11. The first sub-portion 123a and the second sub-portion 123b are connected and integrally formed. In the second direction X, the second sub-portion 123b is offset from the first sub-portion 123a. In the third direction Z, the second sub-portion 123b is located above the first sub-portion 123a. Figure 11As shown in (c). In some embodiments, in a plane direction parallel to the surface of the substrate 10, the plurality of first sub-parts 123a are arranged in a tetragonal distribution, while the plurality of second sub-parts 123b are arranged in a hexagonal distribution, as shown in (c). Figure 11 As shown in (a).

[0043] In some embodiments, the semiconductor structure includes a plurality of memory node contact structures 12 located between adjacent bit line structures 11 and spaced apart along a first direction Y. The semiconductor structure also includes a gate layer 13 located between adjacent bit line structures 11 and also between adjacent memory node contact structures 12, as shown below. Figure 11 As shown in (a) and 11(b).

[0044] The material of the fence layer 13 can be at least one or any combination of the following: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In an exemplary embodiment of this disclosure, the material of the fence layer 13 is silicon nitride.

[0045] In some embodiments, the storage node contact structure 12 further includes a protective layer 122, which covers only the sidewall of the lower contact portion 121 adjacent to the fence layer 13, such as... Figure 11 As shown in (b). In some embodiments, the material of the protective layer 122 includes silicon oxide, germanium oxide, and silicon-germanium oxide. In an exemplary embodiment of this disclosure, the material of the protective layer 122 is silicon oxide. Due to the presence of the protective layer 122, the width of the upper contact portion 123 (i.e., the first sub-portion 123a) located between adjacent bit line structures 11 in the first direction Y is greater than the width of the lower contact portion 121.

[0046] In some embodiments, the bit line structure 11 includes a bit line body 111 and a spacer layer 112 that at least covers the sidewalls of the bit line body 111; the bit line body 111 includes a bit line contact layer 1111, a bit line conductive layer 1112 and a bit line capping layer 1113 stacked together, a portion of the bottom surface of the bit line contact layer 1111 contacts the substrate 10, the bottom surface of the bit line conductive layer 1112 contacts the top surface of the bit line contact layer 1111, and the bottom surface of the bit line capping layer 1113 contacts the top surface of the bit line conductive layer 1112; the spacer layer 112 includes a first spacer layer 1121 stacked together and a second spacer layer 1122 located outside the first spacer layer 1121, the first spacer layer 1121 at least covers the sidewalls of the bit line body 111, and the second spacer layer 1122 at least covers the sidewalls of the first spacer layer 1121. In an exemplary embodiment of this disclosure, a first spacer layer 1121 covers the sidewalls and top surface of the bit line body 111, and a second spacer layer 1122 covers the sidewalls and top surface of the first spacer layer 1121. The bit line structure 11 is used to provide or sense stored charge.

[0047] The bit line contact layer 1111 can be made of doped polycrystalline silicon, doped polycrystalline germanium, doped polycrystalline silicon-germanium, or a III-V compound semiconductor material. In an exemplary embodiment of this disclosure, the bit line contact layer 1111 is made of doped polycrystalline silicon. The bit line conductive layer 1112 can be made of tungsten, aluminum, nickel, platinum, titanium, tantalum, molybdenum, ruthenium, or their nitrides. In an exemplary embodiment of this disclosure, the bit line conductive layer 1112 is made of a combination of tungsten and titanium nitride. The bit line capping layer 1113, the first spacer layer 1121, and the second spacer layer 1122 can be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, or silicon carbonitride. In an exemplary embodiment of this disclosure, the bit line capping layer 1113 is made of silicon nitride, the first spacer layer 1121 is made of silicon oxide, and the second spacer layer 1122 is made of a combination of silicon oxide and silicon carbon oxycarbide with a low dielectric constant.

[0048] In an exemplary embodiment of this disclosure, the material of the second spacer layer 1122 includes silicon oxide and silicon carbide having a low dielectric constant, which are spaced apart in the first direction Y. Specifically, the material of the portion of the second spacer layer 1122 adjacent to the gate layer 13 is silicon oxide, and the material of the portion of the second spacer layer 1122 adjacent to the storage node contact structure 12 is silicon carbide having a low dielectric constant.

[0049] In some embodiments, refer to Figure 12 As shown, the semiconductor structure also includes a memory transistor structure (not shown), a word line structure 103, and a memory node structure 15. The substrate 10 further includes an active area (AA) 101 and a shallow trench isolation (STI) structure 102. The STI structure 102 isolates the active area 101, which provides a first source / drain, a second source / drain, and a channel region for the memory transistor structure. The word line structure 103 is located in the substrate 10, covering the surface of the channel region, and serves as the gate of the memory transistor structure or is electrically connected to the gate of the memory transistor structure. The first source / drain is in contact with and electrically connected to the bottom surface of the bit line structure 11, and the second source / drain is in contact with and electrically connected to the bottom surface of the memory node contact structure 12. The memory node structure 15 is located on the substrate 10 and is in contact with and electrically connected to the top surface of the memory node contact structure 12.

[0050] Specifically, a shallow trench isolation structure 102 is formed on the surface of the substrate 10 to divide the surface of the substrate 10 into a plurality of arrayed active regions 101, which may be doped with N-type or P-type ions. In some embodiments, the material of the shallow trench isolation structure 102 may be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In an exemplary embodiment of this disclosure, the material of the shallow trench isolation structure 102 is silicon oxide.

[0051] In some embodiments, the word line structure 103 can be a buried word line structure, formed in a region of the shallow surface of the substrate 10, interspersed between the plurality of active regions 101 and the shallow trench isolation structure 102. In an exemplary embodiment of this disclosure, a portion of the word line structure 103 in the active region 101 itself serves as the gate of the storage transistor structure. In some embodiments, the word line structure 103 includes a gate dielectric layer 1031, a word line conductive layer 1032, and a word line insulating layer 1033 stacked sequentially. The gate dielectric layer 1031 can be made of any one or more of silicon oxide, hafnium oxide, zirconium oxide, and aluminum oxide. The word line conductive layer 1032 can be made of any one or more of doped polycrystalline silicon, tungsten, and titanium nitride. The word line insulating layer 1033 can be made of at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonoxide, silicon carbonitride, and silicon carbonitride. In one exemplary embodiment of this disclosure, the gate dielectric layer 1031 is made of silicon oxide, the word line conductive layer 1032 is made of titanium nitride, and the word line insulating layer 1033 is made of silicon nitride (not shown in detail in the figures). In some embodiments, the portion of the word line structure 103 in the active region 101 has a smaller depth and width than the portion in the shallow trench isolation structure 102 (not shown in detail in the figures). In other embodiments, the word line structure 103 is connected to the gate of a transistor structure formed within the active region 101. The word line structure 103 is used to provide a gate signal to control the turning on or off of the storage transistor structure. In some embodiments, multiple word line structures 103 extend along a second direction X and are arranged parallel to each other at intervals. It should be noted that the term "surface" as used above should be understood as the region near the surface, including not only the region above the surface but also the shallow surface region below the surface.

[0052] In some embodiments, a first support layer 141 is provided between the second sub-parts 123b of adjacent upper contact portions 123 for isolation, and the material of the first support layer 141 may be silicon nitride.

[0053] In an exemplary embodiment of this disclosure, the storage node structure 15 is a storage capacitor, comprising a first electrode layer 151, a capacitor dielectric layer 152, and a second electrode layer 153 stacked sequentially. In other embodiments, the storage node structure may also be a phase-change transistor, a ferroelectric transistor, a magnetoresistive transistor, a resistive switching transistor, etc. In some embodiments, the storage node structure 15 is located on the storage node contact structure 12, and the first electrode layer 151 of the storage node structure 15 is in direct contact with the upper contact portion 123 of the storage node contact structure 12. In an exemplary embodiment of this disclosure, the storage node structure 15 is arranged in a plurality of hexagonal close-packed cylindrical shapes, i.e., the first electrode layer 151 is a hollow cylinder. In another exemplary embodiment, the storage node structure 15 is arranged in a plurality of hexagonal close-packed cylindrical shapes, i.e., the first electrode layer 151 is a solid column. Adjacent cylindrical capacitors are supported by a support layer as a stabilizing structure. The support layer includes a first support layer 141, a second support layer 142, and a third support layer 143 spaced apart along a third direction Z. The top surface of the first electrode layer 151 is flush with the top surface of the third support layer 143. In other embodiments, the support layer may include two or more layers. The first support layer 141, the second support layer 142, and the third support layer 143 are all parallel to the plane of the substrate surface. In some embodiments, the material of the first support layer 141, the second support layer 142, and the third support layer 143 may be silicon nitride.

[0054] In some embodiments, the storage capacitor of the storage node structure 15 is a double-sided capacitor, that is, the capacitor dielectric layer 152 covers the inner and outer surfaces of the cylindrical first electrode layer 151, while the second electrode layer 153 covers the surface of the capacitor dielectric layer 152. This forms capacitors on both the inner and outer surfaces of the cylindrical first electrode layer 151, increasing the area of ​​the capacitor plates to a certain extent, thereby improving the capacity of stored charge. In some embodiments, the materials of the first electrode layer 151 and the second electrode layer 153 of the storage node structure 15 can be one or more of titanium nitride, tantalum nitride, and silicon-doped titanium nitride. The capacitor dielectric material of the capacitor dielectric layer 152 of the storage node structure 15 can be at least one or more of zirconium oxide (ZrO2) and aluminum oxide (Al2O3). In other embodiments, the capacitor dielectric material can also be at least one or more of silicon oxide (SiO2), hafnium oxide (HfO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (STO), and lead titanate (PZT).

[0055] In some embodiments, the semiconductor structure further includes a conductive electrode plate 16 covering the surface of the second electrode layer 153, and the conductive electrode plate 16 is partially inserted into the cylindrical storage node structure 15. The conductive electrode plate 16 is electrically connected to the second electrode layer 153, and the material of the conductive electrode plate 16 can be doped polycrystalline silicon or doped polycrystalline silicon germanium. A contact 17 is inserted into the conductive electrode plate 16 and is electrically connected to the second electrode layer 153 through the conductive electrode plate 16. The material of the contact 17 can be tungsten, copper, or other metal materials with good conductivity. An interlayer dielectric layer 18 covers the surface of the conductive electrode plate 16. The material of the interlayer dielectric layer 18 can be silicon oxide.

[0056] The semiconductor structure disclosed herein includes, on the one hand, a low dielectric constant material comprising the sidewalls of the bit line structure and the memory node contact structure, which reduces parasitic capacitance or resistance between adjacent bit line structures and memory node contact structures, as well as between adjacent bit lines, due to insufficient distance, thereby reducing interference or coupling effects between adjacent structures in operation; on the other hand, in the first direction, the width of the upper contact portion of the memory node contact structure is greater than the width of the lower contact portion, making it less prone to voids in the formed memory node contact structure when filling the memory node contact material, thereby improving the conductivity and process reliability of the memory node contact structure and improving the yield of semiconductor devices.

[0057] Based on the above semiconductor structure, this disclosure also provides a method for fabricating a semiconductor structure, comprising: providing a substrate 10, such as... Figure 1 As shown, where Figure 1 (a) is a top view of the substrate 10 in the opposite direction of the third direction Z. Figure 1 (b) is along Figure 1 (a) is a cross-sectional view along the dashed line A-A' direction. The cross-section along the dashed line A-A' direction is perpendicular to the top surface of the substrate 10.

[0058] The substrate 10 may be made of at least one of the following semiconductor materials or group III-V materials: silicon, germanium, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). In an exemplary embodiment of this disclosure, the substrate 10 is made of single-crystal silicon.

[0059] Next, refer to Figure 2 As shown, where Figure 2 (a) is a top view of the substrate 10 in the opposite direction of the third direction Z. Figure 2 (b) is along Figure 2(a) is a schematic cross-sectional view along the dashed line A-A'. The cross-section along the dashed line A-A' is perpendicular to the top surface of the substrate 10. A shallow trench isolation (STI) structure 102 is formed on the surface of the substrate 10 to divide the surface of the substrate 10 into multiple arrayed active areas 101 (AA). Specifically, the substrate 10 can be etched to form shallow trenches, which divide the surface of the substrate 10 into multiple arrayed active areas 101. Then, isolation material is filled into the shallow trenches to form the shallow trench isolation structure 102. Before or after forming the shallow trench isolation structure 102, the active areas 101 can be doped with N-type or P-type ions. In an exemplary embodiment of this disclosure, from Figure 2 As shown in (a), the top view of the active region 101 is a long strip with rounded ends, and adjacent active regions 101 are staggered. In other embodiments, the top view of the active region 101 may also be a long strip of parallelogram, and adjacent active regions 101 may be arranged without staggering. In some other embodiments, the top view of the active region 101 may also be a circular or square shape distributed in a square.

[0060] In some embodiments, a photolithography process can be used to etch the surface of the substrate 10 to form shallow trenches. Specifically, a photoresist mask layer can be formed on the surface of the substrate 10. By exposure and development, the pattern of the active region 101 is formed in the photoresist mask layer, and then dry etching is performed to etch the substrate 10 along the pattern to form shallow trenches. In some embodiments, before coating the photoresist mask layer, an anti-reflection layer and a hard mask layer (not shown) are also formed on the surface of the substrate 10, and both are removed after the shallow trenches are formed.

[0061] In some embodiments, the material of the shallow trench isolation structure 102 may be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In some embodiments, the deposition method of the isolation material in the shallow trench isolation structure 102 may employ at least one of the following deposition methods: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin-coated dielectric layer (SOD), and thermal oxidation growth.

[0062] Then, refer to Figure 3 As shown, where Figure 3 (a) is a top view of the substrate 10 in the opposite direction of the third direction Z. Figure 3 (b) is along Figure 3 (a) is a cross-sectional view along the dashed line A-A'. The cross-section along the dashed line A-A' is perpendicular to the top surface of the substrate 10, forming a word line structure 103 extending along the second direction X in the substrate 10. The word line structure 103 is an embedded word line structure, meaning that the word line structure 103 is located in a portion of the area below the top surface of the substrate 10. Specifically, multiple word line trenches extending along the second direction X are first etched on the surface of the substrate 10. The word line trenches span multiple active regions 101 and shallow trench isolation structures 102. Then, a gate dielectric layer 1031, a word line conductive layer 1032, and a word line insulating layer 1033 are sequentially formed in the word line trenches to jointly constitute the word line structure 103. Figure 3 (b) A partially enlarged schematic diagram of the structure within the dashed box E. In some embodiments, such as Figure 3 As shown in (a), a plurality of word line structures 103 extend along a second direction X and are arranged parallel to each other at intervals in a first direction Y. In some embodiments, the depth of the word line structures 103 is less than the depth of the shallow trench isolation structure 103. In some embodiments, the portion of the word line structure 103 located in the shallow trench isolation structure 103 is larger in size than the portion located in the active region 101, including depth and / or width dimensions.

[0063] In some embodiments, photolithography can be used to etch the surface of the substrate 10 to form word line trenches. Specifically, a photoresist mask layer can be formed on the surface of the substrate 10. By exposure and development, the pattern of the word line structure is formed in the photoresist mask layer. Then, dry etching is performed to etch the substrate 10 (including the active region 101 and the first shallow trench isolation structure 102) along the pattern to form word line trenches. In some embodiments, before coating the photoresist mask layer, an anti-reflection layer and a hard mask layer (not shown) are also formed on the surface of the substrate 10, and both are removed after the word line trenches are formed.

[0064] In some embodiments, the gate dielectric layer 1031 may be a combination of at least one or more of silicon oxide (SiO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (STO), and lead titanate (PZT). In an exemplary embodiment of this disclosure, the gate dielectric layer 1031 is made of silicon oxide. In some embodiments, the word line conductive layer 1032 may be a combination of at least one or more of doped polycrystalline silicon, titanium nitride (TiN), silicon-doped titanium nitride (TiSiN), titanium (Ti), tungsten (W), tungsten nitride (WN), and silicon-doped tungsten nitride (WSiN). In other embodiments, the word line conductive layer 1032 may also be a combination of at least one or more of molybdenum (Mo), ruthenium (Ru), tantalum (Ta), platinum (Pt), copper (Cu), and their nitrides. In an exemplary embodiment of this disclosure, the word line conductive layer 1032 is made of titanium nitride. In some embodiments, the material of the word line insulating layer 1033 may be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In an exemplary embodiment of this disclosure, the material of the word line insulating layer 1033 is silicon nitride.

[0065] In some embodiments, the gate dielectric layer 1031, the word line conductive layer 1032, and the word line insulating layer 1033 can be formed using at least one of the following deposition methods: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin-coated dielectric layer (SOD), in-situ water vapor growth (ISSG), and thermal oxidation growth. It should be noted that the gate dielectric layer 1031 in the word line structure 103 can also be selectively formed only in the active region 101.

[0066] In some embodiments, before forming the word line structure 103, the active region 101 is further doped with N-type or P-type. After forming the word line structure 103, the doped portions of the active region 101 located on both sides of the word line structure 103 serve as two source and drain electrodes, and the doped portion of the active region 101 located below the word line structure 103 serves as a channel region. Together with the word line conductive layer 1032 in the word line structure 103 itself serving as the gate, they constitute a storage transistor structure. The word line structure 103 is used to provide a gate signal to control the turning on or off of the storage transistor structure. In an exemplary embodiment of this disclosure, a single active region 101 is spanned by two adjacent word line structures 103 to form two storage transistor structures.

[0067] Next, as Figure 4 As shown, where Figure 4 (a) is a top view of the substrate 10 in the opposite direction of the third direction Z. Figure 4 (b) is along Figure 4 (a) is a cross-sectional view along the dashed line A-A'. The cross-section along the dashed line A-A' is perpendicular to the top surface of the substrate 10, forming a bit line structure 11 on the surface of the substrate 10. Unlike the word line structure 103, the bit line structure 11 is located in a portion of the area above the top surface of the substrate 10. Specifically, bit line contact holes are first formed at the middle position of the top surface of each active region 101, then a bit line material stack is formed on the surface of the substrate 10, and the bit line material stack is etched along the first direction Y to form a bit line body 111. A spacer layer 112 is formed on the surface of the bit line body 111 to jointly constitute the bit line structure 11. The bit line body 111 includes a bit line contact layer 1111, a bit line conductive layer 1112, and a bit line capping layer 1113. In some embodiments, such as Figure 4 As shown in (a), a plurality of bit line structures 11 extend along a first direction Y and are arranged parallel to each other at intervals in a second direction X. In some embodiments, the bit line contact layer 1111 of the bit line structure 11 is partially located within a bit line contact hole, that is, a portion of the bit line contact layer 1111 is inserted below the top surface of the substrate 10 and directly contacts the middle position of the top surface of the active region 101. The bottom surface of the bit line conductive layer 1112 contacts the top surface of the bit line contact layer 1111, and the bottom surface of the bit line capping layer 1113 contacts the top surface of the bit line conductive layer 1112. In some embodiments, forming the spacer layer 112 includes sequentially forming a first spacer layer 1121 and a second spacer layer 1122 located outside the first spacer layer 1121, wherein the first spacer layer 1121 at least covers the sidewall of the bit line body 111, and the second spacer layer 1122 at least covers the sidewall of the first spacer layer 1111. In an exemplary embodiment of this disclosure, a first spacer layer 1121 covers the sidewalls and top surface of the bit line body 111, and a second spacer layer 1122 covers the sidewalls and top surface of the first spacer layer 1121.

[0068] In an exemplary embodiment of this disclosure, the bit line contact layer 1111 is made of doped polycrystalline silicon, the bit line conductive layer 1112 is made of a combination of at least one or more of titanium nitride, titanium, tungsten nitride, and tungsten, such as a combination of tungsten and titanium nitride, the bit line capping layer 1113 is made of silicon nitride, the first spacer layer 1121 is made of silicon oxide, and the second spacer layer 1122 is made of silicon oxycarbonate having a low dielectric constant. In some embodiments, the method for forming the bit line material stack and the spacer layer 112 may employ at least one of the following deposition methods: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin coating dielectric layer (SOD), in-situ water vapor growth (ISSG), and thermal oxidation growth.

[0069] In some embodiments, photolithography can be used to etch the bit line material stack to form the bit line body 111. Specifically, a photoresist mask layer can be formed on the surface of the bit line material stack. By exposure and development, the pattern of the bit line structure is formed in the photoresist mask layer. Then, dry etching is performed to etch the bit line material stack along the pattern to form the bit line body 111. In some embodiments, before coating the photoresist mask layer, an anti-reflection layer and a hard mask layer (not shown) are formed on the surface of the bit line material stack, and both are removed after the bit line body 111 is formed.

[0070] Then, refer to Figure 5 As shown, where Figure 5 (a) is a top view of the substrate 10 in the opposite direction of the third direction Z. Figure 5 (b) is along Figure 5 (a) is a cross-sectional schematic diagram along the dashed line A-A'. It should be noted that the cross-section along the dashed line A-A' is perpendicular to the top surface of the substrate 10. After forming the bit line structure 11, an initial lower contact material layer 121" is formed between adjacent bit line structures 11. The initial lower contact material layer 121" fills the gap between adjacent bit line structures 11. The initial lower contact material layer 121" also extends along the first direction Y and is arranged parallel to each other at intervals in the second direction X, as shown below. Figure 5 As shown in (a).

[0071] In some embodiments, the material of the initial lower contact material layer 121” may be doped polycrystalline silicon, doped polycrystalline germanium, doped polycrystalline silicon-germanium, or a III-V compound semiconductor material. In an exemplary embodiment of this disclosure, the material of the initial lower contact material layer 121” is doped polycrystalline silicon. In some embodiments, the initial lower contact material layer 121” may be formed by at least one of the following deposition methods: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and spin-coated dielectric layer (SOD).

[0072] Next, referring to Figure 6, where Figure 6 (a) is a top view of the substrate 10 in the opposite direction of the third direction Z. Figure 6 (b) is along Figure 6 (a) is a cross-sectional schematic diagram along the dashed line B-B'. It should be noted that the cross-section along the dashed line B-B' is perpendicular to the top surface of the substrate 10, and the extension direction of the dashed line B-B' is parallel to the first direction Y. A mask layer 120 is formed on the substrate 10. The pattern of the mask layer 120 extends along the second direction X and is arranged in parallel intervals along the first direction Y. The initial lower contact material layer 121” is first etched using the mask layer 120 as a mask to divide the initial lower contact material layer 121” into a plurality of initial lower contact layers 121' arranged at intervals along the first direction Y. The first etching stops at the surface of the substrate 10, forming gaps between the plurality of initial lower contact layers 121'. Part of the sidewall of the bit line structure 11 is exposed by the gap. Specifically, part of the sidewall of the second spacer layer 1122 of the bit line structure 11 is exposed by the gap.

[0073] In some embodiments, a photolithography process can be used to first etch the initial lower contact material layer 121” to form a plurality of initial lower contact layers 121'. Specifically, a photoresist mask layer can be formed on the top surface of the bit line structure 11 and the initial lower contact material layer 121”. By exposure and development, spaced patterns are formed in the photoresist mask layer to obtain a patterned mask layer 120. Then, dry etching is performed to etch the initial lower contact material layer 121” along the patterned mask layer 120 to form a plurality of initial lower contact layers 121'. In some embodiments, before coating the photoresist mask layer, an anti-reflection layer and a hard mask layer (not shown) are also formed on the top surface of the bit line structure 11 and the initial lower contact material layer 121”, and both are removed after the initial lower contact layers 121' are formed.

[0074] Then, refer to Figure 7 As shown, where Figure 7 (a) is a top view of the substrate 10 in the opposite direction of the third direction Z. Figure 7 (b) is along Figure 7 (a) Schematic diagram of the cross section along the dashed line B-B' in the middle. Figure 7 (c) is along Figure 7 (a) Schematic diagram of the cross section along the dashed line C-C'. Figure 7 (d) is along Figure 7 (a) is a schematic cross-sectional view along the dashed line D-D'. It should be noted that the cross-sections along the dashed line B-B', C-C', and D-D' are all perpendicular to the top surface of the substrate 10. The extension direction of the dashed line B-B' is parallel to the first direction Y, and the extension directions of the dashed lines C-C' and D-D' are parallel to the second direction X. An ashing process is performed to remove the mask layer 120 and oxidize the initial lower contact layer 121' towards the first direction Y and its opposite sidewalls, forming an initial protective layer 122'. In an exemplary embodiment of this disclosure, the top surface of the initial lower contact layer 121' is also oxidized; that is, the initial protective layer 122' is located not only on the unoxidized sidewalls of the initial lower contact layer 121' but also on its top surface. In some embodiments, the material of the initial lower contact layer 121' includes doped polysilicon. After the ashing process is performed, the polysilicon in the sidewall of the gap exposed by the portion of the initial lower contact material layer 121' that is removed by the first etching is oxidized to form silicon oxide, thereby forming the initial protective layer 122'.

[0075] In some embodiments, an ashing process is performed, and the second spacer layer 1122 exposed by the gap formed by the portion of the initial lower contact material layer 121” removed by the first etching is also oxidized to form a spacer oxide portion 1122a. In some embodiments, the material of the second spacer layer 1122 includes silicon carbide with a low dielectric constant. After the ashing process is performed, the silicon carbide in the sidewalls of the second spacer layer 1122 exposed by the first etching is oxidized to silicon oxide, thereby forming the spacer oxide portion 1122a. Since the sidewalls of the second spacer layer 1122 that are in contact with the portion of the initial lower contact material layer 121” that was not removed by the first etching (i.e., the retained initial lower contact layer 121’) are not oxidized by the ashing process, the material of the sidewalls of the second spacer layer 1122 presents alternating intervals of silicon oxide and silicon carbide with a low dielectric constant along the first direction Y. In other embodiments, the top surface of the second spacer layer 1122 of the bit line structure 11 is also oxidized, that is, the spacer oxide portion 1122a is also formed on the top surface of the second spacer layer 1122.

[0076] In an exemplary embodiment of this disclosure, the ashing process employs oxygen plasma (O2 plasma) to remove the mask layer 120, which is mainly composed of photoresist organic matter, and simultaneously oxidizes the polysilicon and silicon oxide to form silicon oxide.

[0077] Next, refer to Figure 8 As shown, where Figure 8 (a) is a top view of the substrate 10 in the opposite direction of the third direction Z. Figure 8 (b) is along Figure 8 (a) Schematic diagram of the cross section along the dashed line B-B' in the middle. Figure 8 (c) is along Figure 8 (a) Schematic diagram of the cross section along the dashed line C-C'. Figure 8 (d) is along Figure 8 (a) is a schematic cross-sectional view along the dashed line D-D'. It should be noted that the cross-sections along the dashed line B-B', C-C', and D-D' are all perpendicular to the top surface of the substrate 10. The extension direction of the dashed line B-B' is parallel to the first direction Y, and the extension directions of the dashed lines C-C' and D-D' are both parallel to the second direction X. A barrier layer 13 is formed between adjacent bitline structures 11, filling the gap between adjacent initial lower contact layers 121'.

[0078] In some embodiments, the material of the barrier layer 13 may be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, and silicon carbonitride. In an exemplary embodiment of this disclosure, the material of the barrier layer 13 is silicon nitride. In some embodiments, the deposition method of the barrier layer 13 may be at least one of the following deposition methods: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and spin-coated dielectric layer (SOD).

[0079] Then, refer to Figure 9 As shown, where Figure 9 (a) is a top view of the substrate 10 in the opposite direction of the third direction Z. Figure 9 (b) is along Figure 9 (a) Schematic diagram of the cross section along the dashed line B-B' in the middle. Figure 9 (c) is along Figure 9 (a) Schematic diagram of the cross section along the dashed line C-C'. Figure 9 (d) is along Figure 9 (a) is a schematic cross-sectional view along the dashed line D-D'. It should be noted that the cross-sections along the dashed line B-B', C-C', and D-D' are all perpendicular to the top surface of the substrate 10. The extension direction of the dashed line B-B' is parallel to the first direction Y, and the extension directions of the dashed lines C-C' and D-D' are parallel to the second direction X. A second etching is performed on the initial lower contact layer 121' and the initial protective layer 122' to reduce their height. The remaining initial protective layer 122' serves as the protective layer 122, and the remaining initial lower contact layer 121' serves as the lower contact 121. The protective layer 122 covers the sidewalls of the lower contact 121 facing the first direction Y and its opposite sidewalls.

[0080] In some embodiments, the second etching may employ selective dry etching or wet etching. In some embodiments, the second etching may also employ an etching method that controls the reaction time or uses an Endpoint Detector (EPD) to control the etching depth.

[0081] Next, refer to Figure 10 As shown, where Figure 10(a) is a top view of the substrate 10 in the opposite direction of the third direction Z. Figure 10 (b) is along Figure 10 (a) Schematic diagram of the cross section along the dashed line B-B' in the middle. Figure 10 (c) is along Figure 10 (a) Schematic diagram of the cross section along the dashed line C-C'. Figure 10 (d) is along Figure 10 (a) is a schematic cross-sectional view along the dashed line D-D'. It should be noted that the cross-sections along the dashed line B-B', C-C', and D-D' are all perpendicular to the top surface of the substrate 10. The extension direction of the dashed line B-B' is parallel to the first direction Y, and the extension directions of the dashed lines C-C' and D-D' are parallel to the second direction X. An upper contact material layer 123' is formed on the substrate 10. Specifically, the upper contact material layer 123' covers and fills the remaining space between the adjacent bit line structure 11 and the adjacent gate layer 13 after the second etching, and also covers the top surface of the bit line structure 11 and the gate layer 13 with a certain thickness.

[0082] In some embodiments, the upper contact material layer 123' comprises a metallic conductive material, such as a combination of tungsten, aluminum, nickel, platinum, titanium, tantalum, molybdenum, ruthenium, or any one or more of these as the main body and any one or more of their nitrides as the barrier layer. In an exemplary embodiment of this disclosure, the metallic conductive material of the upper contact 123 is a combination of tungsten and titanium nitride. In some embodiments, the upper contact material layer 123' can be formed by at least one of the following deposition methods: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin coating dielectric layer (SOD), physical vapor deposition (PVD), and sputtering.

[0083] Then, refer to Figure 11 As shown, where Figure 11 (a) is a top view of the substrate 10 in the opposite direction of the third direction Z. Figure 10 (b) is along Figure 10 (a) Schematic diagram of the cross section along the dashed line B-B' in the middle. Figure 10 (c) is along Figure 10(a) is a schematic cross-sectional view along the dashed line D-D'. It should be noted that the cross-sections along the dashed line B-B' and D-D' are perpendicular to the top surface of the substrate 10. The extension direction of the dashed line B-B' is parallel to the first direction Y, and the extension direction of the dashed line D-D' is parallel to the second direction X. The upper contact material layer 123' located outside the adjacent bit line structures 11 is etched to form the upper contact 123, including a first sub-part 123a located between adjacent bit line structures 11 and a second sub-part 123b located outside the adjacent bit line structures 11. The first sub-part 123a and the second sub-part 123b are connected and integrally formed. In the second direction X, the second sub-part 123b is offset from the first sub-part 123a. In the third direction Z, the second sub-part 123b is located above the first sub-part 123a. Figure 11 As shown in (c). In some embodiments, in a plane direction parallel to the surface of the substrate 10, the plurality of first sub-parts 123a are arranged in a tetragonal distribution, while the plurality of second sub-parts 123b are arranged in a hexagonal distribution, as shown in (c). Figure 11 As shown in (a), the upper contact portion 123, the lower contact portion 121, and the protective layer 122 together constitute the storage node contact structure 12. Due to the presence of the protective layer 122, the width of the upper contact portion 123 (i.e., the first sub-part 123a) located between adjacent bit line structures 11 in the first direction Y is greater than the width of the lower contact portion 121, providing more space when filling the upper contact portion material layer 123', and making it less prone to defects such as voids.

[0084] In some embodiments, a photolithography process can be used to etch the upper contact material layer 123' located outside the adjacent bit line structures 11 to form the upper contact 123. Specifically, a photoresist mask layer can be formed on the surface of the upper contact material layer 123'. By exposure and development, the pattern of the second sub-part 123b is formed in the photoresist mask layer. Then, dry etching is performed to etch the upper contact material layer 123' along the pattern to form upper contacts 123 that are disconnected from each other. In some embodiments, before coating the photoresist mask layer, an anti-reflective layer and a hard mask layer (not shown) are also formed on the surface of the upper contact material layer 123', and both are removed after the upper contact 123 is formed.

[0085] Subsequently, such as Figure 12As shown, a storage node 15 is formed on a substrate 10. A first support layer 141, a second support layer 142, and a third support layer 143 are interposed in the storage node 15. A conductive electrode plate 16 covers the surface of the storage node 15, an interlayer dielectric layer 18 covers the surface of the conductive electrode plate 16, and a contact 17 penetrates the interlayer dielectric layer 18 and is inserted into the conductive electrode plate 16 for electrical connection. In some embodiments, the storage node 15 is a storage capacitor structure, including a first electrode layer 151, a capacitor dielectric layer 152, and a second electrode layer 153 stacked sequentially.

[0086] In some embodiments, the materials of the first support layer 141, the second support layer 142, and the third support layer 143 may be silicon nitride. In some embodiments, the materials of the first electrode layer 151 and the second electrode layer 153 of the storage node 15 may be a combination of one or more of titanium nitride, tantalum nitride, and silicon-doped titanium nitride; the material of the capacitor dielectric layer 152 of the storage node 15 may be a combination of at least one or more of zirconium oxide (ZrO2) and aluminum oxide (Al2O3). In other embodiments, the capacitor dielectric material may also be a combination of at least one or more of silicon oxide (SiO2), hafnium oxide (HfO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (STO), and lead titanate (PZT). In some embodiments, the material of the contact 17 may be tungsten, copper, or other metals with good conductivity; the material of the conductive electrode plate 16 may be doped polycrystalline silicon or doped polycrystalline silicon germanium; and the material of the interlayer dielectric layer 18 may be silicon oxide. In some embodiments, the formation of each support layer, storage node 15, conductive electrode plate 16, contact 17, and interlayer dielectric layer 18 may employ at least one of the following deposition methods: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin coating dielectric layer (SOD), physical vapor deposition (PVD), and sputtering.

[0087] The semiconductor structure formed by the semiconductor structure formation method provided in this disclosure has the following advantages: First, the sidewalls of the bit line structure and the memory node contact structure are made of a low dielectric constant material, which can reduce the parasitic capacitance or resistance between adjacent bit line structures and memory node contact structures, as well as between adjacent bit lines, due to the small distance between them, thereby reducing interference or coupling effects between adjacent structures in the working state. Second, in the first direction, the width of the upper contact portion of the memory node contact structure is larger than the width of the lower contact portion, making it less likely for voids to be generated in the formed memory node contact structure when filling the memory node contact material, thereby improving the conductivity and process reliability of the memory node contact structure and improving the yield of semiconductor devices.

[0088] It should be noted that the semiconductor structure in this embodiment can be used to fabricate DRAM devices, or other devices that require the formation of capacitor structures or conductive plates in different regions, without further limitations.

[0089] The various semiconductor structures illustrated in this specific embodiment can be used in electronic devices with storage functions. These electronic devices can be terminal devices, such as mobile phones, tablets, and smart bracelets, or personal computers (PCs), servers, workstations, etc. The storage function in these electronic devices can be implemented using the following types of memory: Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), Magnetic Random Access Memory (MRAM), or Resistive Random Access Memory (RRAM).

[0090] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized by, include: Substrate; Multiple bit line structures are located on the substrate surface. The multiple bit line structures extend along a first direction and are spaced apart along a second direction. The first direction and the second direction are perpendicular to each other and both are parallel to the substrate surface. A memory node contact structure is located between adjacent bit line structures. The memory node contact structure includes a lower contact portion and an upper contact portion stacked together. The bottom surface of the lower contact portion contacts the substrate, and the bottom surface of the upper contact portion contacts the top surface of the lower contact portion. The upper contact portion includes a metal conductive material, and the lower contact portion includes a semiconductor conductive material. In the first direction, the width of the upper contact portion located between adjacent bit line structures is greater than the width of the lower contact portion; the sidewall of the bit line structure adjacent to the memory node contact structure comprises a low dielectric constant material.

2. The semiconductor structure of claim 1, wherein, The semiconductor structure includes: a plurality of memory node contact structures located between adjacent bit line structures and spaced apart along the first direction.

3. The semiconductor structure of claim 2, wherein, The semiconductor structure further includes a gate layer located between adjacent bit line structures and also between adjacent memory node contact structures, the gate layer comprising a material including silicon nitride.

4. The semiconductor structure of claim 3, wherein, The storage node contact structure also includes a protective layer that covers only the sidewall of the lower contact portion adjacent to the fence layer, and the material of the protective layer includes silicon oxide.

5. The semiconductor structure of claim 3, wherein, The bitline structure includes a bitline body and a spacer layer that covers at least the sidewalls of the bitline body; The bit line body includes a bit line contact layer, a bit line conductive layer and a bit line capping layer stacked together. A portion of the bottom surface of the bit line contact layer is in contact with the substrate, the bottom surface of the bit line conductive layer is in contact with the top surface of the bit line contact layer, and the bottom surface of the bit line capping layer is in contact with the top surface of the bit line conductive layer. The spacer layer includes a first spacer layer stacked on top of the first spacer layer and a second spacer layer located outside the first spacer layer. The first spacer layer at least covers the sidewall of the bit line body, and the second spacer layer at least covers the sidewall of the first spacer layer.

6. The semiconductor structure of claim 5, wherein, Also includes: The first spacer layer is made of silicon oxide, and the second spacer layer is made of silicon oxide and the low dielectric constant material spaced apart in the first direction.

7. The semiconductor structure according to claim 6, characterized in that, The material of the portion of the second spacer layer adjacent to the fence layer is silicon oxide, and the material of the portion of the second spacer layer adjacent to the storage node contact structure is the low dielectric constant material.

8. The semiconductor structure according to claim 1, characterized in that, The low dielectric constant material includes silicon oxide.

9. The semiconductor structure according to any one of claims 1-8, characterized in that, Also includes: A storage transistor structure is located on the surface of the substrate. The storage transistor structure includes a first source and drain that are in contact with and electrically connected to a bit line structure, and a second source and drain that are in contact with and electrically connected to a storage node contact structure. A word line structure is located in the substrate and extends along the second direction, serving as the gate of the storage transistor structure or being electrically connected to the gate of the storage transistor structure. A storage node structure is located on the substrate and is in contact with and electrically connected to the top surface of the storage node contact structure.

10. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A plurality of bit line structures are formed on the surface of the substrate, the plurality of bit line structures extending along a first direction and spaced apart along a second direction, the first direction and the second direction being perpendicular to each other and both parallel to the surface of the substrate; A memory node contact structure is formed between adjacent bit line structures. The memory node contact structure includes a lower contact portion and an upper contact portion stacked together. The bottom surface of the lower contact portion contacts the substrate, and the bottom surface of the upper contact portion contacts the top surface of the lower contact portion. The upper contact portion includes a metal conductive material, and the lower contact portion includes a semiconductor conductive material. In the first direction, the width of the upper contact portion located between adjacent bit line structures is greater than the width of the lower contact portion; the sidewall of the bit line structure adjacent to the memory node contact structure comprises a low dielectric constant material.

11. The method for fabricating a semiconductor structure according to claim 10, characterized in that, Forming a plurality of bit line structures on the surface of the substrate includes: forming a plurality of bit line bodies and at least a spacer layer covering the sidewalls of each bit line body on the surface of the substrate; The bit line body is formed by sequentially forming a bit line contact layer, a bit line conductive layer and a bit line capping layer on the surface of the substrate. A portion of the bottom surface of the bit line contact layer is in contact with the substrate, the bottom surface of the bit line conductive layer is in contact with the top surface of the bit line contact layer, and the bottom surface of the bit line capping layer is in contact with the top surface of the bit line conductive layer. The formation of the spacer layer includes sequentially forming a first spacer layer and a second spacer layer located outside the first spacer layer. The first spacer layer at least covers the sidewall of the bit line body, and the second spacer layer at least covers the sidewall of the first spacer layer. The material of the second spacer layer includes the low dielectric constant material, which includes silicon oxycarbonate.

12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, Forming a memory node contact structure between adjacent bit line structures includes forming a lower contact portion and an upper contact portion stacked sequentially on the substrate surface between adjacent bit line structures.

13. The method for fabricating a semiconductor structure according to claim 12, characterized in that, A lower contact portion and an upper contact portion are formed sequentially on the substrate surface between adjacent bit line structures, including: An initial lower contact material layer is formed between adjacent bit line structures, and the initial lower contact material layer fills the gap between adjacent bit line structures; The initial lower contact material layer is first etched to divide the initial lower contact material layer into a plurality of initial lower contact layers spaced apart along the first direction; Performing an ashing process includes: oxidizing the initial lower contact layer toward the first direction and its opposite sidewall to form an initial protective layer; A second etching is performed on the initial lower contact layer and the initial protective layer to reduce the height of the initial lower contact layer and the initial protective layer, wherein the remaining initial protective layer serves as a protective layer, the remaining initial lower contact layer serves as the lower contact, and the protective layer covers the sidewalls of the lower contact facing the first direction and the opposite sidewall; The upper contact portion is formed on the lower contact portion.

14. The method for fabricating a semiconductor structure according to claim 13, characterized in that, Performing the ashing process further includes oxidizing the second spacer layer exposed by the portion of the initial lower contact material layer removed by the first etching.

15. The method for fabricating a semiconductor structure according to claim 13, characterized in that, After performing the ashing process and before performing the second etching, the method further includes: forming a fence layer between adjacent bit line structures, the fence layer filling the gap between adjacent initial lower contact layers.

16. The method for fabricating a semiconductor structure according to any one of claims 10-15, characterized in that, Also includes: A storage transistor structure is formed on the surface of the substrate. The storage transistor structure includes a first source and drain that are in contact with and electrically connected to a bit line structure, and a second source and drain that are in contact with and electrically connected to a storage node contact structure. A word line structure is formed in the substrate, the word line structure extending along the second direction, serving as the gate of the storage transistor structure or electrically connected to the gate of the storage transistor structure; A storage node structure is formed on the substrate, and the storage node structure is in contact with and electrically connected to the top surface of the storage node contact structure.

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