Multi-well region integrated resistance element and electronic device thereof

Abstract

An integrated resistive element and its electronic device are suitable for configuration as an integrated sensing unit. The integrated resistive element includes multiple resistive segments, each including a first portion disposed in or on a first well region formed in a substrate and a second portion disposed in or on a second well region. The second portion is used for electrical coupling between a first terminal of the integrated resistive element and a sensing terminal. The first portion is used for electrical coupling between the sensing terminal and the second terminal of the integrated resistive element. The first well region is configured to be biased by a first well region bias circuit. The second well region is configured to be biased by a second well region bias circuit.

Description

Technical Field

[0001] This disclosure relates generally to electrical equipment, and more specifically, but not limited to, integrated resistive elements and related electronic devices. Background Technology

[0002] With the increasing demand for higher integration density in electrical / electronic equipment, resistive sensing circuits such as resistive voltage dividers are being integrated into integrated circuits (ICs), such as those formed within semiconductor chips and integrated with other circuit components. Resistive voltage dividers are typically used to detect the voltage applied across them to provide a sense voltage. This sense voltage reflects the voltage applied across the divider and can be used for applications such as controlling equipment operation. Some applications are extremely sensitive to the sense signal from resistive sensing circuits, thus requiring integrated resistive sensing circuits with higher detection accuracy. Summary of the Invention

[0003] To address one or more of the aforementioned problems, an integrated resistive element according to an embodiment of the present disclosure includes a first well region of a second conductivity type formed in a substrate of the first conductivity type, the second conductivity type being opposite to the first conductivity type; a second well region of the second conductivity type formed in the substrate, wherein the second well region is separated from and electrically isolated from the first well region; and a first set of resistive segments including a first portion disposed in or on the first well region and a second portion disposed in or on the second well region; wherein the second portion is used for electrical coupling between a first terminal and a sensing terminal of the integrated resistive element; and wherein the first portion is used for electrical coupling between the sensing terminal and the second terminal of the integrated resistive element; and wherein the first well region is configured to be biased by a first well region bias circuit, or the second well region is configured to be biased by a second well bias circuit.

[0004] According to one embodiment of the power management device of the present disclosure, it includes a first resistive sensing unit comprising a first integrated resistive element as described in any embodiment of the present disclosure, wherein a first terminal of the first integrated resistive element is electrically connected to an output terminal of the power management device to receive an output signal, a second terminal is electrically connected to a reference ground, and the sensing terminal is used to provide a feedback signal indicating the output signal; or a second resistive sensing unit comprising a second integrated resistive element as described in claim 1, wherein a first terminal of the second integrated resistive element is operatively electrically connected to an input terminal of the power management device to receive an input signal, a second terminal of the second integrated resistive element is operatively electrically connected to a reference ground, and the sensing terminal of the second integrated resistive element is operatively provided with a feedforward signal indicating the input signal.

[0005] An electronic device including an audio amplifier according to an embodiment of the present disclosure includes a resistive sensing unit comprising an integrated resistive element as described in any embodiment of the present disclosure, the resistive sensing unit being coupled between a signal input terminal and a signal output terminal of the audio amplifier, wherein the resistive sensing unit is configured to provide an audio feedback signal indicating the difference between an output signal at the signal output terminal and an input signal at the signal input terminal. Attached Figure Description

[0006] To better understand this disclosure, embodiments of the disclosure will be described with reference to the following accompanying drawings, which are for illustrative purposes only. The drawings typically show only some features of the embodiments and are not necessarily drawn to scale. The same reference numerals in different schematic diagrams denote the same or similar parts or features.

[0007] Figure 1 A top view layout schematic diagram of an integrated resistive element 100 according to an embodiment of the present disclosure is shown.

[0008] Figure 2 A schematic diagram 200 of an equivalent circuit of an integrated resistive element 100 according to an embodiment of the present disclosure is shown, the element being configured as a reference. Figure 1 The resistive sensing unit described in the example.

[0009] Figure 3 A waveform diagram 300 according to an embodiment of the present disclosure is shown, illustrating the corresponding curve 301 of the actual sensed voltage Vs on the integrated resistive element 100 and the corresponding curve 302 of Vs and Vab under the theoretical ideal state.

[0010] Figure 4 A top view layout schematic diagram of an integrated resistive element 400 according to an embodiment of the present disclosure is shown.

[0011] Figure 5 A partial cross-sectional view of an integrated resistive element 400 according to an embodiment of the present disclosure is shown.

[0012] Figure 6 A partial cross-sectional view of an integrated resistive element 400 according to an alternative embodiment of the present disclosure is shown.

[0013] Figure 7 A schematic diagram 700 of the equivalent circuit of an integrated resistive element 400 according to an embodiment of the present disclosure is shown, the element being configured for reference. Figure 4 , Figure 5 and Figure 6 The example shown describes a resistive sensing unit.

[0014] Figure 8Waveform diagram 800 is shown, which shows the actual curve 801 (i.e., the relationship between the sensed voltage Vs and the voltage Vab across the integrated resistive element 400) and the theoretical ideal curve 802 (i.e., the relationship between the ampere voltage Vs and the voltage Vab across the integrated resistive element 400).

[0015] Figure 9 A top view layout schematic diagram of an integrated resistive element 900 according to an embodiment of the present disclosure is shown.

[0016] Figure 10 A schematic diagram 1000 of the equivalent circuit of an integrated resistive element 900 according to an embodiment of the present disclosure is shown, the element being configured for reference. Figure 9 The example shown describes a resistive sensing unit.

[0017] Figure 11 A schematic diagram 1100 of an equivalent circuit of an integrated resistive element 900 configured as a resistive sensing unit is shown according to an alternative embodiment of the present disclosure.

[0018] Figure 11A A top view layout schematic diagram of an integrated resistive element 100A according to an exemplary embodiment of the present disclosure is shown.

[0019] Figure 11B A schematic diagram 100B of the equivalent circuit of an integrated resistive element 100A configured as a resistive sensing unit according to an embodiment of the present disclosure is shown.

[0020] Figure 12 A top view layout schematic diagram of an integrated resistive element 1200 according to an embodiment of the present disclosure is shown.

[0021] Figure 13 A schematic diagram 1300 of an equivalent circuit of an integrated resistive element 1200 according to an embodiment of the present disclosure is shown, the element being configured for reference. Figure 12 The example shown describes a resistive sensing unit.

[0022] Figure 14 A partial cross-sectional view of an integrated resistive element 1200 according to an embodiment of the present disclosure is shown.

[0023] Figure 15 A partial cross-sectional view of an integrated resistive element 1200 according to an alternative embodiment of the present disclosure is shown.

[0024] Figure 16 A schematic diagram of the equivalent circuit 1600 of an integrated resistive element 1600 configured as a resistive sensing unit according to an embodiment of the present disclosure is shown.

[0025] Figure 17A schematic diagram of the equivalent circuit 1700 of an integrated resistive element 1700 configured as a resistive sensing unit according to an embodiment of the present disclosure is shown.

[0026] Figure 18 A top view layout schematic diagram of an integrated resistive element 1800 according to an embodiment of the present disclosure is shown.

[0027] Figure 18A A top view layout schematic diagram of an integrated resistive element 1800A according to another embodiment of the present disclosure is shown.

[0028] Figure 19 A partial cross-sectional view of an integrated resistive element 1800 according to an embodiment of the present disclosure is shown.

[0029] Figure 20 An integrated resistive element 1800 according to an embodiment of this disclosure is shown as... Figure 18 and Figure 19 The equivalent circuit diagram of the resistive sensing unit configuration shown in the example is 2000.

[0030] Figure 20A A schematic diagram 2000A of the equivalent circuit of an integrated resistive element 1800A according to an embodiment of the present disclosure is shown, the element being configured as a reference. Figure 18A The example shown describes a resistive sensing unit.

[0031] Figure 21 A block diagram of a power management device 2100 according to an embodiment of the present disclosure is shown.

[0032] Figure 22 A block diagram of a power management device 2200 according to an alternative embodiment of the present disclosure is shown.

[0033] Figure 23 A block diagram of a power management device 2300 according to an alternative embodiment of the present disclosure is shown.

[0034] Figure 24 A block diagram of a power management device 2400 according to an alternative embodiment of the present disclosure is shown.

[0035] Figure 25 Waveform diagrams of several signals during operation of a power management device 2400 according to an embodiment of the present disclosure are shown.

[0036] Figure 26 A block diagram of a linear voltage regulator 2600 according to an embodiment of the present disclosure is shown.

[0037] Figure 27 A block diagram of an audio amplifier 2700 according to an embodiment of the present disclosure is shown.

[0038] Figure 28A waveform diagram 2800 according to an embodiment of the present disclosure is shown, in which the actual curve 2801 of the amplification gain G1 amplitude of the audio amplifier 2700 versus the input signal Vsig is shown, and the theoretical ideal curve 2802 of the amplification gain G1 amplitude of the audio amplifier 2700 versus the input signal Vsig is shown.

[0039] Figure 29 A block diagram of an audio amplifier 2900 according to another embodiment of the present disclosure is shown.

[0040] Figure 30 A waveform diagram 3000 according to an embodiment of the present disclosure is shown, which shows the relationship between the actual curve 3001 of the amplification gain G2 of the audio amplifier 2900 and the input signal Vsig, and the relationship between the theoretical ideal curve 3002 of the amplification gain G2 of the audio amplifier 2900 and the input signal Vsig. Detailed Implementation

[0041] Specific embodiments of this disclosure will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure. In the following description, numerous specific details are set forth in order to provide a thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that these specific details are not necessary to implement this disclosure. In other embodiments, well-known circuits, materials, or methods have not been specifically described to avoid obscuring this disclosure.

[0042] In this specification and claims, the use of terms such as "left," "right," "inner," "outer," "upper," "lower," "above," and "below" is merely for descriptive convenience and does not indicate a necessary or permanent relative position of components / structures. Those skilled in the art should understand that such terms are interchangeable where appropriate, for example, so that embodiments of this disclosure can still operate in orientations different from those described in this specification. In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, the terms "coupled" and "connected" mean a direct or indirect electrical or non-electrical connection. "A / this / that" is not used to specifically refer to the singular but may encompass the plural form. Phrases such as "an embodiment," "an example," "an example," and "example" appearing throughout the specification do not necessarily refer to the same embodiment or example. Those skilled in the art should understand that the various specific features, structures, parameters, steps, etc., disclosed in one or more embodiments of this disclosure can be combined in any suitable manner. The term “and / or” as used herein includes any and all combinations of one or more of the related listed items.

[0043] When a field-effect transistor (FET) or a bipolar junction transistor (BJT) is used as an embodiment of a transistor, the ranges for “gate,” “drain,” and “source” respectively include “base,” “collector,” and “emitter,” and vice versa. The term “based on” is non-exclusive, allowing for a basis based on additional factors not described unless explicitly required by the context. The term “circuit” refers at least to a single element or a combination of multiple elements (including active and / or passive devices) coupled together to achieve a specific function. The term “signal” refers at least to current, voltage, charge, temperature, data, or other signals. Those skilled in the art will understand that the meanings of the above terms are not necessarily limiting, but merely illustrative examples.

[0044] It should be noted that when a component is described as "fixed to" or "set on" another component, it can be directly on the other component or there may be an intervening component. When a component is described as "connected to" another component, it can be directly connected to the other component or there may be an intervening component.

[0045] Furthermore, if this disclosure uses terms such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of a person skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this disclosure.

[0046] For ease of illustration, this disclosure may select specific semiconductor devices as examples, but this is not intended to be limiting. Those skilled in the art should understand that the structures and principles described herein are equally applicable to other semiconductor devices.

[0047] Figure 1 A top view layout schematic diagram of an integrated resistive element 100 according to an embodiment of the present disclosure is shown. For illustration... Figure 1The integrated resistive element 100 is shown in a coordinate system defined by mutually perpendicular x, y, and z axes, and a perspective view is shown as observed from a conductive wiring layer (such as a metal wiring layer of the integrated resistive element) in the xy plane. The integrated resistive element 100 is formed on or within a semiconductor substrate 103 of a semiconductor chip. In one embodiment, the conductive wiring layer may relate to or constitute part of a conductive wiring structure, which may include one or more conductive wiring layers formed on the substrate 103. An inter-layer dielectric layer (IDL) may be formed between any two adjacent conductive wiring layers of the conductive wiring structure (i.e., adjacent conductive wiring layers along the z-axis). It should be noted that the view viewed from the xy plane in this disclosure may be referred to as a plan view, while the view viewed in section along the z-axis may be referred to as a cross-sectional view. For clarity, Figure 1 The interlayer dielectric layer is not shown, and the conductive wiring layer closest to substrate 103 (relative to other conductive wiring layers in the conductive wiring structure) along the z-axis is highlighted. In one embodiment, semiconductor substrate 103 may be of a first conductivity type, such as P-type in the example. In one embodiment, semiconductor substrate 103 may include one or more semiconductor materials, such as Si, Ge, SiC, or other forms of semiconductor layers. Substrate 103 may also be a silicon-on-insulator (SOI) substrate or other substrate forms compatible with the operation and manufacturing processes of integrated resistive element 100.

[0048] The integrated resistive element 100 may include multiple resistive segments 101_1, 101_2, ..., 101_6 and a well region 102. The well region 102 is formed in a semiconductor substrate 103. The well region 102 may have a second conductivity type opposite to the first conductivity type. For example, in one embodiment, the well region 102 may be N-type. The well region 102 may be electrically connected to a well region bus 102L and / or a well region terminal 102T, thereby achieving electrical coupling with other signal or circuit elements. In one embodiment, the well region bus 102L and the well region terminal 102T may be formed on different conductive wiring layers (e.g., different metal wiring layers) on the substrate 103. Figure 1 As shown, the well bus 102L may be formed on a first conductive wiring layer (e.g., a first metal wiring layer), which is represented by wiring traces filled with sparse diagonal lines; while the well terminal 102T may be formed on a second conductive wiring layer (e.g., a second metal wiring layer), which is represented by wiring traces filled with denser diagonal lines.

[0049] In one embodiment, reference is made to Figure 1As shown in the example, well region 102 can be electrically coupled to well region bus 102L via a plurality of interlayer wiring elements, such as interlayer vias VIA1 formed, for example, in a first interlayer dielectric layer (IDL) disposed between substrate 103 and well bus 102L (or a first conductive wiring layer including well bus 102R). Figure 1 (As shown in the multiple small squares), where multiple interlayer vias VIA2 are filled with conductive material. The well bus 102L and the well terminal 102T can be electrically connected (e.g., vias VIA2 formed in the second interlayer dielectric layer) through one or more interlayer wiring elements. Figure 1 (As shown in multiple small squares), the second interlayer dielectric layer is disposed above the first interlayer dielectric layer or between the first and second conductive wiring layers, wherein one or more interlayer vias VIA2 are filled with conductive material. In one embodiment, as... Figure 1 As shown, when viewed in a planar view (i.e., from an xy-plane view), the well bus 102L can be routed above the periphery (or boundary) of the well 102.

[0050] In one embodiment, still referring to Figure 1 Multiple resistor segments 101_1, 101_2, ..., 101_6 are disposed within or on the well region 102, for example, located within the periphery (or boundary) of the well region 102, and may be arranged in an array or matrix. In one embodiment, the multiple resistor segments 101_1, 101_2, ..., 101_6 may be substantially identical in geometry and / or size. That is, the shape and / or size of the multiple resistor segments 101_1, 101_2, ..., 101_6 are substantially consistent with the remaining resistor segments, for example, in one embodiment the error range is controlled within ±2%. Therefore, those skilled in the art can fully understand that the multiple resistor segments 101_1, 101_2, ..., 101_6 have substantially the same resistance value. That is, the resistance value of any one of the multiple resistor segments 101_1, 101_2, ..., 101_6 may be substantially consistent with the resistance values ​​of the remaining resistor segments. Multiple resistor segments 101_1, 101_2, ..., 101_6 can be electrically connected to each other. For example, in addition to the well bus 102L, the first conductive wiring layer (e.g., the first metal wiring layer) of the integrated resistive element 100 also includes multiple conductive connection segments 101L for electrically connecting the multiple resistor segments 101_1, 101_2, ..., 101_6 to each other. Figure 1In the exemplary embodiment shown, when viewed from a plan view (i.e., an xy-plane view), the well bus 102L may be laid around a plurality of conductive connection segments 101L. In one embodiment, each of the plurality of conductive connection segments 101L may include a metal connection segment. Each of the plurality of conductive connection segments 101L may be electrically connected to the ends of any two adjacent resistive segments of a plurality of resistive segments 101_1, 101_2, ..., 101_6. For example, electrical connections are achieved through a plurality of interlayer wiring elements (such as interlayer vias VIA1) formed in a first interlayer dielectric layer located between the substrate 103 and the first conductive wiring layer. Although Figure 1 The example shows six resistor segments 101_1, 101_2, ..., 101_6, but those skilled in the art will understand that the integrated resistor element 100 may include any number of resistor segments depending on the actual application and / or design requirements.

[0051] The integrated resistor element 100 may have a first terminal 101A and a second terminal 101B for enabling connection of the resistor element 100 to other signal or circuit elements. Multiple resistor segments 101_1, 101_2, ..., 101_6 are electrically connected in series between the first terminal 101A and the second terminal 101B of the integrated resistor element 100. Figure 1 In the exemplary embodiment shown, the first terminal 101A and the second terminal 101B of the integrated resistive element 100 may be formed in a second conductive wiring layer (e.g., a second metal wiring layer) including a well terminal 102T. The first terminal 101A may be connected to the end resistive segment (e.g., in an array or matrix of resistive segments) in the resistor segment array or matrix. Figure 1 In the example, an electrical connection is established in the segment labeled 101_6. This array includes multiple resistor segments 101_1, 101_2, ..., the last resistor segment of 101_6. For example, the electrical connection is achieved through one or more of the following methods: via one or more interlayer wiring elements (such as interlayer vias VIA2) formed in the second interlayer dielectric layer. Figure 1 (Illustrated by multiple small squares); conductive connection segments in the first conductive wiring layer; one or more interlayer wiring elements formed in the first interlayer dielectric layer, such as interlayer vias VIA1 (e.g. Figure 1 (As shown in the multiple small squares), the first interlayer dielectric layer is disposed between the first conductive wiring layer and the substrate 103. Similarly, the second terminal 101B can be electrically connected to the first resistor segment in an array or matrix of multiple resistor segments 101_1, 101_2, ..., 101_6 (e.g., as shown in the multiple small squares). Figure 1 The resistor segment marked 101_1 shown can be used, for example, through one or more interlayer wiring elements formed in the second interlayer dielectric layer, such as interlayer vias VIA2 (e.g., Figure 1(As shown in the multiple small squares), conductive connection segments in the first conductive wiring layer, and interlayer wiring units formed in the first interlayer dielectric layer, such as interlayer vias VIA1, the first interlayer dielectric layer being disposed between the first conductive wiring layer and the substrate 103.

[0052] The resistance value of the integrated resistive element 100 typically depends on the bias voltage Vbs applied to the well region 102 (e.g., applied to the well region through the well region terminal 102T) and the voltage Vab across the resistive element 100, which is the voltage difference between the first voltage Vtop and the second voltage Vbot applied to the first terminal 101A and the second terminal 101B of the integrated resistive element 100. In this example, Vab = Vtop - Vbot.

[0053] In one embodiment, the integrated resistive element 100 may be configured to form a resistive sensing unit to provide a sensed voltage Vs indicating the voltage Vab across the integrated resistive element 100, wherein a second voltage Vbot on the second terminal 101B is taken as the reference potential of the resistive sensing unit (including all sub-circuits and components that the resistive sensing unit may include). That is, Vs = Ga * Vab + Vbot = Ga * (Vtop - Vbot) + Vbot, where Ga is the sensing gain of the resistive sensing unit. Those skilled in the art will understand that the first voltage Vtop, the second voltage Vbot, and the sensed voltage Vs are all ground potentials relative to the reference ground GND. In one embodiment, for example, the second terminal 101B of the integrated resistive element 100 may be connected to the reference ground GND, which means that the second voltage Vbot is set to ground potential (i.e., Vbot = 0V), so in this example, Vs = Ga * Vab = Ga * Vtop.

[0054] In one embodiment, a sensing terminal 101S is disposed between a first portion 101_R1 and a second portion 101_R2 of a plurality of resistive segments 101_1, 101_2, ..., 101_6. The sensing terminal 101S can be electrically connected from an integrated resistive element 100 to provide a sensing voltage Vs at the sensing terminal 101S. The sensing terminal 101S is electrically coupled to the first portion 101_R1 and the second portion 101_R2. The first portion 101_R1 may include a first group of resistive segments among the plurality of resistive segments 101_1, 101_2, ..., 101_6. The second portion 101_R2 may include a second group of resistive segments among the plurality of resistive segments 101_1, 101_2, ..., 101_6. Figure 1In the example, the first portion 101_R1 or the first group of resistor segments exemplarily includes resistor segment 101_1, while the second portion 101_R2 or the second group of resistor segments exemplarily includes resistor segments 101_2, ..., 101_6. The sensing terminal 101S can be electrically connected to the starting resistor segment of the second group of resistor segments 101_2, ..., 101_6 included in the second portion 101_R2 (e.g., ...). Figure 1 The resistor segment marked 101_2 in the example, for example, via Figure 1 The embodiments include one or more interlayer wiring elements formed in the second interlayer dielectric layer, such as interlayer vias VIA2 (illustrated as multiple small squares), conductive connection segments in the first conductive wiring layer, and interlayer wiring elements formed in the first interlayer dielectric layer, such as interlayer vias VIA1 (e.g., in...). Figure 1 (represented by multiple small squares), the first interlayer dielectric layer is disposed between the first conductive wiring layer and the substrate 103. Similarly, according to Figure 1 In this embodiment, the sensing terminal 101S can be connected to the end resistor segment (e.g., in the first portion 101_R1 of the first group of resistor segments 101_1) Figure 1 The segment marked 101_1 in the example is electrically connected. For example, it can be connected via one or more interlayer wiring elements formed in the second interlayer dielectric layer, such as interlayer vias VIA2 (e.g., Figure 1 (represented by multiple small squares), conductive connection segments in the first conductive wiring layer, and one or more interlayer wiring elements formed in the first interlayer dielectric layer, such as interlayer vias VIA1 (e.g., in...). Figure 1 (Represented by multiple small squares in the diagram), the first interlayer dielectric layer is disposed between the first conductive wiring layer and the substrate 103. However, this is for illustrative and exemplary purposes only to help those skilled in the art understand the embodiments of this disclosure and is not intended to be limiting. For example, in other embodiments, the first portion 101_R1 or the first group of resistor segments may include multiple resistor segments. The number of the first group of resistor segments in the first portion 101_R1 and the number of the second group of resistor segments in the second portion 101_R2 can be reasonably selected according to actual application or design requirements, for example, depending on the sensing gain Ga of the resistive sensing unit to be implemented. The sensing gain Ga of the resistive sensing unit can be expressed as: Ga = (Vs - Vbot) / Vab. The accuracy of the sensing voltage Vs depends on the linearity of the resistance ratio K between the first resistor R1 in the first portion 101_R1 and the second resistor R2 in the second portion 101_R2, and the linearity of the resistance ratio K depends on the bias voltage Vbs applied to the well terminal 102T of the well region 102 and the voltage Vab across the integrated resistive element 100. In this example, the resistance ratio K can be expressed as K = R2 / R1. The first resistance R1 depends on the number of resistance segments contained in the first part 101_R1, and the second resistance R2 depends on the number of resistance segments contained in the second part 101_R2.

[0055] Figure 2 FIG. 2 shows an equivalent circuit schematic diagram 200 of an integrated resistor element 100 according to an embodiment of the present disclosure. The integrated resistor element is configured as a resistive sensing unit described in reference to Figure 1 the examples.

[0056] Figure 3 FIG. 3 shows a waveform diagram 300, which shows the actual curve 301 of the sensing voltage Vs and the voltage Vab on the integrated resistor element 100, and the theoretical ideal curve 302 of the sensing voltage Vs and the voltage Vab on the integrated resistor element 100 when the bias voltage Vbs applied to the well region 102 is set to the first voltage Vtop or the second voltage Vbot. As shown by the actual curve 301, when the bias voltage Vbs applied to the well region 102 is set to the first voltage Vtop or the second voltage Vbot, in practical applications, the sensing voltage Vs may not vary linearly with the voltage Vab across the integrated resistor element 100. And according to the actual application requirements, when the voltage Vab across the integrated resistor element 100 increases and / or the required sensing voltage Vs relatively decreases (for example: in one example, Vs < Vab / 3 or Ga < 1 / 3; in another example, Vs < Vab / 10 or Ga < 1 / 10; or in another example, Vs < Vab / 20 or Ga < 1 / 20), the non-linearity will become more obvious. However, it is expected or desired that the actual curve 301 should approach or match the ideal curve 302 infinitely, so that the sensing voltage Vs provided by the resistive sensing unit can accurately indicate the voltage Vab across the integrated resistor element 100 based on the resistance ratio K in a substantially simple linear relationship. Those skilled in the art can understand that the well region terminal 102T for receiving the bias voltage Vbs can at least to some extent improve the linearity of the resistance ratio K between multiple parts (such as the first part 101_R1 and the second part 101_R2 in the example) in the integrated resistor element (such as 100), for example, by setting the bias voltage Vbs to a value between the first voltage Vtop and the second voltage Vbot. In another embodiment, when the integrated resistor element (such as 100) of the present disclosure constitutes a resistive sensing unit, by adjusting or tuning the bias voltage Vbs, for example, setting the bias voltage Vbs to a value between the first voltage Vtop and the second voltage Vbot, at least the measurement accuracy of the sensing voltage Vs (for example, the linearity of the relationship between the sensing voltage Vs and the voltage Vab) can be effectively improved.

[0057] Figure 4 FIG. shows a top view layout schematic diagram of an integrated resistor element 400 according to an embodiment of the present disclosure. Figure 5 FIG. shows a partial cross-sectional view of an integrated resistor element 400 according to an embodiment of the present disclosure. Figure 6 FIG. shows a partial cross-sectional view of an integrated resistor element 400 according to an alternative embodiment of the present disclosure. It should be noted that Figure 5 and Figure 6 The sectional view shown can be considered as along... Figure 4 The cross-section cut by cutting line A-A' in the top view. To avoid obscuring certain features of certain embodiments, Figure 4 The top view does not show multilayer wiring elements (such as interlayer vias VIA1 filled with conductive material) formed within the first interlayer dielectric layer (IDL), but in combination with... Figure 1 , Figure 5 and Figure 6 Its structure can be fully understood.

[0058] The integrated resistor element 400 may include multiple resistor segments 101_1, ..., 101_N. For example... Figure 4 In the example shown, the total number of resistor segments 101_1,…,101_N included in the integrated resistor element 400 is more generally represented by the variable N. This variable N is an integer greater than 1, and its specific value can be selected or designed according to the actual application and / or design requirements. Those skilled in the art will understand that most of the description of the integrated resistor element 100 also applies to the integrated resistor element 400, except that the total number of resistor segments 101_1,…101_N included in the integrated resistor element 400 is extended to be more generally represented by the variable N. Figure 5 and Figure 6 The cross-sectional view shown provides a clearer understanding of various embodiments such as integrated resistor element 100 and integrated resistor element 400. For example, multiple (e.g., N) resistor segments 101_1, ..., 101_N can be electrically coupled (connected) through multiple conductive connection segments 101L formed in the first conductive wiring layer 401 of integrated resistor element 400. Figure 5 and Figure 6(A cross-sectional schematic diagram can be further understood). In an exemplary embodiment, the first conductive wiring layer 401 may include or be embodied as a first metallic wiring layer. In one embodiment, a plurality of (e.g., N) resistor segments 101_1, ..., 101_N may be substantially identical in geometry and / or size. That is, in one embodiment, the shape and / or size of each of the plurality of (e.g., N) resistor segments 101_1, ..., 101_N may be substantially consistent with the remaining resistor segments of the plurality of resistor segments 101_1, ..., 101_N, for example, within an error range controlled within ±2%. Therefore, those skilled in the art will fully understand that the plurality of resistor segments 101_1, ..., 101_N have substantially the same resistance value. That is, the resistance value of each resistor segment 101_1, ..., 101_N is substantially consistent with the resistance value of the remaining resistor segments. Multiple (e.g., N) resistor segments 101_1, ..., 101_N can be divided into: a first part 101_R1 of the first group (the resistor segments in this group can be arranged into a first array or a first matrix), and a second part 101_R2 of the second group (the resistor segments in this group can be arranged into a second array or a second matrix).

[0059] and Figure 1 Similar to the description of the integrated resistive element 100, the integrated resistive element 400 can be configured to form a resistive sensing unit to provide a sense voltage Vs. The sensing terminal 101S can be electrically connected to the end resistive segment in the first portion 101_R1, which includes the first set of resistive segments 101_1, ..., 101_i (e.g., in...). Figure 4 In the example, it is labeled 101_i), and the starting resistance segment is electrically connected to the second part 101_R2, which includes the second set of resistance segments 101_(i+1), ..., 101_N (e.g., in...). Figure 4 The example is marked 101_(i+1)). Those skilled in the art will understand that, as referenced above... Figure 1 As illustrated in the example, further details and substantial descriptions relating to the configuration of the integrated resistive element 100 to form a resistive sensing unit apply. Figure 4 An example of configuring the integrated resistor unit 400 to form a resistive sensing unit is provided, but for simplicity, it will not be described further here. Figure 4In the example, the first part 101_R1 or the first group of resistor segments is more generally shown as including resistor segments 101_1, ..., 101_i, while the second part 101_R2 or the second group of resistor segments is more generally shown as including resistor segments 101_(i+1), ..., 101_N. Here, the variable i is an integer representing the number of resistor segments contained in the first part 101_R1 (i.e., the first group of resistor segments), and its value can be set or predetermined based on the required sensing voltage Vs or sensing gain Ga. The first resistor R1 depends on the number i of resistor segments contained in the first part 101_R1. The second resistor R2 depends on the number (Ni) of resistor segments contained in the second part 101_R2. In one example, the value of the variable i can be set based on the sensing gain Ga and the total number N of the multiple resistor segments 101_1, ..., 101_N contained in the integrated resistive element 400. For example, in Figure 4 In the example shown, the variable i can be set between 1 and N, satisfying the expression Ga = i / N. This setting is for illustrative and exemplary purposes only, intended to help those skilled in the art understand the embodiments of this disclosure, and should not be considered as a limitation. The number i of the first group of resistor segments contained in the first part 101_R1, and the number (Ni) of the second group of resistor segments contained in the second part 101_R2, can be reasonably selected according to actual application or design requirements, for example, depending on the sensing gain Ga required by the resistive sensing unit to be implemented.

[0060] In another respect, compared to Figure 1 The integrated resistor element 100 shown is, for example Figure 4 In the integrated resistor element 400 shown, the well region 102 is divided into a first well region 102_1 and a second well region 102_2, corresponding to the first portion 101_R1 and the second portion 101_R2 of a plurality of resistor segments 101_1, 101_2, ..., 101_N, respectively. That is, the first portion 101_R1 of the plurality of resistor segments 101_1, 101_2, ..., 101_N is disposed within or on the first well region 102_1, for example, within the perimeter (or boundary) of the first well region 102_1; while the second portion 101_R2 of the plurality of resistor segments 101_1, 101_2, ..., 101_N is located within or on the second well region 102_2, for example, within the perimeter (or boundary) of the second well region 102_2. The first well region 102_1 and the second well region 102_2 are separate from each other and electrically isolated. The first conductive wiring layer of the integrated resistive element 400 (labeled 401, combined with...) Figure 5 and Figure 6 (A cross-sectional schematic diagram can provide a clearer understanding) includes multiple conductive connection segments 101L for electrically connecting multiple resistor segments 101_1, 101_2, ..., 101_N to each other. The first conductive wiring layer 401 of the integrated resistor element 400 may also include a first well region bus 102L1 and a second well region bus 102L2 that are separated from each other and electrically isolated. Figure 4 As shown in the illustrated embodiment, when viewed in a planar view (i.e., from the xy-plane perspective), the first well bus 102L1 can be routed above the first well 102_1 along its perimeter (or boundary), while the second well bus 102L2 can be routed above the second well 102_2 along its perimeter (or boundary). In one embodiment, according to... Figure 4 The exemplary embodiment shown, when viewed in a plan view (i.e., from an xy-plane view), indicates that the first well bus 102L1 may extend around a first set of conductive connection segments among a plurality of conductive connection segments 101L, while the second well bus 102L2 may extend around a second set of conductive connection segments among the plurality of conductive connection segments 101L. Those skilled in the art will readily understand that, among the plurality of conductive connection segments 101L, the first set of conductive connection segments is used to connect a first set of resistor segments 101_1, ..., 101_i in series, while the second set of conductive connection segments among the plurality of conductive connection segments 101L is configured to connect a second set of resistor segments 101_(i+1), ..., 101_N in series.

[0061] like Figure 4 In the exemplary embodiment shown, the first well region 102_1 may be electrically connected to the first well region bus 102L1 and / or the first well region terminal 102T1, and the second well region 102_2 may be electrically connected to the second well region bus 102L2 and / or the second well region terminal 102T2. Those skilled in the art will understand that... Figure 4 The example shown can also be considered as Figure 1 In an alternative embodiment shown, the well bus 102L is divided into a first well bus 102L1 and a second well bus 102L2, and the well terminal 102T is divided into a first well terminal 102T1 and a second well terminal 102T2, corresponding to the well region 102 being divided into a first well region 102_1 and a second well region 102_2. Those skilled in the art will understand that... Figure 4 The electrical connections between the first well region terminal 102T1 and the first well region bus 102L1 and the first well region 102_1, and the electrical connections between the second well region terminal 102T2 and the second well region bus 102L2 and the second well region 102_2, in the example can be referred to Figure 1The electrical connection between the well region terminal 102T, the well region bus 102, and the well region 102 is implemented. In this way, the first well region 102_1 and the second well region 102_2 can be configured to receive different bias voltages, thereby improving the linearity of the resistance ratio K. This will be able to improve the accuracy of the sensed voltage Vs by independently adjusting the bias voltages applied to the first well region 102_1 and the second well region 102_2 respectively. For example, the first well region 102_1 can be electrically coupled to receive a first bias voltage Vbs1, and the first bias voltage Vbs1 can be applied to the first well region 102_1 via, for example, the first well region terminal 102T1 and the first well region bus 102L1. The second well region 102_2 can be electrically coupled to receive a second bias voltage Vbs2, and the second bias voltage Vbs2 can be applied to the second well region 102_2 via, for example, the second well region terminal 102T2 and the second well region bus 102L2. Those skilled in the art can understand that the first bias voltage Vbs1 and the second bias voltage Vbs2 mentioned here are also the ground potentials relative to the reference ground GND.

[0062] According to an embodiment, the first bias voltage Vbs1 is different from the second bias voltage Vbs2. In another embodiment, the first bias voltage Vbs1 may not exceed the range from the second voltage Vbot to the second bias voltage Vbs2, that is, Vbs1 ∈ [Vbot, Vbs2). In an embodiment, the first well region terminal 102T1 may be coupled to the second terminal 101B of the integrated resistance element 400, such that the first bias voltage Vbs1 can be substantially set to the second voltage Vbot applied to the second terminal 101B of the integrated resistance element 400. In an embodiment, the first well region terminal 102T1 may be connected to the sense terminal 101S, such that the first bias voltage Vbs1 can be substantially set to the sensed voltage Vs. In an embodiment, the first bias voltage Vbs1 may be set between the sensed voltage Vs at the sense terminal 101S and the second voltage Vbot applied to the second terminal 101B of the integrated resistance element 400, that is, Vbs1 ∈ (Vbot, Vs). In an embodiment, the first bias voltage Vbs1 may be configured to be close to the intermediate value [(Vs - Vbot) / 2 + Vbot] of the sensed voltage Vs and the second voltage Vbot, and have a predetermined deviation margin (such as ±10% or other appropriate values), and this margin can be adjusted according to actual applications or design requirements. In an embodiment, the first bias voltage Vbs1 can be derived from the sensed voltage Vs through a first scaling factor K1, for example: Vbs1 = K1 * (Vs - Vbot) + Vbot, where 0 < K1 < 1. In one embodiment, the first scaling factor K1 may be within the range of 1 / 3 to 2 / 3. In another embodiment, the first scaling factor K1 may be substantially set to 1 / 2 and have a predetermined deviation range (such as ±10% or other reasonable values depending on actual applications or design requirements).

[0063] In one embodiment, the second terminal 101B of the integrated resistor element 400 can be connected to a reference ground GND having a ground potential, which means that in this example, the second voltage Vbot is set to the ground potential (i.e., Vbot = 0V).

[0064] In one embodiment, the second bias voltage Vbs2 can be set between the first bias voltage Vbs1 and the first voltage Vtop applied to the first terminal 101A of the integrated resistor element 400, i.e., Vbs2 ∈ (Vbs1, Vtop). In one embodiment, the second bias voltage Vbs2 can be set between the sense voltage Vs at the sense terminal 101S and the first voltage Vtop applied to the first terminal 101A of the integrated resistor element 400, i.e., Vbs2 ∈ (Vs, Vtop). In one embodiment, the second bias voltage Vbs2 can be configured to be within the range of (Vab / 3 + Vbot) to (2*Vab / 3 + Vbot), or within the range of [(Vtop - Vs) / 3 + Vs] to [2*(Vtop - Vs) / 3 + Vs]. In one embodiment, the second bias voltage Vbs2 can be configured to be substantially close to the intermediate value [(Vtop - Vs) / 2 + Vs] between the sense voltage Vs and the first voltage Vtop within a predetermined deviation range (e.g., ±10%); or substantially close to the intermediate value [(Vtop - Vbs1) / 2 + Vbs1] between the first bias voltage Vbs1 and the first voltage Vtop, with the deviation range preset to ±10%; or substantially close to the intermediate value (Vab / 2 + Vbot) between the second voltage Vbot and the first voltage Vtop, with the deviation range preset to ±10%; other suitable values can also be selected according to actual applications or design requirements.

[0065] In one embodiment, when the sense voltage Vs at the sense terminal 101S is used as the reference potential, the second bias voltage Vbs2 can be derived from the first voltage Vtop applied to the first terminal 101A of the integrated resistor element 400 with a second scaling factor K2. For example, it can be expressed as Vbs2 = K2*(Vtop - Vs) + Vs, where 0 < K2 < 1. In one embodiment, the second scaling factor K2 can be within the range of 1 / 3 to 2 / 3. In another embodiment, the second scaling factor K2 can be set to 1 / 2 and a predetermined deviation margin is reserved, such as ±10% or other suitable values, and this value can be adjusted according to actual applications or design requirements.

[0066] Refer to Figure 5The partial cross-sectional view in the example shows that the semiconductor substrate 103 includes an initial substrate layer 1031 of a first conductivity type (e.g., P-type) and an epitaxial layer 1032 of the first conductivity type formed on top of the initial substrate layer 1031. In one example, the doping concentration of the epitaxial layer 1032 may be lower than that of the initial substrate layer 1031. Figure 5 The diagram is illustrated using a P-type layer. Figure 5 In the example, each of the first group of resistor segments 101_1, 101_2, and 101_3 is formed on the first well region 102_1, while each of the second group of resistor segments 101_4, 101_5, ..., 101_N is formed on the second well region 102_2. Figure 5 The cross-sectional view shows an observable resistor segment 101_N as an example to aid in understanding the embodiment. In one embodiment, each of the plurality of resistor segments 101_1, 101_2, ..., 101_N may include a polysilicon segment.

[0067] In one embodiment, each of the plurality of resistor segments 101_1, 101_2, ..., 101_N may be electrically connected at its first end to one of the plurality of conductive connection segments 101L (e.g., Figure 5 The left end of the resistive segment 101_N is coupled to a conductive connection segment 101L on the left, and the second end is electrically connected to another conductive connection segment 101L (e.g., in...). Figure 5 In the middle, the right end of the resistive segment 101_N is coupled to another conductive connection segment 101L on the right. Multiple resistive segments 101_1, 101_2, ..., 101_N can be electrically coupled to multiple conductive connection segments 101L, for example, through multiple interlayer wiring elements 403 formed in a first interlayer dielectric layer 405 disposed between the substrate 103 and the first conductive wiring layer 401. Figure 1 As illustrated in the example, the plurality of interlayer wiring elements 403 may include interlayer vias VIA1 that penetrate the first interlayer dielectric layer 405 and are filled with a conductive material (such as metal and / or metal alloy).

[0068] In one embodiment, still referring to Figure 5 The insulating layer 406 can be formed in each of the first well region 102_1 and the second well region 102_2, and disposed below the plurality of resistive segments 101_1, 101_2, ..., 101_N. That is, the insulating layer 406 in the first well region 102_1 is disposed below the first group of resistive segments 101_1, ..., 101_i, while the insulating layer 406 in the second well region 102_2 is disposed below the second group of resistive segments 101_(i+1), ..., 101_N. In another example, the insulating layer 406 includes a shallow trench isolation (STI) structure.

[0069] In one embodiment, still referring to Figure 5 A well contact region 402 is formed in each of the first well region 102_1 and the second well region 102_2. The doping concentration of the well contact region 402 may be higher than that of the first well region 102_1 and the second well region 102_2. The well contact region 402 of the first well region 102_1 is connected to the first well region bus 102L1, while the well contact region 402 of the second well region 102_2 is coupled to the second well region bus 102L2 through, for example, a plurality of interlayer wiring elements 404 formed in a first interlayer dielectric layer 405 disposed between the substrate 103 and the first conductive wiring layer 401. The plurality of interlayer wiring elements 404 may include interlayer vias VIA1 that penetrate the first interlayer dielectric layer 405 and are filled with a conductive material (such as metal and / or metal alloy). The well contact region 402 facilitates the formation of ohmic contacts between the first well region 102_1 and the interlayer wiring element 404, and between the second well region 102_2 and the interlayer wiring element 404; therefore, those skilled in the art may refer to it as a “highly doped” or “heavily doped” region (e.g., Figure 5 (The region is marked as N+).

[0070] In one embodiment, still referring to Figure 5 According to application requirements, several segments of the first well bus 102L1, the second well bus 102L2, and multiple conductive connection segments 101L can be electrically coupled to corresponding conductive buses formed in the second conductive wiring layer 410 disposed above the conductive wiring layer 401. A second interlayer dielectric layer 408 is disposed between the conductive wiring layer 401 and the second conductive wiring layer 410. In an exemplary embodiment, the second conductive wiring layer 410 may include or be embodied as a second metal wiring layer. The second interlayer dielectric layer 408 may be formed on the first interlayer dielectric layer 405, covering the conductive elements formed in the first conductive wiring layer 401 (such as the first well bus 102L1, the second well bus 102L2, and multiple conductive connection segments 101L). It can also be understood that the second interlayer dielectric layer 408 is disposed between the first interlayer dielectric layer 405 and the second conductive wiring layer 410. Figure 4 and Figure 5In the example, the first well bus 102L1 in the first conductive wiring layer 401 is electrically connected to the corresponding bus 102T1 in the second conductive wiring layer 410, and the second well bus 102L2 in the first conductive wiring layer 401 is electrically connected to the corresponding bus 102T2 in the second conductive wiring layer 410. The conductive connection segment 101L in the first conductive wiring layer 401, which is coupled to the last resistor segment 101_i in the first part 101_R1 and the first resistor segment 101_(i+1) in the second part 101_R2, is electrically coupled to the corresponding bus 101S in the second conductive wiring layer 410. The conductive connection segment 101L in the first conductive wiring layer 401 is connected to the last resistor segment 101_N among the multiple resistor segments 101_1, ..., 101_N. The conductive connection segment 101L is electrically connected to the corresponding bus 101A in the second conductive wiring layer 410. In the conductive wiring layer 401, the conductive connection segment 101L, which is connected to the first resistor segment 101_1 among the plurality of resistor segments 101_1,...,101_N, is electrically connected to the corresponding bus 101B in the second conductive wiring layer 410. Those skilled in the art will understand, with reference to... Figure 5 The buses 102T1, 102T2, 101S, 101A, and 101B in the exemplary second conductive wiring layer 410 can be used as the first well terminal 102T1, the second well terminal 102T2, the sensing terminal 101S, the first terminal 101A, and the second terminal 101B of the integrated resistive element 400, respectively. Depending on actual needs, a plurality of interlayer wiring elements 409 formed in the second interlayer dielectric layer 408 can be used to achieve electrical coupling between buses (e.g., 102L1, 102L2, etc.) or connecting elements (e.g., 101L, etc.) in the first conductive wiring layer 401 and busbars (e.g., 101A, 101B, 101S, 102T1, 102T2, etc.) in the second conductive wiring layer 410. For example, the plurality of interlayer wiring elements 409 may include interlayer vias VIA2 that penetrate the second interlayer dielectric layer 408 and are filled with a conductive material (such as metal and / or metal alloy, etc.).

[0071] In one embodiment, still referring to Figure 5Shallow trench isolation structures 407 can be formed around the first well region 102_1 and the second well region 102_2. In other words, the first shallow trench isolation structure 407 can be formed around the first well region 102_1 in the substrate 103 (e.g., surrounding or encircling it when viewed in a corresponding plan view), and the second shallow trench isolation structure 407 can be formed around the second well region 102_2 in the substrate 103 (e.g., surrounding or encircling it). Those skilled in the art will readily understand that, when viewed in a corresponding plan view, the first shallow trench isolation structure 407 can be formed, for example, surrounding or encircling the first well region 102_1. When viewed in a corresponding plan view, the second shallow trench isolation structure 407 can be formed, for example, surrounding or encircling the second well region 102_2. Here, "first" and "second" are only used to distinguish the isolation structures 407 formed around the first well region 102_1 and the second well region 102_2, respectively.

[0072] Reference Figure 6 The partial cross-sectional views in the example should be understood by those skilled in the art. Figure 5 The substantive descriptions used in the examples also apply. Figure 6 Example. One aspect of the difference might be that, in Figure 6 In the example, each of the plurality of resistor segments 101_1, 101_2, ..., 101_N can alternatively include a first conductivity type (e.g., ) formed in the respective first well region 102_1 and second well region 102_2. Figure 6 The doped regions are P-type doped regions, not polysilicon segments. Specifically, each of the first group of resistor segments 101_1,…101_i includes a first conductivity type doped region formed in the first well region 102_1, while each of the second group of resistor segments 101_(i+1),…,101_N includes a first conductivity type doped region formed in the second well region 102_2. The doped regions used to implement the multiple resistor segments 101_1, 101_2,…,101_N have a higher doping concentration than the first well region 102_1 and the second well region 102_2. Figure 6 In the example, this is labeled as the P+ region. Ohmic contacts can be formed between the doped regions 101_1, 101_2, ..., 101_N and the interlayer wiring element 403. On another aspect, in... Figure 6 In the example, insulation layer 406 can be omitted.

[0073] Figure 7 A schematic diagram 700 of an equivalent circuit of an integrated resistive element 400 according to an embodiment of the present disclosure is shown, the integrated resistive element being configured as a reference. Figure 4 , Figure 5 and Figure 6 The resistive sensing unit described in the example shown.

[0074] Figure 8Waveform diagram 800 is shown, illustrating the actual curve 801 of the sensed voltage Vs versus the voltage Vab across the integrated resistive element 400 when the second bias voltage Vbs2 applied to the second well region 102_2 is substantially set between the first bias voltage Vbs1 and the first voltage Vtop (e.g., in the range from (Vab / 3+Vbot) to (2*Vab / 3+Vbot)). The theoretical ideal curve 802 is also shown. Figure 8 As shown, the actual curve 801 basically follows the ideal curve 802 with low distortion, at least lower than... Figure 3 The distortion level of the actual curve 301 is shown. This means that in practical applications, the sensing voltage Vs provided by the integrated resistive element 400 configured as a sensing unit can improve accuracy and linearity while reducing distortion when tracking changes in the voltage Vab across the integrated resistive element 400. The second bias voltage Vbs2 is configured to be closer to the midpoint between the sensing voltage Vs and the first voltage Vtop [(Vtop-Vs) / 2+Vs], or closer to the midpoint between the bias voltage Vbs1 and the first voltage Vtop [(Vtop-Vbs1) / 2+Vbs1], or closer to the midpoint between the second voltage Vbot and the first voltage Vbop (Vab / 2+Vbot), resulting in lower distortion between the actual curve 801 and the ideal curve 802.

[0075] Figure 9 A top view layout schematic diagram of an integrated resistive element 900 according to an embodiment of the present disclosure is shown. Figure 4 Similar to the integrated resistive element 400 shown, the integrated resistive element 900 can be configured to form a resistive sensing unit to provide a sensed voltage Vs. Those skilled in the art will understand that... Figures 4 to 8 The substantive description of the integrated resistor element 400 also applies to... Figure 9 The examples shown are omitted here for the sake of simplicity.

[0076] like Figure 9 In the example shown, the second well region 102_2 can be self-biased via the second portion 101_R2 of the integrated resistor element 900. That is, the second bias voltage Vbs2 supplied to the second well region terminal 102T2 can be generated by multiplexing the second portion 101_R2 of the integrated resistor element 900. For example, the second bias voltage Vbs2 can be provided by a connection terminal 903 between the third portion 901 and the fourth portion 902 of the second portions 101_R2 of multiple resistor segments 101_1, ... 101_N. Therefore, this terminal 903 can also be referred to as the second well region bias terminal 903. The second well region terminal 102T2 can be coupled to the second well region bias terminal 903. Figure 9In the example, the third part 901 schematically includes the third group of resistor segments 101_(i+1), ..., 101_j of the second part 101_R2, while the fourth part 902 schematically includes the fourth set resistor segment 101_(j+1), ..., 101_N of the second part 101_R2. Here, the variable j is an integer related to the number of resistor segments contained in the third part 901 (i.e., the third group of resistor segments 101_(i+1), ..., 101_j), and its value can be set or predetermined according to the required applied second bias voltage Vbs2. For example, in... Figure 9 In the example shown, variable j can be set between (i+1) and N, and the number of resistor segments contained in the third part 901 (i.e., the third group of resistor segments 101_(i+1),…,101_j) can be represented as (ji). In one example, the value of variable j can be set according to the second scaling factor K2, the number i of resistor segments contained in the first part 101_R1 (i.e., the first group of resistor segments 101_1,…,101_i), and the total number N of all resistor segments 101_1,…101_N in the integrated resistor element 900. In one embodiment, variable j can satisfy the expression K2=(ji) / (Ni), as shown below. Figure 9 As shown. The third group of resistor segments 101_(i+1),…,101_j has a third resistance value R3, which depends on the number of resistor segments (ji) contained in the third part 901; the fourth part 902 includes a fourth group of resistor segments 101_(j+1),…101_N, which has a fourth resistance value R4, which depends on the number of resistor segments (Nj) contained in the fourth part 902. According to… Figure 9 In an exemplary embodiment, the second well bias terminal 903 can be connected, for example, through one or more interlayer wiring elements 409 (such as interlayer vias VIA2 filled with conductive material, in conjunction with the attached...) Figure 5-6 To better understand) electrically coupled to the starting resistance segment in the fourth part 902, which includes the fourth set of resistance segments 101_(j+1), ... 101_N (e.g., in Figure 9 A resistor segment labeled 101_(j+1) and the last resistor segment in the third part 901, which includes the third group of resistor segments 101_(i+1), ..., 101_j (e.g., Figure 9(the resistor segment labeled 101_j in the figure). One or more interlayer wiring elements 409 are formed in the second interlayer dielectric layer 408, conductive connection segments 101L in the first conductive wiring layer 401, and one or more interlayer wiring elements 403 (such as interlayer vias VIA1 filled with conductive material) formed in the first interlayer dielectric layer 405 located between the first conductive wiring layer 401 and the substrate 103. For this case, the second bias voltage Vbs2 can be expressed as: Vbs2 = (Vtop - Vs) * R3 / (R3 + R4) + Vs = (Vtop - Vs) * R3 / R2 + Vs. In one example, when the sense voltage Vs is relatively low compared to the voltage Vab across the integrated resistor element 900 (e.g., lower than Vab / 3 + Vbot, i.e., Vs < Vab / 3 + Vbot), the second bias voltage Vbs2 can be approximately expressed as Vbs2 ≈ Vab * R3 / (R3 + R4) = Vab * R3 / R2. In one example, for an embodiment where the sense voltage Vs is relatively low and the second terminal 101B of the integrated resistor element 900 is connected to a ground GND having a ground potential, Figure 9 The second bias voltage Vbs2 in the self - bias configuration shown can be approximately expressed as: Vbs2 ≈ Vtop * R3 / (R3 + R4) = Vtop * R3 / R2.

[0077] Figure 10 FIG. 1000 shows an equivalent circuit schematic diagram of an integrated resistor element 900 according to an embodiment of the present disclosure, and this integrated resistor element is configured as a resistive sensing unit described by referring to Figure 9 the example shown. In Figure 10 the example of, the second well region 102_2 is configured to obtain self - bias from the second portion 101_R2.

[0078] In one embodiment, the first well region 102_1 can be configured to be biased from the sense voltage Vs, for example, by connecting the first well region terminal 102T1 to the sense terminal 101S, or biased from the second voltage Vbot applied to the second terminal 101B of the integrated resistor element 900, for example, by connecting the first well region terminal 102T1 to the second terminal 101B.

[0079] Those skilled in the art can understand that in another embodiment, the first well region 102_1 can obtain self - bias from the first portion 101_R in a manner similar to the self - bias of the second well region 102_2. Therefore, by referring to Figure 9 the above description of configuring the second well region 102_2 to obtain self - bias from the second portion 101_R2 by reading the exemplary schematic diagram of, those of ordinary skill in the art can fully understand the details of configuring the first well region 102_1 to obtain self - bias from the first portion 101_R, and for the sake of brevity, it will not be elaborated here. Figure 11A schematic diagram 1100 of the equivalent circuit 1100 is shown in an alternative embodiment of this disclosure when the integrated resistive element 900 is configured as a resistive sensing unit. Figure 11 In the example, the first well region 102_1 is configured to self-bias from the first portion 101_R1, and the second well region 102_2 is configured to self-bias from the second portion 101_R2. For example, as can be seen by those skilled in the art... Figure 9 Example combination Figure 11 In an embodiment understood by analogy to the schematic diagram, a first well bias terminal 906, disposed between and connected to the fifth portion 904 and the sixth portion 905 of the first portion 101_R1 of multiple resistor segments 101_1,…101_N, can be configured to provide a first bias voltage Vbs1. A first well terminal 102T1 can be coupled to the first well bias terminal 906. For example, the fifth portion 904 may include a fifth group of resistor segments (e.g., 101_1,…,101_k) of the first portion 101_R1, and the sixth portion 905 may include a sixth group of resistor segments (e.g., 101_(k+1),…,101_i) of the first portion 101_R1. The variable k is an integer related to the number of resistor segments included in the fifth portion 904 (i.e., the fifth group of resistor segments 101_1,…,101_k), and its value can be set or predetermined according to the required first bias voltage Vbs1. For example, refer to… Figure 11 In the example shown, the variable k can be set between 1 and i, and the number of resistor segments contained in the fifth section 904 (i.e., the fifth group of resistor segments 101_1,…,101_k) can be represented by k. In one example, the value of the variable k can be set according to a first scaling factor K1. In another example, the variable k can satisfy the expression K1 = k / i. The first well bias terminal 906 can be electrically connected to the first resistor segment (e.g., 101_(k+1)) in the sixth section 905, which includes the sixth group of resistor segments 101_(k+1),…101_i, and to the last resistor segment (e.g., 101_k) in the fifth section 904, which includes the fifth group of resistor segments 101_1,…,101_k.

[0080] Those skilled in the art will further understand that the well region 102 in the integrated resistive element 100 can be self-biased in a manner similar to the self-biasing of the first well region 102_1 or the second well region 102_2. For example, Figure 11A A top view layout diagram of the integrated resistive element 100A in an exemplary embodiment of this disclosure is shown. The integrated resistive element 100A can be considered as based on... Figure 1 A variation of the integrated resistive element 100 shown is achieved by further configuring the self-biased well region 102, and the total number of the plurality of resistive segments included in the integrated resistive element 100B is extended to be represented more generally by the variable N. Figure 11BA schematic diagram 100B illustrates the equivalent circuit of the integrated resistive element 100A configured as a resistive sensing unit. Figure 11A and Figure 11B In the example, the well region 102 of the integrated resistor element 100A is configured to be self-biased by the integrated resistor element 100A body. A well region bias terminal 106, located between and connected to a first well region bias portion 104 and a second well region bias portion 105 of a plurality of resistor segments 101_1,…101_N, is configured to provide a bias voltage Vbs. The well region terminal 102T may be coupled to the well region bias terminal 106. For example, the first well region bias portion 104 may include a first set of well region bias resistor segments (e.g., 101_1,…101_p) among the plurality of resistor segments 101_1,…101_N, and the second well region bias portion 105 may include a second set of well region bias resistor segments (e.g., 101_(p+1),…,101_N). The variable p is an integer related to the number of resistor segments contained in the first portion 104 of the well bias (i.e., the first group of resistor segments 101_1,...,101_p of the well bias), and its value can be set or predetermined according to the required bias voltage Vbs. The well bias terminal 106 can be electrically connected to the starting resistor segment (e.g., 101_(p+1)) in the second portion 105 of the well bias, which includes the second group of resistor segments 101_(p+1),...,101_N of the well bias, and to the ending resistor segment (e.g., 101_p) of the first group of resistor segments 101_1,...,101_p of the well bias included in the first portion 104 of the well bias (e.g., 101_p).

[0081] Figure 12 A top view layout schematic diagram of an integrated resistive element 1200 according to an embodiment of the present disclosure is shown. Figure 4 Similar to the integrated resistive element 400 shown, the integrated resistive element 1200 can be configured to form a resistive sensing unit to provide a sense voltage Vs. Those skilled in the art will understand that... Figures 4 to 8 The substantive description of the integrated resistor element 400 also applies to... Figure 12 The examples shown are omitted here for the sake of simplicity.

[0082] exist Figure 12In the example shown, the second well region 102_2 may be biased by a second well region bias circuit 1201. The second well region bias circuit 1201 may be configured to provide a second bias voltage Vbs2. The second well terminal 102T2 of the second well 102_2 may be electrically connected to the second well region bias circuit 1201 to receive the second bias voltage Vbs2. In one embodiment, the second well region bias circuit 1201 may have a first terminal 1201A adapted to receive a first input signal, a second terminal 1201B adapted to receive a second input signal, and a third terminal 1202 adapted to provide the second bias voltage Vbs2. The second well region bias circuit 1201 may be configured to provide the second bias voltage Vbs2 at the third terminal 1202 according to the first input signal and the second input signal. In one embodiment, the first input signal may be proportional to a first voltage Vtop applied to the first terminal 101A of the integrated resistive element 1200. In one embodiment, the second input signal may be proportional to the sensed voltage Vs or the second voltage Vbot applied to the second terminal 101B of the integrated resistive element 1200, or set to ground potential.

[0083] In one embodiment, a first terminal of the second well bias circuit 1201 may be electrically connected to a first terminal 101A of the integrated resistive element 1200. In one embodiment, the first terminal 1201A of the second well bias circuit 1201 may be configured to receive a first voltage Vtop provided to the first terminal 101A of the integrated resistive element 1200. In one embodiment, a second terminal 1201B of the second well bias circuit 1201 may be electrically connected to a sensing terminal 101S or a second terminal 101B of the integrated resistive element 1200. In one embodiment, the second terminal 1201B of the second well bias circuit 1201 may be configured to receive a sensing voltage Vs or a second voltage Vbot provided to the second terminal 101B of the integrated resistive element 1200. In one embodiment, the second terminal 1201B of the second well bias circuit 1201 may be electrically connected to a reference ground GND having a ground potential.

[0084] exist Figure 12 In the example, the second well bias circuit 1201 may be formed inside or on the surface of the second well region 102_2, including a second plurality of resistor segments 1201_1, 1201_2, ..., 1201_M. The total number of the second plurality of resistor segments 1201_1, 1201_2, ..., 1201_M included in the second well bias circuit 1201 is more generally represented by the variable M, which is an integer greater than 1, and its value can be selected or designed according to the actual application and / or design requirements. The second plurality of (e.g., M) resistor segments 1201_1, ..., 1201_M can be electrically interconnected through a second plurality of conductive connection segments 1201L formed in the first conductive wiring layer 401 of the integrated resistive element 1200. In this case, as Figure 12In the exemplary embodiment shown, when viewed from a planar view (i.e., an xy-plane perspective), the second well bus 102L2 may extend around the first plurality of conductive connection segments 101L and the second plurality of conductive connection segments 1201L. In one embodiment, the second plurality of (e.g., M) resistor segments 1201_1,..., 1201_M may be substantially identical in geometry and / or size. That is, the shape and / or size of the second plurality of (e.g., M) resistor segments 1201_1,..., 1201_M are substantially consistent with the remaining resistor segments; for example, in one embodiment, the error range is controlled within ±2%. Therefore, it is understood that for those skilled in the art, the second plurality of (e.g., M) resistor segments 1201_1,..., 1201_M have substantially the same resistance value. That is, the resistance value of any one of the second plurality of (e.g., M) resistor segments 1201_1,..., 1201_M is substantially consistent with the resistance value of the remaining resistor segments in that group. The second plurality of resistor segments 1201_1,…,1201_M can be divided into a second well region biasing first portion 1203 and a second well region biasing second portion 1204. The third terminal 1202 of the second well region biasing circuit 1201 is located between the second well region biasing first portion 1203 and the second portion 1204 of the second plurality of resistor segments 1201_1,…1201_M, and is used to provide a second bias voltage Vbs2 to the second well region 102_2. The second well region terminal 102T2 can be connected to the third terminal 1202 of the second well region biasing circuit 1201.

[0085] exist Figure 12 In the example, the first portion 1203 of the second well bias schematically includes a first group of resistor segments 1201_1, ..., 1201_q from a second plurality (e.g., M) of resistor segments 1201_1, ..., 1201_M, and the second portion 1204 of the second well bias schematically includes a second group of resistor segments 1201_(q+1), ..., 1201_M from a second plurality (e.g., M) of resistor segments 1201_1, ..., 1201_M. Here, the variable q is an integer representing the number of resistor segments 1201_1, ..., 1201_q included in the first portion 1203 of the second well bias, and its value can be set or predetermined according to the required applied second bias voltage Vbs2. For example, in Figure 12 In the example shown, the variable q can be set between 1 and M. In a specific example, the value of the variable q can be set based on the second scaling factor K2 and the total number M of the second plurality of resistor segments 1201_1,…1201_M included in the second well bias circuit 1201. Figure 12In an example, the variable q can satisfy the expression K2 = q / M. The first part 1203 of the second well region bias that includes the first group of resistor segments 1201_1, …, 1201_q among the second plurality (e.g., M) of resistor segments 1201_1, …, 1201_M has a fifth resistance value R5, which depends on the number q of the resistor segments 1201_1, …, 1201_q included in the first part 1203 of the second well region bias. The second part 1204 of the second well region bias includes the second group of resistor segments 1201_(q + 1), …, 1201_M, which belongs to the second plurality (e.g., M) of resistor segments 1201_1, …, 1201_M, and has a sixth resistance R6, whose value depends on the number (M - q) of the resistor segments 1201_(q + 1), …, 1201_M included in the second part 1204 of the second well region bias. In this case, the second bias voltage Vbs2 can be expressed as: Vbs2 = (Vtop - Vs)*R5 / (R5 + R6) + Vs. In one example, when the sense voltage Vs is relatively low compared to the voltage Va across the integrated resistor element 1200 (e.g., lower than Vab / 3, i.e., Vs < Vab / 3), the second bias voltage Vbs2 can be approximately expressed as Vbs2 ≈ Vab*R5 / (R5 + R6) + Vbot. In one embodiment, when the sense voltage Vs is relatively low and the second terminal 101B of the integrated resistor element 1200 is connected to a reference ground GND having a ground potential, Figure 12 The second bias voltage Vbs2 of the shown configuration can be approximately expressed as Vbs2 ≈ Vtop*R5 / (R5 + R6).

[0086] Figure 13 FIG. 1300 shows an equivalent circuit schematic of an integrated resistor element 1200 according to an embodiment of the present disclosure, which is configured as a resistive sensing unit described in the shown example and with reference to Figure 12 In the example shown, the second well region 102_2 is configured to be biased by the second well region bias circuit 1201. Figure 13 In an example, the second well region 102_2 is configured to be biased by the second well region bias circuit 1201.

[0087] In one embodiment, the first well region 102_1 can be configured to be biased from the sense voltage Vs, for example, by connecting the first well region terminal 102T1 to the sense terminal 101S, or to be biased from the second voltage Vbot applied to the second terminal 101B of the integrated resistor element 1200, for example, by connecting the first well region terminal 102T1 to the second terminal 101B.

[0088] Those skilled in the art will understand that, in one embodiment, the first well region 102_1 can be biased by a first well region bias circuit, in a manner similar to the biasing of the second well region 102_2 by a second well region bias circuit 1201. The first well region bias circuit can be configured to provide a first bias voltage, and its operating principle is similar to that of the second well region bias circuit 1201 providing a second bias voltage Vbs2. Therefore, those skilled in the art can fully understand the specific details of configuring the first well region 102_1 to be biased by the first well region bias circuit by reading the above description of configuring the second well region 102_2 to be biased by the second well region bias circuit 1201, and will not be repeated here for the sake of brevity. For example, in a similar manner, the first well region bias circuit may include a first terminal adapted to receive a third input signal, a second terminal adapted to receive a fourth input signal, and a third terminal providing a first bias voltage Vbs1 based on the third and fourth input signals. In one embodiment, a first terminal of the first well bias circuit may be electrically connected to a sensing terminal 101S of the integrated resistor element 1200 to receive a sensed voltage Vs. A second terminal of the circuit may be electrically connected to a second terminal 101B of the integrated resistor element 1200 to receive a second voltage Vbot applied to that second terminal. A first well terminal 102T1 may be coupled to a third terminal of the first well bias circuit. (Refer to...) Figure 12 As can be understood from the example, those skilled in the art can implement it in a similar manner. The first well bias circuit can be formed inside or on the surface of the first well 102_1, including a third set of resistor segments. The total number of the third set of resistor segments included in the first well bias circuit can be more generally represented as an integer variable greater than 1, the specific value of which can be selected or designed according to the actual application and / or design requirements. The third set of resistor segments can be electrically connected to each other through a third set of conductive connection segments formed in the first conductive wiring layer 401 of the integrated resistive element 1200. In this case, if viewed from a plan view (i.e., xy plane perspective), the first well bus 102L1 can be extended around the first set of conductive connection segments (located between the plurality of conductive connection segments 101L and the third set of conductive connection segments). In one embodiment, the third set of resistor segments can be substantially the same in terms of geometry and / or geometric dimensions and / or resistance values, for example, in one embodiment the error range is controlled within ±2%. The third set of resistor segments can be divided into a first well bias segment and a second well bias segment. The third terminal of the first well region bias circuit is located between the first well region bias segment and the second well region bias segment of the third group of resistor segments and connects the two segments, and is used to provide the first bias voltage Vbs1 to bias the first well region 102_1.

[0089] Figure 14 A partial cross-sectional view of an integrated resistive element 1200 according to an embodiment of the present disclosure is shown. Figure 15A partial cross-sectional view of an integrated resistive element 1200 according to another embodiment of the present disclosure is shown. It should be noted that... Figure 14 and Figure 15 The schematic cross-sectional view shown can be considered as along... Figure 12 In the top view, the cutting line A-A' is used to cut the plane, which is parallel to the xz plane defined by the x-axis and z-axis.

[0090] Those skilled in the art will understand that, for Figures 4 to 6 The descriptions made regarding the multiple resistor segments 101_1, ..., 101_N also apply. Figure 12 , Figure 14 and Figure 15 Examples.

[0091] exist Figure 14 In the example, the second plurality of resistor segments 1201_1,…,1201_M of the second well bias circuit 1201 are all formed on the top of the second well 102_2. Figure 14 In the cross-sectional view, for ease of understanding of this embodiment, the observable resistor segment 1201_M is shown as an example. In one embodiment, each of the second plurality of resistor segments 1201_1, ..., 1201_M of the second well region bias circuit 1201 may include a polysilicon segment. In one embodiment, each of the second plurality of resistor segments 1201_1, ..., 1201_M may be located at a first end (e.g., Figure 14 The left end of the resistive segment 1201_M is electrically connected to one of the second plurality of conductive connection segments 1201L, and the right end (e.g., the right end of the resistive segment 1201_M) is electrically connected to another of the second plurality of conductive connection segments 1201L. The second plurality of resistive segments 1201_1, ..., 1201_M can be electrically connected to the second plurality of conductive connection segments 1201L through, for example, a plurality of interlayer wiring elements 403 formed in the first interlayer dielectric layer 405. In one embodiment, an insulating layer 1206 can be formed in the second well region 102_2 and disposed below the second plurality of resistive segments 1201_1, ..., 1201_M. The insulating layer 1206 includes a silicon dioxide layer in one example and a shallow trench isolation (STI) structure in another example.

[0092] for Figure 15 The embodiments shown will be understood by those skilled in the art. Figure 14 The substantive descriptions in the illustrated embodiments also apply to... Figure 15 The implementation examples are shown. The difference between the two may lie in... Figure 15 In the example, each of the second plurality of resistor segments 1201_1,…,1201_M may alternatively include a first conductivity type doped region formed in the second well region 102_2 (e.g., Figure 15The doped region (P-type) is not a polycrystalline silicon segment. That is, each of the second plurality of resistive segments 1201_1, ..., 1201_M includes a doped region of a first conductivity type formed in the second well region 102_2. The doped region used to implement the second plurality of resistive segments 1201_1, ..., 1201_M has a higher doping concentration than the second well 102_2. Figure 15 In the example, this is labeled as the P+ region. Ohmic contacts can be formed between the doped regions 1201_1, ..., 1201_M and the interlayer wiring element 403. Figure 15 In the example, insulating layer 1206 can be omitted.

[0093] Those skilled in the art will understand that, except Figures 12 to 15 In addition to the specific embodiment shown, there are various alternative solutions that can be used to implement a second well region bias circuit that biases the second well region 102_2 and / or a first well region bias circuit that biases the first well region 102_1.

[0094] For example, Figure 16 A schematic diagram 1600 of the equivalent circuit of an integrated resistive element 1600 configured as a resistive sensing unit according to an embodiment of the present disclosure is shown. It will be apparent to those skilled in the art that... Figures 4 to 8 The substantive description of the integrated resistor element 400 in the text also applies to... Figure 16 The example shown will not be repeated here for the sake of simplicity.

[0095] Reference Figure 16 The schematic diagram illustrates that, in one embodiment, the first well region 102_1 may be configured to be biased by a first well region bias circuit 1601, which provides a first bias voltage Vbs1. Specifically, the first well region terminal 102T1 of the first well region 102_1 may be electrically connected to the first well region bias circuit 1601 to receive the first bias voltage Vbs1. In one embodiment, the first well region bias circuit 1601 may include a first voltage scaling circuit 161 having a first scaling factor K1. The first voltage scaling circuit 161 may have a first terminal 161A, a second terminal 161B, and a third terminal 161C, and may be configured to provide a first scaling voltage at the third terminal 161C based on signals received at the first terminal 161A and the second terminal 161B, respectively. For example, the first scaling voltage may be proportional to the voltage difference between the signals received at the first terminal 161A and the second terminal 161B, and has a first scaling factor K1. In one embodiment, the first well bias circuit 1601 may further include a first buffer buf1 connected to the third terminal 161C of the first voltage scaling circuit 161. The first scaled voltage output through the first buffer buf1 can be used as the first bias voltage Vbs1.

[0096] In one embodiment, the second well region 102_2 may be configured to be biased by a second well region bias circuit 1602, which is configured to provide a second bias voltage Vbs2. That is, the second well region terminal 102T2 of the second well region 102_2 may be electrically connected to the second well region bias circuit 1602 to receive the second bias voltage Vbs2. In one embodiment, the second well region bias circuit 1602 may include a second voltage scaling circuit 162 having a second scaling factor K2. The second voltage scaling circuit 162 may have a first terminal 162A, a second terminal 162B, and a third terminal 162C, and may be configured to provide a second scaling voltage at the third terminal 162C based on signals received at the first terminal 162A and the second terminal 162B, respectively. For example, the second scaling voltage may be proportional to the voltage difference between the signals received at the first terminal 162A and the second terminal 162B on the second voltage scaling circuit 162, and has a second scaling factor K2. In one embodiment, the second well bias circuit 1602 may further include a second buffer buf2 connected to the third terminal 162C of the second voltage scaling circuit 162. The second scaled voltage can be output as a second bias voltage Vbs2 through the second buffer buf2.

[0097] Figure 17 A schematic diagram 1700 of the equivalent circuit of the integrated resistive element 1700 when configured as a resistive sensing unit according to an embodiment of the present disclosure is shown. (Refer to...) Figure 16 The substantial description of the integrated resistor element 1600 also applies to... Figure 17 Examples will not be elaborated here for the sake of simplicity. Figure 17 In the example, the first buffer buf1 includes a first transistor 171 configured as a source follower, and the second buffer buf2 includes a second transistor 172 configured as a source follower. For example, the first transistor 171 and the second transistor 172 may each be composed of a MOSFET.

[0098] Figure 18 A top view layout schematic diagram of an integrated resistive element 1800 according to an embodiment of the present disclosure is shown. Figure 4 Similar to the integrated resistive element 400 shown, the integrated resistive element 1800 can be configured to form a resistive sensing unit to provide a sense voltage Vs. Those skilled in the art will understand that various integrated resistive elements disclosed with respect to the exemplary embodiments described above (such as those referenced) Figures 1 to 2 The integrated resistor element 100 shown, reference Figures 4 to 8 The integrated resistor element 400 shown, reference Figures 9 to 11 The integrated resistor element 900 shown Figures 12 to 15 The integrated resistor element 1200 shown Figure 16 The integrated resistor element 1600 shown and Figure 17The integrated resistor element 1700 shown is suitable for... Figure 18 The examples shown are for simplicity and will not be described in detail here. Compared to the various integrated resistive elements in the exemplary embodiments described above, the integrated resistive element 1800 may further include a protection circuit 180 at some level. Although Figure 18 The example describes the integrated resistor element 1800 as based on Figure 12 The integrated resistor element 1200 is a variation developed by adding protection circuit 180. Those skilled in the art will understand that this is merely to provide examples and help to better understand various embodiments of integrated resistor elements including such protection circuit 180, while also understanding that other embodiments of integrated resistor elements including such protection circuit 180 can be developed based on other exemplary embodiments of the integrated resistor element disclosed above (e.g., 100, 400, 900, 1600, or 1700).

[0099] For example, Figure 18A A top view layout schematic diagram of an integrated resistive element 1800A according to an embodiment of the present disclosure is shown. The integrated resistive element 1800A can be considered as based on Figure 1 A variation of the integrated resistor element 100 shown is implemented by further integrating a protection circuit 180, and the total number of its multiple resistor segments is extended to represent the general variable N. Furthermore, by way of example only, the integrated resistor element 1800A may also include a well region biasing circuit configured to provide a bias voltage Vbs to bias the well region 102. The well region terminal 102T of the integrated resistor element 1800A can be electrically connected to the well region biasing circuit to receive the bias voltage Vbs. For example, in... Figure 18A In the example shown, the well bias circuit for the integrated resistor element 1800A can be used with... Figure 12 The second well bias circuit 1201 described in the example is implemented similarly, wherein the second bias voltage Vbs2 generated by the second well bias circuit 1201 is used as the bias voltage Vbs to bias the well region 102 of the integrated resistor element 1800A. In this case, for example, when the well bias circuit is implemented with reference to the second well bias circuit 1201, it includes a second plurality of resistor segments 1201_1, 1201_2, ..., 1201_M, which can be formed inside or on the surface of the well region 102. In other embodiments, the well bias circuit of the integrated resistor element 1800A can be implemented using other types of bias circuits, all of which can provide a bias voltage, for example, referencing Figure 16 and Figure 17 The implementation of the first well region bias circuit 1601 or the second well region bias circuit 1602 is obvious and easy to understand to those skilled in the art.

[0100] The protection circuit 180 can be electrically connected between the first part 101_R1 and the second part 101_R2 of multiple resistor segments 101_1, 101_2, ..., 101_N, such as... Figure 18 An example of the integrated resistive element 1800 is shown. In one embodiment, the protection circuit 180 may include a third well region 181 formed in the substrate 103, which is isolated from the second well region 102 (or, in embodiments where the second well region 102 is divided into multiple well regions including the first well region 102_1 and the second well region 102_2, it is isolated from the first well region 102_1 and the second well region 102_2). The third well region 181 may be of a first conductivity type, for example... Figure 18 and Figure 18AThe example shows a P-type. In one embodiment, the protection circuit 180 is formed within the third well region 181. The protection circuit 180 may include, for example, a protection first terminal 180A electrically connected to the first portion 101_R1 via a protection first connection bus 180L1, a protection second terminal 180B electrically connected to the second portion 101_R2 via a protection second connection bus 180L2, and a protection third terminal 180C configured as a protection control terminal. In one embodiment, the protection first terminal 180A and the protection second terminal 180B may be formed in the first conductive wiring layer 401 of the integrated resistive element (e.g., 1800 or 1800A), and the protection first connection bus 180L1, the protection second connection bus 180L2, and the protection third terminal 180C may be formed in the second conductive wiring layer 410 of the integrated resistive element (e.g., 1800 or 1800A). The protection circuit 180 can be configured to enable or disable the path between the protection first terminal 180A and the protection second terminal 180B based on the electrical state of the protection control terminal 180C. In one example, the sensing terminal 101S can be disposed between the protection circuit 180 and the first portion 101_R1, and electrically connected to the protection first terminal 180A and the first portion 101_R1 of the protection circuit 180. In other words, in this example, the sensing terminal 101S can be led out from the protection first terminal 180A of the protection circuit 180. The protection circuit 180 can be considered as electrically connecting the sensing terminal 101S to the second portion 101_R2 of the plurality of resistor segments 101_1, 101_2, ..., 101_N in the integrated resistor element 1800, wherein the sensing terminal 101S is electrically connected to the first portion 101_R1. When the first portion 101_R1 (i.e., including the first group of resistor segments 101_1, ..., 101_i) of the multiple resistor segments 101_1, 101_2, ..., 101_N of the integrated resistor element 1800 is electrically connected between the sensing terminal 101S and the second terminal 101B of the integrated resistor element 1800 or 1800A, wherein the sensing terminal 101S is electrically connected to the protection circuit 180 (e.g., connected to the protection second terminal 180B of the protection circuit 180), when the integrated resistor element 1800... The second portion 101_R2 (i.e., including the second group of resistor segments 101_(i+1), ..., 101_N) of the resistive element 1800 or 1800A is electrically connected between the protection circuit 18000 and the first terminal 101A (e.g., in this example, the connection between the first terminal 101A of the integrated resistive element 1800 or 1800A and the protection second terminal 180B of the protection circuit 180). The sensing terminal 101S can be electrically coupled to the end of the resistor segment in the first portion 101_R1 (i.e., including the first group of resistor segments 101_1, ..., 101_i) (e.g., in... Figure 18 or Figure 18AIn the example, the resistor segment labeled 101_i) and the protection first terminal 180A of the protection circuit 180, while the resistor segment starting in the second part 101_R2 (i.e., including the second group of resistor segments 101_(i+1), ..., 101_N) (e.g., Figure 18 Or, in example 18A, marked as 101_(i+1)), it can be compared with... Figure 18 or Figure 18A The second protection terminal 180B of the protection circuit 180 in the embodiment is electrically connected.

[0101] Protection circuit 180 can effectively protect other components or circuits electrically connected to sensing terminal 101S, preventing damage caused by the protection circuit 180 (e.g., ...). Figure 18 The integrated resistor element 1800 shown is or Figure 18A Damage occurs when the voltage Vab across the integrated resistive element (1800A) is too high (e.g., above the maximum permissible value), for example, exceeding the maximum withstand voltage of the component or circuit connected to the sensing terminal 101S. In one embodiment, the maximum withstand voltage of the component or circuit connected to the sensing terminal 101S may not exceed 5V, while the voltage Vab across the integrated resistive element 1800 or 1800A may be as high as 20V or even exceed 70V. The breakdown voltage of the protection circuit 180 may be higher than the maximum rated voltage Vab that the integrated resistive element 1800 or 1800A withstands in practical applications. In practical applications, the protection circuit 180 may also help reduce the impact of the protection circuit 180 (e.g., Figure 18 Integrated resistor element 1800 or Figure 18A The power consumption and power consumption of the sensing unit implemented with an integrated resistor unit including protection circuitry 1800 (e.g., integrated resistive element 1800A). This disclosure may not exhaustively describe the above and other advantages, as those skilled in the art will appreciate the various advantages upon reading this disclosure.

[0102] In one embodiment, the protection circuit 180 may be configured to enable the path between the first protection terminal 180A and the second protection terminal 180B when the protection control terminal 180C is in a first electrical state; and to disable the path between the first protection terminal 180A and the second protection terminal 180B when the protection control terminal 180C is in a second electrical state. When the path between the first protection terminal 180A and the second protection terminal 180B is enabled, the path forms a conductive path, allowing signal transmission between the first protection terminal 180A and the second protection terminal 180B, thereby electrically connecting the first portion 101_R1 and the sensing terminal 101S to the second portion 101_R2. When the path between the first protection terminal 180A and the second protection terminal 180B is disabled, the path becomes non-conductive, blocking signal transmission between the first protection terminal 180A and the second protection terminal 180B, thereby electrically decoupling or disconnecting the first portion 101_R1 and the sensing terminal 101S from the second portion 101_R2. In other words, the protection circuit 180 can be configured to establish electrical coupling or connection between the second part 101_R2 and the sensing terminal 101S and the first part 101_R1 when the protection control terminal 180C is in the first electrical state; when the protection control terminal 180C is in the second electrical state, the circuit can also be configured to disable the electrical coupling or connection between the second part 101_R2 and the sensing terminal 101S and the first part 101_R1.

[0103] like Figure 18 or Figure 18A In the exemplary embodiment shown, the protection circuit 180 includes a controllable transistor (such as an asymmetric field-effect transistor), which can be selected from various devices, including double-diffused metal-oxide-semiconductor (DMOS), junction field-effect transistor (JFET), etc. The controllable transistor has a source terminal configured to protect the first terminal 180A, a drain terminal configured to protect the second terminal 180B, and a gate terminal configured to protect the control terminal 180C. Figure 18 or Figure 18A In the example provided, for ease of understanding this embodiment, the protection circuit 180 is exemplarily constructed using a DMOS structure. However, this is not intended to limit the scope of this disclosure.

[0104] Figure 19 A partial cross-sectional view of an integrated resistive element 1800 according to an embodiment of the present disclosure is shown. It will be understood that... Figure 19 The cross-sectional view shown can be considered as along... Figure 18 The view intercepted by the cutting line B-B' in the top view. By combining Figure 18 , Figure 19, Figure 14 and / or Figure 15 This allows for a deeper understanding of the integrated resistor element 1800 and its working principle. Figure 19 In the partial cross-sectional view shown, the DMOS of the protection circuit 180 exemplarily includes a second conductivity type source region 182 (e.g., illustrated as an N+ region) formed in a third well region 181; a second conductivity type drain region 183 (e.g., illustrated as another N+ region) separated from the source region 182, which is formed in a drift region 185 (e.g., illustrated as an N region) with a lower doping concentration than the drain region 183. The drain region 183 is separated from the source region 182 and formed in the drift region 185 (e.g., shown as an N- region), which is a second conductivity type region with a lower doping concentration than the drain region 183; and a gate region 186 formed on top of the epitaxial layer 1032, located between the source region 182 and the drain region 183. A body contact region 184 may be further formed adjacent to the source region 182, which contacts the source region 182 in the third well region 181. In one embodiment, the protection first terminal 180A can be electrically connected to the source region 182 via one or more interlayer wiring elements 404 formed in the first interlayer dielectric layer 405, and can be electrically connected to the protection first connection bus 180L1 via one or more interlayer wiring elements 409 formed in the second interlayer dielectric layer 408. The protection first connection bus 180L1 can be electrically connected to the first portion 101_R1 (e.g., the end resistor segment 101_i of the first portion 101_R1) via one or more interlayer wiring elements 409 formed in the second interlayer dielectric layer 408. The protection second terminal 180B can be electrically connected to the drain region 183 via one or more interlayer wiring elements 404 formed in the first interlayer dielectric layer 405, and can be further electrically connected to the protection second connection bus 180L2 via one or more interlayer wiring elements 409 formed in the second interlayer dielectric layer 408. The second protection bus 180L2 can be electrically connected to the second portion 101_R2 (e.g., the starting resistance segment 101_(i+1) of the second portion 101_R2) via one or more interlayer wiring elements 409 formed in the second interlayer dielectric layer 408. The third protection terminal 180C can be electrically connected to the gate region 186.

[0105] Figure 20 A schematic diagram 2000 of the equivalent circuit of an integrated resistive element 1800 according to an embodiment of the present disclosure is shown, the element being configured for reference. Figure 18 and Figure 19 The resistive sensing unit described in the example shown. Figure 20A A schematic diagram 2000A of the equivalent circuit of an integrated resistive element 1800A according to an embodiment of the present disclosure is shown, the element being configured as a reference. Figure 18A The example shown describes a resistive sensing unit.

[0106] The integrated resistive element, which functions as a resistive sensing unit according to various embodiments of this disclosure, can be applied to a variety of scenarios and can be used in various electronic devices that require signal sensing.

[0107] Figure 21 A block diagram of an electronic device according to an embodiment of the present disclosure is shown, the device including a power management device 2100. The power management device 2100 is adapted to supply power from a power source to a load. The power management device 2100 has an input terminal IN for receiving an input power signal from the power source; and an output terminal OUT for providing an output power signal. As will be described in detail below, the power management device 2100 may need to perform signal sensing to control power transfer between the input terminal IN and the output terminal OUT or to regulate the output power signal. The power source may include a battery / battery pack or other circuitry that supplies power to other circuitry. Figure 21 As shown, the power supply provides an input power signal to the power management device 2100 in the form of an input voltage VIN (which may be a DC voltage) or an input current Ii. However, this description is not restrictive, and power supplies capable of providing input power signals to the power management device 2100 in other forms are also applicable.

[0108] In one embodiment, the power management device 2100 may include a power switching unit 110. The power switching unit 110 may be responsive to a control signal (such as...). Figure 21 The control signal CTRL shown in the example regulates the energy or power transmitted from the input IN to the output OUT (or load). In one embodiment, the power switching unit 110 may include at least one power switch (such as a power transistor device) that can be controlled to switch on and off. In another embodiment, the power switching unit 110 may also include a driver for driving at least one power switch within the unit.

[0109] According to an exemplary embodiment, the power switching unit 110 may be adapted to a configurable structure for use according to a control signal (such as...) Figure 21 The control signal CTRL shown controls the switching of energy storage and release in the inductive storage device 120, thereby switching the input power signal (e.g., Figure 21 The input voltage VIN and / or input current Ii are converted into an output power signal (e.g., ...). Figure 21The output voltage VOUT and / or output current Io are specified in the diagram. Typically, the power switching unit 110 is configured to couple the inductive storage device 120 within a specific cycle, allowing energy to be transferred from the input terminal IN to the device for energy storage. This cycle can be called the on-time Ton (also considered as the on-time of the power switching unit 110, or the on-time of the power management device 2100). The cycle in which the power switching unit 110 is configured to couple the inductive storage device 120, allowing energy to be transferred from the inductive storage device 120 to the output port OUT for energy release, is called the off-time Toff (also known as the off-time). The turn-off time (which can be considered as the turn-off time of the power switching unit 110, or the turn-off time of the power management device 2100) is the sum of the on-time Ton and the off-time Toff experienced each time the energy storage and release switching in the inductive storage device 120 is completed. This sum can be called the duty cycle or switching cycle Top of the power management device 2100. The ratio of the on-time Ton to the sum of the on-time Ton and the off-time Toff in each duty cycle Top can be called the duty cycle of the power switching unit 110 or the duty cycle of the power management device 2100. Figure 21 The control signals shown, such as CTRL, can be used to control the power switching unit 110, enabling switching between energy storage and release in the inductive storage device 120. They can also adjust the on-time Ton and / or off-time Toff, the duty cycle, or the switching period Top (or the switching frequency Fop = 1 / Top). In this way, the energy or power transmitted to the output terminal OUT in each switching cycle can be adjusted. For example, the form of the output power signal can be adjusted, including the output voltage VOUT and / or the output current Io.

[0110] According to an exemplary embodiment, the power switching unit 110 may be configured to cooperate with the inductive storage device 120 to implement a power conversion topology 130. The power conversion topology 130 may include any isolated or non-isolated synchronous or asynchronous power conversion topology, including but not limited to DC-DC power conversion topologies, AC-DC power conversion topologies, or DC-AC power conversion topologies. For example, the power conversion topology 130 may include a synchronous non-isolated DC-DC power conversion topology, such as a DC-DC buck power conversion topology, a DC-DC boost power conversion topology, or a DC-DC buck-boost power conversion topology. Figure 21 An exemplary DC-DC buck power conversion topology 130A is shown to provide an example. Figure 21 An exemplary DC-DC boost power conversion topology 130B is also shown to provide another example.

[0111] In one embodiment, the power management device 2100 may further include a control unit 140 for providing control signals to the power switching unit 110. In one embodiment, the control unit 140 may be adapted to provide control signals to the power switching unit 110 based on information indicating input signals (e.g., information indicating input voltage VIN and / or input current Ii) and / or information indicating output signals (e.g., information indicating output voltage VOUT and / or output current Io).

[0112] In one embodiment, the power management device 2100 may further include a sensing unit 160. The sensing unit 160 may be configured to detect output signals (e.g., output voltage VOUT and / or output current Io) to provide, for example... Figure 21 The output signal indication information is shown in the example. The sensing unit 160 can employ the methods described in this disclosure. Figures 1 to 20A In the various embodiments shown, it can be implemented as one of the integrated resistive elements of a resistive sensing unit. In this application example, the integrated resistive element used to implement the sensing unit 160 is configured such that its first terminal 101A is electrically connected to the output terminal OUT to receive the output signal, its second terminal 101B is electrically connected to the reference ground GND, and its sensing terminal 101S is configured to provide a sensing voltage Vs as a feedback signal Vfb, which can be provided to the control unit 140 as output signal indication information. The power management device 2100 constructed by the sensing unit 160 implemented with the integrated resistive element in the embodiments of this disclosure can effectively improve the detection accuracy of the output signal (such as the output voltage VOUT and / or the output current Io) of the power management device 2100, and can also improve the adjustment accuracy of the output signal (such as the output voltage VOUT and / or the output current Io) to a predetermined value. In another embodiment, using the integrated resistive element described in the embodiments of this disclosure to implement the sensing unit 160 of the power management device helps to improve performance while maintaining a good chip size (at least without significantly increasing the chip size).

[0113] In one embodiment, the power switching unit 110 may be implemented and manufactured within an integrated circuit (IC) chip 210. In another embodiment, the control unit 140 and the sensing unit 160 may be co-integrated with the power switching unit 110 on the same IC chip 210. In yet another embodiment, the control unit 140 and the sensing unit 160 may be manufactured and / or integrated on a separate IC chip different from the power switching unit 110. In yet another alternative embodiment, the control unit 140 may be provided by other circuitry in an application system that may use a power management device 2100. For example, a microcontroller in the application system may be configured to implement the functions of the control unit 140.

[0114] In one embodiment, the capacitive energy storage unit 150 may be connected to the output port OUT. The capacitive energy storage unit 150 may include one or more capacitors and may operate as an output filter to smooth the output voltage VOUT at the output port OUT. Those skilled in the art will understand that the power management device 100 may also include other active and / or passive components, which are not described in detail herein.

[0115] Figure 22 A block diagram of an electronic device according to another embodiment of the present disclosure is shown, the device including a power management device 2200. Those skilled in the art will understand that, referring to… Figure 21 The substantive description of the power management device 2100 also applies to Figure 22 Examples of these will not be repeated here for the sake of simplicity. One difference between the two is that the power management device 2200 includes a sensing unit 260 configured to operatively sense input signals (e.g., input voltage VIN and / or input current Ii) and provide, for example... Figure 22 The example shows the input signal indication information. The sensing unit 260 can employ the information disclosed herein, such as... Figures 1 to 20A The embodiments described are implemented using an integrated resistive element that can be configured as a resistive sensing unit. In this application example, the integrated resistive element used to implement sensing unit 260 is configured such that its first terminal 101A is operably electrically connected to the input terminal IN to receive an input signal, its second terminal 101B is operably electrically connected to the reference ground GND, and its sensing terminal 101S is configured to provide a sensing voltage Vs as a feedforward signal Vff, which can be provided to the control unit 140 as an input signal indication. Similar to sensing unit 160, sensing unit 260 can be co-manufactured and / or integrated on the same IC chip 210 as power switch unit 110, or separately manufactured and / or co-integrated with control unit 140 on a separate IC chip different from power switch unit 110. In another embodiment, compared to Figure 21 The power management device 2100 and power management device 2200 shown have a control unit 140 that can receive an output feedback signal Vfb1 (e.g., output voltage VOUT and / or output current Io) carrying output signal indication information. This output feedback signal Vfb1 may be provided in one embodiment by a feedback circuit coupled to the output terminal OUT; or in another embodiment by, for example... Figure 21 The sensing unit 160 described in the example provides (i.e., uses the feedback signal Vfb as the output feedback signal Vfb1); or in another embodiment, it is provided directly by the output terminal OUT (i.e., uses the output signal as the output feedback signal Vfb1).

[0116] The power management device 2200 of the sensing unit 260 implemented with integrated resistive elements described in the embodiments of this disclosure can effectively improve the detection accuracy of the input voltage VIN and improve the control accuracy of adjusting the output voltage VOUT to a predetermined value.

[0117] Figure 23 A block diagram of a power management device 2300 according to another embodiment of the present disclosure is shown. Those skilled in the art will understand that, for... Figure 21 and Figure 22 The substantive descriptions of the power management devices 2100 and 2200 also apply to... Figure 23 The example shown will not be repeated here for the sake of simplicity. The power management device 2300 includes: a sensing unit 160 configured to operatively sense output signals (e.g., output voltage VOUT and / or output current Io) to provide, for example... Figure 21 The information indicating the output signal; sensing unit 260, configured to operably sense input signals (e.g., input voltage VIN and / or input current Ii) to provide, for example Figure 22 The information indicating the input signal.

[0118] Figure 24 A block diagram of a power management device 2400 according to an alternative embodiment of the present disclosure is shown. The power management device 2400 includes a sensing unit 260 configured to operablely detect input signals (e.g., input voltage VIN and / or input current Ii) to provide, for example... Figure 22 The information indicating the input signal. Figure 22 The substantive description of the power management device 2200 in the text also applies to Figure 24 The example shown is omitted for simplicity. The power management device 2400 includes a control unit 240, which can be considered as... Figure 22 An exemplary embodiment of the control unit 140.

[0119] The control unit 240 may include a set control module 241, a reset control module 242, and a logic control module 243. The set control module 241 may be configured to receive a reference signal Vref at a first input terminal, receive a feedback signal Vfb1 indicating an output signal (such as output voltage VOUT or output current Io) at a second input terminal, compare the feedback signal Vfb1 with the reference signal Vref, and finally generate a set control signal SET at the output terminal. In one embodiment, the output feedback signal Vfb1 may be provided by a feedback circuit connected to the output port OUT; in another embodiment, it may be provided by a feedback circuit such as... Figure 21 The sensing unit 160 shown provides (i.e., uses the feedback signal Vfb as the output feedback signal Vfb1). In an alternative embodiment, the second input of the set control module 241 can receive the output signal as the output feedback signal Vfb1. Although Figure 24 In the exemplary embodiment, the set control module 241 schematically includes a first comparator CM1, but it should be understood that this design is not a limiting requirement, and the set control module 241 can obviously be implemented in many other variations to realize the comparison function.

[0120] Reset control module 242 is coupled to sensing unit 260 and receives a feedforward signal Vff from sensing unit 260, which indicates an input signal (e.g., input voltage VIN or input current Ii). Reset control module 242 is configured to generate a reset control signal RESET based on the feedforward signal Vff and a threshold signal Vth having a predetermined threshold voltage value. The reset control signal RESET may be a pulse-width modulated signal, with its pulse width indicating the on-time Ton. Reset control module 242 is configured to adjust the pulse width of the reset control signal RESET (indicating the on-time Ton) to vary with the input signal, thereby enabling the on-time Ton to dynamically track changes in the input signal and achieve a substantially fixed (or substantially constant) operating frequency Top over a relatively wide range of variations in the input signal (e.g., input voltage VIN or input current Ii). For example, in an embodiment, the input voltage VIN may vary from 20V to 70V, while the operating frequency Top of the power management device 2400 remains substantially constant (or substantially stable). This is at least partly due to the use of sensing unit 260, which can detect input signals (such as input voltage VIN or input current Ii) with higher accuracy and good linearity, thereby providing a feedforward signal Vff that tracks the input signal in a more accurate and substantially linear manner. A substantially fixed (or substantially constant) operating frequency Top benefits the power management device 2400 in several ways, including but not limited to improving power conversion efficiency, enhancing system stability, keeping the output voltage VOUT ripple relatively fixed, and reducing electromagnetic interference (EMI).

[0121] exist Figure 24 In the example, the reset control module 242 includes a voltage-controlled current source (VCCS) 2421, a ramp generation circuit 2422, and a comparator circuit 2425. The VCCS 2421 is configured to receive a feedforward signal Vff and provide a charging current Ich controlled by that signal, such that the charging current Ich is proportional to the input signal (e.g., input voltage VIN or input current Ii). The ramp generation circuit 2422 is configured to charge a ramp capacitor 2423 based on the charging current Ich and discharge the ramp capacitor 2423 in response to the reset control signal RESET, thereby generating a ramp signal Vramp. The comparator circuit 2425 is configured to compare the ramp signal Vramp with a threshold voltage Vth to generate the reset control signal RESET. It should be understood that... Figure 24 The configuration of the reset control module 242 described in the specific example shown is for illustrative purposes only and is not intended to limit its application. The reset control module 242 can obviously be implemented in many other variations, all of which provide a reset control signal RESET indicating the on-time Ton as a function of the input voltage VIN.

[0122] The logic control module 243 is configured to receive a set control signal SET and a reset control signal RESET, and generate a control signal CTRL based on these two signals. The control unit 240 can be configured to control the switching unit 110 to couple the inductive storage device 120, so that energy can be transferred from the input terminal IN to the inductive storage device 120 for energy storage according to the control signal CTRL in response to the set control signal SET. It can also be further configured to: in response to the reset control signal RESET, control the switching unit 110 to couple the inductive energy storage device 120 according to the control signal CTRL, so that energy can be transferred from the inductive energy storage device 120 to the output port OUT to release energy.

[0123] exist Figure 24 In the example, logic control module 243 is exemplarily depicted as including an RS flip-flop having a set input S, a reset input R, and an output Q. The RS flip-flop RS1 is configured to receive an ON control signal SETON at the set input S, an OFF control signal SETOFF at the reset input R, and provide a control signal CTRL at the output Q. However, this is merely an illustrative example and not a limiting provision; logic control module 243 can obviously employ various other implementations to generate the control signal CTRL based on the set control signal SET and the reset control signal RESET.

[0124] Those skilled in the art will understand that, Figure 24 The control unit 240 shown can also be used as Figure 23 An exemplary embodiment of the control unit 140. In this case, the feedback signal Vfb received at the second input terminal of the set control module 241 can be obtained from... Figure 23 The resistive sensing unit 160 is provided in the middle.

[0125] Figure 25 The waveforms of several signals during the operation of the power management device 2400 are shown. Figure 25 As can be seen, the pulse width of the reset signal RESET, which indicates the conduction time Ton, can change dynamically with the input voltage VIN. For example, the pulse width decreases when the input voltage VIN increases and increases when the input voltage VIN decreases, thereby keeping the operating frequency Top basically constant (or basically unchanged) when the input voltage VIN changes.

[0126] Although Figure 24In this embodiment, the control unit 240 is configured as a power management device 2400 that executes a conduction time control scheme. However, those skilled in the art should understand that in other embodiments, such as... Figures 21 to 23 The power management device, wherein the control unit 140 can be configured to implement other control schemes, such as a turn-off time control scheme, a peak current control scheme, a valley current control scheme, an average current mode control scheme, a voltage mode control scheme, a ripple-based control scheme, and V... 2 Current-mode control schemes, etc., are all within the spirit and scope of this disclosure.

[0127] In addition to being applied to Figures 21 to 25 Besides the power management device described above, the integrated resistive element that can be configured as a resistive sensing unit according to the embodiments of this disclosure can also be applied to many other application scenarios that require signal sensing. Therefore, electronic devices that include at least one resistive sensing unit in the embodiments of this disclosure to realize various application functions are all within the spirit and scope of the embodiments of this disclosure.

[0128] For example, Figure 26 A block diagram of an electronic device according to an embodiment of the present disclosure is shown, the device including a linear voltage regulator 2600. Those skilled in the art will understand that the linear voltage regulator 2600 is itself a power management device and can be provided as a standalone device or integrated into a larger-scale power management device (such as...). Figures 21 to 25 (As shown in the embodiment). The linear voltage regulator 2600 may include a sensing unit 261 configured to operably detect the output voltage VOUT at the output terminal OUT of the linear voltage regulator 2600. The sensing unit 261 is also configured to provide a feedback signal Vfb2 indicating the output voltage VOUT of the linear voltage regulator 2600. According to this disclosure as Figures 1 to 20AIn the various embodiments shown, the sensing unit 261 can be implemented using any integrated resistive element, which can be configured as a resistive sensing unit. In this application example, the integrated resistive element used to implement the sensing unit 261 is configured such that its first terminal 101A is electrically connected to the output terminal OUT of the linear voltage regulator 2600, its second terminal 101B is electrically connected to ground GND, and its sensing terminal 101S is configured to provide a sensed voltage Vs as a feedback signal Vfb, which can be provided to the regulator control unit 263. The regulator control unit 263 can be configured to provide a voltage regulation control signal REG based on the difference between the regulator feedback signal Vfb2 and the voltage regulation reference signal Vref2. The linear voltage regulator 2600 also includes a Zener transistor 262 connected between the input terminal IN and the output terminal OUT of the linear voltage regulator 2600. The regulator control unit 263 can be configured to control the Zener transistor 262 according to the Zener control signal REG, thereby regulating the output voltage VOUT of the linear voltage regulator 2600. Figures 1 to 20A The sensing unit 261 implemented by any of the integrated resistive elements shown can at least significantly improve the accuracy of adjusting the output voltage VOUT of the linear voltage regulator 2600 to the target voltage value.

[0129] In another example, Figure 27 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. The device includes an audio amplifier 2700. For example, the audio amplifier 2700 includes a first amplification unit 271 and a sensing unit 272. The audio amplifier 2700 may have a signal input terminal IN and a signal output terminal OUT. The signal input terminal IN may be configured to receive an input signal Vsig indicating audio input, and the signal output terminal OUT may be configured to provide an output signal VOUT indicating audio output. The audio amplifier 2700 may be configured to provide an amplification gain G1 to amplify the input signal Vsig to generate the output signal VOUT. That is, VOUT = G1 * Vsig. In one embodiment, the amplification gain G1 of the audio amplifier 2700 is adjusted by the sensing unit 272.

[0130] In one embodiment, the first amplification unit 271 may include a first operational amplifier OP1, which has a first input terminal (e.g., a non-inverting input terminal "+"), a second input terminal (e.g., an inverting input terminal "-"), and an output terminal. Figure 27 As shown, the first input terminal of the first amplification unit 271 is connected to ground GND, the second input terminal is connected to the sensing unit 272, and its output terminal is implemented as the signal output terminal OUT of the audio amplifier 2700.

[0131] In one embodiment, sensing unit 272 may be coupled between the signal input terminal IN and the signal output terminal OUT of audio amplifier 2700, and configured to provide an audio feedback signal Vfb3 indicating the difference between the output signal VOUT and the input signal Vsig. Sensing unit 272 may employ the methods disclosed herein. Figures 1 to 20A The embodiments shown are implemented using an integrated resistive element that can be configured as a resistive sensing unit. In this application example, the integrated resistive element used to implement the sensing unit 272 is configured such that its first terminal 101A is electrically connected to the signal output terminal OUT of the audio amplifier 2700, its second terminal 101B is electrically connected to the signal input terminal IN of the audio amplifier 2700, and its sensing terminal 101S is configured to provide a sensing voltage Vs, which can be supplied as an audio feedback signal Vfb3 to the second input terminal of the first amplification unit 271.

[0132] For such a typical configuration, the amplification gain G1 of the audio amplifier 2700 can be adjusted by the sensing unit 272, for example, by adjusting the sensing gain Ga of the integrated resistive element used to implement the sensing unit 272, where the sensing gain Ga depends on the resistance ratio K = R2 / R1. Figure 27 In the exemplary configuration of the audio amplifier 2700 shown, its amplification gain G1 can be expressed as G1 = -R2 / R1. Figures 1 to 20A The sensing unit 272, implemented by any of the integrated resistive elements, can at least effectively improve the linearity or stability of the amplification gain G1 of the audio amplifier 2700, thereby enabling the audio output to track the audio input with lower loss and distortion.

[0133] Figure 28 Waveform diagram 2800 is shown, including the actual curve 2801 showing the amplitude of the amplification gain G1 of the audio amplifier 2700 as a function of the input signal Vsig, and the theoretical ideal curve 2802 showing the amplitude of this gain as a function of the input signal Vsig. It is evident that the actual curve 2801 closely approximates the ideal curve 2802 with extremely low distortion. This means that in practical applications, the audio amplifier 2700 can achieve high-precision tracking of the audio output to the input signal while reducing loss and distortion.

[0134] In another embodiment, Figure 29A block diagram of an electronic device including an audio amplifier 2900 is shown in an alternative embodiment of this disclosure. By way of example, the audio amplifier 2900 includes a second amplification unit 291 and a sensing unit 292. The audio amplifier 2900 may have a signal input terminal IN and a signal output terminal OUT. The signal input terminal IN may be configured to receive an input signal Vsig indicating audio input, and the signal output terminal OUT may be configured to provide an output signal VOUT indicating audio output. The audio amplifier 2900 may be configured to provide an amplification gain G2 to amplify the input signal Vsig to generate the output signal VOUT. That is, VOUT = G2 * Vsig. In one embodiment, the amplification gain G2 of the audio amplifier 2900 is adjusted by the sensing unit 292.

[0135] In one embodiment, the second amplification unit 291 may include a second operational amplifier OP2, having a first input terminal (e.g., a non-inverting input terminal "+"), a second input terminal (e.g., an inverting input terminal "-"), and an output terminal. Figure 29 As shown, the first input terminal of the second amplification unit 291 is configured as the signal input terminal IN of the audio amplifier 2900, its second input terminal is connected to the sensing unit 292, and its output terminal is configured as the signal output terminal OUT of the audio amplifier 2900.

[0136] In one embodiment, the sensing unit 292 may be connected between the signal output terminal OUT of the audio amplifier 2900 and the reference ground GND, and configured to provide an audio feedback signal Vfb4 indicating the difference between the output signal VOUT and the input signal Vsig. The sensing unit 292 may employ the methods disclosed herein. Figures 1 to 20A The embodiments shown are implemented using an integrated resistive element that can be configured as a resistive sensing unit. In this application example, the integrated resistive element used to implement sensing unit 292 is configured such that its first terminal 101A is electrically connected to the signal output terminal OUT of audio amplifier 2900, its second terminal 101B is electrically connected to reference ground GND, and its sensing terminal 101S is configured to provide a sensed voltage Vs as an audio feedback signal Vfb4, which can be supplied to the second input terminal of the second amplification unit 291.

[0137] For such a typical configuration, the amplification gain G2 of the audio amplifier 2900 can be adjusted by the sensing unit 292, for example, by adjusting the sensing gain Ga of the integrated resistive element used to implement the sensing unit 292, where the sensing gain Ga depends on the resistance ratio K = R2 / R1. Figure 29 In the exemplary configuration of the audio amplifier 2900 shown, its amplification gain G2 can be expressed as G2 = 1 + R2 / R1. Figures 1 to 20AThe sensing unit 292, implemented by any of the integrated resistive elements, can at least effectively improve the linearity or stability of the amplification gain G2 of the audio amplifier 2900, thereby enabling the audio output to track the audio input with lower loss and distortion.

[0138] Figure 30 Waveform diagram 3000 is shown, including the actual curve 3001 (varying with input signal Vsig) and the theoretical ideal curve 3002 (varying with input signal Vsig) of the amplification gain G2 amplitude of the audio amplifier 2900. It can be seen that the actual curve 3001 closely approximates the ideal curve 3002 with extremely low distortion. This means that in practical applications, the audio amplifier 2900 can achieve high-precision tracking of the audio output to the input signal while reducing loss and distortion.

[0139] The integrated resistive elements involved in the various embodiments of this disclosure have many other applications, which cannot be fully listed herein, but these applications do not depart from the spirit and scope of the embodiments of this disclosure.

[0140] The advantages of the embodiments of this disclosure are not limited to those described above. These and other advantages of the embodiments of this disclosure will become clearer upon reading the full detailed description and studying the accompanying schematic diagrams.

[0141] In summary, the specific embodiments disclosed herein are intended to illustrate purposes, but the technical solutions can be modified in various ways without departing from their core technology. Many elements of a particular embodiment can be used in combination with other embodiments, or can replace elements of other embodiments.

Claims

1. An integrated resistive element, comprising: A first well region of a second conductivity type is formed in a substrate of a first conductivity type, wherein the second conductivity type is opposite to the first conductivity type. A second well region of a second conductivity type is formed in the substrate, wherein the second well region is separated from and electrically isolated from the first well region; and The first set of resistor segments includes a first portion disposed in or on a first well region and a second portion disposed in or on a second well region; wherein... The second part is used for electrical coupling between the first terminal and the sensing terminal of the integrated resistive element; and wherein The first portion is used for electrical coupling between the sensing terminal and the second terminal of the integrated resistive element; and in The first well region is configured to be biased by a first well region bias circuit, or the second well region is configured to be biased by a second well bias circuit.

2. The integrated resistive element of claim 1, wherein the second well bias circuit is formed in or on the second well region and includes a second plurality of resistive segments.

3. The integrated resistive element of claim 2, wherein, The second plurality of resistor segments are configured to be electrically coupled to each other between a first terminal of the second well region bias circuit and a second terminal of the second well region bias circuit, wherein the second well region is configured to be biased by a third terminal of the second well region bias circuit, the third terminal being disposed and connected between the second well region biased first portion and the second well region biased second portion of the second plurality of resistor segments.

4. The integrated resistive element as claimed in claim 2, wherein the second plurality of resistive segments are substantially identical to each other.

5. The integrated resistive element of claim 2, wherein each of the second plurality of resistive segments is formed on the second well region and includes a polysilicon segment.

6. The integrated resistive element as claimed in claim 5, further comprising: An insulating layer formed in the second well region and located below the second plurality of resistive segments.

7. The integrated resistive element of claim 2, wherein each of the second plurality of resistive segments includes a doped region of a first conductivity type formed in the second well region and having a higher doping concentration than the second well region.

8. The integrated resistive element as claimed in claim 2, further comprising: The second plurality of conductive connection segments are used to connect the second plurality of resistor segments in series.

9. The integrated resistive element as described in claim 2, further comprising: The first set of conductive connection segments is used for series electrical coupling of the first set of resistor segments in the first plurality of resistor segments; The second set of conductive connection segments is used for series electrical coupling of the second set of resistor segments in the first plurality of resistor segments; and The second well area bus is routed around the second set of conductive connection segments and the second and a plurality of conductive connection segments.

10. The integrated resistive element of claim 1, wherein the second well bias circuit includes a first terminal, a second terminal, and a third terminal, the first terminal being operatively electrically connected to a first terminal of the integrated resistive element or receiving a first input signal, the second terminal being operatively electrically connected to a sensing terminal or a second terminal of the integrated resistive element or a reference ground having a ground potential, or receiving a second input signal, and the third terminal being operatively configured to provide the second bias voltage.

11. The integrated resistive element of claim 1, wherein the second well bias circuit comprises: A second voltage scaling circuit has a first terminal, a second terminal and a third terminal, and is configured to operate to provide a second scaling voltage at its third terminal based on signals received at its first terminal and the second terminal, respectively. and The second buffer is connected to the third terminal of the second voltage scaling circuit and is configured to operate to provide a second scaled voltage as a second bias voltage through the second buffer.

12. The integrated resistive element of claim 1, wherein the first well region bias circuit is formed in or on the first well region and includes a third plurality of resistive segments.

13. The integrated resistive element of claim 12, wherein the third plurality of resistive segments are configured to be electrically coupled to each other between a first terminal of the first well region bias circuit and a second terminal of the first well region bias circuit, and wherein the first well region is configured to be biased by a third terminal of the first well region bias circuit, the third terminal being disposed and connected between a first well region biased first portion and a first well region biased second portion of the third plurality of resistive segments.

14. The integrated resistive element of claim 12, wherein the third plurality of resistive segments are substantially identical to each other.

15. The integrated resistive element of claim 12, wherein each of the third plurality of resistive segments is formed on top of the first well region and comprises a polysilicon segment.

16. The integrated resistive element of claim 15, further comprising: An insulating layer is formed in the first well region and disposed below the third plurality of resistive segments.

17. The integrated resistive element of claim 12, wherein each of the third plurality of resistive segments includes a doped region of a first conductivity type formed in the first well region, and the doping concentration of the doped region is higher than that of the first well region.

18. The integrated resistive element of claim 12, further comprising: The third plurality of conductive connection segments are configured to be series-coupled to the third plurality of resistive segments.

19. The integrated resistive element of claim 12, further comprising: The first set of conductive connection segments is used for series electrical coupling of the first set of resistor segments in the first plurality of resistor segments; The second set of conductive connection segments is used for series electrical coupling of the second set of resistor segments in the first plurality of resistor segments; and The first well area bus is wired around the first set of conductive connection segments and the third set of conductive connection segments.

20. The integrated resistive element of claim 1, wherein the first well bias circuit includes a first terminal, a second terminal, and a third terminal, the first terminal being operably configured to be electrically connected to a sensing terminal of the integrated resistive element or to receive a first input signal, the second terminal being operably electrically connected to a second terminal of the integrated resistive element or to a reference ground having a ground potential or to receive a second input signal, and the third terminal being operably configured to provide the first bias voltage.

21. The integrated resistive element of claim 1, wherein the first well bias circuit comprises: A first voltage scaling circuit has a first terminal, a second terminal and a third terminal, and is configured to be operable to provide a first scaling voltage at its third terminal based on signals received at its first terminal and the second terminal, respectively. and A first buffer is connected to the third terminal of a first voltage scaling circuit and configured to operate to provide a first scaled voltage as a first bias voltage through the first buffer.

22. The integrated resistive element as claimed in claim 1, further comprising: The protection circuit is electrically coupled between the sensing terminal of the integrated resistive element and the second portion of the plurality of resistive segments.

23. The integrated resistive element of claim 22, wherein the protection circuit is formed in a third well region, the third well region being formed in the substrate and isolated from the first well region and the second well region.

24. The integrated resistive element of claim 22, wherein the protection circuit is configured to be operable to enable or disable electrical coupling between the sensing terminal of the integrated resistive element and a second portion of the plurality of resistive segments.

25. The integrated resistor element of claim 22, wherein the protection circuit comprises: Protect the first terminal, which is electrically coupled to the first portion of the plurality of resistive segments of the sensing terminal or the integrated resistive element; The second terminal is protected, which is electrically coupled to the second portion of the plurality of resistive segments of the integrated resistive element; and The third terminal is protected and configured as a protection control terminal.

26. The integrated resistive element of claim 25, wherein the protection circuit is operable to enable or disable the path between the first protection terminal and the second protection terminal based on the electrical state of the protection control terminal.

27. The integrated resistive element of claim 22, wherein the protection circuit comprises a controllable transistor.

28. A power management device, comprising: A first resistive sensing unit includes a first integrated resistive element as claimed in claim 1, wherein the first terminal of the first integrated resistive element is electrically connected to the output terminal of the power management device to receive an output signal, the second terminal is electrically connected to a reference ground, and the sensing terminal is used to provide a feedback signal indicating the output signal. or The second resistive sensing unit includes the second integrated resistive element as claimed in claim 1, wherein the first terminal of the second integrated resistive element is operatively electrically connected to the input terminal of the power management device to receive an input signal, the second terminal of the second integrated resistive element is operatively electrically connected to a reference ground, and the sensing terminal of the second integrated resistive element is operatively provided with a feedforward signal indicating the input signal.

29. The power management device of claim 28, further comprising: A power switching unit for regulating the energy or power transfer between the input and output terminals of the power management device in response to at least one control signal.

30. The power management device of claim 29, wherein the power switching unit is formed in an integrated circuit chip including a first resistive sensing unit or a second resistive sensing unit.

31. The power management device of claim 28, further comprising: The control unit is used to receive feedback signals or feedforward signals and further to provide at least one control signal to control the power switching unit of the power management device.

32. The power management device of claim 31, wherein the control unit is formed in an integrated circuit chip including a first resistive sensing unit or a second resistive sensing unit.

33. The power management device of claim 31, wherein the control unit comprises: A set control module is configured to receive an output feedback signal that is a reference signal and an indication output signal, and to compare the output feedback signal with the reference signal to provide a set control signal, wherein the output feedback signal is provided by a feedback circuit connected to the output terminal of the power management device, or by a first resistive sensing unit, or is the output signal itself; A reset control module is coupled to a second resistive sensing unit to receive a feedforward signal and is configured to provide a reset control signal based on the feedforward signal and a threshold signal, and to adjust the pulse width of the reset control signal to vary with the input signal. as well as The logic control module is configured to receive the set control signal and the reset control signal, and to provide at least one control signal based on the set control signal and the reset control signal.

34. The power management device of claim 33, wherein the reset control module comprises: A voltage-controlled current source is configured to receive a feedforward signal and provide a charging current controlled by the feedforward signal. The ramp generation circuit is configured to charge the ramp capacitor according to the charging current and discharge the ramp capacitor in response to the reset control signal, thereby providing a ramp signal; as well as The comparator circuit is configured to compare the ramp signal with the threshold signal to provide a reset control signal.

35. The power management device of claim 28, wherein the power management device simultaneously includes a first resistive sensing unit and a second resistive sensing unit.

36. The power management device of claim 35, further comprising: The control unit is used to receive feedback signals and feedforward signals, and further to provide at least one control signal to control the power switching unit of the power management device.

37. The power management device of claim 28, further comprising: A linear voltage regulator for providing a voltage regulator output voltage, wherein the linear voltage regulator includes a third resistive sensing unit comprising a third integrated resistive element as described in claim 1, wherein a first terminal of the third integrated resistive element is electrically connected to an output terminal of the linear voltage regulator, a second terminal of the third integrated resistive element is electrically connected to a reference ground, and a sensing terminal of the third integrated resistive element is used to provide a regulator feedback signal indicating the regulator output voltage.

38. The power management device of claim 37, wherein the linear voltage regulator further comprises: The regulating transistor is coupled between the input and output terminals of the linear voltage regulator; as well as The adjustment control unit is configured to provide an adjustment control signal to control the adjustment transistor based on the difference between the regulator feedback signal and the adjustment reference signal.

39. The power management device of claim 37, wherein the first resistance detection unit and the second resistance detection unit are omitted.

40. An electronic device including an audio amplifier, comprising: A resistive sensing unit comprising the integrated resistive element of claim 1, the resistive sensing unit being coupled between the signal input and signal output of an audio amplifier, wherein the resistive sensing unit is configured to provide an audio feedback signal indicating the difference between the output signal and the input signal.

41. The electronic device of claim 40, wherein a first terminal of the integrated resistive element is electrically connected to a signal output terminal, a second terminal of the integrated resistive element is electrically connected to a signal input terminal, and a sensing terminal of the integrated resistive element is used to provide an audio feedback signal.

42. The electronic device of claim 40, wherein the audio amplifier further comprises: The first amplification unit has its first input terminal connected to a reference ground, its second input terminal connected to a resistive sensing unit to receive audio feedback signals, and its output terminal serving as the signal output terminal of the audio amplifier.

43. The electronic device of claim 40, wherein the audio amplifier is used to provide amplification gain to amplify the input signal, thereby generating an output signal, and the resistive sensing unit is used to adjust the amplification gain.

44. The electronic device of claim 43, wherein the amplification gain depends on the resistance ratio between a first resistance of a first portion of a plurality of resistance segments and a second resistance of a second portion of a plurality of resistance segments.

45. The electronic device of claim 40, wherein the resistive sensing unit comprises the integrated resistive element of claim 1, the resistive sensing unit being connected between the signal output of the audio amplifier and a reference ground.

46. ​​The electronic device of claim 45, wherein a first terminal of the integrated resistive element is used for electrical connection to a signal output terminal, a second terminal is used for electrical connection to a reference ground, and a sensing terminal is used for providing an audio feedback signal.

47. The electronic device of claim 45, wherein the audio amplifier further comprises: The second amplification unit has a first input terminal configured as the signal input terminal of an audio amplifier, a second input terminal connected to a resistive sensing unit to receive audio feedback signals, and an output terminal serving as the signal output terminal of the audio amplifier.

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