Semiconductor device and method of forming the same

Abstract

This disclosure provides a semiconductor device and a method for forming the same. A capacitor structure included in the semiconductor device may include one or more electrode layers comprising materials with low hydrogen absorption characteristics to achieve a low hydrogen concentration in the capacitor structure. These materials enable the capacitor structure to be formed using low-temperature processes compatible with the layers and / or structure of the semiconductor device, while also enabling the capacitor structure to achieve fast charging and discharging speeds. Furthermore and / or alternatively, one or more electrode layers of the capacitor structure may comprise a metallic material with a high bandgap, which reduces the likelihood (and / or number) of charge carrier tunneling. This enables the capacitor structure to achieve low leakage current, allowing the capacitor structure to retain charge for a longer period with fewer charge refreshes (which reduces the power consumption of the semiconductor device).

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for forming the same. Background Technology

[0002] Capacitor structures, such as deep trench capacitors (DTC), can include metal-insulator-metal (MIM) structures, where an insulating layer is sandwiched between two conductive electrode layers. Various types of semiconductor devices can include one or more capacitor structures, such as image sensor devices, radio frequency (RF) devices, memory devices (e.g., dynamic random access memory (DRAM) devices), logic devices, processors, system-on-chip (SoC) devices, and / or integrated passive devices (IPDs).

[0003] In semiconductor devices, capacitor structures can be contained within interconnect layers (e.g., back-end regions) of the semiconductor device. The capacitor structure can extend through multiple dielectric layers in the interconnect layer and can be electrically coupled to one or more conductive structures in the interconnect layer. Summary of the Invention

[0004] One embodiment of this disclosure provides a semiconductor device, including: a device layer; a plurality of transistors located in the device layer; an interconnect layer located above the plurality of transistors, wherein the interconnect layer includes: a plurality of dielectric layers interleaved with a plurality of etch stop layers; and a plurality of metallization structures disposed in the plurality of dielectric layers, wherein a first thickness of a first metallization structure located at the bottom of the interconnect layer is less than a second thickness of a second metallization structure located above the first metallization structure; and a capacitor structure located in one or more of the plurality of dielectric layers of the interconnect layer, wherein the capacitor structure includes: a bottom electrode layer coupled to the second metallization structure, wherein the bottom electrode layer comprises a metallic material having a work function greater than that of titanium and a hydrogen diffusion coefficient less than that of titanium; a top electrode layer; and an insulating layer located between the top electrode layer and the bottom electrode layer.

[0005] Another embodiment of this disclosure provides a semiconductor device, including: a device layer; a plurality of transistors, wherein at least one of the plurality of transistors includes: a gate structure connected to at least three sides of a channel layer; a gate dielectric layer, above the channel layer and between the channel layer and the gate structure; an interconnect layer, above the plurality of transistors, including: a plurality of dielectric layers; a multilayer metallization structure disposed in the plurality of dielectric layers, wherein the multilayer metallization structures are spaced apart from each other by the plurality of dielectric layers, and wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the plurality of dielectric layers; and a capacitor structure disposed in one of the plurality of dielectric layers of the interconnect layer. In one or more of these, the capacitor structure includes: a bottom electrode layer coupled to a first metallization structure in the multilayer metallization structure; a top electrode layer coupled to a second metallization structure in the multilayer metallization structure; and an insulating layer between the top electrode layer and the bottom electrode layer, wherein at least one of the bottom electrode layer or the top electrode layer includes a multilayer thin film, the multilayer thin film including: a first metal layer containing a first metal material; and a second metal layer containing a second metal material different from the first metal material, wherein the hydrogen diffusion coefficient of the first metal material is less than that of titanium, and wherein the work function of the second metal material is greater than that of titanium.

[0006] One embodiment of this disclosure provides a method comprising: forming a plurality of transistors in a device layer of a semiconductor device; forming a plurality of dielectric layers and a multilayer conductive structure in the plurality of dielectric layers over the plurality of transistors; forming a recess through at least a portion of the plurality of dielectric layers; depositing a bottom electrode layer of a capacitor structure in the recess such that a portion of the bottom electrode layer is deposited over the conductive structure of the multilayer conductive structure, wherein a first metal material of the bottom electrode layer has a hydrogen diffusion coefficient less than a second metal material of the conductive structure; depositing an insulating layer of the capacitor structure over the bottom electrode layer in the recess; and depositing a top electrode layer of the capacitor structure over the insulating layer in the recess. Attached Figure Description

[0007] The various aspects of this disclosure are best understood when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A and Figure 1B This is a diagram of a portion of the example semiconductor device described in this article.

[0009] Figures 2A-2C This is an illustration of an example embodiment of the charging and discharging operation of the capacitor structure described herein.

[0010] Figures 3A-3C This is an illustration of an example embodiment of the charging and discharging operation of the capacitor structure described herein.

[0011] Figures 4A-4K This is an illustration of an example embodiment forming the semiconductor device described herein.

[0012] Figures 5A-5F This is an illustration of an example embodiment of the electrode layer combination of the capacitor structure described herein.

[0013] Figures 6A-6E This is a diagram illustrating an example embodiment of the structural arrangement of the capacitor structure described in this article.

[0014] Figure 7 This is a flowchart of an example process related to the formation of the semiconductor device described herein. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments where the first and second features form direct contact, or embodiments where an additional feature may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to facilitate the description of the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to also encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein will be interpreted accordingly.

[0017] In some cases, back-end process techniques that are thermally budget-compatible with layers and / or structures formed in other regions of the semiconductor device (e.g., device layers, such as the front-end region) can be used to form capacitor structures in the interconnect layers of the semiconductor device. Some layers and / or structures formed from metal silicides and metals (e.g., copper (Cu)) may be prone to degradation when subjected to high-temperature processes, which can lead to material diffusion and consequently affect performance, such as increased leakage current in the semiconductor device.

[0018] However, if cryogenic processes are used to form the capacitor structure, some layers of the capacitor structure may be susceptible to hydrogen (H) contamination. These cryogenic processes may not be able to effectively remove hydrogen from the layers of the capacitor structure. Hydrogen retained in the capacitor structure may cause charge trapping, which could lead to increased charging and discharging times.

[0019] Furthermore and / or alternatively, the electrode layer of the capacitor structure may be formed of a metallic material that is prone to leakage current. For example, titanium-containing materials may be prone to leakage current from the electrode layer, which may reduce the charge retention performance of the capacitor structure. Reduced charge retention capability of the capacitor structure may lead to increased power consumption when the capacitor structure is implemented as a memory structure, as an increased number of charge refreshes may be required to retain data in the capacitor structure.

[0020] In some embodiments described herein, the capacitor structure contained within a semiconductor device (e.g., an interconnect layer of the semiconductor device) may include one or more electrode layers containing materials with low hydrogen absorption properties to achieve a low hydrogen concentration in the capacitor structure. These materials enable the capacitor structure to be formed using low-temperature processes compatible with the layers and / or structure of the semiconductor device, while also enabling the capacitor structure to achieve fast charging and discharging speeds.

[0021] Furthermore and / or alternatively, one or more electrode layers of the capacitor structure may contain metallic material for adjusting the bandgap of the electrode layers. For example, the metallic material of the electrode layers may have a high bandgap, which reduces the likelihood (and / or number) of charge carrier tunneling. This enables the capacitor structure to achieve low leakage current, allowing it to retain charge for longer periods with fewer charge refreshes (which reduces the power consumption of the semiconductor device).

[0022] Figure 1A and Figure 1BThis is an icon representing a portion of the example semiconductor device 100 described herein. The semiconductor device 100 may include a system-on-chip (SoC) device, a logic device (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)), a memory device (e.g., a high bandwidth memory (HBM) device), a panel driver device, an integrated circuit (IC) driver, a radio frequency (RF) power amplifier, a display driver IC (DDIC), and / or other types of semiconductor devices.

[0023] like Figure 1A As shown, the semiconductor device 100 may include a device layer 102 and an interconnect layer 104 located above the device layer 102 in the z-direction of the semiconductor device 100. The device layer 102 includes a substrate layer 106. The substrate layer 106 may correspond to a portion of a semiconductor wafer forming the semiconductor device 100. The substrate layer 106 may include a silicon (Si) substrate, a substrate formed of a silicon-containing material, a III-V compound semiconductor material substrate (e.g., gallium arsenide (GaAs)), a silicon-on-insulator (SOI) substrate, or other types of semiconductor substrates. The substrate layer 106 may extend in the x-direction and / or y-direction of the semiconductor device 100.

[0024] A dielectric layer 108 is contained above a substrate layer 106. The dielectric layer 108 includes an interlayer dielectric (ILD) layer (e.g., an ILD0 layer), an etch stop layer (ESL), and / or other types of dielectric layers. The dielectric layer 108 includes dielectric materials that allow portions of the substrate layer 106 to be selectively etched or protected from etching, and / or electrically isolates integrated circuit devices 110 in the device layer 102. The dielectric layer 108 includes silicon nitride (Si). x N y ), oxides (e.g., silicon dioxide (SiO2) x (and / or other oxide materials) and / or other types of dielectric materials. The dielectric layer 108 may extend in the x direction and / or y direction of the semiconductor device 100.

[0025] Integrated circuit device 110 may be contained in and / or on substrate layer 106, and / or in dielectric layer 108 in device layer 102 of semiconductor device 100. Integrated circuit device 110 includes transistors (e.g., planar transistors, fin field-effect transistors (finFETs), gate all-around (GAA) transistors), pixel sensors, capacitors, resistors, inductors, photosensors, transceivers, transmitters, receivers, optical circuits, and / or other types of semiconductor devices.

[0026] Integrated circuit device 110 may include a plurality of source / drain regions 112, which are grown and / or otherwise formed on and / or around portions of substrate 106. “Source / drain region” may refer individually or collectively to a source or drain, depending on the context. Source / drain regions 112 may be formed by epitaxial growth of doped semiconductor regions and / or by other semiconductor processes. In some embodiments, source / drain regions 112 are formed in recessed portions of substrate 106. Recessed portions may be formed by strained source / drain (SSD) etching and / or other types of etching operations on substrate 106. In some embodiments, source / drain regions 112 are formed in recesses formed in alternating stacks of channel layers and sacrificial layers (e.g., silicon-germanium (SiGe)) layers.

[0027] The integrated circuit device 110 may further include a gate dielectric layer 114 located between the gate structure 116 and the channel layer 118 of the integrated circuit device 110. The channel layer 118 may extend between the source / drain regions 112 of the integrated circuit device 110, and the gate dielectric layer 114 and the gate structure 116 may surround two or more sides of the channel layer 118. In some embodiments, the gate dielectric layer 114 and the gate structure 116 surround all four sides of the channel layer 118. In these embodiments, the integrated circuit device 110 may be referred to as a nanostructure transistor, such as a GAA transistor.

[0028] The channel layer 118 may include a nanoscale semiconductor material layer, such as silicon (Si), silicon germanium (SiGe), and / or other instances of doped silicon. The channel layer 118 may be formed of silicon nanosheets as part of a stack of nanosheets above the substrate layer 106.

[0029] In some embodiments, the gate dielectric layer 114 comprises a low-k dielectric material, such as silicon oxide (SiO2). xIn some embodiments, the gate dielectric layer 114 comprises a high-k dielectric material, such as hafnium oxide (HfO). x ).

[0030] The gate structure 116 may be laterally located between the source / drain regions 112. In some embodiments, the gate structure 116 is formed of a polysilicon material. In these embodiments, the polysilicon material may be doped with one or more types of dopants (e.g., p-type dopants, n-type dopants) to adjust the work function of the gate structure 116.

[0031] In some embodiments, the gate structure 116 is formed of one or more metallic materials (e.g., tungsten (W), titanium (Ti), cobalt (Co), and / or other metals). In these embodiments, the gate structure 116 may include one or more work function metal layers (e.g., p-type metal layers, n-type metal layers) to adjust the work function of the gate structure 116. The work function metal layers may be included between the gate dielectric layer 114 and the gate structure 116.

[0032] The p-type work function metal layer may include one or more p-type metals, such as tungsten (W), cobalt (Co), titanium nitride (TiN), tungsten nitride (WN), and / or other metals having a work function greater than about 4.7 electron volts (eV). The p-type work function metal layer can be used to adjust the work function of the gate structure 116 to bring it closer to the valence band of the material of the channel layer 118.

[0033] The n-type work function metal layer may include one or more metallic materials that modulate or adjust the work function of the gate structure 116 to the conduction band of the channel layer 118 material adjacent to the semiconductor device 100. In some embodiments, the n-type work function metal layer may include titanium aluminum (TiAl). In some embodiments, the n-type work function metal layer includes titanium aluminum carbide (TiAlC). In some embodiments, the n-type work function metal layer includes other aluminum-containing metals. In some embodiments, the n-type work function metal layer includes other n-type metallic materials.

[0034] The integrated circuit device 110 may include various spacers. For example, a sidewall spacer 120a may be disposed on the sidewall of the gate structure 116 to provide electrical isolation and other functions for the gate structure 116. In some embodiments, the sidewall spacer 120a is in contact with the gate dielectric layer 114. In some embodiments, the sidewall spacer 120a is in contact with the work function metal layer. The sidewall spacer 120a may include silicon oxide (SiO2). x ), silicon nitride (Si x N y), silicon oxycarbonate (SiOC), silicon oxycarbonitrile (SiOCN) and / or other suitable materials.

[0035] As another example, the inner spacer 120b may be laterally located between the gate structure 116 and the source / drain region 112 of the integrated circuit device 110. The inner spacer 120b can be used to reduce parasitic capacitance in the integrated circuit device 110 and protect the source / drain region 112 from etching during nanosheet release operations (to remove the sacrificial layer between channel layers 118). The inner spacer 120b may comprise silicon nitride (Si). x N y ), silicon dioxide (SiO) x Silicon oxynitride (SiON), silicon oxycarbonate (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and / or other dielectric materials.

[0036] The source / drain region 112 is electrically coupled and / or physically coupled to the source / drain contact structure 122. The source / drain contact structure 122 may include contact vias, contact plugs, and / or other types of contact structures that electrically connect the source / drain region 112 of the integrated circuit device 110 to the interconnect layer 104 of the semiconductor device 100. The source / drain contact structure 122 includes cobalt (Co), ruthenium (Ru), tungsten (W), molybdenum (Mo), copper (Cu), and / or other conductive or metallic materials. One or more substrates 124 may be included on the sidewalls of the source / drain contact structure 122. The substrate 124 may include a barrier layer, an adhesive layer, or a glue layer, and / or other types of substrates. The barrier layer is used to prevent or minimize the diffusion of material from the source / drain contact structure 122 to the surrounding dielectric layer. The adhesive layer or glue layer is used to promote adhesion between the source / drain contact structure 122 and the surrounding dielectric layer. Examples of materials for liner 124 include titanium nitride (TiN), tantalum nitride (TaN), and / or other suitable liner materials.

[0037] Interconnect layer 104 of semiconductor device 100 is located above device layer 102 and above integrated circuit device 110 in the z-direction of semiconductor device 100. Interconnect layer 104 includes a plurality of dielectric layers arranged along a direction substantially perpendicular to substrate layer 106 (e.g., z-direction). The dielectric layers may include ILD layer 126 and ESL 128, which are arranged alternately in the z-direction. ILD layer 126 and ESL 128 may extend in the x-direction and / or y-direction of semiconductor device 100.

[0038] ILD layers 126 may each comprise oxides (e.g., silicon oxide (SiO2)). xThe dielectric material can be an undoped silicate glass (USG), a borosilicate glass (BSG), a fluorine-containing silicate glass (FSG), a tetraethyl orthosilicate (TEOS), a hydrogensilsesquioxane (HSQ), or other suitable dielectric materials. In some embodiments, the ILD layer 126 comprises an extremely low dielectric constant (ELK) dielectric material with a dielectric constant less than about 2.5. Examples of ELK dielectric materials include carbon-doped silicon oxide (C-SiO₂). x ), amorphous fluorinated carbon (aC) x F y ), parylene, bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon carbide (SiOC) polymers, porous hydrosilsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylether (PAE), and / or porous silica (SiO2). x Examples such as ).

[0039] ESL 128 may each include silicon nitride (Si) x N y Silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials. In some embodiments, ILD layers 126 and ESL 128 comprise different dielectric materials to provide etch selectivity, enabling various structures to be formed in interconnect layer 104.

[0040] Interconnect layer 104 may further include multilayer conductive structures in the dielectric layers of interconnect layer 104 (e.g., ILD layers 126 and ESL 128). The conductive structures in interconnect layer 104 may be interconnected to allow signal and / or power distribution throughout the semiconductor device 100 via interconnect layer 104. The conductive structures include combinations of metallization structures 130 and interconnect structures 132. Metallization structure 130 may include trenches, conductive traces, and / or other types of conductive structures extending primarily in the x and / or y directions of interconnect layer 104. Interconnect structure 132 may include vias, plugs, conductive pillars, and / or other types of conductive structures extending primarily in the z direction of the semiconductor device. In some embodiments, the conductive structures in interconnect layer 104 include dual damascene structures, which include combinations of metallization structures 130 and interconnect structures 132.

[0041] The metallization structure 130 and the interconnect structure 132 may each comprise one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, or other examples of conductive materials. In some embodiments, one or more liner layers are included between the metallization structure 130 and / or the interconnect structure 132 and the dielectric layer surrounding the interconnect layer 104. The one or more liner layers may include barrier liner layers, adhesion liner layers, and / or other types of liner layers. Examples of materials for the one or more liner layers include tantalum nitride (TaN) and / or titanium nitride (TiN).

[0042] In some embodiments, the metallization structures 130 and interconnect structures 132 of interconnect layer 104 may be arranged vertically (e.g., in the z-direction). In other words, multiple stacked metallization structures 130 and interconnect structures 132 may extend between the top of device layer 102 and interconnect layer 104 to facilitate the routing of electrical signals and / or power between device layer 102 and the connection structure (not shown) of semiconductor device 100.

[0043] Multiple stacked metallization structures 130 may be arranged in a layer, which may be referred to as the M layer, while multiple stacked interconnect structures 132 may be arranged in a layer, which may be referred to as the V layer. The bottommost interconnect structure 132a in the interconnect layer 104 may be referred to as the V0 layer and may include a source / drain interconnect structure 134 to be connected to a gate interconnect structure 136. The source / drain interconnect structure 134 is electrically coupled and / or physically coupled to the source / drain contact structures 122 of one or more integrated circuit devices 110, and the gate interconnect structure 136 is electrically coupled and / or physically coupled to the gate structures 116 of one or more integrated circuit devices 110. The source / drain interconnect structure 134 is referred to as a source / drain via (VD), and the gate interconnect structure 136 is referred to as a gate via (VG). In some embodiments, a gate contact (not shown) is included between the gate structure 116 and the gate interconnect structure 136.

[0044] The metallized layer 130a may be referred to as the metal-0 (M0) layer and may be located above the interconnect layer 132a (including the source / drain interconnect structure 134 and the gate interconnect structure 136) in the interconnect layer 104. The metallized structure in the M0 layer may be electrically coupled and / or physically coupled to the source / drain interconnect structure 134 and / or the gate interconnect structure 136.

[0045] Additional conductive structure layers can be arranged in a similar manner within interconnect layer 104. For example, interconnect layer 132b may be referred to as via-1 (V1) layer, which is located above and electrically and / or physically coupled to the metallization layer 130a in layer M0. Metallization layer 130b may be referred to as metal-1 (M1) layer, which is located above and electrically and / or physically coupled to the interconnect layer 132b in layer V1. Interconnect layer 132c may be referred to as via-2 (V2) layer, which is located above and electrically and / or physically coupled to the metallization layer 130b in layer M1. Metallization layer 130c may be referred to as metal-2 (M2) layer, which is located above and electrically and / or physically coupled to the interconnect layer 132c in layer V2. Interconnect layer 132d may be referred to as via-3 (V3) layer, which is located above and electrically and / or physically coupled to the metallization layer 130c in layer M2. Layer 130d of the metallized structure may be referred to as the Metal-3 (M3) layer, which is located above and electrically and / or physically coupled to layer 132d of the interconnect structure in layer V3. Layer 132e of the interconnect structure may be referred to as the Via-4 (V4) layer, which is located above and electrically and / or physically coupled to layer 130d of the metallized structure in layer M3. Layer 130e of the metallized structure may be referred to as the Metal-4 (M4) layer, which is located above and electrically and / or physically coupled to layer 132e of the interconnect structure in layer V4. In some embodiments, interconnect layer 104 includes... Figure 1AThe different numbers of metallization structures 130 and / or different numbers of interconnect structures 132 shown.

[0046] like Figure 1A As further shown, the metallization structure size of the layer of metallization structure 130 can increase with its position in the interconnect layer 104. For example, the thickness of metallization structure 130a (as in the M0 layer) can have a first thickness (in Figure 1A The thickness of the metallized structure 130b (as indicated by dimension D1, such as in layer M1) may have a second thickness (in...). Figure 1A The dimension is indicated as D2), and the second thickness can be greater than the first thickness. Another example is that the thickness of the metallized structure 130a (e.g., in the M0 layer) can have a first thickness (in...). Figure 1A The thickness of the metallized structure 130e (as indicated by dimension D1) can have a second thickness (in the M4 layer). Figure 1A The designation is D3), and the second thickness can be greater than the first thickness. Another example is that the thickness of the metallized structure 130b (e.g., in layer M1) can have a first thickness (in...). Figure 1A The thickness of the metallized structure 130e (as indicated by dimension D2) can have a second thickness (in the M4 layer). Figure 1A The dimension is indicated as D3), and the second thickness can be greater than the first thickness.

[0047] The increased thickness of the metallization structure 130 layer in interconnect layer 104 allows higher voltage and / or higher current signals and / or power to be distributed closer to the top of interconnect layer 104. As the signal propagates downward in interconnect layer 104, the voltage and / or power of the signal are reduced to achieve power efficiency and / or to allow for a higher density of metallization structures 130 to be arranged at the bottom of interconnect layer 104.

[0048] like Figure 1AAs further shown, the semiconductor device 100 may include one or more capacitor structures 138 in the interconnect layer 104. The capacitor structure 138 may include a trench capacitor structure contained within one or more dielectric layers of the interconnect layer 104 (e.g., one or more ILD layers 126, one or more ESL 128) and extending through one or more dielectric layers of the interconnect layer 104. The capacitor structure 138 may include a deep trench capacitor (DTC) structure because the capacitor structure 138 has a high aspect ratio between its vertical (z-direction) height and its lateral (x-direction) width. For example, the aspect ratio of the capacitor structure 138 may be greater than about 10:1, and in some embodiments is included in the range of about 18:1 to about 55:1. However, other values ​​and ranges of the aspect ratio of the capacitor structure 138 are also within the scope of this disclosure.

[0049] like Figure 1A As shown, the capacitor structure 138 may include multiple conformal layers, including a bottom electrode layer 140, a top electrode layer 142, and an insulating layer 144 sandwiched between the bottom electrode layer 140 and the top electrode layer 142.

[0050] Bottom electrode layer 140, insulating layer 144, and top electrode layer 142 correspond to the MIM stack of capacitor structure 138. Therefore, capacitor structure 138 can also be referred to as MIM capacitor structure. Bottom electrode layer 140 (also referred to as capacitor bottom metal (CBM)) and top electrode layer 142 (also referred to as capacitor top metal (CTM)) may each comprise one or more conductive metals, one or more materials containing conductive metals, one or more conductive ceramic materials, and / or other types of conductive materials. Examples include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), gold (Au), titanium nitride (TiN), and / or tantalum nitride (TaN), etc. In some embodiments, bottom electrode layer 140 and top electrode layer 142 comprise the same material or the same material composition. In some embodiments, bottom electrode layer 140 and top electrode layer 142 comprise different materials or different material compositions.

[0051] The insulating layer 144 may include one or more electrically insulating materials. In some embodiments, the insulating layer 144 includes one or more low-k dielectric materials, such as silicon oxide (SiO2). x (e.g., SiO2). Additionally and / or alternatively, the insulating layer 144 may comprise one or more high-k dielectric materials, such as zirconium oxide (ZrO2). x Such as ZrO2), aluminum oxide (Al)x O y Such as Al2O3), silicon nitride (Si) x N y Such as Si3N4), yttrium oxide (Y) x O y Such as Y2O3), lanthanum oxide (La) x O y (e.g., La2O3) and / or hafnium oxide (HfO) x Other examples include HfO2. In some embodiments, insulating layer 144 is a multilayer stack comprising multiple dielectric layers. For example, insulating layer 144 may comprise a ZrO2 / Al2O3 / ZrO2 (ZAZ) layer stack.

[0052] In some embodiments, the capacitor structure 138 includes a single trench segment, wherein a bottom electrode layer 140, a top electrode layer 142, and an insulating layer 144 may extend along the sidewalls and bottom surface of a trench through one or more dielectric layers of the interconnect layer 104. A dielectric filler 146 may fill the remaining portion of the trench segment. However, in other embodiments, the dielectric filler 146 is omitted. In some embodiments, the capacitor structure 138 includes multiple trench segments. In some embodiments, the bottom electrode layer 140, the top electrode layer 142, and the insulating layer 144 may extend continuously through the trench segments and between the trench segments. In some embodiments, such as Figure 1A In the example shown, each trench segment contains a discontinuous bottom electrode layer 140.

[0053] like Figure 1A As further shown, the capacitor structure 138 may be electrically coupled and / or physically coupled to one or more conductive structures in the interconnect layer 104. In some embodiments, the bottom electrode layer 140 of the capacitor structure 138 is located on and / or electrically connected to the metallization structure 130, such as metallization structure 130b (e.g., in layer M1). In these embodiments, the bottom electrode layer 140 is electrically coupled to the metallization structure 130b at the bottom of the capacitor structure 138. In some embodiments, the metallization structure 130, such as metallization structure 130e (e.g., in layer M4), is located on and / or electrically connected to the top electrode layer 142 of the capacitor structure 138. In these embodiments, the top electrode layer 142 is electrically coupled to the metallization structure 130e at the top of the capacitor structure 138. However, other connection arrangements are also within the scope of this disclosure. For example, the bottom electrode layer 140 and the top electrode layer 142 may both be electrically coupled to the metallization structure 130 on top of the capacitor structure 138.

[0054] like Figure 1BAs shown, the bottom electrode layer 140 and / or top electrode layer 142 of capacitor structure 138 may contain one or more metallic materials that suppress hydrogen (H) absorption in capacitor structure 138. Various conductive structures in interconnect layer 104 (e.g., metallization structure 130, interconnect structure 132) may contain copper (Cu) and / or other metallic materials that absorb hydrogen more readily than other metallic materials. Therefore, the bottom electrode layer 140 and / or top electrode layer 142 may be formed of metallic materials that prevent hydrogen from being absorbed into insulating layer 144 from being absorbed, which could otherwise lead to charge trapping in insulating layer 144. Charge trapping can create leakage paths in insulating layer 144. Therefore, the metallic materials of the bottom electrode layer 140 and / or top electrode layer 142 enable capacitor structure 138 to achieve low leakage current.

[0055] The metallic material of the bottom electrode layer 140 and / or the top electrode layer 142 may have a low hydrogen diffusion coefficient to facilitate hydrogen diffusion. As used herein, a metallic material with a low hydrogen diffusion coefficient can refer to a metallic material having a lower hydrogen diffusion coefficient at approximately the same temperature than titanium-containing materials such as titanium (Ti) and titanium nitride (TiN). Examples of such metallic materials include various transition metals from Groups 6 to 12 of the periodic table, such as ruthenium (Ru), tungsten (W), nickel (Ni), silver (Ag), and / or palladium (Pd), among others. In some embodiments, the bottom electrode layer 140 and / or the top electrode layer 142 may comprise another metallic material with a low hydrogen diffusion coefficient, such as aluminum (Al).

[0056] These metallic materials have crystalline structures with a limited number of interstitial sites available for hydrogen diffusion, thus restricting the material's ability to diffuse through. For example, ruthenium may have a hexagonal close-packed (hcp) crystal structure with a limited number of interstitial sites available for hydrogen diffusion. Another example is tungsten, which may have a body-centered cubic (bcc) crystal structure with a limited number of interstitial sites available for hydrogen diffusion.

[0057] In some embodiments, the bottom electrode layer 140 and the top electrode layer 142 may each comprise a metallic material having a lower hydrogen diffusion coefficient than that of titanium. In these embodiments, the bottom electrode layer 140 may prevent hydrogen from diffusing from the conductive structure below the capacitor structure 138 into the insulating layer 144, while the top electrode layer 142 may prevent hydrogen from diffusing from the conductive structure above the capacitor structure 138 into the insulating layer 144.

[0058] In some embodiments, the bottom electrode layer 140 comprises a metallic material having a lower hydrogen diffusion coefficient than that of titanium, while the top electrode layer 142 comprises a different metallic material, such as titanium (Ti). In these embodiments, the hydrogen diffusion coefficient of the metallic material of the bottom electrode layer 140 may be less than that of the metallic material of the top electrode layer 142. In some embodiments, the top electrode layer 142 comprises a metallic material having a lower hydrogen diffusion coefficient than that of titanium, while the bottom electrode layer 140 comprises a different metallic material, such as titanium (Ti). In these embodiments, the hydrogen diffusion coefficient of the metallic material of the bottom electrode layer 140 may be greater than that of the metallic material of the top electrode layer 142.

[0059] In some embodiments, the bottom electrode layer 140 and the top electrode layer 142 comprise the same metallic material having a low hydrogen diffusion coefficient. For example, both the bottom electrode layer 140 and the top electrode layer 142 comprise ruthenium (Ru). In some embodiments, the bottom electrode layer 140 and the top electrode layer 142 comprise different metallic materials, each having a low hydrogen diffusion coefficient. For example, the bottom electrode layer 140 may comprise tungsten (W), while the top electrode layer 142 may comprise nickel (Ni).

[0060] Additionally and / or the metal material replacing the bottom electrode layer 140 and / or the top electrode layer 142 has a low hydrogen diffusion coefficient, and the metal material of the bottom electrode layer 140 and / or the top electrode layer 142 may have a high work function to adjust the operating speed and / or leakage performance of the capacitor structure 138. In particular, the metal material of the bottom electrode layer 140 and / or the top electrode layer 142 may have a higher work function than titanium (Ti). In other words, the metal material of the bottom electrode layer 140 and / or the top electrode layer 142 may have a work function greater than about 4.33. Examples of such metallic materials include various transition metals in groups 6 to 12 of the periodic table, such as chromium (Cr), iron (Fe), cobalt (Co), copper (Cu), ruthenium (Ru), molybdenum (Mo), platinum (Pt), rhodium (Rh), tungsten (W), nickel (Ni), gold (Au), palladium (Pd), rhenium (Re), osmium (Os), iridium (Ir), and / or mercury (Hg), as well as other metallic materials with work functions ranging from about 4.5 electron volts (eV) to about 5.7 eV or higher.

[0061] The high work function of the metallic material in the bottom electrode layer 140 and / or the top electrode layer 142 provides a larger bandgap between the Fermi energy level and the vacuum energy level of the metallic material, thereby creating a higher barrier height between the top of the bandgap of the insulating layer 144 and the Fermi energy level of the metallic material in the bottom electrode layer 140 and / or the top electrode layer 142. This higher barrier height allows charge carriers to be more reliably retained in the capacitor structure, reducing leakage current through the insulating layer 144.

[0062] In some embodiments, the bottom electrode layer 140 and / or the top electrode layer 142 may comprise a metallic material having a low hydrogen diffusion coefficient and a high work function, such as ruthenium (Ru), tungsten (W), nickel (Ni), and / or palladium (Pd), among other examples. This enables the bottom electrode layer 140 and / or the top electrode layer 142 to block hydrogen absorption and improve the operating speed (e.g., charging and / or discharging speed) of the capacitor structure 138 without the need for additional photomask and etching processes.

[0063] In some embodiments, the bottom electrode layer 140 and the top electrode layer 142 may each comprise a metallic material with a work function greater than that of titanium. In some embodiments, the bottom electrode layer 140 comprises a metallic material with a work function greater than that of titanium, while the top electrode layer 142 comprises a different metallic material, such as titanium (Ti). In these embodiments, the work function of the metallic material of the bottom electrode layer 140 may be greater than that of the metallic material of the top electrode layer 142. In some embodiments, the top electrode layer 142 comprises a metallic material with a work function greater than that of titanium, while the bottom electrode layer 140 comprises a different metallic material, such as titanium (Ti). In these embodiments, the work function of the metallic material of the bottom electrode layer 140 may be less than that of the metallic material of the top electrode layer 142.

[0064] In some embodiments, the bottom electrode layer 140 and the top electrode layer 142 comprise the same metallic material having a high work function. For example, both the bottom electrode layer 140 and the top electrode layer 142 comprise ruthenium (Ru). In some embodiments, the bottom electrode layer 140 and the top electrode layer 142 comprise different metallic materials, each having a high work function. For example, the bottom electrode layer 140 may comprise palladium (Pd) while the top electrode layer 142 may comprise platinum (Pt).

[0065] As mentioned above, providing Figure 1A and 1B As an example. Other examples may be related to... Figure 1A and Figure 1B The descriptions are different.

[0066] Figures 2A-2C This is an illustration of an example embodiment 200 of the charging and discharging operation of the capacitor structure 138 described herein. In example embodiment 200, the bottom electrode layer 140 and the top electrode layer 142 of the capacitor structure 138 each comprise the same metallic material having a high work function (e.g., a work function greater than that of titanium).

[0067] Figure 2A The energy band diagram of capacitor structure 138 is shown when no electrical bias is applied. Figure 2A As shown, since the bottom electrode layer 140 and the top electrode layer 142 contain the same metallic material, the barrier height 202 of the bottom electrode layer 140 and the barrier height 204 of the top electrode layer 142 are likely to be approximately equal. The barrier height 202 is the difference between the Fermi level of the bottom electrode layer 140 and the top of the bandgap of the insulating layer 144. The barrier height 204 is the difference between the Fermi level of the top electrode layer 142 and the top of the bandgap of the insulating layer 144. Furthermore, the work function 206 of the bottom electrode layer 140 and the work function 208 of the top electrode layer 142 (which are respectively the differences between their respective Fermi levels and the vacuum level 210) are approximately equal.

[0068] Figure 2B The energy band diagram of capacitor structure 138 is shown when an electrical bias voltage is applied to it. Figure 2B As shown, the electrical bias applied to the capacitor structure 138 results in a potential 212 in the insulating layer 144, which in turn causes a shift in the vacuum level 210. In this configuration, the capacitor structure 138 can be charged, allowing charge carriers to be stored and retained in the bottom electrode layer 140 and the top electrode layer 142. In particular, the potential 212 causes opposite types of charge carriers (e.g., electrons and holes) to be stored and retained in the bottom electrode layer 140 and the top electrode layer 142.

[0069] Figure 2C The diagram shows the energy band structure of capacitor structure 138 when an electrical bias voltage is applied. This bias voltage may be relative to... Figure 2B The applied bias voltage has opposite polarity. For example... Figure 2C As shown, the electrical bias applied to capacitor structure 138 causes a potential 214 to appear in insulating layer 144, which in turn causes a shift in vacuum level 210. In this configuration, capacitor structure 138 can be discharged, causing opposite charge carriers stored in bottom electrode layer 140 and top electrode layer 142 to recombine, thereby releasing the stored energy in capacitor structure 138.

[0070] The high work function of the metallic materials in the bottom electrode layer 140 and the top electrode layer 142 enables... Figure 2BThe charging state shown enables low leakage, allowing charge carriers to remain in the bottom electrode layer 140 and top electrode layer 142 for longer periods between refreshes. This increases the energy efficiency and data retention reliability of the capacitor structure 138.

[0071] As mentioned above, providing Figures 2A-2C As an example. Other examples may be related to... Figures 2A-2C The descriptions are different.

[0072] Figures 3A-3C This is a diagram of an example embodiment 300 of the charging and discharging operation of the capacitor structure 138 described herein. In example embodiment 200, the bottom electrode layer 140 and the top electrode layer 142 of the capacitor structure 138 comprise different metallic materials with different work functions.

[0073] Figure 3A The energy band diagram of capacitor structure 138 is shown when no electrical bias is applied. Figure 3A As shown, because the bottom electrode layer 140 and the top electrode layer 142 contain different metallic materials, the barrier height 302 of the bottom electrode layer 140 and the barrier height 304 of the top electrode layer 142 are different. The barrier height 302 is the difference between the Fermi level of the bottom electrode layer 140 and the top of the bandgap of the insulating layer 144. The barrier height 304 is the difference between the Fermi level of the top electrode layer 142 and the top of the bandgap of the insulating layer 144. The work function 306 of the bottom electrode layer 140 and the work function 308 of the top electrode layer 142 (which are the differences between their respective Fermi levels and the vacuum level 310) are also different.

[0074] The bottom electrode layer 140 mainly comprises a metallic material having a work function 306 that is larger than the work function 308 of the top electrode layer 142. Therefore, the barrier height between the Fermi level of the bottom electrode layer 140 and the top of the insulating layer 144 may be greater than the barrier height between the Fermi level of the top electrode layer 142 and the top of the insulating layer 144.

[0075] Figure 3B The energy band diagram of capacitor structure 138 is shown when an electrical bias voltage is applied to it. Figure 3B As shown, the electrical bias applied to the capacitor structure 138 results in a potential 312 in the insulating layer 144, which in turn causes a shift in the vacuum level 310. In this configuration, the capacitor structure 138 can be charged, allowing charge carriers to be stored and retained in the bottom electrode layer 140 and the top electrode layer 142. In particular, the potential 312 causes opposite types of charge carriers (e.g., electrons and holes) to be stored and retained in the bottom electrode layer 140 and the top electrode layer 142.

[0076] Figure 3CThe diagram shows the energy band structure of capacitor structure 138 when an electrical bias voltage is applied. This bias voltage may be relative to... Figure 3B The applied bias voltage has opposite polarity. For example... Figure 3C As shown, the electrical bias applied to the capacitor structure 138 causes a potential 314 to appear in the insulating layer 144, which in turn causes a shift in the vacuum level 310. In this configuration, the capacitor structure 138 can be discharged, causing opposite charge carriers stored in the bottom electrode layer 140 and the top electrode layer 142 to recombine, thereby releasing the stored energy in the capacitor structure 138.

[0077] The high work function of the metallic material in the bottom electrode layer 140 enables... Figure 3B Low leakage can be achieved in the charging state shown, allowing charge carriers to remain in the bottom electrode layer 140 and top electrode layer 142 for a longer period between refreshes. This increases the energy efficiency and data retention reliability of the capacitor structure 138. Furthermore, the lower work function of the metallic material in the top electrode layer 142 enables the capacitor structure 138 to achieve... Figure 3C It discharges rapidly with a lower electrical bias voltage. This increases the operating speed of the capacitor structure 138.

[0078] As indicated above, Figures 3A-3C This is provided as an example. Other instances may be related to... Figures 3A-3C The descriptions are different.

[0079] Figures 4A-4K This is a diagram of an example embodiment 400 forming the semiconductor device 100 described herein. In some embodiments, with Figures 4A-4K One or more related semiconductor processing operations may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, wafer / die transport tools and / or other types of semiconductor processing tools.

[0080] like Figure 4A As shown, a substrate layer 106 is provided. The substrate layer 106 may be provided in the form of a semiconductor wafer, such as a silicon (Si) wafer, a silicon-on-insulator (SOI) wafer, and / or other types of semiconductor workpieces. The semiconductor device 100 may be formed on the semiconductor wafer together with other semiconductor devices.

[0081] like Figure 4AAs further shown, a layer stack can be formed on the substrate 106. This layer stack may be referred to as a superlattice. The layer stack may include multiple alternating layers arranged in a direction approximately perpendicular to the substrate 106 (e.g., the z-direction). For example, the layer stack may include alternating layers of a sacrificial layer 402 and a nanostructured channel layer 404 perpendicularly arranged on the substrate 106. Figure 4A The number of sacrificial layers 402 and nanostructured channel layers 404 shown are examples, and other numbers of sacrificial layers 402 and nanostructured channel layers 404 are also within the scope of this disclosure.

[0082] The sacrificial layer 402 enables the definition of the vertical distance between adjacent nanostructure channels formed by the nanostructure channel layer 404, and the sacrificial layer 402 serves as a placeholder for the subsequently formed gate structure of the integrated circuit device 110 of the semiconductor device 100, which is formed around the nanostructure channels.

[0083] The sacrificial layer 402 comprises a first material composition, and the nanostructured channel layer 404 comprises a second material composition. In some embodiments, the first and second material compositions are the same. In some embodiments, the first and second material compositions are different. For example, the sacrificial layer 402 may comprise silicon germanium (SiGe), while the nanostructured channel layer 404 may comprise silicon (Si). This allows the sacrificial layer 402 and / or the nanostructured channel layer 404 to be selectively etched (e.g., etch the sacrificial layer 402 but not the nanostructured channel layer 404, or etch the nanostructured channel layer 404 but not the sacrificial layer 402), depending on the type of etchant used.

[0084] One or more types of deposition tools can be used to deposit and / or grow alternating layers of stacked layers to incorporate nanostructures (e.g., nanosheets) on substrate layer 106. For example, the sacrificial layer 402 and / or the nanostructured channel layer 404 can be grown via epitaxial growth using deposition tools, which may include processes such as molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial techniques. Furthermore and / or alternatively, the sacrificial layer 402 and / or the nanostructured channel layer 404 can be deposited via chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or other suitable deposition techniques.

[0085] In the y direction (in) Figure 4A (Not visible in the view), the layer stack and substrate layer 106 can be etched to form a fin structure extending in the x-direction. The fin structure may include a portion of the layer stack and a portion of the substrate layer 106 beneath the layer stack. The fin structure can be formed by patterning one or more shielding layers and etching based on the pattern formed in the one or more shielding layers. The one or more shielding layers can be patterned using lithography techniques, including double patterning or multiple patterning techniques. Etching tools can be used to etch the layer stack and substrate layer 106 based on the pattern using dry etching techniques (e.g., reactive ion etching), wet etching techniques, and / or combinations thereof. In some embodiments, shallow trench isolation (STI) regions (not shown) may be formed between adjacent fin structures in the y-direction.

[0086] like Figure 4B As shown, a dummy gate structure 406 (also referred to as a dummy gate stack or temporary gate structure) may be formed above a portion of the stack of sacrificial layer 402 and nanostructure channel layer 404. The dummy gate structure 406 may extend in the y-direction and may be aligned in the x-direction such that the dummy gate structure 406 is approximately perpendicular to the fin structure. The dummy gate structure 406 is a sacrificial structure that will be replaced by a replacement gate structure or replacement gate stack in subsequent process stages of the integrated circuit device 110 of the semiconductor device 100. The dummy gate structure 406 may also be used to define source / drain (S / D) recesses in which the source / drain regions of the nanostructure transistor are formed in the stack of sacrificial layer 402 and nanostructure channel layer 404.

[0087] The dummy gate structure 406 may include polysilicon (PO) or other materials. The layers of the dummy gate structure 406 may be formed using various semiconductor process techniques, such as depositing the layers of the dummy gate structure 406, patterning the layers of the dummy gate structure 406 to define the dummy gate structure 406, and / or other semiconductor process techniques. Sidewall spacers 120a may be formed on the sidewalls of the dummy gate structure 406.

[0088] like Figure 4CAs shown, the source / drain region 112 of the integrated circuit device 110 is formed in a layer stack of sacrificial layer 402 and nanostructured channel layer 404. To form the source / drain region 112, a source / drain recess can be formed in an etching operation through the layer stack of sacrificial layer 402 and nanostructured channel layer 404. The source / drain recess can be formed in the x-direction on opposite sides of the dummy gate structure 406. The etching operation can be performed using an etching tool and can be referred to as a strained source / drain (SSD) etching operation. In some embodiments, the etching operation includes using plasma etching technology, wet chemical etching technology and / or other types of etching technology.

[0089] The formation of source / drain recesses may define channel layer 118. Channel layer 118 may include silicon-based nanostructures (e.g., nanosheets or nanowires, etc.) that serve as semiconductor channels for integrated circuit device 110 of semiconductor device 100. Channel layer 118 is aligned in one direction (e.g., the z-direction) that is approximately perpendicular to substrate layer 106. In other words, channel layer 118 is vertically aligned or stacked on substrate layer 106.

[0090] Before forming the source / drain region 112 in the source / drain recess, the ends of the sacrificial layer 402 exposed in the source / drain recess can be laterally etched during an etching operation to form a cavity in the ends of the sacrificial layer 402. An inner spacer 120b can be formed in the cavity. To form the inner spacer 120b, a dielectric material layer can be deposited in the cavity and along the sidewalls and bottom surface of the source / drain recess using a deposition tool. The dielectric material layer can be deposited using CVD, PVD, ALD, and / or other deposition techniques. An etching tool is used to subsequently remove excess material from the dielectric material layer in the source / drain recess, leaving the remaining portion corresponding to the inner spacer 120b in the cavity.

[0091] After forming the inner spacer 120b, the source / drain recess may be filled with one or more layers of epitaxial material to form a source / drain region 112 within the source / drain recess. For example, a deposition tool may be used to deposit a buffer zone at the bottom of the source / drain recess, and the deposition tool may deposit the source / drain region 112 on the buffer zone within the source / drain recess. In some embodiments, a capping layer is deposited on the source / drain region 112 within the source / drain recess using a deposition tool. As another example, the deposition tool may epitaxially grow a first layer (referred to as L1) of the source / drain region 112 on a relevant buffer zone (referred to as L0), and may epitaxially grow a second layer (referred to as L2, L2-1, and / or L2-2) of the source / drain region 112 on the first layer. The first layer may include lightly doped silicon (e.g., doped with boron (B), phosphorus (P), and / or other dopants) and may serve as a shielding layer to reduce short channel effects in the semiconductor device 100 and reduce extrusion or migration of dopants into the channel layer 118. The second layer may include highly doped silicon or highly doped silicon-germanium. The second layer may be used to provide compressive stress in the source / drain regions 112 to reduce boron loss.

[0092] like Figure 4C Further, a dielectric layer 108 may be formed over the source / drain region 112 and around the dummy gate structure 406. The dielectric layer 108 may fill the region between the dummy gate structures 406. In some embodiments, prior to the formation of the dielectric layer 108, a contact etch stop layer (CESL) is conformally deposited (e.g., using a deposition tool) over the source / drain region 112. The dielectric layer 108 is then formed on the CESL. The CESL may provide a mechanism to stop the etching process when the source / drain contact structure 122 of the source / drain region 112 is formed. The CESL may be formed of a dielectric material having a different etch selectivity than adjacent layers or components. The CESL may contain or may be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Furthermore, the CESL may contain or may be silicon nitride (Si). x N y Other examples include silicon carbonitride (SiCN), carbon nitride (CN), silicon oxynitride (SiON), silicon oxycarbonate (SiCO), or combinations thereof. CESL can be deposited using deposition processes such as ALD, CVD, or other deposition techniques.

[0093] like Figure 4DAs shown, a gate replacement process can be performed to replace the dummy gate structure 406 with the gate structure 116 of the integrated circuit device 110. A dummy gate removal operation can be performed to remove the dummy gate structure 406 from the semiconductor device 100. Removing the dummy gate structure 406 leaves an opening (or recess) in the dielectric layer 108 and provides contact to the underlying sacrificial layer 402. The dummy gate structure 406 can be removed by one or more etching operations. These etching operations may include plasma etching, wet chemical etching, and / or other types of etching techniques.

[0094] The gate replacement process may include a nanostructure release operation (e.g., a SiGe release operation). The nanostructure release operation is performed to remove the sacrificial layer 402 (e.g., a silicon-germanium layer). This results in the formation of openings between the channel layers 118 (e.g., regions surrounding the channel layers 118). The sacrificial layer 402 can be removed through the space previously occupied by the dummy gate structure 406. The nanostructure release operation may include performing an etching operation using an etching tool to remove the sacrificial layer 402 based on the etch selectivity differences between the materials of the sacrificial layer 402 and the channel layers 118, and between the materials of the sacrificial layer 402 and the inner spacer 120b. The inner spacer 120b may act as an etch stop layer during the etching operation, protecting the source / drain regions 112 from etching.

[0095] The gate replacement operation includes forming a gate dielectric layer 114 and a gate structure (e.g., a replacement gate structure) 116 of the integrated circuit device 110 in the openings between the source / drain regions 112 and between the inner spacers 120b. Specifically, the gate dielectric layer 114 and the gate structure 116 fill the regions between and around the channel layers 118 previously occupied by the sacrificial layer 402, such that the gate structure 116 completely encloses and surrounds the channel layers 118. This increases control over the channel layers 118, increases the drive current of the integrated circuit device 110, and / or reduces other instances such as the short channel effect (SCE) of the integrated circuit device 110. The gate structure 116 may also fill spaces previously occupied by the dummy gate structure 406. Portions of the gate structure 116 are formed in an alternating vertical arrangement between pairs of channel layers 118. In other words, the semiconductor device 100 includes a vertical stack of one or more alternating portions of the channel layers 118 and the gate structure 116.

[0096] like Figure 4DAs further shown, the source / drain contact structure 122 of the integrated circuit device 110 may be formed through the dielectric layer 108. The source / drain contact structure 122 may be formed in a recess in the dielectric layer 108. In some embodiments, a pattern in the photoresist layer is used to etch the dielectric layer 108 to form the recess. In these embodiments, a photoresist layer may be formed on the dielectric layer 108 using a deposition tool. An exposure tool may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool may be used to etch the dielectric layer based on the pattern to form the recess. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, a photoresist removal tool may be used to remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique to pattern-based etching of the dielectric layer 108 to form a recess.

[0097] Source / drain contact structure 122 may be formed in a recess, such that source / drain contact structure 122 rests on source / drain region 112. Material of source / drain contact structure 122 may be deposited in the recess using deposition tools via CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. Material of source / drain contact structure 122 may be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and then material of source / drain contact structure 122 is deposited on the seed layer. In some embodiments, one or more substrates 124 are deposited in the recess, and source / drain contact structure 122 is deposited on substrates 124. In some embodiments, a planarization operation (e.g., chemical mechanical planarization (CMP) operation) is performed using a planarization tool to planarize source / drain contact structure 122 after deposition, such that the top of source / drain contact structure 122 is substantially coplanar with the top of dielectric layer 108.

[0098] like Figure 4E As shown, a first portion of the interconnect layer 104 of the semiconductor device 100 is formed on the device layer 102. Alternating layers of ILD layers 126 and ESL 128 are deposited in the interconnect layer 104 of the semiconductor device 100 using one or more deposition tools. In this way, the ILD layers 126 and ESL 128 can be aligned along the z-direction in the semiconductor device 100. Each ILD layer 126 and each ESL 128 can be deposited using one or more deposition tools via PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. In some embodiments, a planarization tool can be used to planarize the ILD layers 126 and / or ESL 128 after deposition.

[0099] like Figure 4E As further shown, a multilayer conductive structure can be formed in the dielectric layer of interconnect layer 104. For example, various operations can be performed using deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor processing tools to form source / drain interconnect structures 134 and / or gate interconnect structures 136 at the bottom of interconnect layer 104. One or more source / drain interconnect structures 134 can be formed on one or more source / drain contact structures 122 of one or more integrated circuit devices 110. One or more gate interconnect structures 136 can be formed on one or more gate structures 116 of one or more integrated circuit devices 110.

[0100] Various operations can be performed using deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor processing tools to form a metallization structure 130 and an interconnect structure 132 in the interconnect layer 104 of the semiconductor device 100. In some embodiments, the interconnect layer 104 may be formed in a multilayer configuration. For example, ILD layers 126 and ESL 128 may be formed (e.g., using one or more deposition tools and / or one or more planarization tools), recesses may be formed in and / or through ILD layers 126 and ESL 128 (e.g., using exposure tools, developing tools, and / or etching tools), and a metallization structure 130 (e.g., an M0 layer) may be formed in ILD layers 126 and ESL 128 (e.g., using one or more deposition tools and / or one or more planarization tools). Another ILD layer 126 and another ESL 128 may be formed, and an interconnect structure 132 (e.g., a V1 layer) may be formed in ILD layers 126 and ESL 128. Additional layers of the metallization structure 130 and the interconnection structure 132 can be formed in a similar manner.

[0101] The source / drain interconnect structure 134, gate interconnect structure 136, metallization structure 130, and / or interconnect structure 132 can be deposited using one or more deposition tools via PVD, ALD, CVD, electroplating (e.g., electrochemical electroplating) and / or other suitable deposition techniques. In some embodiments, a planarization tool can be used to planarize the source / drain interconnect structure 134, gate interconnect structure 136, metallization structure 130, and / or interconnect structure 132 after deposition.

[0102] like Figure 4FAs shown, one or more recesses 408 may be formed within and / or through one or more dielectric layers (e.g., one or more ILD layers 126 and / or one or more ESL 128) in interconnect layer 104. The recesses 408 may be formed over conductive structures in interconnect layer 104, such as over metallization structure 130. In some embodiments, the top of metallization structure 130 may be exposed at the bottom of the recess 408.

[0103] In some embodiments, the pattern in the photoresist layer is used to etch one or more dielectric layers to form a recess 408. In these embodiments, a photoresist layer can be formed on the topmost dielectric layer using a deposition tool (e.g., using spin coating and / or other suitable deposition techniques). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch one or more dielectric layers based on the pattern to form the recess 408. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique for forming the pattern-based recess 408.

[0104] like Figure 4G As shown, the bottom electrode layer 140 of the capacitor structure 138 can be conformally deposited on the sidewalls and bottom surface of the recess 408. In some embodiments, the bottom electrode layer 140 is deposited on the top surface of the metallized structure 130 at the bottom of the recess 408. The bottom electrode layer 140 can be deposited using deposition tools and other examples of conformal deposition techniques such as CVD and / or ALD. In some embodiments, the bottom electrode layer 140 is formed of a metallic material having a high work function and / or a low hydrogen diffusion coefficient. In some embodiments, the bottom electrode layer 140 is formed of another type of metallic material.

[0105] In some embodiments, a plurality of recesses 408 are formed for a capacitor structure 138, and a bottom electrode layer 140 is conformally deposited in each recess 408. A conformal metal layer can be deposited continuously across the interior and between the plurality of recesses 408 using a deposition tool, and a planarization tool can then be used to planarize the metal layer to form a discontinuous bottom electrode layer 140 in the recesses 408. In this way, each bottom electrode layer 140 is electrically coupled to its own metallization structure 130 at the bottom of the recess 408.

[0106] like Figure 4HAs shown, the insulating layer 144 of the capacitor structure 138 can be conformally deposited on the sidewalls and bottom surface of the recess 408, such that the insulating layer 144 is deposited on top of the bottom electrode layer 140. The insulating layer 144 can be deposited using deposition tools and other examples of conformal deposition techniques such as CVD and / or ALD.

[0107] In some embodiments, a plurality of recesses 408 are formed for a capacitor structure 138, and an insulating layer 144 is conformally deposited in each recess 408. The insulating layer 144 can be deposited as a conformal dielectric layer continuously spanning the interior and between the plurality of recesses 408 using a deposition tool.

[0108] like Figure 4I As shown, the top electrode layer 142 of the capacitor structure 138 can be conformally deposited on the sidewalls and bottom surface of the recess 408, such that the top electrode layer 142 is deposited on the insulating layer 144. The top electrode layer 142 can be deposited using deposition tools and other examples of conformal deposition techniques such as CVD and / or ALD. In some embodiments, the top electrode layer 142 is formed of a metallic material having a high work function and / or a low hydrogen diffusion coefficient. In some embodiments, the top electrode layer 142 is formed of another type of metallic material.

[0109] In some embodiments, a plurality of recesses 408 are formed for a capacitor structure 138, and a top electrode layer 142 is conformally deposited in each recess 408. The top electrode layer 142 can be deposited as a conformal metal layer continuously spanning the interior and between the plurality of recesses 408 using a deposition tool.

[0110] like Figure 4J As shown, the remaining area in the recess 408 can be filled by depositing dielectric filler 146 in the recess 408. Dielectric filler 146 can be deposited using PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. Dielectric filler 146 can be deposited as a single layer and then planarized using a planarization tool to remove excess material from the layer to define dielectric filler 146.

[0111] like Figure 4K As shown, additional dielectric layers of interconnect layer 104 may be formed above and / or on capacitor structure 138. For example, additional alternating layers of ILD layer 126 and ESL 128 may be deposited in interconnect layer 104 of semiconductor device 100 using one or more deposition tools via PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. In some embodiments, planarization tools may be used to planarize the additional ILD layer 126 and / or the additional ESL 128.

[0112] like Figure 4KAs further shown, additional conductive structures may be formed in an additional dielectric layer above the capacitor structure 138 in the interconnect layer 104. In some embodiments, the interconnect structure 132 may be formed above the capacitor structure 138 such that the interconnect structure 132 rests on the top electrode layer 142 of the capacitor structure 138 and forms an electrical and / or physical connection with the top electrode layer 142 of the capacitor structure 138. A metallization structure 130 may be formed above the interconnect structure 132.

[0113] As mentioned above, providing Figures 4A-4K As an example. Other instances may be similar. Figures 4A-4K The descriptions are different.

[0114] Figures 5A-5F This is an example embodiment of the electrode layer combination of the capacitor structure 138 described in this paper. Figures 5A-5F The electrode layer assembly shown includes various components of a single-layer thin film and / or multiple-layer thin films of the bottom electrode layer 140 and / or the top electrode layer 142 of the capacitor structure 138. The electrode layer assembly of the capacitor structure 138 can be coupled with... Figures 4A-4K Similar processes are formed as described in the relevant instructions and descriptions.

[0115] Figure 5A An example embodiment 500 of the electrode layer combination is shown, wherein the bottom electrode layer 140 of the capacitor structure 138 comprises a multilayer thin film, while the top electrode layer 142 of the capacitor structure 138 comprises a single-layer thin film. The multilayer thin film allows the different layers of the bottom electrode layer 140 to emphasize different properties, such as hydrogen blocking and work function adjustment.

[0116] For example, the bottom electrode layer 140 may include a metal layer 140a and a metal layer 140b located on top of the metal layer 140a. The metal layer 140a may contain a metal material with a low hydrogen diffusion coefficient, while the metal layer 140b may contain a different metal material with a high work function. The metal with a low hydrogen diffusion coefficient can serve as the outer layer of the multilayer film to block hydrogen diffusion, which allows the metal layer 140b to be formed from a high work function metal such as copper (Cu).

[0117] In some embodiments, the bottom electrode layer 140 may have a clearly visible interface between the metal layers 140a and 140b. In some embodiments, at least partial mixing of the metal layers 140a and 140b may occur in the bottom electrode layer 140.

[0118] In some embodiments, the top electrode layer 142 includes titanium (Ti), titanium nitride (TiN), a metallic material with a low hydrogen diffusion coefficient, and / or a metallic material with a high work function, among other examples. In some embodiments, the metal layer 140a of the top electrode layer 142 and the bottom electrode layer 140 contains the same metallic material. In some embodiments, the metal layer 140a of the top electrode layer 142 and the bottom electrode layer 140 contains different metallic materials. In some embodiments, the metal layer 140b of the top electrode layer 142 and the bottom electrode layer 140 contains the same metallic material. In some embodiments, the metal layer 140b of the top electrode layer 142 and the bottom electrode layer 140 contains different metallic materials.

[0119] Figure 5B An example embodiment 504 of the electrode layer combination is shown, wherein the top electrode layer 142 of the capacitor structure 138 comprises a multilayer thin film, while the bottom electrode layer 140 of the capacitor structure 138 comprises a single-layer thin film. The multilayer thin film allows the different layers of the top electrode layer 142 to emphasize different properties, such as hydrogen blocking and work function adjustment.

[0120] For example, the top electrode layer 142 may include a metal layer 142a and a metal layer 142b located on top of the metal layer 142a. The metal layer 142a may contain a metal material with a high work function, while the metal layer 142b may contain a different metal material with a low hydrogen diffusion coefficient. The metal with the low hydrogen diffusion coefficient can serve as the outer layer of the multilayer film to block hydrogen diffusion, which allows the metal layer 142a to be formed from a high work function metal such as copper (Cu).

[0121] In some embodiments, the top electrode layer 142 may have a clearly visible interface between the metal layers 142a and 142b. In some embodiments, at least partial mixing of the metal layers 142a and 142b may occur in the top electrode layer 142.

[0122] In some embodiments, the bottom electrode layer 140 includes other examples such as titanium (Ti), titanium nitride (TiN), a metallic material with a low hydrogen diffusion coefficient, and / or a metallic material with a high work function. In some embodiments, the metal layer 142a of the bottom electrode layer 140 and the top electrode layer 142 contains the same metallic material. In some embodiments, the metal layer 142a of the bottom electrode layer 140 and the top electrode layer 142 contains different metallic materials. In some embodiments, the metal layer 142b of the bottom electrode layer 140 and the top electrode layer 142 contains the same metallic material. In some embodiments, the metal layer 142b of the bottom electrode layer 140 and the top electrode layer 142 contains different metallic materials.

[0123] Figure 5CAn example embodiment 506 of the electrode layer combination is shown, wherein the bottom electrode layer 140 of the capacitor structure 138 comprises a multilayer thin film, and the top electrode layer 142 of the capacitor structure 138 also comprises a multilayer thin film. The multilayer thin film allows the different layers of the bottom electrode layer 140 and the top electrode layer 142 to emphasize different properties, such as hydrogen blocking and work function adjustment.

[0124] For example, the bottom electrode layer 140 may include a metal layer 140a and a metal layer 140b located on top of the metal layer 140a. The metal layer 140a may contain a metal material with a low hydrogen diffusion coefficient, while the metal layer 140b may contain a different metal material with a high work function. The metal with a low hydrogen diffusion coefficient can serve as the outer layer of the multilayer film to block hydrogen diffusion, which allows the metal layer 140b to be formed from a high work function metal such as copper (Cu).

[0125] The top electrode layer 142 may include a metal layer 142a and a metal layer 142b located on top of the metal layer 142a. The metal layer 142a may contain a metal material with a high work function, while the metal layer 142b may contain a different metal material with a low hydrogen diffusion coefficient. The metal with the low hydrogen diffusion coefficient can serve as the outer layer of the multilayer film to block hydrogen diffusion, which allows the metal layer 142a to be formed from a high work function metal such as copper (Cu).

[0126] In some embodiments, the metal layer 140a of the bottom electrode layer 140 and the metal layer 142a of the top electrode layer 142 comprise the same metal material. In some embodiments, the metal layer 140a of the bottom electrode layer 140 and the metal layer 142a of the top electrode layer 142 comprise different metal materials. In some embodiments, the metal layer 140b of the bottom electrode layer 140 and the metal layer 142b of the top electrode layer 142 comprise the same metal material. In some embodiments, the metal layer 140b of the bottom electrode layer 140 and the metal layer 142b of the top electrode layer 142 comprise different metal materials.

[0127] In some embodiments, the metal layer 140a of the bottom electrode layer 140 and the metal layer 142b of the top electrode layer 142 comprise the same metal material. In some embodiments, the metal layer 140a of the bottom electrode layer 140 and the metal layer 142b of the top electrode layer 142 comprise different metal materials. In some embodiments, the metal layer 140b of the bottom electrode layer 140 and the metal layer 142a of the top electrode layer 142 comprise the same metal material. In some embodiments, the metal layer 140b of the bottom electrode layer 140 and the metal layer 142a of the top electrode layer 142 comprise different metal materials.

[0128] Figure 5DAn example embodiment 508 of the electrode layer combination is shown, wherein the bottom electrode layer 140 of the capacitor structure 138 comprises a multilayer thin film, and the top electrode layer 142 of the capacitor structure 138 also comprises a multilayer thin film. The multilayer thin film allows the different layers of the bottom electrode layer 140 and the top electrode layer 142 to emphasize different properties, such as hydrogen blocking and work function adjustment.

[0129] For example, the bottom electrode layer 140 may include a metal layer 140a, a metal layer 140b on top of the metal layer 140a, and a metal layer 140c on top of the metal layer 140b. Metal layer 140a may contain a metal material with a low hydrogen diffusion coefficient, metal layer 140b may contain different metal materials such as titanium (Ti) and / or titanium nitride (TiN), and metal layer 140c may contain different metal materials with a high work function. The metal with a low hydrogen diffusion coefficient can serve as the outer layer of the multilayer film to block hydrogen diffusion, which allows metal layer 140c to be formed from a high work function metal such as copper (Cu). The high work function metal closest to the insulating layer 144 can have a greater influence on the barrier height between the bottom electrode layer 140 and the insulating layer 144 to prevent leakage.

[0130] In some embodiments, the bottom electrode layer 140 may have a clearly visible interface between the metal layers 140a, 140b, and 140c. In some embodiments, the metal layers 140a, 140b, and 140c in the bottom electrode layer 140 may be at least partially mixed.

[0131] The top electrode layer 142 may include a metal layer 142a and a metal layer 142b located on top of the metal layer 142a. The metal layer 142a may contain a metal material with a high work function, while the metal layer 142b may contain a different metal material with a low hydrogen diffusion coefficient. The metal with the low hydrogen diffusion coefficient can serve as the outer layer of the multilayer film to block hydrogen diffusion, which allows the metal layer 142a to be formed from a high work function metal such as copper (Cu).

[0132] In some embodiments, the metal layer 140a of the bottom electrode layer 140 and the metal layer 142a of the top electrode layer 142 comprise the same metal material. In some embodiments, the metal layer 140a of the bottom electrode layer 140 and the metal layer 142a of the top electrode layer 142 comprise different metal materials. In some embodiments, the metal layer 140b of the bottom electrode layer 140 and the metal layer 142b of the top electrode layer 142 comprise the same metal material. In some embodiments, the metal layer 140b of the bottom electrode layer 140 and the metal layer 142b of the top electrode layer 142 comprise different metal materials.

[0133] In some embodiments, the metal layer 140a of the bottom electrode layer 140 and the metal layer 142b of the top electrode layer 142 comprise the same metal material. In some embodiments, the metal layer 140a of the bottom electrode layer 140 and the metal layer 142b of the top electrode layer 142 comprise different metal materials. In some embodiments, the metal layer 140b of the bottom electrode layer 140 and the metal layer 142a of the top electrode layer 142 comprise the same metal material. In some embodiments, the metal layer 140b of the bottom electrode layer 140 and the metal layer 142a of the top electrode layer 142 comprise different metal materials.

[0134] In some embodiments, the metal layer 140c of the bottom electrode layer 140 and the metal layer 142a of the top electrode layer 142 comprise the same metal material. In some embodiments, the metal layer 140c of the bottom electrode layer 140 and the metal layer 142a of the top electrode layer 142 comprise different metal materials. In some embodiments, the metal layer 140c of the bottom electrode layer 140 and the metal layer 142b of the top electrode layer 142 comprise the same metal material. In some embodiments, the metal layer 140c of the bottom electrode layer 140 and the metal layer 142b of the top electrode layer 142 comprise different metal materials.

[0135] Figure 5E An embodiment 510 of the electrode layer combination is shown, wherein the bottom electrode layer 140 of the capacitor structure 138 comprises a multilayer thin film, and the top electrode layer 142 of the capacitor structure 138 also comprises a multilayer thin film. The multilayer thin film allows the different layers of the bottom electrode layer 140 and the top electrode layer 142 to emphasize different properties, such as hydrogen blocking and work function adjustment.

[0136] For example, the bottom electrode layer 140 may include a metal layer 140a and a metal layer 140b on top of the metal layer 140a. The metal layer 140a may contain a metal material with a low hydrogen diffusion coefficient, while the metal layer 140b may contain a different metal material with a high work function. The metal with a low hydrogen diffusion coefficient can serve as the outer layer of the multilayer film to block hydrogen diffusion, allowing the metal layer 140b to be formed of a high work function metal such as copper (Cu). The high work function metal closest to the insulating layer 144 can have a greater impact on the barrier height between the bottom electrode layer 140 and the insulating layer 144 to prevent leakage.

[0137] The top electrode layer 142 may include a metal layer 142a, a metal layer 142b on top of the metal layer 142a, and a metal layer 142c on top of the metal layer 142b. Metal layer 142a may contain different metallic materials with high work functions, metal layer 142b may contain different metallic materials such as titanium (Ti) and / or titanium nitride (TiN), and metal layer 142c may contain a metallic material with a low hydrogen diffusion coefficient. The low hydrogen diffusion coefficient metal can serve as the outer layer of the multilayer film to block hydrogen diffusion, which allows metal layer 142a to be formed from a high work function metal such as copper (Cu). The high work function metal closest to the insulating layer 144 can have a greater influence on the barrier height between the top electrode layer 142 and the insulating layer 144 to prevent leakage.

[0138] In some embodiments, the bottom electrode layer 140 may have a clearly visible interface between the metal layers 140a and 140b. In some embodiments, at least partial mixing of the metal layers 140a and 140b may occur in the bottom electrode layer 140.

[0139] In some embodiments, the top electrode layer 142 may have a clearly visible interface between the metal layers 142a, 142b, and 142c. In some embodiments, at least partial mixing of the metal layers 142a, 142b, and 142c may occur in the top electrode layer 142.

[0140] In some embodiments, the metal layer 140a of the bottom electrode layer 140 and the metal layer 142a of the top electrode layer 142 comprise the same metal material. In some embodiments, the metal layer 140a of the bottom electrode layer 140 and the metal layer 142a of the top electrode layer 142 comprise different metal materials. In some embodiments, the metal layer 140b of the bottom electrode layer 140 and the metal layer 142b of the top electrode layer 142 comprise the same metal material. In some embodiments, the metal layer 140b of the bottom electrode layer 140 and the metal layer 142b of the top electrode layer 142 comprise different metal materials.

[0141] In some embodiments, the metal layer 140a of the bottom electrode layer 140 and the metal layer 142b of the top electrode layer 142 comprise the same metal material. In some embodiments, the metal layer 140a of the bottom electrode layer 140 and the metal layer 142b of the top electrode layer 142 comprise different metal materials. In some embodiments, the metal layer 140b of the bottom electrode layer 140 and the metal layer 142a of the top electrode layer 142 comprise the same metal material. In some embodiments, the metal layer 140b of the bottom electrode layer 140 and the metal layer 142a of the top electrode layer 142 comprise different metal materials.

[0142] In some embodiments, the metal layer 142c of the top electrode layer 142 and the metal layer 140a of the bottom electrode layer 140 comprise the same metal material. In some embodiments, the metal layer 142c of the top electrode layer 142 and the metal layer 140a of the bottom electrode layer 140 comprise different metal materials. In some embodiments, the metal layer 142c of the top electrode layer 142 and the metal layer 140b of the bottom electrode layer 140 comprise the same metal material. In some embodiments, the metal layer 142c of the top electrode layer 142 and the metal layer 140b of the bottom electrode layer 140 comprise different metal materials.

[0143] Figure 5F An embodiment 512 of the electrode layer combination is shown, wherein the bottom electrode layer 140 of the capacitor structure 138 comprises a multilayer thin film, and the top electrode layer 142 of the capacitor structure 138 also comprises a multilayer thin film. The multilayer thin film allows the different layers of the bottom electrode layer 140 and the top electrode layer 142 to emphasize different properties, such as hydrogen blocking and work function adjustment.

[0144] For example, the bottom electrode layer 140 may include a metal layer 140a, a metal layer 140b on top of the metal layer 140a, and a metal layer 140c on top of the metal layer 140b. Metal layer 140a may contain a metal material with a low hydrogen diffusion coefficient, metal layer 140b may contain different metal materials such as titanium (Ti) and / or titanium nitride (TiN), and metal layer 140c may contain different metal materials with a high work function. The metal with a low hydrogen diffusion coefficient can serve as the outer layer of the multilayer film to block hydrogen diffusion, which allows metal layer 140c to be formed from a high work function metal such as copper (Cu). The high work function metal closest to the insulating layer 144 can have a greater impact on the barrier height between the bottom electrode layer 140 and the insulating layer 144 to prevent leakage.

[0145] The top electrode layer 142 may include a metal layer 142a, a metal layer 142b on top of the metal layer 142a, and a metal layer 142c on top of the metal layer 142b. Metal layer 142a may contain different metallic materials with high work functions, metal layer 142b may contain different metallic materials such as titanium (Ti) and / or titanium nitride (TiN), and metal layer 142c may contain a metallic material with a low hydrogen diffusion coefficient. The low hydrogen diffusion coefficient metal can serve as the outer layer of the multilayer film to block hydrogen diffusion, which allows metal layer 142a to be formed from a high work function metal such as copper (Cu). The high work function metal closest to the insulating layer 144 can have a greater impact on the barrier height between the top electrode layer 142 and the insulating layer 144 to prevent leakage.

[0146] In some embodiments, the metal layer 140a of the bottom electrode layer 140 and the metal layer 142a of the top electrode layer 142 comprise the same metal material. In some embodiments, the metal layer 140a of the bottom electrode layer 140 and the metal layer 142a of the top electrode layer 142 comprise different metal materials. In some embodiments, the metal layer 140b of the bottom electrode layer 140 and the metal layer 142b of the top electrode layer 142 comprise the same metal material. In some embodiments, the metal layer 140b of the bottom electrode layer 140 and the metal layer 142b of the top electrode layer 142 comprise different metal materials. In some embodiments, the metal layer 140c of the bottom electrode layer 140 and the metal layer 142c of the top electrode layer 142 comprise the same metal material. In some embodiments, the metal layer 140c of the bottom electrode layer 140 and the metal layer 142c of the top electrode layer 142 comprise different metal materials.

[0147] In some embodiments, the metal layer 140a of the bottom electrode layer 140 and the metal layer 142b of the top electrode layer 142 comprise the same metal material. In some embodiments, the metal layer 140a of the bottom electrode layer 140 and the metal layer 142b of the top electrode layer 142 comprise different metal materials. In some embodiments, the metal layer 140b of the bottom electrode layer 140 and the metal layer 142a of the top electrode layer 142 comprise the same metal material. In some embodiments, the metal layer 140b of the bottom electrode layer 140 and the metal layer 142a of the top electrode layer 142 comprise different metal materials.

[0148] In some embodiments, the metal layer 140c of the bottom electrode layer 140 and the metal layer 142a of the top electrode layer 142 comprise the same metal material. In some embodiments, the metal layer 140c of the bottom electrode layer 140 and the metal layer 142a of the top electrode layer 142 comprise different metal materials. In some embodiments, the metal layer 140c of the bottom electrode layer 140 and the metal layer 142b of the top electrode layer 142 comprise the same metal material. In some embodiments, the metal layer 140c of the bottom electrode layer 140 and the metal layer 142b of the top electrode layer 142 comprise different metal materials.

[0149] In some embodiments, the metal layer 142c of the top electrode layer 142 and the metal layer 140a of the bottom electrode layer 140 comprise the same metal material. In some embodiments, the metal layer 142c of the top electrode layer 142 and the metal layer 140a of the bottom electrode layer 140 comprise different metal materials. In some embodiments, the metal layer 142c of the top electrode layer 142 and the metal layer 140b of the bottom electrode layer 140 comprise the same metal material. In some embodiments, the metal layer 142c of the top electrode layer 142 and the metal layer 140b of the bottom electrode layer 140 comprise different metal materials.

[0150] As mentioned above, Figures 5A-5F Provided as an example. Other examples may be related to... Figures 5A-5F The descriptions are different.

[0151] Figures 6A-6E This is a diagram of an example embodiment of the structural arrangement of capacitor structure 138 described herein. The example structural arrangement of capacitor structure 138 may be implemented in interconnect layer 104 and / or other locations of semiconductor device 100. For the example structural arrangement, capacitor structure 138 may include one or more electrode layer arrangements described herein and can be connected to… Figures 4A-4K Similar processes are formed as described in the relevant instructions and descriptions.

[0152] Figure 6A Example embodiment 600 is shown, in which capacitor structure 138 includes a via structure arrangement. In the via structure arrangement, bottom electrode layer 140, top electrode layer 142, and insulating layer 144 may extend into the via, which passes through one or more dielectric layers in interconnect layer 104. Top electrode layer 142 may extend outward from the top of the via.

[0153] Figure 6B Example embodiment 602 is shown, in which capacitor structure 138 includes a trench structure arrangement. In the trench structure arrangement, a bottom electrode layer 140, a top electrode layer 142, and an insulating layer 144 may extend into a trench that passes through one or more dielectric layers in interconnect layer 104. The trench may extend in one or more lateral directions, unlike a via structure arrangement that extends primarily vertically. The top electrode layer 142 may extend outward from the top of the trench.

[0154] Figure 6C Example embodiment 604 is shown, in which capacitor structure 138 includes a columnar structure arrangement. In the columnar structure arrangement, bottom electrode layer 140, top electrode layer 142, and insulating layer 144 may form columns extending from the dielectric layer of interconnect layer 104. The columnar structure arrangement may be similar to a via structure arrangement, except that the bottom electrode layer 140 may extend outward from the bottom of the column.

[0155] Figure 6D Example embodiment 606 is shown, in which capacitor structure 138 comprises a cylindrical arrangement. In the cylindrical arrangement, bottom electrode layer 140, top electrode layer 142, and insulating layer 144 may form cylinders extending from the dielectric layer of interconnect layer 104. The cylindrical arrangement may be similar to a columnar arrangement, except that it may include dielectric filler 146 such that top electrode layer 142 extends along the inner and outer walls of bottom electrode layer 140 in the cylindrical arrangement, as shown. Figure 6D The cross-sectional view along line AA is shown.

[0156] Figure 6E Example embodiment 608 is shown, in which capacitor structure 138 comprises a planar structure arrangement. In the planar structure arrangement, bottom electrode layer 140, top electrode layer 142, and insulating layer 144 may form a thin film stack that extends horizontally primarily in interconnect layer 104.

[0157] As mentioned above, Figures 6A-6E This is provided as an example. Other examples may be related to... Figures 6A-6E The descriptions are different.

[0158] Figure 7 This is a flowchart of an example process 700 associated with the semiconductor device forming this document. In some embodiments, Figure 7 One or more process blocks are performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools and / or other types of semiconductor processing tools.

[0159] like Figure 7 As shown, process 700 may include forming a plurality of transistors in a device layer of a semiconductor device (block 710). For example, one or more semiconductor processing tools may be used to form a plurality of transistors (e.g., integrated circuit device 110) in a device layer (e.g., device layer 102) of a semiconductor device (e.g., semiconductor device 100), as described herein.

[0160] like Figure 7 As further shown, process 700 may include forming a plurality of dielectric layers over a plurality of transistors and a plurality of conductive structure layers within the plurality of dielectric layers (block 720). For example, one or more semiconductor processing tools may be used to form a plurality of dielectric layers (e.g., ILD layer 126, ESL 128) over a plurality of transistors and a plurality of conductive structure layers (e.g., metallization structure 130, interconnect structure 132) within the plurality of dielectric layers, as described herein.

[0161] like Figure 7 As further shown, process 700 may include forming a recess (block 730) through at least a portion of the plurality of dielectric layers. For example, one or more semiconductor processing tools may be used to form a recess (e.g., recess 408) through at least a portion of the plurality of dielectric layers, as described herein.

[0162] like Figure 7As further shown, process 700 may include depositing a bottom electrode layer of a capacitor structure in a recess, such that a portion of the bottom electrode layer is deposited over the conductive structures of a plurality of conductive structure layers (block 740). For example, one or more semiconductor processing tools may be used to deposit a bottom electrode layer (e.g., bottom electrode layer 140) of a capacitor structure (e.g., capacitor structure 138) in a recess, such that a portion of the bottom electrode layer is deposited over the conductive structures of a plurality of conductive structure layers, as described herein. In some embodiments, the hydrogen (H) diffusion coefficient of the first metal material of the bottom electrode layer is less than the hydrogen diffusion coefficient of the second metal material of the conductive structure.

[0163] like Figure 7 As further shown, process 700 may include depositing an insulating layer (block 750) of a capacitor structure over the bottom electrode layer in the recess. For example, one or more semiconductor processing tools may be used to deposit an insulating layer (e.g., insulating layer 144) of a capacitor structure over the bottom electrode layer in the recess, as described herein.

[0164] like Figure 7 As further shown, process 700 may include depositing a top electrode layer (block 760) of a capacitor structure over an insulating layer in the recess. For example, one or more semiconductor processing tools may be used to deposit a top electrode layer (e.g., top electrode layer 142) of a capacitor structure over an insulating layer in the recess, as described herein.

[0165] Process 700 may include additional embodiments, such as any single embodiment or any combination of embodiments of one or more other processes described below and / or in conjunction with one or more other processes described elsewhere herein.

[0166] In the first embodiment, the work function of the first metal material of the bottom electrode layer is greater than the work function of the second metal material of the conductive structure.

[0167] In the second embodiment, alone or in combination with the first embodiment, the second metal material of the conductive structure includes copper (Cu), and the first metal material of the bottom electrode layer includes at least one of ruthenium (Ru), nickel (Ni), platinum (Pt), or palladium (Pd).

[0168] In a third embodiment, either alone or in combination with one or more of the first and second embodiments, depositing a top electrode layer includes depositing a first metal layer (e.g., metal layer 142a) of a multilayer thin film over an insulating layer and a second metal layer (e.g., metal layer 142b) of a multilayer thin film over the first metal layer, wherein the first metal layer contains a third metal material, wherein the second metal layer contains a fourth metal material, and wherein the third metal material and the fourth metal material are different metal materials.

[0169] In the fourth embodiment, the third and fourth metal materials, individually or in combination with one or more of the first to third embodiments, are different from the first and second metal materials.

[0170] In the fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, the work function of the third metal material is greater than that of the second metal material, and the hydrogen diffusion coefficient of the fourth metal material is less than that of the second metal material.

[0171] although Figure 7 Example blocks of display process 700 are shown. In some embodiments, process 700 includes... Figure 7 The blocks described herein are those that, compared to additional blocks, fewer blocks, different blocks, or blocks arranged differently. Additionally or alternatively, two or more blocks in process 700 can be executed in parallel.

[0172] In this manner, a capacitor structure included in a semiconductor device (e.g., an interconnect layer of the semiconductor device) may include one or more electrode layers comprising materials with low hydrogen absorption characteristics to achieve a low hydrogen concentration in the capacitor structure. These materials enable the capacitor structure to be formed using low-temperature processes compatible with the layers and / or structure of the semiconductor device, while also enabling the capacitor structure to achieve fast charging and discharging speeds. Furthermore and / or alternatively, one or more electrode layers of the capacitor structure may include metallic materials for adjusting the bandgap of the electrode layers. For example, the metallic materials of the electrode layers may have a high bandgap, which reduces the likelihood (and / or number) of charge carrier tunneling. This enables the capacitor structure to achieve low leakage current, allowing the capacitor structure to retain charge for longer periods with less charge refresh (which reduces the power consumption of the semiconductor device).

[0173] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a device layer. The semiconductor device includes a plurality of transistors in the device layer. The semiconductor device includes an interconnect layer above the plurality of transistors. The interconnect layer includes a plurality of dielectric layers interleaved with a plurality of etch stop layers. The interconnect layer includes a plurality of metallization structures disposed in the plurality of dielectric layers. A first thickness of a first metallization structure of the plurality of metallization structures at the bottom of the interconnect layer is less than a second thickness of a second metallization structure of the plurality of metallization structures above the first metallization structure. The semiconductor device includes a capacitor structure in one or more of the plurality of dielectric layers of the interconnect layer. The capacitor structure includes a bottom electrode layer coupled to a second metallization structure, a top electrode layer, and an insulating layer between the top electrode layer and the bottom electrode layer. The bottom electrode layer comprises a metallic material having a work function greater than that of titanium (Ti) and a hydrogen (H) diffusion coefficient less than that of titanium.

[0174] In some embodiments, the top electrode layer is coupled to an interconnect structure located above the capacitor structure. The interconnect structure is coupled to a third metallization structure among a plurality of metallization structures located above the interconnect structure. The third thickness of the third metallization structure is greater than the second thickness of the second metallization structure. In some embodiments, the metallic material includes at least one of the following: ruthenium, nickel, platinum, palladium, or molybdenum. In some embodiments, the top electrode layer comprises the same metallic material as the bottom electrode layer. In some embodiments, the top electrode layer comprises a metallic material different from the metallic material of the bottom electrode layer. In some embodiments, the work function of the metallic material of the bottom electrode layer is greater than the work function of the metallic material of the top electrode layer. In some embodiments, the hydrogen diffusion coefficient of the metallic material of the bottom electrode layer is less than the hydrogen diffusion coefficient of the metallic material of the top electrode layer.

[0175] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a device layer. The semiconductor device includes a plurality of transistors in the device layer. At least one of the plurality of transistors includes a gate structure connected to at least three sides of a channel layer, and a gate dielectric layer above the channel layer and between the channel layer and the gate structure. The semiconductor device includes an interconnect layer above the plurality of transistors. The interconnect layer includes a plurality of dielectric layers and a multilayer metallization structure disposed in the plurality of dielectric layers. The multilayer metallization structure is spaced apart from each other by the plurality of dielectric layers. The dielectric constant of the gate dielectric layer is greater than the dielectric constant of the plurality of dielectric layers. The semiconductor device includes a capacitor structure in one or more of the plurality of dielectric layers in the interconnect layer. The capacitor structure includes a bottom electrode layer coupled to a first metallization structure in the multilayer metallization structure, a top electrode layer coupled to a second metallization structure in the multilayer metallization structure, and an insulating layer between the top electrode layer and the bottom electrode layer. At least one of the bottom electrode layer or the top electrode layer includes a multilayer thin film. The multilayer thin film includes a first metal layer comprising a first metallic material, and a second metal layer comprising a second metallic material different from the first metallic material. The hydrogen (H) diffusion coefficient of the first metallic material is less than that of titanium (Ti). The work function of the second metallic material is greater than that of titanium (Ti).

[0176] In some embodiments, the bottom electrode layer includes the multilayer thin film. A first metal layer is located between the second metal layer and the first metallization structure. In some embodiments, the multilayer thin film includes a third metal layer containing a third metal material different from the first and second metal materials. In some embodiments, the top electrode layer includes a third metal material different from the first and second metal materials. In some embodiments, the work function of the second metal material is greater than the work function of the third metal material. In some embodiments, the top electrode layer includes another multilayer thin film, the other multilayer thin film including: a third metal layer containing a third metal material; and a fourth metal layer containing a fourth metal material different from the third metal material. The work function of the third metal material is greater than the work function of titanium. The hydrogen diffusion coefficient of the fourth metal material is less than the hydrogen diffusion coefficient of titanium. The fourth metal layer is located between the third metal layer and the second metallization structure. In some embodiments, the third metal material is different from the first and second metal materials. The fourth metal material is different from the first and second metal materials.

[0177] As described in more detail above, some embodiments described herein provide a method. The method includes forming a plurality of transistors in a device layer of a semiconductor device. The method includes forming a plurality of dielectric layers over the plurality of transistors and a multilayer conductive structure within the plurality of dielectric layers. The method includes forming a recess through at least a portion of the plurality of dielectric layers. The method includes depositing a bottom electrode layer of a capacitor structure in the recess, such that a portion of the bottom electrode layer is deposited over the conductive structure of the multilayer conductive structure. The hydrogen (H) diffusion coefficient of a first metal material of the bottom electrode layer is less than the hydrogen diffusion coefficient of a second metal material of the conductive structure. The method includes depositing an insulating layer of the capacitor structure over the bottom electrode layer in the recess. The method includes depositing a top electrode layer of the capacitor structure over the insulating layer in the recess.

[0178] In some embodiments, the work function of the first metal material of the bottom electrode layer is greater than the work function of the second metal material of the conductive structure. In some embodiments, the second metal material of the conductive structure comprises copper. The first metal material of the bottom electrode layer comprises at least one of the following: ruthenium, nickel, platinum, or palladium. In some embodiments, depositing the top electrode layer comprises: depositing a first metal layer of a multilayer thin film of the top electrode layer over an insulating layer; and depositing a second metal layer of a multilayer thin film over the first metal layer. The first metal layer comprises a third metal material. The second metal layer comprises a fourth metal material. The third metal material and the fourth metal material are different metal materials. In some embodiments, the third metal material and the fourth metal material are different from the first metal material and the second metal material. In some embodiments, the work function of the third metal material is greater than the work function of the second metal material. The hydrogen diffusion coefficient of the fourth metal material is less than the hydrogen diffusion coefficient of the second metal material.

[0179] The terms “approximately” and “substantially” can indicate that the value of a given quantity varies within a range of 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely illustrative and not restrictive. It should be understood that the terms “approximately” and “substantially” can refer to a percentage of the value of a given quantity according to this disclosure.

[0180] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions disclosed herein, and are not intended to limit them. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments disclosed herein.

Claims

1. A semiconductor device, characterized by comprising: include: Device layer; Multiple transistors are located in the device layer; An interconnect layer is located above the plurality of transistors, wherein the interconnect layer includes: Multiple dielectric layers, interspersed with multiple etch stop layers; and Multiple metallization structures are disposed in the multiple dielectric layers. Wherein the first thickness of the first metallization structure among the plurality of metallization structures located at the bottom of the interconnect layer is less than the second thickness of the second metallization structure among the plurality of metallization structures located above the first metallization structure; and A capacitor structure is located in one or more of the plurality of dielectric layers of the interconnect layer, wherein the capacitor structure includes: The bottom electrode layer is coupled to the second metallization structure. The bottom electrode layer comprises a metallic material having a work function greater than that of titanium and a hydrogen diffusion coefficient less than that of titanium. Top electrode layer; and An insulating layer is located between the top electrode layer and the bottom electrode layer.

2. The semiconductor device according to claim 1, characterized in that, The metallic material includes at least one of the following: ruthenium, nickel, platinum, Palladium, or molybdenum.

3. The semiconductor device according to claim 1, characterized in that, The work function of the metal material in the bottom electrode layer is greater than the work function of the metal material in the top electrode layer.

4. The semiconductor device according to claim 1, characterized in that, The hydrogen diffusion coefficient of the metal material in the bottom electrode layer is less than that of the metal material in the top electrode layer.

5. A semiconductor device, characterized in that, include: Device layer; Multiple transistors, in the device layer, At least one of the plurality of transistors includes: A gate structure, connected to at least three sides of the channel layer; and A gate dielectric layer is located above the channel layer and between the channel layer and the gate structure. An interconnect layer, above the plurality of transistors, includes: Multiple dielectric layers; A multilayer metallized structure is disposed within the plurality of dielectric layers. The multilayer metallized structures are separated from each other by the plurality of dielectric layers, and The dielectric constant of the gate dielectric layer is greater than the dielectric constant of the plurality of dielectric layers; and A capacitor structure, in one or more of the plurality of dielectric layers of the interconnect layer, wherein the capacitor structure comprises: The bottom electrode layer is coupled to the first metallization structure in the multilayer metallization structure; The top electrode layer is coupled to the second metallization structure in the multilayer metallization structure; and An insulating layer is located between the top electrode layer and the bottom electrode layer. At least one of the bottom electrode layer or the top electrode layer comprises a multilayer thin film, the multilayer thin film comprising: A first metal layer, comprising a first metallic material; and The second metal layer comprises a second metal material different from the first metal material. Wherein the hydrogen diffusion coefficient of the first metallic material is less than that of titanium, and The work function of the second metallic material is greater than that of titanium.

6. The semiconductor device according to claim 5, characterized in that, The bottom electrode layer includes the multilayer thin film; and The first metal layer is located between the second metal layer and the first metallized structure.

7. The semiconductor device according to claim 6, characterized in that, The multilayer thin film includes: The third metal layer comprises a third metal material that is different from the first metal material and the second metal material.

8. The semiconductor device according to claim 6, characterized in that, The top electrode layer includes another multilayer thin film, which includes: A third metal layer, comprising a third metal material; and The fourth metal layer comprises a fourth metal material different from the third metal material. The work function of the third metallic material is greater than that of titanium. The hydrogen diffusion coefficient of the fourth metallic material is less than that of titanium, and The fourth metal layer is located between the third metal layer and the second metallization structure.

9. A method for forming a semiconductor device, characterized in that, include: Multiple transistors are formed in the device layer of a semiconductor device; A plurality of dielectric layers and a multilayer conductive structure are formed above the plurality of transistors; Forming a recess that extends through at least a portion of the plurality of dielectric layers; A bottom electrode layer of a capacitor structure is deposited in the recess, such that a portion of the bottom electrode layer is deposited above the conductive structure of the multilayer conductive structure. The hydrogen diffusion coefficient of the first metal material in the bottom electrode layer is less than that of the hydrogen diffusion coefficient of the second metal material in the conductive structure. An insulating layer of the capacitor structure is deposited over the bottom electrode layer in the recess; as well as A top electrode layer of the capacitor structure is deposited over the insulating layer in the recess.

10. The method according to claim 9, characterized in that, The second metallic material of the conductive structure comprises copper; and The first metallic material of the bottom electrode layer comprises at least one of the following: ruthenium, nickel, Platinum, or palladium.

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