A fast response zero-point adaptive compensation LDO circuit

Abstract

The application discloses a kind of fast response zero point adaptive compensation LDO circuit, it is related to integrated circuit design technical field, including: bias circuit, error amplifier circuit, output drive stage circuit, output stage circuit and zero point adaptive compensation circuit;The bias circuit is error amplifier circuit and output drive stage circuit provide current and voltage bias;Through the error amplifier circuit, level conversion is realized, simultaneously with the P tube bias voltage and N tube bias voltage formed is converted to secondary point;The output drive stage circuit provides the voltage of secondary point to output stage circuit, limits its static current;Zero point adaptive compensation circuit is based on load current variation dynamic adjustment zeroing resistance, dynamically compensates the change of secondary point, so that it can be zeroed in the preset current range by zero point.This application reduces compensation capacitor, saves chip area, and enhances dynamic response speed.In practical application, it can also meet more extensive load current and load capacitance demand.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and more specifically to a fast-response zero-point adaptive compensation LDO circuit. Background Technology

[0002] With the increasing demand for System-on-Chip (SoC) integration, Low-Noise Detectors (LDOs) are playing an increasingly important role in analog and mixed-signal chips due to their advantages such as low noise and fast response to load changes. Since SoCs need to integrate many functions, many of which are clock-synchronized, the LDO output must respond quickly to changes in load current. Conventional unidirectional LDOs can only provide unidirectional output current; for instantaneous decreases in load current, large filter capacitors are often required for voltage regulation, consuming significant chip area and limiting response speed. Currently, bidirectional LDOs are mainly used to address this issue. In the design of bidirectional LDOs, the mainstream output driver stage design currently adopts a push-pull output method, and the compensation method often requires separate stability compensation for the PMOS and NMOS drive loops.

[0003] For example, patent CN117032370A provides a fast-response low-dropout LDO circuit, which uses a second capacitor C2 and a third capacitor C3 to perform Miller compensation for the PMOS feedback loop and the NMOS feedback loop, respectively. However, when facing application scenarios where the output load current and the first capacitor C1 vary greatly, this application needs to set different second capacitors C2 and third capacitors C3 to ensure circuit stability. Moreover, the capacitance values ​​of the second capacitor C2 and the third capacitor C3 are usually several times or tens of times that of the first capacitor C1, resulting in a huge waste of chip area and affecting the response speed.

[0004] Current stability designs often employ fixed capacitors as Miller capacitors and fixed zero-point compensation resistors, which severely limits the maximum load current of bidirectional LDOs. As the load current increases, the secondary pole of the bidirectional LDO changes, and a fixed zero-point compensation resistor cannot handle the large-range zero-point drift, resulting in the secondary pole not being canceled out by the zero point and affecting system stability. This invention employs an adaptive zero-point compensation method, dynamically converting load current changes into changes in the zero-point compensation resistor, thereby dynamically canceling out secondary pole changes. A lower-value compensation capacitor can meet the driving requirements of a wide range of load capacitance and load current, and also increases the speed of dynamic response. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a fast-response zero-point adaptive compensation LDO circuit.

[0006] The objective of this invention is achieved through the following technical solution: This application discloses a fast-response zero-point adaptive compensation LDO circuit, comprising: a bias circuit, an error amplifier circuit, an output driver stage circuit, an output stage circuit, and a zero-point adaptive compensation circuit; the bias circuit provides current and voltage bias for the error amplifier circuit and the output driver stage circuit; the error amplifier circuit realizes level conversion and simultaneously converts the P-transistor bias voltage and N-transistor bias voltage to the secondary point; the output driver stage circuit provides the voltage of the secondary point to the output stage circuit, limiting its quiescent current; the zero-point adaptive compensation circuit dynamically adjusts the zero-adjustment resistor based on the load current change, dynamically compensating for the change of the secondary point, so that it can be canceled by the zero point within a preset current range.

[0007] Preferably, the bias circuit includes a first PMOS transistor PMc1, a second PMOS transistor PMc2, a third PMOS transistor PMc3, a fourth PMOS transistor PMc4, a fifth PMOS transistor PMb1, a sixth PMOS transistor PMb2, a seventh PMOS transistor PMb3, an eighth PMOS transistor PMb4, a first NMOS transistor NMb1, a second NMOS transistor NMb2, a third NMOS transistor NMb3, a fourth NMOS transistor NMc1, a fifth NMOS transistor NMc2, and a sixth NMOS transistor NMc3; The source of the first PMOS transistor PMc1 is connected to the power supply voltage VCC. The drain of the first PMOS transistor PMc1 is connected to the source of the fifth PMOS transistor PMb1. The gate of the first PMOS transistor PMc1 is connected to the gate of the second PMOS transistor PMc2 and the first resistor R1. The drain of the fifth PMOS transistor PMb1 is connected to the first resistor R1. The first resistor R1 is connected to the bias current IBIAS and then to the ground terminal VSS. The gate of the fifth PMOS transistor PMb1 is connected to the gate of the sixth PMOS transistor PMb2 and the first resistor R1. The source of the second PMOS transistor PMc2 is connected to the power supply voltage VCC. The drain of the second PMOS transistor PMc2 is connected to the source of the sixth PMOS transistor PMb2. The drain of the sixth PMOS transistor PMb2 is connected to the second resistor R2. The drain of the first NMOS transistor NMb1 is connected to the second resistor R2, the source of the first NMOS transistor NMb1 is connected to the drain of the fourth NMOS transistor NMc1, and the gate of the first NMOS transistor NMb1 is connected to the gate of the second NMOS transistor NMb2 and the second resistor R2. The source of the fourth NMOS transistor NMc1 is connected to the ground terminal VSS, and the gate of the fourth NMOS transistor NMc1 is connected to the gate of the fifth NMOS transistor NMc2 and the second resistor R2. The second NMOS transistor NMb1... The source of transistor 2 is connected to the drain of the fifth NMOS transistor NMc2, and the drain of the second NMOS transistor NMb2 is connected to the third resistor R3; the source of the fifth NMOS transistor NMc2 is connected to the ground terminal VSS; the source of the third PMOS transistor PMc3 is connected to the power supply voltage VCC, the drain of the third PMOS transistor PMc3 is connected to the source of the seventh PMOS transistor PMb3, and the gate of the third PMOS transistor PMc3 is connected to the third resistor; the third resistor R3 is connected between the drain and gate of the seventh PMOS transistor PMb3. The source of the fourth PMOS transistor PMC4 is connected to the power supply voltage VCC, and the drain of the fourth PMOS transistor PMC4 is connected to the source of the eighth PMOS transistor PMb4. The gate of the fourth PMOS transistor PMC4 is connected to the gate of the first PMOS transistor PMC1, the gate of the second PMOS transistor PMC2, and the first resistor R1. The gate of the eighth PMOS transistor PMb4 is connected to the gate of the fifth PMOS transistor PMC1, the gate of the sixth PMOS transistor PMC2, and the first resistor R1. The drain of the eighth PMOS transistor PMb4 is connected to the fourth resistor R4 and then to the drain of the third NMOS transistor NMb3. The source of the third NMOS transistor NMb3 is connected to the drain of the sixth NMOS transistor NMc3, and the gate of the third NMOS transistor NMb3 is connected to the fourth resistor R4. The source of the sixth NMOS transistor NMc3 is connected to the ground terminal VSS, and the gate of the sixth NMOS transistor NMc3 is also connected to the drain of the third NMOS transistor NMb3 and the fourth resistor.

[0008] Preferably, the error amplifier circuit includes a ninth PMOS transistor PMc5, a tenth PMOS transistor PMc6, an eleventh PMOS transistor PMc7, a twelfth PMOS transistor PMc8, a thirteenth PMOS transistor PMs1, a fourteenth PMOS transistor PMs2, a seventh NMOS transistor NMb4, an eighth NMOS transistor NMc4, a ninth NMOS transistor NMc5, a tenth NMOS transistor NMc6, an eleventh NMOS transistor NMs1, a first input pair NMinp, and a second input pair NMinn. The gate of the first input pair transistor NMinp is connected to the reference voltage input terminal Vref, and the gate of the second input pair transistor NMinn is connected to the feedback voltage input terminal Fb. After the source of the first input pair transistor NMinp is connected to the source of the second input pair transistor NMinn, it is connected to the drain of the seventh NMOS transistor NMb4. The gate of the seventh NMOS transistor NMb4 is connected to the gate of the first NMOS transistor NMb1, the gate of the second NMOS transistor NMb2, and the second resistor R2. The source of the seventh NMOS transistor NMb4 is connected to the drain of the eighth NMOS transistor NMc4. The source of the eighth NMOS transistor NMc4 is connected to the ground terminal VSS. The gate of the eighth NMOS transistor NMc4 is connected to the gate of the fourth NMOS transistor NMc1, the gate of the fifth NMOS transistor NMc2, and the second resistor R2. The sources of the ninth PMOS transistor PMC5, the tenth PMOS transistor PMC6, the eleventh PMOS transistor PMC7, and the twelfth PMOS transistor PMC8 are connected to the power supply voltage VCC. The gate and drain of the ninth PMOS transistor PMC5 are connected and then connected to the gate of the eleventh PMOS transistor PMC7. The gate and drain of the tenth PMOS transistor PMC6 are connected and then connected to the gate of the twelfth PMOS transistor PMC8. The drain of the ninth PMOS transistor PMC5 is connected to the drain of the first input pair transistor NMinp, and the drain of the tenth PMOS transistor PMC6 is connected to the drain of the second input pair transistor NMinn. The source of the thirteenth PMOS transistor PMs1 is connected to the drain of the eleventh PMOS transistor PMc7; the gate of the thirteenth PMOS transistor PMs1 is connected to the third resistor R3; the drain of the thirteenth PMOS transistor PMs1 is connected to the drain of the ninth NMOS transistor NMc5; the gate of the ninth NMOS transistor NMc5 is connected to its drain, and then connected to the gate of the tenth NMOS transistor NMc6; the sources of the ninth NMOS transistor NMc5 and the tenth NMOS transistor NMc6 are respectively connected to the ground terminal VSS; the drain of the tenth NMOS transistor NMc6 is connected to the second node B; and the second node B is connected to the output driver stage circuit. The drain of the twelfth PMOS transistor PMC8 is connected to the first node A, which is connected to the output driver stage circuit. The drain of the eleventh NMOS transistor NMs1 and the source of the fourteenth PMOS transistor PMs2 are connected to the first node A. The source of the eleventh NMOS transistor NMs1 and the drain of the fourteenth PMOS transistor PMs2 are connected to the second node B. The gate of the fourteenth PMOS transistor PMs2 is connected to the third resistor R3. The gate of the eleventh NMOS transistor NMs1 is connected to the zero-point adaptive compensation circuit.

[0009] Preferably, the zero-point adaptive compensation circuit includes a fifteenth PMOS transistor PMs3 and a twelfth NMOS transistor NMs2. The source of the fifteenth PMOS transistor PMs3 is connected to the first node A and the output drive stage circuit, respectively. The gate of the fifteenth PMOS transistor PMs3 is connected to the third resistor R3. The drain of the fifteenth PMOS transistor PMs3 is connected to the sixth resistor R6 and the fifth resistor R5 in sequence, and then connected to the drain of the twelfth NMOS transistor NMs2. The source of the twelfth NMOS transistor NMs2 is connected to the output drive stage circuit and the second node B, respectively. The gate of the twelfth NMOS transistor NMs2 is connected to the fourth resistor R4 and the gate of the eleventh NMOS transistor NMs1, respectively. A third node is provided between the fifth resistor R5 and the sixth resistor R6. The third node is connected to the compensation capacitor Cc and the zero-adjustment resistor Rc in sequence, and then connected to the output stage circuit.

[0010] Preferably, the output drive stage circuit includes a sixteenth PMOS transistor PMbuf and a thirteenth NMOS transistor NMbuf; the gate of the thirteenth NMOS transistor NMbuf is connected to the second node B, and the source of the thirteenth NMOS transistor NMbuf is connected to the seventh resistor R7; the source of the sixteenth PMOS transistor PMbuf is connected to the eighth resistor R8, and the gate of the sixteenth PMOS transistor PMbuf is connected to the first node A.

[0011] Preferably, the output stage circuit includes a seventeenth PMOS transistor PMpower and a fourteenth NMOS transistor NMpower; the gate of the fourteenth NMOS transistor NMpower is connected to the source of the thirteenth NMOS transistor NMbuf and the seventh resistor R7, respectively; the gate of the seventeenth PMOS transistor PMpower is connected to the source of the thirteenth NMOS transistor NMbuf and the eighth resistor R8, respectively; the drain of the seventeenth PMOS transistor PMpower is connected to the drain of the fourteenth NMOS transistor NMpower, and a fourth node is provided between the drains of the seventeenth PMOS transistor PMpower and the drain of the fourteenth NMOS transistor NMpower. The fourth node is connected to the compensation capacitor Cc and also to the output node OUT. A fifth node and a sixth node are provided between the fourth node and the output node OUT. The fifth node is connected to the tenth resistor Rfb1 and the eleventh resistor Rfb2 in sequence and then to the ground terminal GND. The tenth resistor Rfb1 and the eleventh resistor Rfb2 are also connected to the feedback voltage input terminal Fb, respectively; the sixth node is connected to the load capacitor Cout and then to the ground terminal GND.

[0012] The beneficial effects of this invention are: 1) This application provides a bidirectional LDO compensation method. By introducing a zero-point compensation resistor that varies with the load current, it dynamically compensates for changes in the secondary point, allowing the secondary point to be canceled out by the zero point over a wider current range. This improves system stability, reduces the compensation capacitor, saves chip area, and enhances dynamic response speed. In practical applications, it can also meet a wide range of load current and load capacitance requirements. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a fast-response zero-point adaptive compensation LDO circuit according to an embodiment of the present invention. Detailed Implementation

[0014] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] This application discloses a fast-response zero-point adaptive compensation LDO circuit. By introducing a zero-point compensation resistor that varies with the load current, it dynamically compensates for changes in the secondary point, allowing the secondary point to be canceled out by the zero point over a wider current range. This improves system stability and design, reduces the compensation capacitor area, and accelerates the LDO's response speed to bidirectional load currents. A schematic diagram of the fast-response zero-point adaptive compensation LDO circuit is shown below. Figure 1 As shown, it includes: a bias circuit, an error amplifier circuit, an output driver stage circuit, an output stage circuit, and a zero-point adaptive compensation circuit; the bias circuit provides current and voltage bias for the error amplifier circuit and the output driver stage circuit; the error amplifier circuit realizes level conversion and converts the P-transistor bias voltage and N-transistor bias voltage to the secondary point; the output driver stage circuit provides the voltage of the secondary point to the output stage circuit, limiting its quiescent current; the zero-point adaptive compensation circuit dynamically adjusts the zero-adjustment resistor based on the load current change, dynamically compensating for the change of the secondary point, so that it can be canceled by the zero point within a preset current range.

[0016] For example, the bias circuit includes a first PMOS transistor PMc1, a second PMOS transistor PMc2, a third PMOS transistor PMc3, a fourth PMOS transistor PMc4, a fifth PMOS transistor PMb1, a sixth PMOS transistor PMb2, a seventh PMOS transistor PMb3, an eighth PMOS transistor PMb4, a first NMOS transistor NMb1, a second NMOS transistor NMb2, a third NMOS transistor NMb3, a fourth NMOS transistor NMc1, a fifth NMOS transistor NMc2, and a sixth NMOS transistor NMc3; The source of the first PMOS transistor PMc1 is connected to the power supply voltage VCC. The drain of the first PMOS transistor PMc1 is connected to the source of the fifth PMOS transistor PMb1. The gate of the first PMOS transistor PMc1 is connected to the gate of the second PMOS transistor PMc2 and the first resistor R1. The drain of the fifth PMOS transistor PMb1 is connected to the first resistor R1. The first resistor R1 is connected to the bias current IBIAS and then to the ground terminal VSS. The gate of the fifth PMOS transistor PMb1 is connected to the gate of the sixth PMOS transistor PMb2 and the first resistor R1. The source of the second PMOS transistor PMc2 is connected to the power supply voltage VCC. The drain of the second PMOS transistor PMc2 is connected to the source of the sixth PMOS transistor PMb2. The drain of the sixth PMOS transistor PMb2 is connected to the second resistor R2. The drain of the first NMOS transistor NMb1 is connected to the second resistor R2, the source of the first NMOS transistor NMb1 is connected to the drain of the fourth NMOS transistor NMc1, and the gate of the first NMOS transistor NMb1 is connected to the gate of the second NMOS transistor NMb2 and the second resistor R2. The source of the fourth NMOS transistor NMc1 is connected to the ground terminal VSS, and the gate of the fourth NMOS transistor NMc1 is connected to the gate of the fifth NMOS transistor NMc2 and the second resistor R2. The second NMOS transistor NMb1... The source of transistor 2 is connected to the drain of the fifth NMOS transistor NMc2, and the drain of the second NMOS transistor NMb2 is connected to the third resistor R3; the source of the fifth NMOS transistor NMc2 is connected to the ground terminal VSS; the source of the third PMOS transistor PMc3 is connected to the power supply voltage VCC, the drain of the third PMOS transistor PMc3 is connected to the source of the seventh PMOS transistor PMb3, and the gate of the third PMOS transistor PMc3 is connected to the third resistor; the third resistor R3 is connected between the drain and gate of the seventh PMOS transistor PMb3. The source of the fourth PMOS transistor PMC4 is connected to the power supply voltage VCC, and the drain of the fourth PMOS transistor PMC4 is connected to the source of the eighth PMOS transistor PMb4. The gate of the fourth PMOS transistor PMC4 is connected to the gate of the first PMOS transistor PMC1, the gate of the second PMOS transistor PMC2, and the first resistor R1. The gate of the eighth PMOS transistor PMb4 is connected to the gate of the fifth PMOS transistor PMb1, the gate of the sixth PMOS transistor PMb2, and the first resistor R1. The drain of the eighth PMOS transistor PMb4 is connected to the fourth resistor R4 and then to the drain of the third NMOS transistor NMb3. The source of the third NMOS transistor NMb3 is connected to the drain of the sixth NMOS transistor NMc3, and the gate of the third NMOS transistor NMb3 is connected to the fourth resistor R4. The source of the sixth NMOS transistor NMc3 is connected to the ground terminal VSS, and the gate of the sixth NMOS transistor NMc3 is also connected to the drain of the third NMOS transistor NMb3 and the fourth resistor.

[0017] For example, the error amplifier circuit includes a ninth PMOS transistor PMc5, a tenth PMOS transistor PMc6, an eleventh PMOS transistor PMc7, a twelfth PMOS transistor PMc8, a thirteenth PMOS transistor PMs1, a fourteenth PMOS transistor PMs2, a seventh NMOS transistor NMb4, an eighth NMOS transistor NMc4, a ninth NMOS transistor NMc5, a tenth NMOS transistor NMc6, an eleventh NMOS transistor NMs1, a first input pair NMinp, and a second input pair NMinn; the seventh NMOS transistor NMb4 and the eighth NMOS transistor NMc4 constitute a case-code tail current mirror, and the current mirror PMc5-PMc... 8 and the current mirrors NMc5-NMc6 form a differential single circuit. The fourteenth PMOS transistor PMs2 and the eleventh NMOS transistor NMs1 perform level conversion, converting the P-tube bias voltage composed of the third PMOS transistor PMc3, the seventh PMOS transistor PMb3 and the third resistor R3, and the N-tube bias voltage composed of the sixth NMOS transistor NMc3, the third NMOS transistor NMb3 and the fourth resistor R4 to the first node A and the second node B, respectively. The thirteenth PMOS transistor PMs1 reduces the leakage voltage modulation effect, making the leakage voltages of the ninth NMOS transistor NMc5 and the tenth NMOS transistor NMc6 nearly the same, reducing current error and making the output voltage more accurate. The gate of the first input pair transistor NMinp is connected to the reference voltage input terminal Vref, and the gate of the second input pair transistor NMinn is connected to the feedback voltage input terminal Fb. After the source of the first input pair transistor NMinp is connected to the source of the second input pair transistor NMinn, it is connected to the drain of the seventh NMOS transistor NMb4. The gate of the seventh NMOS transistor NMb4 is connected to the gate of the first NMOS transistor NMb1, the gate of the second NMOS transistor NMb2, and the second resistor R2. The source of the seventh NMOS transistor NMb4 is connected to the drain of the eighth NMOS transistor NMc4. The source of the eighth NMOS transistor NMc4 is connected to the ground terminal VSS. The gate of the eighth NMOS transistor NMc4 is connected to the gate of the fourth NMOS transistor NMc1, the gate of the fifth NMOS transistor NMc2, and the second resistor R2. The sources of the ninth PMOS transistor PMC5, the tenth PMOS transistor PMC6, the eleventh PMOS transistor PMC7, and the twelfth PMOS transistor PMC8 are connected to the power supply voltage VCC. The gate and drain of the ninth PMOS transistor PMC5 are connected and then connected to the gate of the eleventh PMOS transistor PMC7. The gate and drain of the tenth PMOS transistor PMC6 are connected and then connected to the gate of the twelfth PMOS transistor PMC8. The drain of the ninth PMOS transistor PMC5 is connected to the drain of the first input pair transistor NMinp, and the drain of the tenth PMOS transistor PMC6 is connected to the drain of the second input pair transistor NMinn. The source of the thirteenth PMOS transistor PMs1 is connected to the drain of the eleventh PMOS transistor PMc7; the gate of the thirteenth PMOS transistor PMs1 is connected to the third resistor R3; the drain of the thirteenth PMOS transistor PMs1 is connected to the drain of the ninth NMOS transistor NMc5; the gate of the ninth NMOS transistor NMc5 is connected to its drain, and then connected to the gate of the tenth NMOS transistor NMc6; the sources of the ninth NMOS transistor NMc5 and the tenth NMOS transistor NMc6 are respectively connected to the ground terminal VSS; the drain of the tenth NMOS transistor NMc6 is connected to the second node B; and the second node B is connected to the output driver stage circuit. The drain of the twelfth PMOS transistor PMC8 is connected to the first node A, which is connected to the output driver stage circuit. The drain of the eleventh NMOS transistor NMs1 and the source of the fourteenth PMOS transistor PMs2 are connected to the first node A. The source of the eleventh NMOS transistor NMs1 and the drain of the fourteenth PMOS transistor PMs2 are connected to the second node B. The gate of the fourteenth PMOS transistor PMs2 is connected to the third resistor R3. The gate of the eleventh NMOS transistor NMs1 is connected to the zero-point adaptive compensation circuit.

[0018] For example, the zero-point adaptive compensation circuit includes a fifteenth PMOS transistor PMs3 and a twelfth NMOS transistor NMs2. The source of the fifteenth PMOS transistor PMs3 is connected to the first node A and the output driver stage circuit, respectively. The gate of the fifteenth PMOS transistor PMs3 is connected to the third resistor R3. The drain of the fifteenth PMOS transistor PMs3 is connected to the sixth resistor R6 and the fifth resistor R5 in sequence, and then connected to the drain of the twelfth NMOS transistor NMs2. The source of the twelfth NMOS transistor NMs2 is connected to the output driver stage circuit and the second node B, respectively. The gate of the twelfth NMOS transistor NMs2 is connected to the fourth resistor R4 and the gate of the eleventh NMOS transistor NMs1, respectively. A third node is provided between the fifth resistor R5 and the sixth resistor R6. The third node is connected to the compensation capacitor Cc and the zero-adjustment resistor Rc in sequence, and then connected to the output stage circuit.

[0019] For example, the fifteenth PMOS transistor PMs3 and the sixth resistor R6 modulate the zero-adjustment resistor at the A terminal of the first node, and the twelfth NMOS transistor NMs2 and the fifth resistor R5 modulate the zero-adjustment resistor at the B terminal of the second node.

[0020] For example, the output driver stage circuit includes a sixteenth PMOS transistor PMbuf and a thirteenth NMOS transistor NMbuf; the gate of the thirteenth NMOS transistor NMbuf is connected to the second node B, and the source of the thirteenth NMOS transistor NMbuf is connected to the seventh resistor R7; the source of the sixteenth PMOS transistor PMbuf is connected to the eighth resistor R8, and the gate of the sixteenth PMOS transistor PMbuf is connected to the first node A. The output driver stage circuit is a buffer stage, consisting of a P-type buffer composed of the eighth resistor R8 and the sixteenth PMOS transistor PMbuf, and an N-type buffer composed of the seventh resistor R7 and the thirteenth NMOS transistor NMbuf. It supplies the voltage of the first node A and the voltage of the second node B to the P-type power transistor PMpower and the N-type power transistor NMpower respectively, limiting their quiescent current and providing a certain dynamic output current capability.

[0021] For example, the output stage circuit includes a seventeenth PMOS transistor PMpower and a fourteenth NMOS transistor NMpower; the gate of the fourteenth NMOS transistor NMpower is connected to the source of the thirteenth NMOS transistor NMbuf and the seventh resistor R7, respectively; the gate of the seventeenth PMOS transistor PMpower is connected to the source of the thirteenth NMOS transistor NMbuf and the eighth resistor R8, respectively; the drain of the seventeenth PMOS transistor PMpower is connected to the drain of the fourteenth NMOS transistor NMpower, and a fourth node is provided between the drain of the seventeenth PMOS transistor PMpower and the drain of the fourteenth NMOS transistor NMpower. The fourth node is connected to the compensation capacitor Cc and also to the output node OUT. A fifth node and a sixth node are provided between the fourth node and the output node OUT. The fifth node is connected to the tenth resistor Rfb1 and the eleventh resistor Rfb2 in sequence and then to the ground terminal GND. The tenth resistor Rfb1 and the eleventh resistor Rfb2 are also connected to the feedback voltage input terminal Fb, respectively; the sixth node is connected to the load capacitor Cout and then to the ground terminal GND.

[0022] For example, let the zero point formed by the seventeenth PMOS transistor PMpower and the compensation capacitor Cc be... , , Let the transconductance of the seventeenth PMOS transistor PMpower be denoted as ; let the zero point formed by the fourteenth NMOS transistor NMpower and the compensation capacitor Cc be denoted as . , , This indicates the transconductance of the fourteenth NMOS transistor, NMpower. This indicates the capacitance value of the compensation capacitor Cc. The output port typically has a large load capacitor Cout as a filter capacitor. In this application, under no-load conditions, only static current flows through PMpower and NMpower, so the compensation capacitor Cc has almost no effect. At this time, the dominant pole is at the output terminal, and the fifteenth PMOS transistor PMs3 and the twelfth NMOS transistor NMs2 are turned on. The pole of the first node A is... for The pole of the second node B for ;in, This indicates the resistance value of the sixth resistor, R6. This indicates the resistance value of the seventh resistor, R7. The total parasitic capacitance at point A includes the gate-drain parasitic capacitances of the twelfth PMOS transistor PMc8 and the eleventh NMOS transistor NMs1, the gate-source parasitic capacitances of the fourteenth PMOS transistor PMs2, the fifteenth PMOS transistor PMs3 and the sixteenth PMOS transistor PMbuf, and the drain-source parasitic capacitances of the twelfth PMOS transistor PMc, the eleventh NMOS transistor NMs1, the fourteenth PMOS transistor PMs2 and the fifteenth PMOS transistor PMs3. The total parasitic capacitance at point B includes the gate-drain parasitic capacitances of the fourteenth PMOS transistor PMs2 and the tenth NMOS transistor NMc6, the gate-source parasitic capacitances of the eleventh NMOS transistor NMs1, the twelfth NMOS transistor NMs2, and the thirteenth NMOS transistor NMbuf, and the drain-source parasitic capacitances of the fourteenth PMOS transistor PMs2, the tenth NMOS transistor NMc6, the eleventh NMOS transistor NMs1, and the twelfth NMOS transistor NMs2. At this point, and All are relatively small. and It is also relatively low-frequency. It can be... and respectively with and To offset. And P Mpower The gate is connected to the eighth resistor R8 to the power supply, N Mpower A seventh resistor R7 is connected to ground at the gate of the LDO, allowing the pole to be pushed to a higher frequency. Therefore, this application significantly improves the circuit's stability under no-load conditions. As the LDO output current increases, the output pole shifts to higher frequencies, while the dominant pole moves towards an internal node in the circuit. A zero-point resistor needs to be introduced to cancel out one of these poles. The zero-adjustment resistor Rc and the sixth resistor R6 are introduced to make the zero-point resistor... If the LDO is adjusted to a frequency near this range, it can achieve good stability, provided that: ,but ; This indicates the resistance value of the zero-adjustment resistor Rc. This indicates the resistance value of the sixth resistor, R6. This represents the capacitance value of the load capacitor Cout; since R6 and R7 are offset... and If the time has been confirmed, it can be confirmed according to the above formula. The value of . When the PMpower pull-down current increases. The required zero-adjustment resistor Rc and the sixth resistor R6 will decrease. Simultaneously, the gate voltage of the PMpower transistor drops, causing the voltage at the first node A to decrease, while the gate voltage of the fifteenth PMOS transistor PMs3 remains unchanged. As the pull-down current of the PMpower transistor further increases... The voltage is large enough that the zero-adjustment resistor Rc and the sixth resistor R6 are no longer needed for PMpower, and the fifteenth PMOS transistor PMs3 is turned off. Meanwhile, the NMpower's operating state remains unchanged; the twelfth NMOS transistor NMs2 remains on, and the zero-adjustment resistor Rc and the fifth resistor R5 function normally.

[0023] When the NMpower input current increases The voltage will increase, and the required zero-adjustment resistor Rc and the fifth resistor R5 will decrease. Simultaneously, the gate voltage of the NMpower transistor rises, causing the voltage at point B to rise, while the gate voltage of the twelfth NMOS transistor NMs2 remains unchanged. As the sink current of the NMpower transistor further increases, The current is large enough that the zero-adjustment resistor Rc and the fifth resistor R5 are no longer needed for the NMpower, and NMs2 is turned off. The PMpower's operating state remains unchanged; the fifteenth PMOS transistor PMs3 remains on, and the zero-adjustment resistor Rc and the sixth resistor R6 function normally. When the LDO load current increases, the zero-point compensation resistor can be dynamically adjusted according to the output current. No additional Miller capacitor is needed to achieve stability under no-load or heavy-load conditions, significantly reducing the capacitor area and thus accelerating the LDO's response to bidirectional current.

[0024] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A fast-response zero-point adaptive compensation LDO circuit, characterized in that, include: The circuit includes a bias circuit, an error amplifier circuit, an output driver stage circuit, an output stage circuit, and a zero-point adaptive compensation circuit; the bias circuit provides current and voltage bias for the error amplifier circuit and the output driver stage circuit. The error amplifier circuit achieves level conversion and simultaneously converts the bias voltages of the P-tube and N-tube to the secondary point; the output driver circuit provides the voltage of the secondary point to the output stage circuit, limiting its quiescent current. The zero-point adaptive compensation circuit dynamically adjusts the zero-adjustment resistor based on the load current change, dynamically compensates for the change of the secondary point, and makes it able to be canceled by the zero point within the preset current range. The zero-point adaptive compensation circuit includes a fifteenth PMOS transistor PMs3 and a twelfth NMOS transistor NMs2. The source of the fifteenth PMOS transistor PMs3 is connected to the first node A and the output driver stage circuit, respectively. The gate of the fifteenth PMOS transistor PMs3 is connected to the third resistor R3. The drain of the fifteenth PMOS transistor PMs3 is connected to the sixth resistor R6 and the fifth resistor R5 in sequence, and then connected to the drain of the twelfth NMOS transistor NMs2. The source of the twelfth NMOS transistor NMs2 is connected to the output driver stage circuit and the second node B, respectively. The gate of the twelfth NMOS transistor NMs2 is connected to the fourth resistor R4 and the gate of the eleventh NMOS transistor NMs1, respectively. A third node is provided between the fifth resistor R5 and the sixth resistor R6. The third node is connected to the compensation capacitor Cc and the zero-adjustment resistor Rc in sequence, and then connected to the output stage circuit. The output stage circuit includes a seventeenth PMOS transistor PMpower and a fourteenth NMOS transistor NMpower; the gates of the fourteenth NMOS transistor NMpower and the seventeenth PMOS transistor PMpower are respectively connected to the output drive stage circuit. The drain of the seventeenth PMOS transistor PMpower is connected to the drain of the fourteenth NMOS transistor NMpower. A fourth node is provided between the drains of the seventeenth PMOS transistor PMpower and the fourteenth NMOS transistor NMpower. The fourth node is connected to the compensation capacitor Cc and also to the output node OUT. A fifth node and a sixth node are provided between the fourth node and the output node OUT. The fifth node is connected to the tenth resistor Rfb1 and the eleventh resistor Rfb2 in sequence and then to the ground terminal GND. The tenth resistor Rfb1 and the eleventh resistor Rfb2 are also connected to the feedback voltage input terminal Fb respectively. The sixth node is connected to the load capacitor Cout and then to the ground terminal GND. The bias circuit includes a first PMOS transistor PMc1, a second PMOS transistor PMc2, a third PMOS transistor PMc3, a fourth PMOS transistor PMc4, a fifth PMOS transistor PMb1, a sixth PMOS transistor PMb2, a seventh PMOS transistor PMb3, an eighth PMOS transistor PMb4, a first NMOS transistor NMb1, a second NMOS transistor NMb2, a third NMOS transistor NMb3, a fourth NMOS transistor NMc1, a fifth NMOS transistor NMc2, and a sixth NMOS transistor NMc3; The source of the first PMOS transistor PMc1 is connected to the power supply voltage VCC. The drain of the first PMOS transistor PMc1 is connected to the source of the fifth PMOS transistor PMb1. The gate of the first PMOS transistor PMc1 is connected to the gate of the second PMOS transistor PMc2 and the first resistor R1. The drain of the fifth PMOS transistor PMb1 is connected to the first resistor R1. The first resistor R1 is connected to the bias current IBIAS and then to the ground terminal VSS. The gate of the fifth PMOS transistor PMb1 is connected to the gate of the sixth PMOS transistor PMb2 and the first resistor R1. The source of the second PMOS transistor PMc2 is connected to the power supply voltage VCC. The drain of the second PMOS transistor PMc2 is connected to the source of the sixth PMOS transistor PMb2. The drain of the sixth PMOS transistor PMb2 is connected to the second resistor R2. The drain of the first NMOS transistor NMb1 is connected to the second resistor R2, the source of the first NMOS transistor NMb1 is connected to the drain of the fourth NMOS transistor NMc1, and the gate of the first NMOS transistor NMb1 is connected to the gate of the second NMOS transistor NMb2 and the second resistor R2. The source of the fourth NMOS transistor NMc1 is connected to ground VSS. The gate of the fourth NMOS transistor NMc1 is connected to the gate of the fifth NMOS transistor NMc2 and the second resistor R2. The source of the second NMOS transistor NMb2 is connected to the drain of the fifth NMOS transistor NMc2, and the drain of the second NMOS transistor NMb2 is connected to the third resistor R3. The source of the fifth NMOS transistor NMc2 is connected to ground VSS. The source of the third PMOS transistor PMc3 is connected to the power supply voltage VCC. The drain of the third PMOS transistor PMc3 is connected to the source of the seventh PMOS transistor PMb3, and the gate of the third PMOS transistor PMc3 is connected to the third resistor. The third resistor R3 is connected between the drain and gate of the seventh PMOS transistor PMb3. The source of the fourth PMOS transistor PMC4 is connected to the power supply voltage VCC, and the drain of the fourth PMOS transistor PMC4 is connected to the source of the eighth PMOS transistor PMb4. The gate of the fourth PMOS transistor PMC4 is connected to the gate of the first PMOS transistor PMC1, the gate of the second PMOS transistor PMC2, and the first resistor R1. The gate of the eighth PMOS transistor PMb4 is connected to the gate of the fifth PMOS transistor PMb1, the gate of the sixth PMOS transistor PMb2, and the first resistor R1. The drain of the eighth PMOS transistor PMb4 is connected to the fourth resistor R4 and then to the drain of the third NMOS transistor NMb3. The source of the third NMOS transistor NMb3 is connected to the drain of the sixth NMOS transistor NMc3, and the gate of the third NMOS transistor NMb3 is connected to the fourth resistor R4. The source of the sixth NMOS transistor NMc3 is connected to the ground terminal VSS, and the gate of the sixth NMOS transistor NMc3 is also connected to the drain of the third NMOS transistor NMb3 and the fourth resistor. The error amplifier circuit includes the ninth PMOS transistor PMc5, the tenth PMOS transistor PMc6, the eleventh PMOS transistor PMc7, the twelfth PMOS transistor PMc8, the thirteenth PMOS transistor PMs1, the fourteenth PMOS transistor PMs2, the seventh NMOS transistor NMb4, the eighth NMOS transistor NMc4, the ninth NMOS transistor NMc5, the tenth NMOS transistor NMc6, the eleventh NMOS transistor NMs1, the first input pair NMinp, and the second input pair NMinn. The gate of the first input pair transistor NMinp is connected to the reference voltage input terminal Vref, and the gate of the second input pair transistor NMinn is connected to the feedback voltage input terminal Fb. After the source of the first input pair transistor NMinp is connected to the source of the second input pair transistor NMinn, it is connected to the drain of the seventh NMOS transistor NMb4. The gate of the seventh NMOS transistor NMb4 is connected to the gate of the first NMOS transistor NMb1, the gate of the second NMOS transistor NMb2, and the second resistor R2. The source of the seventh NMOS transistor NMb4 is connected to the drain of the eighth NMOS transistor NMc4. The source of the eighth NMOS transistor NMc4 is connected to the ground terminal VSS. The gate of the eighth NMOS transistor NMc4 is connected to the gate of the fourth NMOS transistor NMc1, the gate of the fifth NMOS transistor NMc2, and the second resistor R2. The sources of the ninth PMOS transistor PMC5, the tenth PMOS transistor PMC6, the eleventh PMOS transistor PMC7, and the twelfth PMOS transistor PMC8 are connected to the power supply voltage VCC. The gate and drain of the ninth PMOS transistor PMC5 are connected and then connected to the gate of the eleventh PMOS transistor PMC7. The gate and drain of the tenth PMOS transistor PMC6 are connected and then connected to the gate of the twelfth PMOS transistor PMC8. The drain of the ninth PMOS transistor PMC5 is connected to the drain of the first input pair transistor NMinp, and the drain of the tenth PMOS transistor PMC6 is connected to the drain of the second input pair transistor NMinn. The source of the thirteenth PMOS transistor PMs1 is connected to the drain of the eleventh PMOS transistor PMc7; the gate of the thirteenth PMOS transistor PMs1 is connected to the third resistor R3; the drain of the thirteenth PMOS transistor PMs1 is connected to the drain of the ninth NMOS transistor NMc5; the gate of the ninth NMOS transistor NMc5 is connected to its drain, and then connected to the gate of the tenth NMOS transistor NMc6; the sources of the ninth NMOS transistor NMc5 and the tenth NMOS transistor NMc6 are respectively connected to the ground terminal VSS; the drain of the tenth NMOS transistor NMc6 is connected to the second node B; and the second node B is connected to the output driver stage circuit. The drain of the twelfth PMOS transistor PMC8 is connected to the first node A, which is connected to the output driver stage circuit. The drain of the eleventh NMOS transistor NMS1 and the source of the fourteenth PMOS transistor PMs2 are connected, and then connected to the first node A. After the source of transistor NMs1 and the drain of the fourteenth PMOS transistor PMs2 are connected, they are connected to the second node B; the gate of the fourteenth PMOS transistor PMs2 is connected to the third resistor R3; the gate of the eleventh NMOS transistor NMs1 is connected to the zero-point adaptive compensation circuit. The output drive stage circuit includes a sixteenth PMOS transistor PMbuf and a thirteenth NMOS transistor NMbuf; The gate of the thirteenth NMOS transistor NMbuf is connected to the second node B, and the source of the thirteenth NMOS transistor NMbuf is connected to the seventh resistor R7; the source of the sixteenth PMOS transistor PMbuf is connected to the eighth resistor R8, and the gate of the sixteenth PMOS transistor PMbuf is connected to the first node A. The gate of the fourteenth NMOS transistor NMpower is connected to the source of the thirteenth NMOS transistor NMbuf and the seventh resistor R7, respectively; the gate of the seventeenth PMOS transistor PMpower is connected to the source of the thirteenth NMOS transistor NMbuf and the eighth resistor R8, respectively.

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