A kind of transconductance capacitor type residual amplification method and device based on loop operation

Abstract

The application discloses a kind of based on the transconductance capacitance type residual amplification method and device of cycle operation, belong to integrated circuit design technical field.Transconductance capacitance type residual amplification device includes: based on the transconductance capacitance amplifier and amplifier bias circuit of cycle operation;Adopt odd-even cycle discharge technology, odd cycle and even cycle are alternately carried out cycle discharge and amplification cooperation, realize equivalent gain promotion under low voltage;At the same time, even cycle reduces power consumption by reducing supply voltage;Again adopt tail resistance linearization technology, inhibit the transconductance change in cycle amplification process;The application can more simply construct high-precision, medium-speed pipeline successive approximation ADC under the constraint of low voltage, low power consumption, applicable to industrial internet of things, intelligent sensor and portable medical monitoring and other energy efficiency requirements strict application scenarios, and need and digital chip deep combination system level design.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, and relates to data converter design technology, specifically to a high-efficiency transconductance capacitive residual amplification method and apparatus based on cyclic operation. Background Technology

[0002] In the design of analog-to-digital converters (ADCs), pipelined successive approximation register architectures are widely used to balance high accuracy and low power consumption. In this architecture, the residual amplifier is the core connecting the preceding and following stages of the circuit. Its main task is to accurately amplify the residual signal from the previous stage for quantization in the next stage.

[0003] With the continuous evolution of integrated circuit technology, chip power supply voltages are constantly decreasing, posing a significant challenge to designing high-performance amplifiers in low-voltage environments. While traditional closed-loop amplification schemes offer accurate gain, insufficient voltage margin in transistors at low voltages makes it difficult to achieve adequate gain and bandwidth, and circuit stability design is extremely complex. In contrast, open-loop amplification schemes, which do not require a feedback network, exhibit better energy efficiency and swing characteristics at low voltages. However, this approach also has significant drawbacks: 1) at extremely low voltages, the amplification capability of an open-loop amplifier within a single cycle is limited; 2) linearity deteriorates rapidly with increasing output swing, making it difficult to meet the requirements of high-resolution ADCs.

[0004] Therefore, it is difficult to design a high-efficiency amplifier with both high gain and high linearity at low voltage using existing technologies. This makes it difficult to meet the stringent energy efficiency requirements of edge devices such as industrial IoT and smart sensors, and is not conducive to the deep integration of ADCs with advanced process digital chips. Summary of the Invention

[0005] To address the shortcomings of existing pipelined successive approximation ADC residual amplifiers in achieving high gain, high linearity, and high energy efficiency at low voltages, this invention provides a transconductance capacitive residual amplification method and apparatus based on cyclic operation. Specifically, it relates to a dynamic amplifier structure utilizing cyclic gain enhancement technology and tail resistor linearization technology. This technology allows for the simpler construction of high-precision, medium-to-high-speed pipelined successive approximation ADCs under low voltage and low power consumption constraints. It is highly suitable for applications with stringent energy efficiency requirements, such as industrial IoT, smart sensors, and portable medical monitoring, or for system-level designs requiring deep integration with digital chips.

[0006] The technical solution of this invention is:

[0007] A transconductance capacitive residual amplification method based on cyclic operation employs an "odd-even" cyclic discharge technique. Its essential difference from existing technologies lies in that it does not use a single discharge to complete residual amplification, but instead utilizes alternating cyclic discharge and amplification with odd and even periods to achieve equivalent gain improvement at low voltage. At the same time, the even period does not simply repeat the operation of the previous period, but reduces power consumption by lowering the supply voltage. Combined with tail resistor linearization technology, the transconductance change during the cyclic amplification process is suppressed, thus balancing gain, power consumption, and linearity under limited voltage swing.

[0008] The present invention relates to a transconductance capacitive residual amplifier device (system) based on cyclic operation, comprising: a transconductance capacitive amplifier based on cyclic operation and an amplifier bias circuit. The transconductance capacitive amplifier amplifies the residual signal. The bias circuit includes a constant transconductance bias circuit and a flying capacitor bias circuit. The constant transconductance bias circuit generates a bias current with the following characteristics: ensuring stable transconductance of the amplifier under varying process, voltage, and temperature (PVT) conditions. The flying capacitor bias circuit acts as a bridge between the constant transconductance bias circuit and the amplifier, responsible for copying the bias voltage to the transconductance capacitive amplifier. Together, they amplify the residual signal.

[0009] The specific components of the transconductance capacitive residual amplifier system based on cyclic operation proposed in this invention will be described in detail below.

[0010] A. A transconductance capacitor amplifier based on cyclic operation

[0011] In specific implementation, the residual amplifier used in this invention is a transconductance capacitor amplifier based on cyclic operation. As the core design of this invention, it includes an input transconductance pair, a linearization tail resistor, a capacitor load array, and digital logic. During operation, the amplifier receives the residual voltage generated by the first-stage ADC and achieves high-gain amplification at extremely low supply voltages through multiple cycles of charge integration and reset processes. This amplifier not only eliminates the gain limitation of traditional open-loop structures at low voltages but also reduces power consumption through energy reuse. Specific details are as follows:

[0012] A1. Cyclic gain enhancement technique

[0013] The transconductance capacitor amplifier designed and employed in this invention eliminates the limitation on transconductance amplifier gain caused by low-voltage environments through cyclic operation. Specific implementation details are as follows:

[0014] The amplifier's operating cycle is divided into odd-numbered and even-numbered amplification cycles. During the odd-numbered cycles, the input transconductance pair converts the residual voltage into current, discharging the capacitive load array and generating initial gain. Before entering the even-numbered cycles, digital logic controls the capacitor plate switching, using the principle of charge conservation to raise the common-mode level of the output node to near the supply voltage, thus reserving a voltage margin for the subsequent second discharge integration. Through four and a half cycles of reciprocating motion, a closed-loop equivalent gain of 16 times is achieved at a supply voltage of 0.65V.

[0015] The capacitor load array serves as the integrating load of the amplifier during the amplification stage, and directly as the sampling capacitor for the second-stage successive approximation ADC during the subsequent fine quantization stage. This highly multiplexed structure eliminates the dedicated sampling circuit required by traditional residual amplifiers. Digital logic, through a precise synchronous clock, ensures that the differential voltage signal accumulated in the previous cycle is not lost during the common-mode level reset process, achieving lossless energy transfer between cycles. Since the voltage providing charge in even-numbered cycles is the common-mode voltage (i.e., half the supply voltage), this structure improves energy efficiency by approximately 25% compared to a single large-current discharge.

[0016] A2. Tail resistance linearization

[0017] This invention solves the problems of limited swing and degraded linearity caused by constant current source bias at low voltages by introducing a linearization resistor at the tail of the transconductance pair. It is worth noting that although this part applies existing technology, the implementation objectives differ, as detailed below:

[0018] The input transconductance pair is biased in the weak inversion region, and its transconductance exhibits exponential characteristics due to the drain current. By precisely selecting the value of the tail resistor, the transconductance compression effect is compensated over a wide input swing range, significantly reducing the amplifier's third harmonic distortion.

[0019] It is worth noting that this invention is the first to apply this linearized resistor technology in the ultra-low voltage domain, achieving good linearity. Because the voltage drop generated by the tail resistor is much smaller than the minimum drain-source voltage of the transistor in the saturation region, even at a low supply voltage of 0.65V, all transistors remain in the strong saturation region, ensuring a linearity greater than 60dB even with a differential output swing of 40% of the supply voltage. Simultaneously, the resistor bias is suitable for fast startup operations, avoiding the transistor power-on time delay in traditional bias circuits, supporting femtosecond-level fast power-on response, and significantly reducing the system's static power consumption in the idle state.

[0020] B. Amplifier bias circuit

[0021] In specific implementation, the bias circuit of this invention employs a combined bias scheme of a constant transconductance bias source and a flying capacitor bias network. During operation, because the residual amplifier uses a tail resistor structure, its drain current cannot be directly mirrored by a traditional active current mirror. This invention utilizes a constant transconductance bias source to generate a precise reference voltage, and then transfers this voltage to the amplifier's input transconductor gate through a flying capacitor bias network using discrete charge transfer, thereby achieving precise locking of the quiescent operating point. Specific implementation details are as follows:

[0022] B1. Constant transconductance bias circuit

[0023] A constant transconductance bias source generates a reference voltage independent of PVT fluctuations. Specifically, a bias current generated through positive feedback makes the reciprocal of the input transistor's transconductance proportional to the resistance of an on-chip precision resistor. Since this bias circuit only needs to drive a small subsequent flying capacitor, it does not require strong driving capability itself, effectively reducing the system's static overhead. The generated bias voltage is sent to the subsequent flying capacitor sampling stage as a physical reference for the DC bias of the amplifier's input transistor gate.

[0024] B2. Flying Capacitor Bias Network

[0025] In practice, the flying capacitor bias network consists of a flying capacitor, a coupling capacitor, and multiple sets of controlled switches. Its specific implementation is as follows:

[0026] The flying capacitor bias network is driven by a two-phase non-overlapping clock. In the first stage (sampling stage), the flying capacitor is connected to a constant transconductance bias source to obtain a bias voltage. In the second stage (amplification stage), the flying capacitor is connected to a coupling capacitor connected to the amplifier gate for charge sharing. Through repeated charge sampling and transfer cycles, the voltage on the coupling capacitor gradually stabilizes, eventually establishing a stable DC bias potential at the amplifier's transconductance gate. This method effectively isolates the backlash interference from large-signal swings in the amplifier on the bias reference source, ensuring consistent gain under low-voltage conditions.

[0027] The transconductance capacitive residual amplification method based on cyclic operation proposed in this invention includes the following steps:

[0028] 1) Fabricate a transconductance capacitive residual amplifier, comprising three parts: a transconductance input stage, a tail resistor, and a controlled load array. Specifically, a pair of input metal-oxide-semiconductor transistors biased in the weak inversion region are fabricated, with their common source terminal connected to a tail resistor. The essential difference between this and existing residual amplifiers that use tail current sources is that replacing the tail transistors with a tail resistor not only releases the voltage margin under low voltage conditions but also compensates for the nonlinearity of the input stage under weak inversion bias. A set of symmetrical capacitive loads is designed, which is controlled by multiple switches. Unlike existing capacitor arrays that only serve as integration loads, this load serves as both the integration load of the amplifier and is multiplexed as the digital-to-analog converter capacitor for the subsequent quantization stage, thus enabling cyclic amplification and subsequent quantization to be completed collaboratively on the same capacitor array.

[0029] 2) Fabrication of digital logic. Integrating sequential circuitry to generate complementary odd-even control signals. Its fundamental difference from existing technologies lies in: instead of using a single integration to complete residual amplification, it performs cyclic amplification by alternating odd and even cycles; in odd cycles, the capacitor array performs transconductance integration to establish residual differential charge; in even cycles, instead of simply repeating the previous cycle or resetting the output node, it utilizes charge conservation to raise the common-mode level of the output node while retaining the differential charge formed in the odd cycles, creating voltage space for subsequent integration cycles and continuing gain accumulation.

[0030] 3) Fabrication of a constant transconductance bias circuit. A transconductance reference source with a self-biasing structure is constructed, and a stable bias voltage is generated through internal resistor compensation technology, which serves as a uniform reference for the system transconductance. This bias circuit provides a stable transconductance reference under PVT conditions for the transconductance input stage in cyclic operation, ensuring the stability of the cyclic gain.

[0031] 4) Fabrication of a flying capacitor bias network. A sampling circuit incorporating miniature flying capacitors and controlled sequential switches is designed, and a two-phase non-overlapping clock drive logic is configured to obtain the output level of the constant transconductance bias source through discrete sampling. Its fundamental difference from existing static bias allocation methods lies in the fact that the flying capacitors, under timing control, repeatedly share charge, gradually transferring and stabilizing the constant transconductance bias on the gate coupling capacitor of the residual amplifier input transistor. This allows the input transistor to continuously operate in a preset weak inversion region during cyclic amplification, thereby supporting high gain, linearization, and fast startup at low voltages.

[0032] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0033] This invention provides a transconductance amplifier based on cyclic operation, enabling residual voltage amplification. By employing a cyclic operation, the equivalent gain and output swing under low-voltage conditions are improved without increasing the number of cascaded stages, thereby alleviating the insufficient gain problem caused by the limited voltage margin of residual amplifiers in low-voltage ADCs. The amplifier adopts an open-loop transconductance capacitor structure and an odd-even cyclic amplification mechanism. In odd-numbered cycles, the capacitor load array discharges through the input transistor to achieve initial amplification of the residual signal; in even-numbered cycles, the output common-mode level is raised by the principle of charge conservation, providing voltage space for subsequent amplification and continuing to amplify the residual signal. Simultaneously, the utilization of the output common-mode level in even-numbered cycles also helps reduce system power consumption and improve energy efficiency.

[0034] This invention is applicable to the resistive linearization and fast startup of the aforementioned cyclic transconductance amplifier. This scheme replaces the traditional current source bias with a tail resistor, completely eliminating the occupation of voltage margin by the tail transistor, allowing the amplifier to support a larger output swing. By optimizing the tail resistor value, input stage nonlinearity can be compensated, thereby improving the amplifier's linearity. Furthermore, the resistive bias structure eliminates the need for the traditional current source setup process, thus shortening startup time and making it more suitable for intermittent operation and low-power applications with low duty cycles.

[0035] This invention provides a constant transconductance bias scheme based on a flying capacitor. Addressing the problem that the tail resistor current cannot be directly controlled, this invention utilizes a flying capacitor to transfer the precise voltage generated by the constant transconductance bias circuit to the gate of the input transistor. This method establishes a stable bias potential through a charge-sharing mechanism, and the bias circuit only needs to drive a tiny flying capacitor, significantly reducing the power consumption of the auxiliary circuitry. Attached Figure Description

[0036] Figure 1 The circuit structure diagram and timing diagram of the transconductance capacitor amplifier based on cyclic operation of the present invention are shown.

[0037] Figure 1 (a) is the circuit structure diagram, where M1 and M2 are differential input transistors operating in the weak inversion region; R tail This is the tail resistor connected between the input transistor source stage and ground; the enable switch is controlled by EN and is used to achieve rapid turn-on and turn-off of the amplifier; capacitor C P / C N This capacitor serves as the load for storing charge in the transconductance amplifier, and it is also reused as the sampling capacitor for the second-stage ADC; S1-S3 are control switches that control the amplifier's cyclic operation; in addition, the figure also includes the input signal V. IP / V IN Output signal V OP / V ON . Figure 1(b) is the working timing. The amplifier's operation is divided into a reset stage and an odd-even cycle discharge stage, where EN is the enable signal and S1-S3 are the corresponding switch control signals.

[0038] Figure 2 This is a schematic diagram of the time-domain waveform of the transconductance capacitor amplifier based on cyclic operation according to the present invention.

[0039] The horizontal axis represents the operating time of the transconductance capacitor amplifier, and the vertical axis represents the output signal V. OP / V ON The voltage value.

[0040] Figure 3 This is a circuit diagram of the constant transconductance bias circuit of the present invention.

[0041] Among them, transistors M1-M4 form the main body of the constant transconductance bias circuit, R bias The reciprocal of M1 determines the transconductance of the amplifier; M5-M7 are self-starting circuits to prevent the bias circuit from converging to zero current; M8 replicates the current, and M9 and M·R... tail It is the amplifier's replication circuit.

[0042] Figure 4 This is a circuit diagram of the flying capacitor bias network of the present invention.

[0043] Where C F It is a flying capacitor, C B It is a coupling capacitor; V RESP / V RESN It's the top-board signal of the CDAC, V IP / V IN It is the amplifier's input signal, V CM For common-mode voltage, V BIAS Φ is the output voltage of the constant transconductance bias circuit. A and Φ SD These represent the amplification phase and the sampling phase, respectively. Detailed Implementation

[0044] The present invention will be further illustrated below with reference to the accompanying drawings and embodiments, but the scope of the invention is not limited in any way.

[0045] This invention provides a method and apparatus (system) for large residual amplification of transconductance capacitive amplifiers based on cyclic operation, which achieves high gain in the low voltage domain through cyclic discharge of the capacitor.

[0046] The present invention provides a transconductance capacitive residual amplifier based on cyclic operation, comprising: a transconductance capacitive amplifier based on cyclic operation and an amplifier bias circuit. The transconductance capacitive amplifier amplifies the residual signal. The bias circuit includes a constant transconductance bias circuit and a flying capacitor bias circuit. The constant transconductance bias circuit generates a bias voltage, and the generated bias current has the following characteristics: ensuring the stability of the amplifier's transconductance under varying PVT conditions. The flying capacitor bias circuit acts as a bridge between the constant transconductance bias circuit and the amplifier, responsible for copying the bias voltage to the transconductance capacitive amplifier. Together, they amplify the residual signal.

[0047] The transconductance capacitive residual amplification system based on cyclic operation provided by this invention is applied to a low-voltage pipelined successive approximation ADC, such as... Figures 1-3 As shown, the application of this invention has the following significant advantages: The cyclic operation architecture enables the transconductance capacitor amplifier to achieve an open-loop gain of up to 16 times in low-voltage environments through multiple charge-sharing and pump-up cycles, effectively overcoming the gain deficiency problem caused by the limitation of power supply voltage in traditional amplifiers. Simultaneously, since the common-mode voltage is used as the power supply in even-numbered cycles during the loop, its power consumption is significantly reduced compared to traditional structures, improving the overall energy efficiency of the system. Combined with tail resistor linearization technology, this invention removes the current source voltage margin limitation while utilizing the compensation effect of the resistor on the weak inversion region nonlinearity of the transconductance transistor, achieving a third-order harmonic distortion better than -60dB. Furthermore, this structure supports fast power-up, perfectly adapts to duty cycle operating modes, and further reduces standby power consumption.

[0048] Transconductance capacitor amplifiers and their corresponding timing sequences are as follows: Figure 1 As shown, the transconductance capacitor amplifier based on cyclic operation of the present invention can be divided into the following working stages in its specific implementation: 1) Reset stage

[0049] During the reset phase, switches S1 and S2 are closed, and the capacitive load array C of the transconductance amplifier... P and C N The plates are reset to the power supply voltage V. DD and common-mode voltage V CM At the same time, the output terminal V of the amplification system OP With V ON Precharged to V DD This operation aims to completely eliminate the charge memory effect inside the circuit, laying the initial level foundation for subsequent cyclic amplification.

[0050] 2) Odd-even cyclic amplification stage

[0051] The residual amplification process consists of several odd-even cycles. Taking the achievement of a 16x gain as an example, the specific steps are as follows:

[0052] During odd-numbered cycles, only switch S2 is closed, and the transconductance stage utilizes the input transistor, which is in the weak inversion region, to convert the residual voltage into a differential current. Output voltage V OP and V ON From pre-charged V DD To V CM Directional discharge completes the initial voltage amplification (4 times differential gain) at the end of this cycle.

[0053] During even-numbered cycles, switches S1 and S3 are closed, and the internal nodes (nodes A and C) are quickly reset to V. DD Based on capacitor load array C P and C N The principle of charge conservation applies to the output terminal V. OP and V ON Pulled back to power supply voltage V DD Nearby. This action preserves the differential charge accumulated in odd-numbered cycles (i.e., amplified differential-mode information) while raising the output common-mode voltage, creating the necessary voltage space for amplification in even-numbered cycles.

[0054] By executing the above odd-even cycle twice, the system can achieve an open-loop gain of four times compared to a single discharge. Since the even-numbered cycles utilize the common-mode voltage for discharge, the overall energy efficiency of the system is significantly improved, saving approximately 25% of power consumption compared to the conventional structure.

[0055] Because the input transconductance pair is biased in the weak inversion region, its transconductance exhibits an exponential characteristic due to the drain current. By using tail resistor linearization technology and precisely selecting the tail resistor value, the transconductance compression effect is compensated over a wide input swing range, significantly reducing the amplifier's third-order harmonic distortion. Furthermore, since the voltage drop generated by the tail resistor is much smaller than the minimum drain-source voltage of the transistors in the saturation region, all transistors remain in the strong saturation region even at low supply voltages, ensuring linearity greater than 60dB at a differential output swing of 40% of the supply voltage. Simultaneously, resistor biasing avoids the transistor power-on time delay found in traditional biasing circuits, supporting femtosecond-level fast power-on response and greatly reducing the system's static power consumption in the idle state.

[0056] like Figure 2 As shown, the amplifier's time-domain waveform is illustrated using two "odd-even" cycles as an example. During the reset phase, the output node is pre-charged to a high common-mode level; in the first odd-numbered cycle, the input residual is converted into a discharge current via the transconductance stage, causing V... OP V ON As the output changes downwards, the common-mode output decreases, while the differential component V... OP -V ONThe circuit begins to build up; during the first even-numbered cycle, instead of simply clearing it to zero, it utilizes charge conservation to rapidly raise the output common-mode voltage while retaining the differential information formed in the previous cycle; then, in the next odd-numbered cycle, it continues to amplify the voltage at the new high common-mode starting point, making V... OP -V ON The increase continues; the same applies to the last even-numbered period. Therefore, the overall waveform shows that the single-ended output exhibits an alternating change of "decreasing - jumping up - decreasing again", while the differential output shows a trend of accumulating and increasing cycle by cycle.

[0057] Figure 3 and Figure 4 The constant transconductance bias circuit and the flying capacitor bias network are shown respectively.

[0058] The constant transconductance bias circuit provided by this invention aims to generate a stable current independent of PVT variations to maintain the consistency of the transconductance of the residual amplifier input transistor. For example... Figure 3 As shown, M1-M4 and R bias Together, they form the main part of the bias circuit. The bias current generated by positive feedback makes the reciprocal of the transconductance of the input transistor proportional to the resistance of an on-chip precision resistor. The self-starting circuit includes M5-M7. When the bias circuit current is small, M5 and M7 conduct, forcing M3 and M4 to conduct, ensuring that the bias circuit current does not converge to 0. M8 copies the current of M3 to the rightmost branch, and M9 and M·R... tail It is a replica circuit for the amplifier, generating the voltage V at the gate of the bias amplifier. BIAS .

[0059] The flying capacitor bias network is driven by a two-phase non-overlapping clock. For example... Figure 4 As shown, during the sampling phase Φ SD Flying capacitor C F Obtain bias voltage V by connecting a constant transconductance bias source BIAS During the amplification stage, the flying capacitor C F Coupling capacitor C connected to the amplifier gate B They are connected to share charge. Through repeated charge sampling and transfer cycles, C B The voltage across the amplifier gradually stabilizes, eventually reaching the voltage across the amplifier's transconductor gate V. IP / V IN A stable DC bias potential is established. This method effectively isolates the backlash interference from the large signal swing of the amplifier to the bias reference source, ensuring the consistency of gain under low voltage conditions.

[0060] This invention provides a transconductance capacitive residual amplifier system based on cyclic operation, which achieves high gain of the residual signal by performing multiple cyclic operations, and breaks through the gain bottleneck of open-loop amplifiers under low-voltage conditions.

[0061] This system is specifically implemented through a cyclic transconductance amplifier and a matching flying capacitor bias network. The cyclic amplification process is divided into phase reset and multiple odd and even operating cycles: in odd cycles, the transconductance current discharges through the capacitive load array to generate initial gain; in even cycles, by resetting the voltage of the bottom plate of the capacitive load array, the common-mode signal is raised to a high level using the principle of charge conservation, thus preserving signal information while freeing up space for the next round of integration. This cycle-based accumulation method allows the system to achieve a 16x open-loop gain in only two cycles, and because the even cycles utilize common-mode voltage discharge, it achieves approximately 25% energy savings compared to traditional architectures. This invention further designs a tail resistor linearization scheme to address the problem of current sources occupying voltage margins under low voltage conditions. The bias network locks the operating point of the input transistor through a constant transconductance bias circuit and uses flying capacitors as charge transfer media to periodically copy the bias reference to the coupling capacitor at the amplifier input. This method effectively shields back-kick noise generated during the dynamic amplification process by isolating and ensures consistency under transconductance PVT fluctuations, thereby significantly improving the overall linearity and robustness of the pipelined data converter.

[0062] Compared to traditional closed-loop or open-loop residual amplifiers, this invention utilizes a cyclic dynamic structure to resolve the fundamental contradiction between gain and voltage swing. Without the need for complex gain enhancement techniques, it constructs a signal processing unit that combines high energy efficiency and high linearity, providing core support for high-resolution data converters operating in extremely low voltage domains.

[0063] It should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.

Claims

1. A transconductance capacitive residual amplification method based on cyclic operation, characterized in that, The method employs an odd-even cyclic discharge technique, alternating between odd and even periods for cyclic discharge and amplification, achieving an improved equivalent gain at low voltage. Simultaneously, even periods reduce power consumption by lowering the supply voltage. Furthermore, a tail resistor linearization technique is used to suppress transconductance changes during cyclic amplification. The method includes the following steps: 1) Fabricate a transconductance capacitive residual amplifier, comprising a transconductance input stage, a tail resistor, and a controlled load array; including: 11) Fabricate a pair of input metal-oxide-semiconductor transistors biased in the weak inversion region, with their source common terminal connected to the tail resistor; 12) Design a set of symmetrical capacitive loads, which serve as both the integration load of the amplifier and the digital-to-analog converter capacitor for the subsequent quantization stage; the cyclic amplification and the subsequent quantization are completed collaboratively on the same capacitor array; 2) Fabricate digital logic; integrate sequential circuitry to generate complementary odd-even control signals; perform cyclic amplification by alternating odd and even cycles; In odd-numbered cycles, the capacitor array performs transconductance integration to establish residual differential charge; in even-numbered cycles, charge conservation is used to raise the common-mode level of the output node, while retaining the differential charge formed in the odd-numbered cycles, creating voltage space for the integration cycle and continuing to achieve gain accumulation. 3) Fabrication of a constant transconductance bias circuit: Construct a transconductance reference source containing a self-biasing structure, and generate a stable bias voltage through internal resistance compensation technology, which is used as a consistency reference for the system transconductance; 4) Fabrication of flying capacitor bias network: Design a sampling circuit including miniature flying capacitors and controlled sequential switches, and configure two-phase non-overlapping clock drive logic to obtain the output level of constant transconductance bias source in a discrete sampling manner; The flying capacitor, under timing control, performs repeated charge sharing, gradually transferring and stabilizing the constant transconductance bias on the gate coupling capacitor of the residual amplifier input transistor, so that the input transistor continues to operate in the weak inversion region during the cyclic amplification process.

2. The transconductance capacitive residual amplification method based on cyclic operation as described in claim 1, characterized in that, The capacitive load is controlled by multiple switches.

3. The transconductance capacitive residual amplification method based on cyclic operation as described in claim 1, characterized in that, The transconductance capacitive residual amplifier amplifies the residual signal by employing cyclic gain enhancement technology; the operating cycle is divided into odd-numbered amplification cycles and even-numbered amplification cycles; the gain is achieved through cyclic repetition.

4. The transconductance capacitive residual amplification method based on cyclic operation as described in claim 3, characterized in that, During the amplifier's operating cycle: In odd-numbered cycles, the input transconductance pair converts the residual voltage into current, discharging the load capacitor array and generating initial gain; before entering even-numbered cycles, digital logic controls the switching of capacitor plates, raising the common-mode level of the output node to near the power supply voltage, reserving voltage margin for the second discharge integration.

5. A transconductance capacitive residual amplification device based on cyclic operation, characterized in that, include: A transconductance capacitor amplifier and amplifier bias circuit based on cyclic operation; wherein... The cyclic transconductance capacitor amplifier amplifies the residual signal using cyclic gain enhancement technology. It comprises an input transconductance pair, a linearized tail resistor, a capacitive load array, and digital logic. The amplifier's operating cycle is divided into odd and even amplification cycles, achieving gain through cyclic repetition. The capacitive load array acts as the amplifier's integrating load during the amplification phase and directly serves as the sampling capacitor for the second-stage successive approximation ADC during the subsequent fine quantization phase. The digital logic uses a precise synchronous clock, ensuring that the differential voltage signal accumulated in the previous cycle is not lost during the common-mode level reset process, allowing for lossless energy transfer during the cycle. A linearized resistor is introduced at the tail of the transistor; by precisely selecting the resistor value, the transconductance compression effect is compensated within a wide input swing range. The amplifier bias circuit includes a constant transconductance bias circuit and a flying capacitor bias circuit; the constant transconductance bias circuit generates a bias current, which ensures the stability of the amplifier's transconductance under conditions of process, voltage, and temperature PVT variations; the flying capacitor bias circuit copies the bias voltage to the transconductance capacitor amplifier.

6. The transcapacitive residual amplification device based on cyclic operation as described in claim 5, characterized in that, When the cyclic transconductance capacitor amplifier is in operation, it receives the residual voltage generated by the first-stage ADC and achieves high-gain amplification at extremely low power supply voltage through multiple cycles of charge integration and reset process.

7. The transcapacitive residual amplification device based on cyclic operation as described in claim 5, characterized in that, During the amplifier's operating cycle: In odd-numbered cycles, the input transconductance pair converts the residual voltage into current, discharging the load capacitor array and generating initial gain; before entering even-numbered cycles, digital logic controls the switching of capacitor plates, raising the common-mode level of the output node to near the power supply voltage, reserving voltage margin for the second discharge integration.

8. The transcapacitive residual amplifier based on cyclic operation as described in claim 5, characterized in that, The amplifier bias circuit adopts a combined bias scheme of constant transconductance bias source and flying capacitor bias network. During operation, the constant transconductance bias source generates a precise reference voltage, and the voltage is transferred to the gate of the amplifier's input transconductor through the flying capacitor bias network in a discrete charge transfer manner, thereby achieving precise locking of the static operating point.

9. The transconductance capacitive residual amplification device based on cyclic operation as described in claim 8, characterized in that, A constant transconductance bias source is used to generate a reference voltage that is independent of PVT fluctuations. The bias current generated by positive feedback makes the reciprocal of the transconductance of the input transistor proportional to the resistance of the on-chip precision resistor. The generated bias voltage is sent to the flying capacitor sampling stage as a physical reference for the DC bias of the amplifier input transistor gate.

10. The transconductance capacitive residual amplification device based on cyclic operation as described in claim 9, characterized in that, The flying capacitor bias network consists of a flying capacitor, a coupling capacitor, and multiple sets of controlled switches. The flying capacitor bias network is driven by a two-phase non-overlapping clock. In the first stage, i.e. the sampling stage, the flying capacitor is connected to a constant transconductance bias source to obtain the bias voltage. In the second stage, i.e. the amplification stage, the flying capacitor is connected to the coupling capacitor connected to the amplifier gate to share charge.

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