Clock generation device and integrated circuit chip

Abstract

The present disclosure relates to a clock generating device and an integrated circuit chip. The clock generating device can include a phase-locked loop module including a plurality of phase-locked loop modules, and a frequency multiplication module electrically connected to the plurality of phase-locked loop modules and configured to generate a target clock signal according to a plurality of initial clock signals received.

Description

Technical Field

[0001] This disclosure relates to the field of electronic circuit technology, and more specifically, to a clock generator and an integrated circuit chip. Background Technology

[0002] In many applications, a clock generator is required to provide a clock signal to ensure the normal operation of the circuit. To reduce the power consumption of the clock generator and the integrated circuit chip containing it, a simple RC oscillator can be used instead of a phase-locked loop (PLL) with higher power consumption to generate the desired clock signal. However, due to process variations, even after adjustments, the clock signal generated by the RC oscillator may still have a fluctuation range of 1%, which adversely affects the application. Therefore, there is a need to improve the clock generator. Summary of the Invention

[0003] One of the purposes of this disclosure is to provide a clock generator and an integrated circuit chip.

[0004] According to a first aspect of this disclosure, a clock generating apparatus is provided, comprising:

[0005] A phase-locked loop (PLL) module, comprising a multi-phase voltage-controlled oscillator (VCO), wherein the VCO is configured to output a plurality of initial clock signals, each of the plurality of initial clock signals having a different initial phase and each initial clock signal having the same initial frequency; and

[0006] A frequency multiplier module is electrically connected to the multi-phase voltage-controlled oscillator and is configured to generate a target clock signal based on the received plurality of initial clock signals, wherein the target frequency of the target clock signal is a preset multiple of the initial frequency.

[0007] In some embodiments, the multi-phase voltage-controlled oscillator includes:

[0008] Multiple phase shifting units are provided, wherein the output of the previous phase shifting unit is electrically connected to the corresponding input of the next phase shifting unit, and the output of the last phase shifting unit is electrically connected to the corresponding input of the first phase shifting unit. Each phase shifting unit is configured to shift the initial clock signal input to the phase shifting unit by a first preset phase difference and output the phase-shifted initial clock signal to the frequency multiplier module.

[0009] In some embodiments, the phase-shifting unit includes a differential amplifier.

[0010] In some embodiments, the multi-phase voltage-controlled oscillator further includes:

[0011] A current conversion unit is electrically connected to the plurality of phase-shifting units, and the current conversion unit is configured to generate a current signal for driving the plurality of phase-shifting units based on a received first voltage signal.

[0012] In some embodiments, the phase-locked loop module further includes:

[0013] A phase detector configured to generate a second voltage signal based on a received reference clock signal and a frequency-divided clock signal;

[0014] A charge pump electrically connected to the phase detector, and the charge pump being configured to generate a third voltage signal based on the received second voltage signal;

[0015] A filter electrically connected between the charge pump and the multiphase voltage-controlled oscillator, and configured to filter the third voltage signal to generate the first voltage signal for the multiphase voltage-controlled oscillator; and

[0016] A frequency divider is electrically connected between the multi-phase voltage-controlled oscillator and the phase detector, and the frequency divider is configured to divide at least one initial clock signal to generate the divided clock signal.

[0017] In some embodiments, the frequency divider includes a configurable frequency divider having an adjustable division ratio.

[0018] In some embodiments, the multi-phase voltage-controlled oscillator is configured to output N initial clock signals, wherein a first preset phase difference between the two initial clock signals having the closest initial phase is 2π / N, and the target frequency is N times the initial frequency, where N = 2π / N. m And m is a positive integer.

[0019] In some embodiments, the frequency multiplier module includes m-stage frequency multiplier components. The number of frequency multiplier units in the preceding stage frequency multiplier component is twice the number of frequency multiplier units in the following stage frequency multiplier component. The last stage frequency multiplier component has one frequency multiplier unit, and one frequency multiplier unit in the following stage frequency multiplier component is electrically connected to two corresponding frequency multiplier units in the preceding stage frequency multiplier component to generate a corresponding following stage clock signal based on two preceding stage clock signals received by the frequency multiplier unit in the following stage frequency multiplier component. The frequency of the following stage clock signal is twice the frequency of the preceding stage clock signal.

[0020] In some embodiments, the double frequency unit includes:

[0021] Two-input XOR gates: The two inputs of one of the two-input XOR gates in the subsequent doubler stage are electrically connected to the outputs of the corresponding two-input XOR gates in the preceding doubler stage; or

[0022] Two-input XOR gates: The two inputs of one of the two-input XOR gates in the subsequent doubler stage are electrically connected to the outputs of the corresponding two-input XOR gates in the preceding doubler stage.

[0023] In some embodiments, the double frequency unit includes at least one of the following:

[0024] A four-input XOR gate, wherein the four-input XOR gate is configured to generate a fifth clock signal based on a received first clock signal, a second clock signal inverted from the first clock signal, a third clock signal, and a fourth clock signal inverted from the third clock signal, wherein the first, second, third, and fourth clock signals have a first frequency equal to each other, and the fifth clock signal has a second frequency, which is twice the first frequency; and

[0025] A four-input XOR gate is configured to generate a tenth clock signal based on a received sixth clock signal, a seventh clock signal that is inverted by the sixth clock signal, an eighth clock signal, and a ninth clock signal that is inverted by the eighth clock signal. The sixth, seventh, eighth, and ninth clock signals have a third frequency that is equal to each other, and the tenth clock signal has a fourth frequency that is twice the third frequency.

[0026] In some embodiments, the double frequency unit further includes:

[0027] An inverter electrically connected to the output of at least one of the four-input XOR gate and the four-input XOR gate.

[0028] In some embodiments, the frequency multiplier module further includes a switching unit disposed between two adjacent stages of the frequency multiplier components, and the switching unit is configured to control the number of stages of the frequency multiplier components operating in the frequency multiplier module so that the preset multiplier can be adjusted.

[0029] According to a second aspect of this disclosure, an integrated circuit chip is provided, including the clock generating device described above.

[0030] Other features and advantages of this disclosure will become clearer from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0031] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0032] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0033] Figure 1 A circuit diagram of a clock generating apparatus according to an exemplary embodiment of the present disclosure is shown;

[0034] Figure 2 A circuit diagram of a multi-phase voltage-controlled oscillator in a clock generating apparatus according to a specific embodiment of the present disclosure is shown;

[0035] Figure 3 A circuit diagram of a frequency multiplier module in a clock generator according to a specific embodiment of the present disclosure is shown;

[0036] Figure 4 A circuit diagram of a frequency multiplier module in a clock generator according to a specific example of the present disclosure is shown;

[0037] Figure 5 It shows Figure 4 A timing diagram of the clock signals in the frequency multiplier module;

[0038] Figure 6 A circuit diagram of a frequency multiplier module in a clock generator according to another specific example of the present disclosure is shown;

[0039] Figure 7 A circuit diagram of a frequency multiplier module in a clock generator according to yet another specific example of the present disclosure is shown;

[0040] Figure 8 It shows Figure 7 A circuit diagram of a four-input XNOR gate in a frequency multiplier module;

[0041] Figure 9 It shows Figure 7 A circuit diagram of a four-input XOR gate in a frequency multiplier module;

[0042] Figure 10 A circuit diagram of a frequency multiplier module in a clock generator according to yet another specific example of the present disclosure is shown;

[0043] Figure 11 A circuit diagram of a frequency multiplier module in a clock generator according to another specific embodiment of the present disclosure is shown;

[0044] Figure 12 A block diagram of an integrated circuit chip according to an exemplary embodiment of the present disclosure is shown.

[0045] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0046] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, the disclosed invention is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components. Detailed Implementation

[0047] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0048] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the scope of this disclosure or its application or use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in this disclosure. However, those skilled in the art will understand that they merely illustrate exemplary ways that can be used to implement this disclosure, and not exhaustive ways. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components.

[0049] In addition, techniques, methods and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods and equipment should be considered part of the specification.

[0050] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0051] To provide an accurate clock signal while reducing circuit power consumption, this disclosure provides a clock generating device. In an exemplary embodiment of this disclosure, as... Figure 1As shown, the clock generating device 10 may include a phase-locked loop (PLL) module 100 and a frequency multiplier module 200. The PLL module 100 may include a multi-phase voltage-controlled oscillator (VCO) 110, which can be configured to output multiple initial clock signals. The frequency multiplier module 200 may be electrically connected to the multi-phase VCO 110 and can be configured to generate a target clock signal based on the received multiple initial clock signals. Each of the multiple initial clock signals may have a different initial phase and the same initial frequency, so that the frequency multiplier module 200 can generate a frequency-multiplied target clock signal based on the multiple initial clock signals; that is, the target frequency of the target clock signal can be a preset multiple of the initial frequencies of the initial clock signals. In an exemplary embodiment of this disclosure, the multi-phase VCO 110 and the frequency multiplier module 200 can be configured according to a desired preset multiple to generate multiple initial clock signals with appropriate phases and frequencies, thereby generating the desired target clock signal; no limitation is imposed herein.

[0052] In some embodiments, such as Figure 2 As shown, the multi-phase voltage-controlled oscillator 110 may include multiple phase-shifting units 111. The output of a preceding phase-shifting unit 111 can be electrically connected to the corresponding input of a subsequent phase-shifting unit 111, and the output of the last phase-shifting unit 111 can be electrically connected to the corresponding input of the first phase-shifting unit 111. In other words, the multiple phase-shifting units 111 can be arranged in a ring configuration, for example, forming a ring oscillator. Furthermore, each phase-shifting unit 111 may have a tap at its output to output a corresponding initial clock signal provided by that phase-shifting unit 111. Here, each phase-shifting unit 111 can be configured to shift the initial clock signal input to it by a first preset phase difference and output the phase-shifted initial clock signal to the frequency multiplier module 200.

[0053] For example, in Figure 2In the specific example shown, the first-stage phase-shifting unit 111 can receive a pair of initial clock signals ph0 and ph0b that are out of phase with each other, and generate a pair of phase-shifted initial clock signals ph1 and ph1b. Similarly, the second-stage phase-shifting unit 111 can receive a pair of initial clock signals ph1 and ph1b that are out of phase with each other from the first-stage phase-shifting unit 111, and generate a pair of phase-shifted initial clock signals ph2 and ph2b; the third-stage phase-shifting unit 111 can receive a pair of initial clock signals ph2 and ph2b that are out of phase with each other from the second-stage phase-shifting unit 111, and generate a pair of phase-shifted initial clock signals ph3 and ph3b; the fourth-stage phase-shifting unit 111 can receive a pair of initial clock signals ph3 and ph3b that are out of phase with each other from the third-stage phase-shifting unit 111, and generate a pair of phase-shifted initial clock signals ph0 and ph0b, and the initial clock signals ph0 and ph0b will be returned to the first-stage phase-shifting unit 111. Figure 2 Each phase-shifting unit 111 shown can shift the initial clock signal input thereto by a phase of π / 2. Furthermore, the phase-shifting units 111 can be configured in various ways, without limitation here. In a specific example, such as... Figure 2 As shown, the phase shifting unit 111 may include a differential amplifier. As described above, the two input terminals of the differential amplifier can be configured to receive a pair of initial clock signals that are out of phase with each other, and the two output terminals of the differential amplifier can be configured to output a pair of phase-shifted initial clock signals that are out of phase with each other. The amount of phase shifting of the clock signals by the differential amplifier can be set as needed.

[0054] Furthermore, in some embodiments, such as Figure 2 As shown, the multi-phase voltage-controlled oscillator 110 may further include a current conversion unit 112, which can be electrically connected to multiple phase-shifting units 111. The current conversion unit 112 can be configured to generate a current signal for driving the multiple phase-shifting units 111 based on a received first voltage signal u1. Generally, the larger the voltage corresponding to the first voltage signal u1, the larger the current converted by the current conversion unit 112, and correspondingly, the higher the oscillation frequency of the multi-phase voltage-controlled oscillator 110. Therefore, the oscillation frequency (or the initial frequency of the initial clock signal) of the multi-phase voltage-controlled oscillator 110 can be adjusted by the first voltage signal u1 to obtain the desired target frequency. In a specific example, the current conversion unit 112 may include an amplifier, a transistor or field-effect transistor, and resistors, which can be configured according to... Figure 2 The phase-shifting units 111 are interconnected as shown to convert the first voltage signal u1 into a current signal provided to each phase-shifting unit 111. However, it is understood that other arrangements of the current conversion units 112 may also be used, and no limitation is made here.

[0055] In some embodiments, such as Figure 1 As shown, the phase-locked loop module 100 may also include a phase detector 120, a charge pump 130, a filter 140, and a frequency divider 150.

[0056] The phase detector 120 can be configured to generate a second voltage signal u2 based on the received reference clock signal (CLK_R) and the divided clock signal (CLK_D). Specifically, the phase detector 120 can be configured to compare the phase difference between the reference clock signal (CLK_R) and the divided clock signal (CLK_D) to generate a second voltage signal u2 corresponding to the phase difference.

[0057] The charge pump 130 can be electrically connected to the phase detector 120, and the charge pump 130 can be configured to generate a third voltage signal u3 based on the received second voltage signal u2.

[0058] Filter 140 may be electrically connected between charge pump 130 and multiphase voltage-controlled oscillator 110, for example, it may be a low-pass filter, and filter 140 may be configured to filter the third voltage signal u3 to generate a first voltage signal u1 for multiphase voltage-controlled oscillator 110. In a specific example, such as Figure 1 As shown, filter 140 may include resistors and transistors or field-effect transistors. However, it is understood that filter 140 may be configured in other ways, and there are no limitations on this.

[0059] Frequency divider 150 can be electrically connected between multi-phase voltage-controlled oscillator 110 and phase detector 120 to form a feedback control loop of phase-locked loop module 100, and frequency divider 150 can be configured to divide at least one initial clock signal (CLK_I) to generate a divided clock signal (CLK_D), for example, the divided frequency f of the divided clock signal (CLK_D). D It can satisfy f D =f I / η, where f I η is the initial frequency of a corresponding initial clock signal (CLK_I) input to the frequency divider 150, and η is the division ratio. In a specific example, the frequency divider 150 may include a configurable frequency divider with an adjustable division ratio for frequency division as needed. For example, if a configurable frequency divider with 8 control bits is used, frequency division in the range of 2 to 256 can be achieved.

[0060] according to Figure 1 It can be seen that in the phase-locked loop module 100, the frequency and phase of the internal oscillation signal can be controlled by the externally input reference clock signal (CLK_R), thereby realizing the initial frequency f of the generated initial clock signal (CLK_I). IThe reference frequency f of the input reference clock signal (CLK_R) R Automatic tracking, combined with the frequency multiplier module 200, can obtain the desired target clock signal (CLK_T). Here, the target frequency f of the target clock signal (CLK_T) is... T It can be represented as f T =f R *η*N, where η is the division ratio of the frequency divider 150 and N is a preset multiplier determined by the frequency multiplier module 200. Therefore, the frequency divider 150 and the frequency multiplier module 200 can be configured according to the desired target frequency. For example, with N=4, if a target clock signal of 100MHz is required, the initial clock signal frequency in the multiphase voltage-controlled oscillator only needs to be 25MHz, which helps to significantly reduce the power consumption of the voltage-controlled oscillator.

[0061] In some embodiments, the multi-phase voltage-controlled oscillator 110 can be configured to output N initial clock signals. For example, the multi-phase voltage-controlled oscillator 110 can have N phase-shifting units 111, each of which can output a corresponding initial clock signal. Among the multiple initial clock signals, the first preset phase difference between the two initial clock signals with the closest initial phase can be 2π / N, and the target frequency of the target clock signal can be N times the initial frequency of the initial clock signals, where N satisfies N=2. m And m is a positive integer. That is to say, using the clock generating device of this disclosure, a target clock signal that is two times, four times, or eight times the oscillation frequency (or the initial frequency of the initial clock signal) relative to the phase-locked loop module 100 can be generated. On the one hand, the phase-locked loop can provide an accurate clock signal; on the other hand, since the frequency multiplier module 200 is used for frequency multiplication, the multi-phase voltage-controlled oscillator 110 in the phase-locked loop module 100 can oscillate at a lower frequency, thereby effectively reducing the power consumption of the multi-phase voltage-controlled oscillator 110, and thus reducing the power consumption of the entire clock generating device 10.

[0062] Furthermore, in order to generate a target clock signal with an frequency multiple of N, such as Figure 3As shown, the frequency multiplier module 200 may include m-stage double frequency multiplier components 210. Specifically, when N=2, the frequency multiplier module 200 may include only one stage of double frequency multiplier components 210, and this double frequency multiplier component 210 may include only one double frequency multiplier unit 211, which can generate a target clock signal with double frequency multiplied according to a pair of input initial clock signals. Furthermore, when N>2, the frequency multiplier module 200 may include at least two stages of double frequency multiplier components 210. In this design, the number of frequency doubling units 211 in the preceding stage 210 can be twice the number of frequency doubling units 211 in the following stage 210. The final stage 210 can have one frequency doubling unit 211, and one frequency doubling unit 211 in the following stage 210 can be electrically connected to two corresponding frequency doubling units 211 in the preceding stage 210 to generate a corresponding following stage clock signal based on the two preceding stage clock signals received by the frequency doubling unit 211 in the following stage 210. The frequency of the following stage clock signal can be twice the frequency of the preceding stage clock signal. Figure 3 In the specific example shown, a three-stage doubler component 210 is illustrated. However, it is understood that the doubler module 200 may include doubler components 210 with more or fewer stages, and this is not a limitation. Furthermore, in the following text, several configuration methods of the doubler module 200 will be described in detail using the case of N=4 as an example. However, those skilled in the art can configure the doubler module with N taking other values ​​based on the description herein, which will not be elaborated upon here.

[0063] In a specific example, such as Figure 4 and Figure 5 As shown, the frequency multiplier unit 211 may include a two-input XOR gate 212. The two inputs of one of the two-input XOR gates 212 in the subsequent frequency multiplier component 210 can be electrically connected to the outputs of the corresponding two two-input XOR gates 212 in the preceding frequency multiplier component 210. Furthermore, the second preset phase difference between the two initial clock signals received by each frequency multiplier unit 211 in the initial frequency multiplier component 210 can be π. Thus, Figure 4Each of the two XOR gates 212 in the first-stage frequency doubling component 210 shown can generate a doubled clock signal (i.e., clock signal ckd and clock signal ckq) based on a pair of initial clock signals with a preset phase difference of π (i.e., a pair of initial clock signals ph0b and ph2, and a pair of initial clock signals ph1b and ph3b). The phase difference between the clock signals ckd and ckq generated by the first-stage frequency doubling component 210 is π / 2. Further, the second-stage frequency doubling component 210 can generate a target clock signal CLK_T that is four times the frequency of the initial clock signal based on a pair of clock signals with a phase difference of π / 2.

[0064] In another specific example, such as Figure 6 As shown, the frequency multiplier unit 211 may include a two-input XOR gate 213. The two inputs of one of the two-input XOR gates 213 in the subsequent frequency multiplier component 210 can be electrically connected to the outputs of the corresponding two two-input XOR gates 213 in the preceding frequency multiplier component 210. Similarly, the second preset phase difference between the two initial clock signals received by each frequency multiplier unit 211 in the initial frequency multiplier component 210 can be π. Thus, Figure 6 Each of the two XOR gates 213 in the first-stage frequency doubling component 210 shown can generate a clock signal that is twice the frequency based on a pair of initial clock signals with a preset phase difference of π. That is, the first-stage frequency doubling component 210 can generate two clock signals with a phase difference of π / 2. Further, the second-stage frequency doubling component 210 can generate a target clock signal that is four times the frequency of the initial clock signal based on a pair of clock signals with a phase difference of π / 2.

[0065] In some specific examples, such as Figure 7 and Figure 10As shown, the frequency doubling unit 211 may include at least one of a four-input XOR gate 214 and a four-input XOR gate 215. The four-input XOR gate 214 may be configured to generate a fifth clock signal based on a received first clock signal, a second clock signal inverted from the first clock signal, a third clock signal, and a fourth clock signal inverted from the third clock signal. Here, the first, second, third, and fourth clock signals may have a first frequency equal to each other, and the fifth clock signal has a second frequency, which is twice the first frequency. Similarly, the four-input XOR gate 215 may be configured to generate a tenth clock signal based on a received sixth clock signal, a seventh clock signal inverted from the sixth clock signal, an eighth clock signal, and a ninth clock signal inverted from the eighth clock signal. Here, the sixth, seventh, eighth, and ninth clock signals have a third frequency equal to each other, and the tenth clock signal has a fourth frequency, which is twice the third frequency. Figure 8 and Figure 9 Specific circuit structures for a four-input XOR gate and a four-input XNOR gate are shown. In this specific example, the same transistors or field-effect transistors and their arrangement can be used to implement the four-input XOR gate and the four-input XNOR gate, and the logic of the gate circuit can be changed by changing the signals input to the field-effect transistors (e.g., signal a, signal na (inverted from signal a), signal b, and signal nb (inverted from signal b)). However, it is understood that other methods can be used to construct four-input XNOR gates or four-input XOR gates, and no limitation is made here.

[0066] Furthermore, in some specific examples, such as Figure 7 As shown, the doubler unit 211 may further include an inverter 216, which may be electrically connected to the output of at least one of the four-input XOR gate 214 and the four-input XOR gate 215. It is understood that the four-input XOR gate 214 and the inverter 216 connected to its output can be equivalent to a four-input XOR gate; similarly, the four-input XOR gate 215 and the inverter 216 connected to its output can be equivalent to a four-input XOR gate.

[0067] exist Figure 7In the specific example shown, to obtain a target clock signal that is four times the frequency of the initial clock signals (ph0, ph1, ph2, ph3 or signals ph0b, ph1b, ph2b, ph3b that are inverted relative to ph0, ph1, ph2, ph3), the first-stage frequency doubling component 210 may include two four-input XOR gates 214, two four-input XOR gates 215, and an inverter 216 connected to the outputs of each of the four-input XOR gates 214 and the four-input XOR gates 215; the second-stage frequency doubling component 210 may include a four-input XOR gate 215 and an inverter 216 connected to the output of the four-input XOR gate 215. (See reference...) Figure 5 The timing diagram shows that the first four-input XOR gate 214 can generate a clock signal ckd based on the initial clock signal ph0, the signal ph0b inverted from ph0, the signal ph2 with a preset phase difference of π between ph0 and ph2, and the signal ph2b inverted from ph2. The first four-input XOR gate 215 can generate a clock signal ckdb inverted from ckd based on the aforementioned initial clock signals ph0, ph0b, ph2, and ph2b. Similarly, the second four-input XOR gate 215 can generate a clock signal ckq based on the initial clock signal ph1, the signal ph1b inverted from ph1, the signal ph3 with a preset phase difference of π between ph1 and ph3, and the signal ph3b inverted from ph3. The second four-input XOR gate 214 can generate a clock signal ckqb inverted from ckq based on the aforementioned initial clock signals ph1 (or signal na), ph1b (or signal a), ph3 (or signal b), and ph3b (or signal nb). Furthermore, the second-stage frequency doubling component 210 can generate a target clock signal CLK_T that is quadrupled in frequency based on the clock signals ckd, ckdb, ckq and ckqb.

[0068] As can be seen, compared to using two-input XOR gates or two-input XOR gates, using four-input XOR gates or four-input XOR gates requires inverting the two clock signals originally input to the two-input double frequency multiplier unit (two-input XOR gate or two-input XOR gate) to form a total of four clock signals to be input to the four-input double frequency multiplier unit (four-input XOR gate or four-input XOR gate), thereby achieving the desired frequency multiplication. By using four-input XOR gate 214 and / or four-input XOR gate 215 to multiply the clock signal, the adverse effects caused by the deviation between the phase difference between the multiple clock signals to be multiplied and the desired phase difference (or preset phase difference) can be effectively reduced or even eliminated. This avoids significant degradation of clock frequency and jitter, helps to generate accurate and stable target clock signals, and can meet the needs of most clock application scenarios.

[0069] In some embodiments, such as Figure 11As shown, the frequency multiplier module 200 may further include a switching unit 220, which can be disposed between two adjacent stages of the frequency multiplier components 210. The switching unit 220 can be configured to control the number of stages of the frequency multiplier components 210 operating in the frequency multiplier module 200, so that a preset multiplier can be adjusted. For example, in... Figure 11 In this configuration, if both switch units 220 are in the off state, the frequency multiplier module 200 can double the initial clock signal; if the left switch unit 220 is in the off state and the right switch unit 220 is in the on state, the frequency multiplier module 200 can quadruple the initial clock signal; and if both switch units 220 are in the on state, the frequency multiplier module 200 can quadruple the initial clock signal. The desired initial clock signal can be input or the desired target clock signal can be output by setting taps at the input or output terminals of the corresponding frequency multiplier component 210. Furthermore, in some embodiments, the switching units 220 can be automatically controlled to open or close using control signals, thereby enabling flexible and convenient adjustment of the target frequency of the target clock signal.

[0070] According to another aspect of this disclosure, an integrated circuit chip 20 is also provided. Figure 12 A block diagram of an integrated circuit chip according to an exemplary embodiment of the present disclosure is shown. The integrated circuit chip 20 may include a clock generator 10 as described above. The integrated circuit chip 20 may also include various digital circuit units and / or analog circuit units, etc., to achieve the desired function under the action of the clock generator 10.

[0071] This disclosure presents a clock generator and an integrated circuit chip incorporating such a clock generator. In the clock generator, a multi-phase voltage-controlled oscillator in a phase-locked loop module generates multiple initial clock signals that are shifted by a certain phase relative to each other. A frequency multiplier module generates a frequency-multiplied target clock signal based on these initial clock signals. This allows for the generation of a high-frequency target clock signal while maintaining low-frequency oscillation of the voltage-controlled oscillator, thereby reducing circuit power consumption while obtaining an accurate clock signal, showing great promise in ultra-low-power applications. The clock generator of this disclosure can be fabricated using deep submicron technology. Combined with other small-scale digital circuits based on deep submicron technology in the integrated circuit chip, it can still achieve very low power consumption. For example, with a target clock signal of around 200MHz, it can achieve a specification of 100μA (8nm process). Such a clock generator can replace most applications of ring oscillators or RC oscillators. Furthermore, by incorporating a four-input frequency multiplier circuit, the clock generator of this disclosure can significantly reduce the impact of frequency multiplication jitter and phase difference caused by process deviations and fluctuations, improving clock stability and reliability.

[0072] The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “upper,” “lower,” “high,” “lower,” etc., used in the specification and claims, if present, are for descriptive purposes and not necessarily for describing unchanging relative positions. It should be understood that such terms are interchangeable where appropriate, enabling embodiments of this disclosure described herein to operate, for example, in orientations different from those shown or otherwise described herein. For example, when the device in the drawings is reversed, a feature previously described as “above” other features may now be described as “below” other features. The device may also be oriented in other ways (rotated 90 degrees or in other orientations), in which case the relative spatial relationships will be interpreted accordingly.

[0073] In the specification and claims, when an element is described as being "on top of," "attached to," "connected to," "coupled to," or "in contact with" another element, the element may be directly located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with the other element, or one or more intermediate elements may be present. Conversely, when an element is described as being "directly" located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with another element, no intermediate elements are present. In the specification and claims, when a feature is arranged "adjacent" to another feature, it may mean that a feature has a portion overlapping with the adjacent feature or a portion located above or below the adjacent feature.

[0074] As used herein, the term “exemplary” means “serving as an example, instance, or illustration” and not as a “model” to be precisely copied. Any implementation described herein by example is not necessarily to be construed as preferred or advantageous over other implementations. Moreover, this disclosure is not limited to any theory expressed or implied as given in the field of art, background art, summary of invention, or detailed description.

[0075] As used herein, the term "substantially" means any minor variation resulting from design or manufacturing defects, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for differences from the perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in the actual implementation.

[0076] Furthermore, terms such as “first,” “second,” etc., may be used in this document for reference purposes only and are not intended to be limiting. For example, unless the context clearly indicates otherwise, the words “first,” “second,” and other such numerical terms relating to structures or elements do not imply order or sequence.

[0077] It should also be understood that when the term “including / contains” is used herein, it indicates the presence of the indicated feature, whole, step, operation, unit and / or component, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units and / or components and / or combinations thereof.

[0078] Additionally, when used in this disclosure, the terms “here,” “above,” “below,” “below,” “in the preceding text,” and similar terms should refer to the entirety of this disclosure and not any particular part thereof. Furthermore, unless expressly stated otherwise or otherwise understood in the context in which they are used, conditional language used herein, such as “may,” “possibly,” “for example,” “like,” etc., is generally intended to express that certain embodiments include, while other embodiments do not, certain features, elements, and / or states. Therefore, such conditional language is not generally intended to imply that one or more embodiments require features, elements, and / or states in any way, or whether such features, elements, and / or states are included or performed in any particular embodiment.

[0079] In this disclosure, the term "provide" is used broadly to cover all ways of obtaining an object, and therefore "providing an object" includes, but is not limited to, "purchasing," "preparing / manufacturing," "arranging / setting up," "installing / assembling," and / or "ordering" an object. Furthermore, in this disclosure, the terms "circuit," "unit," and "module" are used interchangeably.

[0080] As used herein, the term “and / or” includes any and all combinations of one or more of the listed items in association. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0081] Those skilled in the art will recognize that the boundaries between the above operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, variations, and substitutions are equally possible. Aspects and elements of all the embodiments disclosed above may be combined in any way and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive. In fact, the novel devices, methods, and systems described herein may be embodied in various other forms. Furthermore, various omissions, substitutions, and changes may be made to the form of the methods and systems described herein without departing from the spirit of this disclosure. For example, although blocks are presented in a given arrangement, alternative embodiments may perform similar functions with different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in various different ways.

[0082] The various embodiments of this disclosure can be described in a progressive manner, with references made to similar or identical parts between embodiments. Each embodiment focuses on describing the differences from other embodiments. In this disclosure, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this disclosure. In this disclosure, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples.

[0083] While specific embodiments of this disclosure have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. The various embodiments disclosed herein can be combined in any way without departing from the spirit and scope of this disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A clock generating device, comprising: A phase-locked loop (PLL) module, comprising a multi-phase voltage-controlled oscillator (VCO), wherein the VCO is configured to output a plurality of initial clock signals, each of the plurality of initial clock signals having a different initial phase and each initial clock signal having the same initial frequency; and A frequency multiplier module is electrically connected to the multi-phase voltage-controlled oscillator, and the frequency multiplier module is configured to generate a target clock signal based on the received plurality of initial clock signals, wherein the target frequency of the target clock signal is a preset multiple of the initial frequency.

2. The clock generating device according to claim 1, wherein, The multi-phase voltage-controlled oscillator includes: Multiple phase shifting units are provided, wherein the output of the previous phase shifting unit is electrically connected to the corresponding input of the next phase shifting unit, and the output of the last phase shifting unit is electrically connected to the corresponding input of the first phase shifting unit. Each phase shifting unit is configured to shift the initial clock signal input to the phase shifting unit by a first preset phase difference and output the phase-shifted initial clock signal to the frequency multiplier module.

3. The clock generating device according to claim 2, wherein, The phase-shifting unit includes a differential amplifier.

4. The clock generating device according to claim 2, wherein, The multi-phase voltage-controlled oscillator also includes: A current conversion unit is electrically connected to the plurality of phase-shifting units, and the current conversion unit is configured to generate a current signal for driving the plurality of phase-shifting units based on a received first voltage signal.

5. The clock generating device according to claim 1, wherein, The phase-locked loop module also includes: A phase detector configured to generate a second voltage signal based on a received reference clock signal and a frequency-divided clock signal; A charge pump electrically connected to the phase detector, and the charge pump being configured to generate a third voltage signal based on the received second voltage signal; A filter electrically connected between the charge pump and the multiphase voltage-controlled oscillator, and configured to filter the third voltage signal to generate the first voltage signal for the multiphase voltage-controlled oscillator; and A frequency divider is electrically connected between the multi-phase voltage-controlled oscillator and the phase detector, and the frequency divider is configured to divide at least one initial clock signal to generate the divided clock signal.

6. The clock generating device according to claim 5, wherein, The frequency divider includes a configurable frequency divider with an adjustable division ratio.

7. The clock generating device according to claim 1, wherein, The multi-phase voltage-controlled oscillator is configured to output N initial clock signals, wherein the first preset phase difference between the two initial clock signals having the closest initial phase is 2π / N, and the target frequency is N times the initial frequency, where N = 2π / N. m And m is a positive integer.

8. The clock generating device according to claim 7, wherein, The frequency multiplier module includes m-stage frequency multiplier components. The number of frequency multiplier units in the previous stage frequency multiplier component is twice the number of frequency multiplier units in the next stage frequency multiplier component. The last stage frequency multiplier component has one frequency multiplier unit. One frequency multiplier unit in the next stage frequency multiplier component is electrically connected to two corresponding frequency multiplier units in the previous stage frequency multiplier component to generate a corresponding subsequent stage clock signal based on the two previous stage clock signals received by the frequency multiplier unit in the subsequent stage frequency multiplier component. The frequency of the subsequent stage clock signal is twice the frequency of the previous stage clock signal.

9. The clock generating device according to claim 8, wherein, The double frequency unit includes: Two-input XOR gates: The two inputs of one of the two-input XOR gates in the subsequent doubler stage are electrically connected to the outputs of the corresponding two-input XOR gates in the preceding doubler stage; or Two-input XOR gates: The two inputs of one of the two-input XOR gates in the subsequent doubler stage are electrically connected to the outputs of the corresponding two-input XOR gates in the preceding doubler stage.

10. The clock generating device according to claim 8, wherein, The double frequency unit includes at least one of the following: A four-input XOR gate, wherein the four-input XOR gate is configured to generate a fifth clock signal based on a received first clock signal, a second clock signal inverted from the first clock signal, a third clock signal, and a fourth clock signal inverted from the third clock signal, wherein the first, second, third, and fourth clock signals have a first frequency equal to each other, and the fifth clock signal has a second frequency, which is twice the first frequency; and A four-input XOR gate is configured to generate a tenth clock signal based on a received sixth clock signal, a seventh clock signal that is inverted by the sixth clock signal, an eighth clock signal, and a ninth clock signal that is inverted by the eighth clock signal. The sixth, seventh, eighth, and ninth clock signals have a third frequency that is equal to each other, and the tenth clock signal has a fourth frequency that is twice the third frequency.

11. The clock generating device according to claim 10, wherein, The double frequency unit also includes: An inverter electrically connected to the output of at least one of the four-input XOR gate and the four-input XOR gate.

12. The clock generating device according to claim 8, wherein, The frequency multiplier module also includes a switching unit, which is disposed between two adjacent stages of the frequency multiplier components. The switching unit is configured to control the number of stages of the frequency multiplier components operating in the frequency multiplier module, so that the preset multiplier can be adjusted.

13. An integrated circuit chip, comprising a clock generating device according to any one of claims 1 to 12.

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