Display device, electronic device using the same, and method for manufacturing the same

Abstract

A display device, an electronic device using the same, and a method for manufacturing the same are provided, the display device including a substrate including an emission area and a non-emission area; a bank structure disposed on the emission area of the substrate and having an overhang structure, and an anode contact hole penetrating the bank structure in superposition with the emission area; a connection electrode disposed between the substrate and the bank structure in a portion superposed with the anode contact hole; a first element insulating layer disposed on the bank structure in superposition with the anode contact hole and covering a side surface of the bank structure; an anode electrode disposed on the first element insulating layer; an anode planarization layer disposed between the connection electrode and the anode electrode in a portion superposed with the anode contact hole; and a second element insulating layer covering an edge of the anode electrode, defining an opening, and in contact with the first element insulating layer.

Description

[0001] This application claims priority and all benefits arising therefrom to Korean Patent Application No. 10-2025-0002066, filed on January 7, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The disclosure relates to a display device, an electronic device using the display device, and a method for manufacturing the display device. Background Technology

[0003] With the advancement of the information society, the requirements for display devices that display images in various ways are becoming increasingly stringent. For example, display devices are used in various electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs. Display devices can be flat panel displays such as liquid crystal displays, field emission displays, and organic light-emitting displays. In flat panel displays, particularly light-emitting displays, images can be displayed without a backlight unit that provides light to the display panel because each pixel in the display panel includes a light-emitting element capable of emitting its own light. Summary of the Invention

[0004] The disclosed features provide a display device capable of providing high-resolution images, an electronic device using the display device, and a method for manufacturing the display device.

[0005] The disclosed features address reliability deficiencies in light-emitting elements included in display devices.

[0006] However, the features of the disclosure are not limited to those described herein. The above and other features of the disclosure will become more apparent to a person skilled in the art by referring to the detailed description of the disclosure given below.

[0007] Other features and embodiments will become apparent from the following detailed description and accompanying drawings.

[0008] In the disclosed embodiments, the display device includes: a substrate including an emitting region and a non-emitting region; a dam structure disposed on the emitting region of the substrate and having a cantilever structure, and an anode contact hole superimposed on the emitting region penetrating the dam structure; a connecting electrode disposed between the substrate and the dam structure in the portion superimposed on the anode contact hole; a first element insulating layer disposed on the dam structure, superimposed on the anode contact hole, and covering a side surface of the dam structure; an anode electrode disposed on the first element insulating layer; an anode planarization layer disposed between the connecting electrode and the anode electrode in the portion superimposed on the anode contact hole; and a second element insulating layer covering the edge of the anode electrode, defining an opening, and contacting the first element insulating layer.

[0009] In an embodiment, the dam structure may include: a first dam layer; a second dam layer disposed on the first dam layer; and a third dam layer including a tip that protrudes much more toward the non-emission region than a first side surface of the second dam layer, wherein the anode planarization layer is superimposed on the anode contact hole and penetrates the first dam layer, the second dam layer, and the third dam layer.

[0010] In an embodiment, the anode planarization layer may be spaced apart from the first, second, and third dam layers, and the first element insulating layer is disposed between the anode planarization layer and the first to third dam layers.

[0011] In an embodiment, the display device may further include: a first light-emitting layer disposed on the anode electrode and completely covering the second element insulating layer; a cathode electrode disposed on the first light-emitting layer; and an auxiliary electrode disposed on the cathode electrode and in contact with the tip of the third diaphragm layer.

[0012] In one embodiment, the auxiliary electrode may contact the first side surface of the second dam layer, and in the portion overlapping with the non-emission region, the auxiliary electrode is spaced apart from the first dam layer in a direction perpendicular to the substrate.

[0013] In an embodiment, the anode planarization layer may contact the anode electrode and the connecting electrode, and the anode planarization layer is electrically connected to the anode electrode and the connecting electrode.

[0014] In an embodiment, the display device may further include a transistor disposed between a substrate and a connecting electrode, wherein the anode electrode is connected to the transistor via an anode planarization layer and the connecting electrode.

[0015] In one embodiment, the anode planarization layer can completely fill the anode contact hole.

[0016] In an embodiment, the anode planarization layer may include or be composed of a transparent conductive material.

[0017] In one embodiment, the anode planarization layer may include a first surface facing the anode electrode, and the first surface is completely covered by the anode electrode.

[0018] In an embodiment, in a plan view, the first element insulating layer may expose the anode planarization layer, and in a plan view, the first element insulating layer completely surrounds the anode planarization layer.

[0019] In an embodiment, in a plan view, the dam structure may be spaced apart from the anode planarization layer, and the first element insulating layer is placed between the dam structure and the anode planarization layer, and in a plan view, the dam structure completely surrounds the anode planarization layer.

[0020] In the disclosed embodiments, a method for manufacturing a display device may include the following steps: defining an anode contact hole that penetrates a dam structure and a first element insulating layer; forming an anode planarization layer and an anode electrode; forming a tip of the dam structure after forming a second element insulating layer that defines an opening; and forming a light-emitting layer, a cathode electrode, an auxiliary electrode, and an element inorganic layer on the anode electrode.

[0021] In an embodiment, during the steps of forming the anode planarization layer and the anode electrode, a portion of the anode planarization layer may be removed by performing a chemical mechanical polishing (“CMP”) process. The anode planarization layer includes a first surface in contact with the anode electrode, and the first surface includes a surface polished by the CMP process.

[0022] In the disclosed embodiments, the electronic device includes: a display device including a substrate comprising an emitting region and a non-emitting region; and at least one of a display module, a processor, a memory, and a power module connected to the display device, wherein the display device further includes: a dam structure disposed on the emitting region of the substrate and having a cantilever structure, and an anode contact hole superimposed on the emitting region penetrating the dam structure; a connecting electrode disposed between the substrate and the dam structure in the portion superimposed on the anode contact hole; a first element insulating layer disposed on the dam structure, superimposed on the anode contact hole, and covering a side surface of the dam structure; an anode electrode disposed on the first element insulating layer; an anode planarization layer disposed between the connecting electrode and the anode electrode in the portion superimposed on the anode contact hole; and a second element insulating layer covering the edge of the anode electrode, defining an opening, and contacting the first element insulating layer.

[0023] In an embodiment, the dam structure may include: a first dam layer; a second dam layer disposed on the first dam layer; and a third dam layer including a tip that protrudes much more toward the non-emission region than a first side surface of the second dam layer, wherein the anode planarization layer penetrates the first dam layer, the second dam layer, and the third dam layer while being superimposed with the anode contact hole.

[0024] In an embodiment, the anode planarization layer may be spaced apart from the first, second, and third dam layers, while the first element insulating layer is placed between the anode planarization layer and the first to third dam layers.

[0025] In an embodiment, the display device may further include: a first light-emitting layer disposed on the anode electrode and completely covering the second element insulating layer; a cathode electrode disposed on the first light-emitting layer; and an auxiliary electrode disposed on the cathode electrode and in contact with the tip of the third diaphragm layer.

[0026] In one embodiment, the anode planarization layer can completely fill the anode contact hole.

[0027] In an embodiment, the display device may further include a transistor disposed between a substrate and a connecting electrode, wherein the anode electrode is connected to the transistor via an anode planarization layer and the connecting electrode.

[0028] According to the display device in the embodiments, the electronic device using the display device, and the method for manufacturing the display device, high-resolution images can be provided, and reliability defects of the light-emitting elements included in the display device can be solved.

[0029] It should be noted that the effects of the disclosure are not limited to those described above, and other effects will be clear to those skilled in the art from the following description. Attached Figure Description

[0030] The above and other advantages and features of the disclosure will become more apparent from the detailed description of the disclosed embodiments with reference to the accompanying drawings, in which: Figure 1 This is a perspective view illustrating an embodiment of the display device; Figure 2 This is a cross-sectional view illustrating an embodiment of the display device; Figure 3 This is a plan view illustrating an embodiment of the display layer of a display device; Figure 4 It shows the arrangement in Figure 3 A layout diagram of multiple pixels in the display area; Figure 5 It shows along Figure 4 A cross-sectional view of an embodiment of the display layer, taken by line A1-A1'; Figure 6 Is with Figure 5 An enlarged cross-sectional view of the display element layer superimposed on the first emission region; Figure 7 yes Figure 6 An enlarged sectional view of region A; Figure 8 yes Figure 7 Enlarged plan view of region C; Figure 9 It is shown Figure 7 A plan view showing the arrangement of the embankment structure, the anode planarization layer, and the first element insulation layer. Figure 10 It shows the manufacturing process. Figure 5 A flowchart of the method for displaying the element layer; Figures 11 to 13 It is shown Figure 10 A sectional view of operation S100; Figures 14 to 17 It is shown Figure 10 The sectional view of operation S200; Figures 18 to 21 It is shown Figure 10 The sectional view of the S300 operation; Figures 22 to 25 It is shown Figure 10 The sectional view of the S400 operation; Figure 26 A block diagram of an embodiment of an electronic device; and Figure 27 This is a schematic diagram of an embodiment of an electronic device. Detailed Implementation

[0031] The advantages and features of the disclosure, as well as the methods of implementing the disclosure, can be more readily understood by referring to the detailed description and accompanying drawings of the following embodiments. However, the disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be thorough and complete, and will fully convey the concept of the disclosure to those skilled in the art, and the disclosure will be defined solely by the appended claims.

[0032] It will be understood that when an element or layer is referred to as being "on" another element or layer, the element or layer may be directly on the other element or layer or an intervening element or layer. Throughout the specification, the same reference numerals denote the same elements. The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the drawings used to describe embodiments are merely examples, and the disclosure is not limited to the details shown.

[0033] It will be understood that although the terms first, second, third, etc., may be used here to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the publicly stated teachings, the first element discussed below may be referred to as the second element.

[0034] The features of the various disclosed embodiments can be combined or integrated with each other in part or in whole, and can operate and drive each other in various technical ways. These embodiments can be implemented independently of each other or together in an interdependent relationship.

[0035] In the following description, illustrative embodiments will be described with reference to the accompanying drawings.

[0036] Figure 1 This is a perspective view showing an embodiment of the display device.

[0037] Reference Figure 1The display device 10 can be applied to portable electronic devices, such as mobile phones, smartphones, tablet computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (“PMPs”), navigation systems, or ultra-mobile personal computers (“UMPCs”). In one embodiment, the display device 10 can be applied as a display unit for, for example, a television, laptop computer, monitor, billboard, or Internet of Things (“IoT”) device. In another embodiment, the display device 10 can be applied to wearable devices, such as smartwatches, watch phones, glasses displays, or head-mounted displays (“HMDs”).

[0038] The display device 10 may have a planar shape similar to a quadrilateral. In an embodiment, the display device 10 may have a planar shape, for example, similar to a quadrilateral having a short side in a first direction DR1 and a long side in a second direction DR2. The corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be a right angle or rounded with a selected curvature. The planar shape of the display device 10 is not limited to a quadrilateral shape, and may be formed in a shape similar to other polygonal shapes, circular shapes, or elliptical shapes.

[0039] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400.

[0040] The display panel 100 may include a main area MA and a sub-area SBA. The main area MA may include a display area DDA containing pixels of the displayed image and a non-display area NDA disposed around the display area DDA.

[0041] The display area DDA can emit light from multiple openings or multiple emission areas, which will be described later. In embodiments, the display panel 100 may include, for example, pixel circuitry including switching elements, an element insulating layer defining the emission area or opening, and a self-emissive element. In embodiments, the self-emissive element may include, but is not limited to, at least one of, an organic light-emitting diode (“LED”) including an organic light-emitting layer, a quantum dot LED including a quantum dot light-emitting layer, an inorganic LED including an inorganic semiconductor, and a microLED. The following figures illustrate an embodiment where the self-emissive element is an organic light-emitting diode.

[0042] The non-display area NDA can be an area outside the display area DDA. The non-display area NDA can be defined as the edge area of ​​the main area MA of the display panel 100.

[0043] A sub-region SBA can be a region extending from one side of a main region MA. The sub-region SBA can include a flexible material that can be bent, folded, or rolled. In an embodiment, when the sub-region SBA is bent, it can overlap with the main region MA in, for example, the thickness direction (e.g., the third direction DR3). The sub-region SBA can include a display driver 200 and a pad (or solder pad) portion connected to the circuit board 300. In another embodiment, the sub-region SBA can be omitted, and the display driver 200 and the pad portion can be disposed in a non-display area NDA.

[0044] The display driver 200 can output signals and voltages for driving the display panel 100. The display driver 200 can be formed as an integrated circuit (“IC”) and disposed (e.g., mounted) on the display panel 100 by a chip-on-glass (“COG”) method, a chip-on-plastic (“COP”) method, or an ultrasonic bonding method. In one embodiment, the display driver 200 can be disposed in a sub-region SBA and can be superimposed on the main region MA in the thickness direction by, for example, bending of the sub-region SBA. In another embodiment, the display driver 200 can be disposed (e.g., mounted) on a circuit board 300.

[0045] The circuit board 300 can be attached to the pad portion of the display panel 100 via an anisotropic conductive film (“ACF”). The circuit board 300 can be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0046] Touch driver 400 can be mounted (e.g., installed) on circuit board 300. Touch driver 400 can be connected to touch sensor layer TSL (refer to) for sensing and driving touch. Figure 2 ).

[0047] Figure 2 This is a cross-sectional view showing an embodiment of the display device.

[0048] Reference Figure 2 The display panel 100 may include a display layer DPL, a touch sensor layer TSL, and a color filter layer CFL. The display layer DPL may include a substrate SUB, a transistor layer TFTL, a display element layer EML, and a thin film encapsulation layer TFEL.

[0049] The substrate SUB can be a matrix substrate or a matrix component. The substrate SUB can be a flexible substrate that can be bent, folded, or rolled. In embodiments, for example, the substrate SUB may include, but is not limited to, a polymer resin such as polyimide (“PI”). In another embodiment, the substrate SUB may include a glass material or a metallic material.

[0050] The transistor layer TFTL can be disposed on the substrate SUB. The transistor layer TFTL can be disposed in the portion superimposed with the display area DDA, the non-display area NDA, and the sub-area SBA. The transistor layer TFTL may include multiple transistor TFTs (see reference). Figure 5 ).

[0051] The display element layer (EML) can be disposed on the transistor layer (TFTL). The display element layer (EML) can be disposed in the portion superimposed with the display area (DDA). The display element layer (EML) can include, but is not limited to, at least one of the following: organic LED (“OLED”) containing an organic light-emitting layer, quantum dot LED containing a quantum dot light-emitting layer, inorganic LED containing inorganic semiconductors, and micro LED.

[0052] A thin-film encapsulation layer (TFEL) can be disposed on the display element layer (EML). The TFEL can be disposed in the portion overlapping the display area (DDA) and the non-display area (NDA). The TFEL can cover the top and side surfaces of the display element layer (EML) and protect it from external oxygen and moisture. The TFEL can include at least one inorganic film and at least one organic film for encapsulating the display element layer (EML). According to an embodiment, the TFEL can be omitted.

[0053] The touch sensor layer (TSL) can be disposed on the thin-film encapsulation layer (TFEL). The touch sensor layer (TSL) can be disposed in the portion superimposed with the display area (DDA) and the non-display area (NDA). The touch sensor layer (TSL) can sense the user's touch using mutual capacitance or self-capacitance methods. According to an embodiment, the touch sensor layer (TSL) can be omitted.

[0054] A color filter layer (CFL) can be disposed on the touch sensor layer (TSL). The color filter layer (CFL) can be disposed in the portion superimposed with the display area (DDA) and the non-display area (NDA). The color filter layer (CFL) can absorb a portion of the light from outside the display device 10 to reduce reflected light caused by external light. Therefore, the color filter layer (CFL) can prevent color distortion caused by the reflection of external light.

[0055] Since the color filter layer CFL is directly disposed on the touch sensor layer TSL, the display device 10 does not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 can be relatively small. According to an embodiment, the color filter layer CFL can be omitted.

[0056] like Figure 2As shown, the portion of the display panel 100 that overlaps with the sub-region SBA can be bent. When a portion of the display panel 100 is bent, the display driver 200, the circuit board 300, and the touch driver 400 can be overlapped with the main region MA on the third-party DR3.

[0057] When a portion of the display panel 100 is bent, the bending protection layer BPL can protect the lower structure, which is set to be superimposed with the sub-region SBA, from the effects of bending stress.

[0058] Figure 3 This is a plan view illustrating an embodiment of the display layer of a display device.

[0059] Reference Figure 3 The display layer DPL may include multiple pixels PX in the portion superimposed with the display area DDA, multiple power lines VL connected to the multiple pixels PX, multiple scan lines SL, multiple emission control lines EDL, and multiple data lines DL.

[0060] Each of the multiple scan lines SL can extend along a first direction DR1 and can be spaced apart from each other along a second direction DR2 that intersects the first direction DR1. The scan lines SL can be arranged along the second direction DR2. The scan lines SL can sequentially supply scan signals to multiple pixels PX.

[0061] The transmit control lines EDL can extend along the first direction DR1 and can be spaced apart from each other along the second direction DR2. The transmit control lines EDL can be arranged along the second direction DR2. The transmit control lines EDL can sequentially supply transmit signals to multiple pixels PX.

[0062] Data lines DL can extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. Data lines DL can be arranged along the first direction DR1. Data lines DL can supply data voltage to multiple pixels PX. The data voltage determines the brightness of each pixel PX.

[0063] A power line VL may include a main power line VL1 and a sub-power line VL2. A first power voltage (high potential voltage) or a second power voltage (low potential voltage) can be transmitted to the sub-power line VL2 via the main power line VL1, which is superimposed on the non-display area NDA. In the following text, the main power line VL1 and the sub-power line VL2 may be collectively referred to as power line VL.

[0064] The non-display area NDA may surround the display area DDA. The non-display area NDA may include a scan driver 211 and a transmit control driver 213.

[0065] The scan driver 211 can be located outside one side of the display area DDA, or on one side of the non-display area NDA. The scan driver 211 may include multiple drive transistors that generate gate signals based on gate control signals.

[0066] The emit control driver 213 can be located on the outer side of the display area DDA, or on the outer side of the non-display area NDA. The emit control driver 213 may include multiple emit control transistors that generate emit signals based on emit control signals.

[0067] The display layer DPL of the embodiment may include a display driver 200 and a plurality of pad electrodes PD in a portion superimposed with the sub-region SBA. The plurality of pad electrodes PD may be spaced apart from each other in the first direction DR1, and the pad electrodes PD may be connected to different wirings respectively.

[0068] Figure 4 It shows the arrangement in Figure 3 A layout diagram of multiple pixels in the display area.

[0069] Reference Figure 4 In this embodiment, pixel PX may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 disposed in the portion overlapping with the display area DDA. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be spaced apart from each other.

[0070] Pixel PX may include an emission region EA. The emission region EA may be a portion that emits light. In an embodiment, the first sub-pixel SP1 may include a first emission region EA1, the second sub-pixel SP2 may include a second emission region EA2, and the third sub-pixel SP3 may include a third emission region EA3.

[0071] In an embodiment, the first emission region EA1, the second emission region EA2, and the third emission region EA3 can emit light of different colors. For example, in an embodiment, the first emission region EA1 can emit red light, the second emission region EA2 can emit green light, and the third emission region EA3 can emit blue light. However, the disclosure is not limited thereto, and the first emission region EA1, the second emission region EA2, and the third emission region EA3 can emit light of the same color according to an embodiment.

[0072] In an embodiment, the emission region EA may be defined by an opening OP. The opening OP may be defined by a component insulating layer PDL (see reference OP), which will be described later. Figure 5 )limited.

[0073] In a plan view, the anode contact hole (ACTH) can be defined in the portion overlapping with the emission region (EA). In other words, in a plan view, the anode contact hole (ACTH) can be defined in the portion overlapping with the opening (OP). The anode contact hole (ACTH) will be described later.

[0074] The display device 10 of the embodiment may include a non-emissive region NLA in the portion superimposed with the display area DDA. The non-emissive region NLA can prevent color mixing of light emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0075] The dam structure BN can be disposed in the portion overlapping with the non-emitting region NLA. The dam structure BN can be disposed around the opening OP or the anode contact hole ACTH. The predetermined planar structure of the dam structure BN will be described later.

[0076] Figure 5 It shows along Figure 4 A cross-sectional view of an embodiment of the display layer, taken by line A1-A1'. Figure 6 Is with Figure 5 An enlarged cross-sectional view of the display element layer superimposed on the first emission region. Figure 5 The cross-sectional structure of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 in the portion superimposed with the display area DDA of the display device 10 is shown.

[0077] Reference Figure 5 and Figure 6 The transistor layer TFTL can be disposed on the substrate SUB. The transistor layer TFTL may include a first buffer layer BF1, a lower metal layer BML, a second buffer layer BF2, a transistor TFT, a gate insulating layer GI, a first insulating layer ILD1, a capacitor electrode CPE, a second insulating layer ILD2, a first connection electrode CNE1, a first via layer VIA1, a second connection electrode CNE2, a second via layer VIA2, and a third insulating layer ILD3.

[0078] A first buffer layer BF1 may be disposed on a substrate SUB. The first buffer layer BF1 may include an inorganic membrane capable of preventing the penetration of air or moisture. In an embodiment, the first buffer layer BF1 may include, for example, a plurality of inorganic membranes stacked alternately.

[0079] The lower metal layer BML can be disposed on the first buffer layer BF1. The lower metal layer BML may include a conductive metal and may be formed as a single layer or multiple layers of any one of, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or any alloy thereof.

[0080] The second buffer layer BF2 may cover the first buffer layer BF1 and the lower metal layer BML. The second buffer layer BF2 may include an inorganic membrane capable of preventing the penetration of air or moisture. In an embodiment, the second buffer layer BF2 may include, for example, a plurality of inorganic membranes stacked alternately.

[0081] A transistor TFT can be disposed on the second buffer layer BF2, and the transistor TFT can constitute a pixel circuit. In an embodiment, the transistor TFT can be, for example, a switching transistor or a driving transistor of the pixel circuit.

[0082] A transistor TFT may include an active layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0083] The active layer ACT can be disposed on the second buffer layer BF2. The active layer ACT can be stacked on the third-direction DR3 with the gate electrode GE, and can be insulated from the gate electrode GE through the gate insulating layer GI. The source electrode SE and the drain electrode DE can be the already conductive portions of the active layer ACT.

[0084] A gate insulating layer GI can be disposed on the active layer ACT. The gate insulating layer GI can cover the active layer ACT and the second buffer layer BF2 to insulate the gate electrode GE from the active layer ACT. The gate insulating layer GI can define a contact hole through which the first connection electrode CNE1 passes.

[0085] The gate electrode GE can be disposed on the gate insulating layer GI. The gate electrode GE can be stacked with the active layer ACT, and the gate insulating layer GI is placed between the gate electrode GE and the active layer ACT.

[0086] The gate electrode GE may include a conductive metal and may be formed as a single layer or multiple layers of any of, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or any alloy thereof.

[0087] The first insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first insulating layer ILD1 may define a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first insulating layer ILD1 may extend to the contact hole of the gate insulating layer GI and the contact hole of the second insulating layer ILD2.

[0088] The capacitor electrode CPE can be disposed on the first insulating layer ILD1. The capacitor electrode CPE can be stacked with the gate electrode GE on the third-direction DR3. The capacitor electrode CPE and the gate electrode GE can form a capacitor.

[0089] The second insulating layer ILD2 may cover the capacitor electrode CPE and the first insulating layer ILD1. The second insulating layer ILD2 may define a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second insulating layer ILD2 may extend to the contact hole of the first insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0090] The first connection electrode CNE1 can be disposed on the second insulating layer ILD2. The first connection electrode CNE1 can electrically connect the drain electrode DE of the transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 can be inserted into a contact hole disposed in the first insulating layer ILD1, the second insulating layer ILD2 and the gate insulating layer GI to contact the drain electrode DE of the transistor TFT.

[0091] A first via layer VIA1 can be disposed on the first connecting electrode CNE1 and the second insulating layer ILD2. The first via layer VIA1 can planarize the underlying structure. The first via layer VIA1 may include a contact hole through which the second connecting electrode CNE2 passes.

[0092] The first via layer VIA1 may include an organic insulating material. In embodiments, the first via layer VIA1 may include, for example, acrylic resin, polyimide, polyamide, benzocyclobutene, or phenolic resin.

[0093] The second connecting electrode CNE2 can be disposed on the first via layer VIA1. The second connecting electrode CNE2 can be disposed in the portion overlapping with the emission region EA. The second connecting electrode CNE2 can be inserted into a contact hole defined in the first via layer VIA1 to contact the first connecting electrode CNE1.

[0094] The second via layer VIA2 can be disposed on the first via layer VIA1. The second via layer VIA2 can flatten the step portion formed by the second connecting electrode CNE2.

[0095] The second via layer VIA2 may include organic materials. In embodiments, the second via layer VIA2 may include, for example, acrylic resin, silicone resin, silicone-acrylic resin, epoxy resin, polyimide, polyamide, benzocyclobutene, or phenolic resin.

[0096] The third insulating layer ILD3 can be disposed on the second via layer VIA2. The third insulating layer ILD3 can help prevent exhaust gas caused by the organic material of the second via layer VIA2 from permeating into the display element layer EML.

[0097] The third insulating layer ILD3 may include an inorganic insulating material. In embodiments, the third insulating layer ILD3 may include, for example, at least one of silicon nitride, silicon oxide, and silicon oxynitride, or be composed of, for example, at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0098] The display element layer (EML) can be disposed on the transistor layer (TFTL). The display element layer (EML) may include a barrier structure (BN), an insulating layer (PDL), a light-emitting element (ED), an anode planarization layer (APL), and an inorganic layer (IO).

[0099] The dam structure BN can be disposed on the third insulating layer ILD3. The dam structure BN can be disposed in the portion that does not overlap with the emitter region EA and / or the opening OP and / or the anode contact hole ACTH.

[0100] The dam structure BN can assist the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 in the portions superimposed with the first emission region EA1, the second emission region EA2, and the third emission region EA3, respectively. Furthermore, the dam structure BN can assist in the electrical connection of the cathode electrodes CE, which are spaced apart from each other in the first emission region EA1, the second emission region EA2, and the third emission region EA3.

[0101] The dike structure BN may include a first dike layer BN1, a second dike layer BN2, and a third dike layer BN3. The first dike layer BN1, the second dike layer BN2, and the third dike layer BN3 may be stacked sequentially on the third-direction DR3.

[0102] The first dam layer BN1 can be disposed on the third insulating layer ILD3. The first dam layer BN1 can cover the third insulating layer ILD3 in the portion that overlaps with the non-emitting region NLA.

[0103] The first diaphragm layer BN1 can assist in applying a relatively low potential voltage to the cathode electrode CE. The first diaphragm layer BN1 may include a conductive metal with etch resistance. In an embodiment, the first diaphragm layer BN1 may include titanium (Ti) or be composed of titanium.

[0104] The first dam layer BN1 can be penetrated by the anode contact hole ACTH in the portion overlapping with the emission region EA. In other words, the first dam layer BN1 can be configured to surround the anode contact hole ACTH and can be formed in the form of a conductive pattern arranged around the anode contact hole ACTH.

[0105] The second dam layer BN2 can be configured to contact and be on top of the first dam layer BN1. The second dam layer BN2 can be penetrated by the anode contact hole ACTH in the portion overlapping with the emission region EA. In other words, the second dam layer BN2 can be configured to surround the anode contact hole ACTH.

[0106] Multiple second dam layers BN2 can be formed, and the multiple second dam layers BN2 can be spaced apart from each other in the first direction DR1. In other words, the multiple second dam layers BN2 can be respectively disposed in the portions superimposed with the first emission region EA1, the second emission region EA2 and the third emission region EA3, and each second dam layer BN2 can be spaced apart from each other in an island shape.

[0107] The second layer BN2 can assist in electrically connecting the first layer BN1 to the third layer BN3. In other words, the second layer BN2 can be electrically connected to both the first layer BN1 and the third layer BN3. Therefore, the second layer BN2 disposed in the portion superimposed with the first transmission region EA1, the second layer BN2 disposed in the portion superimposed with the second transmission region EA2, and the second layer BN2 disposed in the portion superimposed with the third transmission region EA3 can be electrically connected through the first layer BN1.

[0108] The second dam layer BN2 may include a metal with relatively high conductivity. In an embodiment, the second dam layer BN2 may include aluminum (Al).

[0109] The third dam layer BN3 can be configured to contact and be on top of the second dam layer BN2. The third dam layer BN3 can be penetrated by the anode contact hole ACTH in the portion overlapping with the emission region EA. In other words, the third dam layer BN3 can be configured to surround the anode contact hole ACTH.

[0110] Multiple third dam layers BN3 can be formed, and the multiple third dam layers BN3 can be spaced apart from each other in the first direction DR1. In other words, the multiple third dam layers BN3 can be respectively disposed in the portions superimposed with the first emission region EA1, the second emission region EA2 and the third emission region EA3, and each third dam layer BN3 can be spaced apart from each other in an island shape.

[0111] The third dam layer BN3 may include an etch-resistant conductive metal. In an embodiment, the third dam layer BN3 may include titanium (Ti).

[0112] In this embodiment, the third dike layer BN3 disposed in the portion overlapping with the first transmission region EA1, the third dike layer BN3 disposed in the portion overlapping with the second transmission region EA2, and the third dike layer BN3 disposed in the portion overlapping with the third transmission region EA3 can be electrically connected through the second dike layer BN2 and the first dike layer BN1. Redundant descriptions are omitted.

[0113] like Figure 6As shown, the second embankment layer BN2 may include a first side surface 2c facing the non-emission region NLA, and the third embankment layer BN3 may include a tip that protrudes significantly beyond the first side surface 2c of the second embankment layer BN2 in the first direction DR1. Therefore, the first side surface 2c of the second embankment layer BN2 and the tip of the third embankment layer BN3 can form an undercut, and the embankment structure BN can have a cantilever structure.

[0114] In the display device 10 of this embodiment, the dam structure BN includes a tip, such that the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3, which are spaced apart from each other, can be formed in the manufacturing process without using a separate fine metal mask. The manufacturing process will be described later.

[0115] The component insulating layer PDL may include a first component insulating layer PDL1 and a second component insulating layer PDL2.

[0116] The first element insulating layer PDL1 can be disposed on the third dam layer BN3. The first element insulating layer PDL1 can cover the third dam layer BN3 and can be configured to overlap with the tip of the third dam layer BN3 on the third-direction DR3.

[0117] The first element insulating layer PDL1 can be penetrated by the anode contact hole ACTH in the portion overlapping with the emitter region EA. In other words, the first element insulating layer PDL1 can be configured to surround the anode contact hole ACTH.

[0118] The first element insulating layer PDL1 can separate and insulate the dam structure BN and the anode electrode AE ​​from each other, preventing contact between the dam structure BN and the anode electrode AE. Therefore, the first element insulating layer PDL1 can cover the entire side surface of the dam structure BN facing the anode contact hole ACTH. Thus, the first element insulating layer PDL1 can resolve the short-circuit defect in the display device 10 caused by contact between the anode electrode AE ​​and the dam structure BN.

[0119] The first element insulating layer PDL1 may include or be composed of an inorganic insulating material. In an embodiment, the first element insulating layer PDL1 may include, for example, at least one of silicon nitride, silicon oxide, and silicon oxynitride, or be composed of, for example, at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0120] A second element insulating layer PDL2 may be disposed on the first element insulating layer PDL1. The second element insulating layer PDL2 may define an opening OP and may expose the anode electrode AE ​​in the portion overlapping with the opening OP. In other words, the second element insulating layer PDL2 may be configured to surround the opening OP and may cover the edge of the anode electrode AE.

[0121] The second element insulating layer PDL2 may include an inorganic insulating material. In an embodiment, the second element insulating layer PDL2 may include, for example, at least one of silicon nitride, silicon oxide, and silicon oxynitride, or be composed of, for example, at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0122] Although the width of the anode contact hole ACTH and the width of the opening OP are shown to be the same in the first direction DR1 in the accompanying drawings, the disclosure is not limited thereto. The anode contact hole ACTH and the opening OP may be configured to be stacked in the third direction DR3, but the width of the anode contact hole ACTH and the width of the opening OP may be different from each other.

[0123] The light-emitting element (ED) can be disposed on the embankment structure BN. The ED can be stacked on the third-direction DR3 with the embankment structure BN and the element insulating layer PDL. Furthermore, the ED can be stacked on the third-direction DR3 with the anode contact hole ACTH.

[0124] The display device 10 of the embodiment can be applied to high-resolution electronic devices. Therefore, it is desirable to arrange the multiple light-emitting elements ED included in the display device 10 in a narrow area while ensuring an appropriate spacing. Therefore, the display device 10 of the embodiment can include multiple light-emitting elements that are effectively arranged in a narrow area by forming light-emitting elements ED disposed on the embankment structure BN.

[0125] The light-emitting element ED may include a first light-emitting element ED1 disposed in a first emission region EA1, a second light-emitting element ED2 disposed in a second emission region EA2, and a third light-emitting element ED3 disposed in a third emission region EA3. The first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 may be spaced apart from each other.

[0126] In an embodiment, the first light-emitting element ED1 may include an anode electrode AE, a first light-emitting layer EL1, a cathode electrode CE, and an auxiliary electrode AX; the second light-emitting element ED2 may include an anode electrode AE, a second light-emitting layer EL2, a cathode electrode CE, and an auxiliary electrode AX; and the third light-emitting element ED3 may include an anode electrode AE, a third light-emitting layer EL3, a cathode electrode CE, and an auxiliary electrode AX.

[0127] The first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 can emit light of different colors. In an embodiment, for example, the first light-emitting element ED1 can emit red light, the second light-emitting element ED2 can emit green light, and the third light-emitting element ED3 can emit blue light. The color of the light emitted by the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 can be determined by the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3.

[0128] In an embodiment, the anode contact hole ACTH may be defined in the portion overlapping with the emission region EA. The anode contact hole ACTH may be defined by penetrating the third insulating layer ILD3, the first dam layer BN1, the second dam layer BN2, and the third dam layer BN3.

[0129] In the display device 10 of this embodiment, the separate region for the anode contact hole ACTH is formed to overlap with the emission region EA rather than being formed in a separate space, so that the contact region of the anode electrode AE ​​and the emission region EA can be integrated. Therefore, in the display device 10 of this embodiment, multiple emission regions EA can be effectively arranged in a narrow area.

[0130] The anode planarization layer APL can be disposed on the second connecting electrode CNE2 in the portion superimposed with the anode contact hole ACTH. The anode planarization layer APL can be disposed in the portion superimposed with the emitter region EA or the opening OP, and may not be superimposed with the non-emitter region NLA. The anode planarization layer APL can contact the second connecting electrode CNE2 and can be electrically connected to the second connecting electrode CNE2. Furthermore, the anode planarization layer APL can contact the third insulating layer ILD3 and the first element insulating layer PDL1 in the portion superimposed with the anode contact hole ACTH.

[0131] The anode planarization layer (APL) can planarize the stepped portions formed in the portion overlapping with the anode contact hole (ACTH). In other words, the anode planarization layer (APL) can fill the stepped portions formed in the portion overlapping with the anode contact hole (ACTH).

[0132] The anode planarization layer (APL) may comprise a conductive metal and / or a transparent conductive oxide (“TCO”) material. In embodiments, the anode planarization layer (APL) may comprise any of, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or may comprise at least one of indium zinc oxide (“IZO”) and indium tin oxide (“ITO”).

[0133] The anode electrode AE ​​can be disposed on the first element insulating layer PDL1 and the anode planarization layer APL. The anode electrode AE ​​can contact the anode planarization layer APL and the first element insulating layer PDL1.

[0134] The anode planarization layer APL and the anode electrode AE ​​can be electrically connected. Therefore, the anode electrode AE ​​can be electrically connected to the second connection electrode CNE2 through the anode planarization layer APL.

[0135] The anode electrode AE ​​can be disposed in the portion overlapping with the emission region EA and / or the opening OP and / or the anode contact hole ACTH. The anode electrode AE ​​can be exposed in the portion overlapping with the opening OP, and the anode electrode AE ​​can contact the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 in the portion overlapping with the opening OP. The edge of the anode electrode AE ​​that does not overlap with the opening OP can be covered by the second element insulating layer PDL2.

[0136] The anode electrode AE ​​can have a stacked structure formed by stacking layers of materials with relatively high work functions, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium oxide (In2O3), and layers of reflective materials such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), or any combination thereof. In embodiments, the anode electrode AE ​​can have, for example, a multilayer structure of ITO / Mg, ITO / MgF2, ITO / Ag, and ITO / Ag / ITO, but is not limited thereto.

[0137] In the manufacturing process of the display device 10, the anode planarization layer APL and the anode electrode AE ​​can be formed through different processes. Specifically, the anode planarization layer APL can be formed through a deposition process, a chemical mechanical polishing (“CMP”) process, and a patterning process, while the anode electrode AE ​​can be formed through a deposition process and a patterning process. Therefore, a boundary surface can be formed on a surface on which the anode planarization layer APL and the anode electrode AE ​​face each other.

[0138] Therefore, in the display device 10 of this embodiment, since the boundary surfaces of the anode planarization layer APL and the anode electrode AE ​​are on the same surface facing each other, it can be seen that the anode planarization layer APL and the anode electrode AE ​​are formed in different processes. The manufacturing process will be described later.

[0139] The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 can be disposed on the anode electrode AE. The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 can be disposed in the portion superimposed with the emitting region EA and the non-emitting region NLA. The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 can be superimposed on the third-direction DR3 with the dam structure BN and the component insulating layer PDL.

[0140] The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 can contact the anode electrode AE ​​in the portion superimposed with the opening OP, and can cover the entire second element insulating layer PDL2 in the portion superimposed with the non-emitting region NLA.

[0141] In an embodiment, when the display device 10 does not include the anode planarization layer APL, the anode electrode AE ​​may cover, for example, the stepped portion formed in the portion superimposed with the anode contact hole ACTH. This may mean that the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 formed on the anode electrode AE ​​also cover the stepped portion formed in the portion superimposed with the anode contact hole ACTH.

[0142] In an embodiment, when the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 cover the stepped portion formed in the portion overlapping with the anode contact hole ACTH, the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 may be formed to have a thickness less than a predetermined range in the portion overlapping with the edge of the anode contact hole ACTH, which may lead to reliability defects in the display device 10 (e.g., light-emitting layer shading defects).

[0143] The aforementioned reliability defects (e.g., light-emitting layer shadow defects) may be the following defects: because the thickness of the material forming the first light-emitting layer EL1, the second light-emitting layer EL2 and the third light-emitting layer EL3 is partially less than a predetermined range, the measured brightness of the display device 10 is partially less than a predetermined range.

[0144] Therefore, the display device 10 of the embodiment includes an anode planarization layer APL in the portion superimposed with the anode contact hole ACTH, thereby planarizing the stepped portion formed in the portion superimposed with the anode contact hole ACTH. Thus, the anode electrode AE ​​can have a relatively flat shape in the portion superimposed with the anode contact hole ACTH.

[0145] Furthermore, since the display device 10 of the embodiment includes an anode planarization layer APL in the portion superimposed with the anode contact hole ACTH, the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 can be formed with a uniform thickness in the portion superimposed with the anode contact hole ACTH. Therefore, the display device 10 can solve reliability defects (e.g., light-emitting layer shading defects).

[0146] The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 can be organic light-emitting layers that include organic materials. The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 can include all commonly used materials.

[0147] The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 can emit light of different colors. In an embodiment, for example, the first light-emitting layer EL1 can emit red light, the second light-emitting layer EL2 can emit green light, and the third light-emitting layer EL3 can emit blue light, but the disclosure is not limited thereto.

[0148] The first light-emitting layer EL1 can be disposed in the portion superimposed with the first emitting region EA1, the second light-emitting layer EL2 can be disposed in the portion superimposed with the second emitting region EA2, and the third light-emitting layer EL3 can be disposed in the portion superimposed with the third emitting region EA3. The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 can be spaced apart from each other in the portion superimposed with the non-emitting region NLA.

[0149] In the display device 10 of this embodiment, the third diaphragm layer BN3 includes a tip, such that the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3, which are spaced apart from each other, can be formed in the manufacturing process of the display device 10 without using a separate fine metal mask. The manufacturing process will be described later.

[0150] The cathode electrode CE can be disposed on the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3. The cathode electrode CE can be disposed in the portion superimposed with the emitting region EA and the non-emitting region NLA. The cathode electrode CE can cover the entire first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3.

[0151] The cathode electrode CE can contact the dam structure BN, and therefore can be electrically connected to the dam structure BN. Specifically, the cathode electrode CE can contact the tip of the third dam layer BN3.

[0152] The cathode electrode CE may include a transparent conductive material, enabling the emission of light generated in the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3. In embodiments, the cathode electrode CE may include, for example, a material layer having a relatively low work function, such as Li, Ca, LiF, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF2, Ba, or compounds or combinations thereof (e.g., a combination of Ag and Mg), or the cathode electrode CE may have a multilayer structure such as LiF / Ca and LiF / Al. The cathode electrode CE may also include a transparent metal oxide layer disposed on a material layer having a relatively low work function.

[0153] In this embodiment, the cathode electrode CE disposed in the portion overlapping with the first emission region EA1, the cathode electrode CE disposed in the portion overlapping with the second emission region EA2, and the cathode electrode CE disposed in the portion overlapping with the third emission region EA3 can be spaced apart from each other. The cathode electrodes CE disposed in the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be electrically connected through the dike structure BN. Specifically, the cathode electrodes CE disposed in the first emission region EA1, the second emission region EA2, and the third emission region EA3 can contact the third dike layer BN3 disposed in the first emission region EA1, the second emission region EA2, and the third emission region EA3, and can be electrically connected to each other through the second dike layer BN2 and the first dike layer BN1, which are electrically connected to the third dike layer BN3.

[0154] In the display device 10 of this embodiment, the third embankment layer BN3 includes a tip, such that the cathode electrodes CE, spaced apart from each other in the first emission region EA1, the second emission region EA2, and the third emission region EA3, can be formed without a separate fine metal mask. The manufacturing process will be described later.

[0155] The auxiliary electrode AX can be disposed on the cathode electrode CE. The auxiliary electrode AX can be disposed in the portion overlapping the emitting region EA and the non-emitting region NLA. The auxiliary electrode AX can cover the entire cathode electrode CE. The auxiliary electrode AX can assist in the electrical connection to the cathode electrode CE.

[0156] The auxiliary electrode AX may comprise a transparent conductive oxide (“TCO”) material. In embodiments, the auxiliary electrode AX may comprise at least one of, for example, indium zinc oxide (“IZO”) and indium tin oxide (“ITO”).

[0157] In this embodiment, the auxiliary electrode AX disposed in the portion overlapping with the first emission region EA1, the auxiliary electrode AX disposed in the portion overlapping with the second emission region EA2, and the auxiliary electrode AX disposed in the portion overlapping with the third emission region EA3 can be spaced apart from each other. The auxiliary electrodes AX spaced apart from each other in the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be electrically connected through the dike structure BN. Specifically, the auxiliary electrodes AX spaced apart from each other in the first emission region EA1, the second emission region EA2, and the third emission region EA3 can contact the third dike layer BN3 spaced apart from each other, and can be electrically connected to each other through the second dike layer BN2 and the first dike layer BN1, which are electrically connected to the third dike layer BN3.

[0158] In one embodiment, the auxiliary electrode AX may be spaced apart from the first dam layer BN1 on the third-direction DR3 in the portion superimposed with the non-emitting region NLA. The organic encapsulation layer TFE1, which will be described later, may be disposed in the spacer portion between the auxiliary electrode AX and the first dam layer BN1.

[0159] The inorganic layer IO can be placed on the light-emitting element ED. The inorganic layer IO can completely cover the light-emitting element ED, thereby reducing or preventing oxygen or moisture from penetrating into the light-emitting element ED.

[0160] The inorganic layer IO of the component may include or be composed of an inorganic insulating material. In an embodiment, the inorganic layer IO of the component may include, for example, any one of silicon nitride, silicon oxide, and silicon oxynitride, or be composed of, for example, any one of silicon nitride, silicon oxide, and silicon oxynitride.

[0161] The inorganic layer IO may include a first inorganic layer IO1, a second inorganic layer IO2, and a third inorganic layer IO3. The first inorganic layer IO1 may be disposed on the first light-emitting element ED1 in a first emission region EA1, the second inorganic layer IO2 may be disposed on the second light-emitting element ED2 in a second emission region EA2, and the third inorganic layer IO3 may be disposed on the third light-emitting element ED3 in a third emission region EA3. The first inorganic layer IO1, the second inorganic layer IO2, and the third inorganic layer IO3 may be spaced apart from each other in the portion superimposed with the non-emission region NLA.

[0162] In the accompanying drawings, the first element inorganic layer IO1, the second element inorganic layer IO2, and the third element inorganic layer IO3 appear to be formed on the same layer. However, in the manufacturing process of the display device 10, the first element inorganic layer IO1 can be formed after the first light-emitting element ED1, the second element inorganic layer IO2 can be formed after the second light-emitting element ED2, and the third element inorganic layer IO3 can be formed after the third light-emitting element ED3. The manufacturing process will be described later.

[0163] The thin-film encapsulation layer TFEL can be disposed on the display element layer EML. The thin-film encapsulation layer TFEL may include an organic encapsulation layer TFE1 and an inorganic encapsulation layer TFE3.

[0164] In this embodiment, the organic encapsulation layer TFE1 can be disposed on the inorganic layer IO of the component. In this embodiment, the organic encapsulation layer TFE1 can, for example, completely contact and cover the first inorganic layer IO1, the second inorganic layer IO2, and the third inorganic layer IO3.

[0165] The organic encapsulation layer TFE1 can flatten the stepped portion formed according to the contour of the lower structure. The organic encapsulation layer TFE1 can fill the space between the auxiliary electrode AX and the first dam layer BN1 in the portion superimposed with the non-emitting region NLA.

[0166] The organic encapsulation layer TFE1 may include polymeric materials. In embodiments, the organic encapsulation layer TFE1 may include, for example, acrylic resin, silicone resin, epoxy resin, silicone-acrylic resin, polyimide, or polyethylene.

[0167] The inorganic encapsulation layer TFE3 can be disposed on the organic encapsulation layer TFE1. The inorganic encapsulation layer TFE3 can protect the underlying structure from moisture and oxygen penetration. According to an embodiment, the inorganic encapsulation layer TFE3 can be omitted.

[0168] The inorganic encapsulation layer TFE3 may include or be composed of inorganic insulating materials. In embodiments, the inorganic encapsulation layer TFE3 may include, for example, any one of silicon nitride, silicon oxide, and silicon oxynitride, or be composed of, for example, any one of silicon nitride, silicon oxide, and silicon oxynitride.

[0169] Figure 7 yes Figure 6 An enlarged sectional view of region A.

[0170] Apart from Figures 1 to 6 In addition, refer to Figure 7 The embankment structure BN can have an asymmetrical structure in the portion facing the anode contact hole ACTH and the portion opposite to the anode contact hole ACTH.

[0171] In an embodiment, in the portion facing the anode contact hole ACTH, the second side surface 1d of the first dam layer BN1, the second side surface 2d of the second dam layer BN2, and the second side surface 3d of the third dam layer BN3 can be arranged on the same line. The above arrangement on the same line can have the same meaning as alignment or extension for arrangement.

[0172] The second side surface 1d of the first diaphragm layer BN1, the second side surface 2d of the second diaphragm layer BN2, and the second side surface 3d of the third diaphragm layer BN3 are formed by the same etching process in the manufacturing process of the display device 10, and therefore can be disposed on the same line. The manufacturing process will be described later.

[0173] In an embodiment, in the portion opposite to the portion facing the anode contact hole ACTH, the first side surface 3c of the third dam layer BN3 may protrude significantly more than the first side surface 2c of the second dam layer BN2 in the first direction DR1. That is, the third dam layer BN3 may include a tip that protrudes significantly more than the first side surface 2c of the second dam layer BN2 in the first direction DR1. Redundant descriptions are omitted.

[0174] In an embodiment, the cathode electrode CE may be configured to contact and lie on the first side surface 3c of the third dam layer BN3. Furthermore, the auxiliary electrode AX may contact the tip of the third dam layer BN3, and further, the auxiliary electrode AX may contact the second dam layer BN2.

[0175] In an embodiment, the first side surface 2c of the second dam layer BN2 may include a first portion 2ca and a second portion 2cb, depending on the contact portion. The first portion 2ca may be the portion in contact with the auxiliary electrode AX, and the second portion 2cb may be the portion in contact with the organic encapsulation layer TFE1.

[0176] In this embodiment, the contact area between the auxiliary electrode AX and the dam structure BN can be larger than the contact area between the cathode electrode CE and the dam structure BN.

[0177] In this embodiment, the first dam layer BN1, the second dam layer BN2, and the third dam layer BN3 may be spaced apart from the anode planarization layer APL, and the first element insulating layer PDL1 is disposed between the first dam layer BN1, the second dam layer BN2, and the third dam layer BN3 and the anode planarization layer APL. The first dam layer BN1, the second dam layer BN2, and the third dam layer BN3 may be configured to surround the anode planarization layer APL. The first element insulating layer PDL1 may completely contact and cover the second side surface 1d of the first dam layer BN1, the second side surface 2d of the second dam layer BN2, and the second side surface 3d of the third dam layer BN3.

[0178] The second element insulating layer PDL2 can cover the edge of the anode electrode AE ​​and can also contact the first element insulating layer PDL1.

[0179] The anode electrode AE ​​can include a first portion ap1 and a second portion ap2, depending on the stacked portion. The first portion ap1 can be the portion that contacts or is stacked with the anode planarization layer APL, and the second portion ap2 can be the portion that contacts or is stacked with the first element insulating layer PDL1. The first portion ap1 can be the central portion of the anode electrode AE, and the second portion ap2 can be the edge portion of the anode electrode AE.

[0180] In an embodiment, the anode planarization layer APL may include a first surface a11 facing the anode electrode AE. The first surface a11 of the anode planarization layer APL may extend in a first direction DR1 to be aligned with the first surface p11 of the first element insulating layer PDL1. The first surface p11 of the first element insulating layer PDL1 may be the surface facing the anode electrode AE. The first surface a11 of the anode planarization layer APL may have a polished surface. A detailed description thereof will follow later.

[0181] Figure 8 yes Figure 7 A magnified plan view of region C.

[0182] Apart from Figures 1 to 7 In addition, refer to Figure 8 In this embodiment, the anolyte layer APL can be formed by performing a CMP process during the manufacturing process. This could mean that a portion of the anolyte layer APL is physically or chemically polished using a CMP process. Therefore, the first surface a11 of the anolyte layer APL can include physically or chemically polished surface characteristics.

[0183] In an embodiment, the first surface a11 of the anode planarization layer APL may have surface characteristics, for example, rougher or more curved than the first surface b11 of the anode electrode AE ​​formed by the deposition process. The shapes of the first surface a11 of the anode planarization layer APL and the first surface b11 of the anode electrode AE ​​can be examined using a cross-sectional analysis apparatus such as a focused ion beam or a scanning electron microscope.

[0184] Figure 9 It is shown Figure 7 A plan view showing the arrangement of the embankment structure, the anode planarization layer, and the first element insulation layer.

[0185] Apart from Figures 1 to 8 In addition, refer to Figure 9 The anode planarization layer (APL) can be disposed in the portion of the planar view that overlaps with the emitter region (EA) and / or the opening (OP) and / or the anode contact hole (ACTH). The anode planarization layer (APL) may not overlap with the non-emitter region (NLA) in the planar view.

[0186] The first element insulating layer PDL1 can expose the anode planarization layer APL in the plan view, and the first element insulating layer PDL1 can be configured to surround the anode planarization layer APL in the plan view. The first element insulating layer PDL1 can cover the entire third dam layer BN3 of the dam structure BN in the plan view.

[0187] The dam structure BN can be spaced apart from the anode planarization layer APL in a plan view, and the first element insulating layer PDL1 is placed between the dam structure BN and the anode planarization layer APL. The dam structure BN can also be configured to surround the anode planarization layer APL in a plan view.

[0188] Specifically, in the planar view, the third dam layer BN3 of the dam structure BN can be configured to surround the anode planarization layer APL and can be formed in an island-shaped conductive pattern. Furthermore, in the planar view, the first dam layer BN1 of the dam structure BN can be configured to surround the anode planarization layer APL and can be entirely formed in the portion superimposed with the non-emitting region NLA. In the planar view, a portion of the first dam layer BN1 can be covered by the third dam layer BN3.

[0189] Figure 10 It shows the manufacturing process. Figure 5 The flowchart shows the method for displaying the element layer.

[0190] Reference Figure 10 In an embodiment, the method S1 for manufacturing a display element layer EML included in the display device 10 may include: defining an anode contact hole that penetrates a dam structure and a first element insulating layer (operation S100); forming an anode planarization layer and an anode electrode (operation S200); forming a tip of the dam structure after a second element insulating layer defining an opening is defined (operation S300); and forming a light-emitting layer, a cathode electrode, an auxiliary electrode, and an element inorganic layer on the anode electrode (operation S400).

[0191] Figures 11 to 13 It is shown Figure 10 The sectional view of operation S100.

[0192] Reference Figures 11 to 13 The operation S100, which defines the anode contact hole that defines the penetrating dike structure and the insulating layer of the first element, will be described.

[0193] First, a plurality of second connection electrodes CNE2 are formed on the first via layer VIA1, and a second via layer VIA2, a third insulating layer ILD3, and a dam structure BN are integrally formed. The dam structure BN may include a first dam layer BN1, a second dam layer BN2, and a third dam layer BN3 stacked in this order.

[0194] In this process, the second dam layer BN2 and the third dam layer BN3 may comprise materials different from each other. In an embodiment, the third dam layer BN3 may comprise, for example, a material having higher etch resistance than the second dam layer BN2. Redundant descriptions are omitted.

[0195] Although not shown in the accompanying drawings, a transistor layer TFTL including a first via layer VIA1 and a second via layer VIA2 can be formed on the substrate SUB, and the predetermined structure of the transistor layer TFTL is consistent with... Figure 5 The structures shown are the same.

[0196] Next, a photoresist PR1 is formed on the third diaphragm layer BN3, and a first etching process is performed. In this process, multiple photoresist PR1s can be formed, and the multiple photoresist PR1s can be disposed in the portion not superimposed with the second connecting electrode CNE2.

[0197] In this process, the first etching process can be performed as a dry etching process. In an embodiment, the dry etching process can be performed using a reactive ion etching (“RIE”) process that uses a reactive gas (such as CHF3, CH3F, CH2F2, C2HF5, CF4, C2F6, or C3F6) and a sputtering gas (such as Ar or O2 / Ar). In this case, an inductively coupled plasma (“ICP”) source or a capacitively coupled plasma (“CCP”) source can be used as the plasma source.

[0198] like Figure 12 As shown, the dam structure BN, which is not stacked with the photoresist PR1, can be removed in one step, thus defining the hole HOL1. The side surfaces of the first dam layer BN1 facing the hole HOL1, the side surfaces of the second dam layer BN2 facing the hole HOL1, and the side surfaces of the third dam layer BN3 facing the hole HOL1 can be arranged on the same line.

[0199] In this process, the third insulating layer ILD3 can be exposed in the portion that overlaps with the hole HOL1.

[0200] Although not shown in the attached figures, photoresist PR1 can be removed by an ashing process.

[0201] Next, a first element insulating layer PDL1 is formed on the embankment structure BN. The first element insulating layer PDL1 can be formed integrally, and it can completely cover the side surfaces of the first embankment layer BN1 facing the hole HOL1, the second embankment layer BN2 facing the hole HOL1, and the third embankment layer BN3 facing the hole HOL1. Furthermore, the first element insulating layer PDL1 can cover the third insulating layer ILD3 in the portion overlapping with the hole HOL1.

[0202] In this process, the process of forming the first element insulating layer PDL1 can be performed as a film-forming process (e.g., deposition process) for forming at least one of the above-mentioned inorganic materials.

[0203] Next, a photoresist PR2 is formed on the first element insulating layer PDL1, and a second etching process is performed. Multiple photoresist PR2s can be formed, and these multiple photoresist PR2s can be disposed in portions not overlapping with the hole HOL1. In an embodiment, the second etching process can be performed, for example, a dry etching process. Redundant descriptions are omitted.

[0204] like Figure 13 As shown, in this process, the first element insulating layer PDL1 and the third insulating layer ILD3, which are not stacked with the photoresist PR2, can be removed in one step. Therefore, the anode contact hole ACTH can be defined. In the portion stacked with the anode contact hole ACTH, the second connection electrode CNE2 can be exposed.

[0205] Although not shown in the attached figures, the photoresist PR2 can be removed by an ashing process.

[0206] Figures 14 to 17 It is shown Figure 10 The sectional view of operation S200.

[0207] Reference Figures 14 to 17 The operation S200 describes the formation of the anode planarization layer and the anode electrode.

[0208] First, an anode planarization layer APL is formed on the first element insulating layer PDL1.

[0209] In this process, the process of forming the anolyte planarization layer (APL) can be performed as a film-forming process (e.g., sputtering) for forming at least one of the aforementioned metallic materials.

[0210] In this process, the anode planarization layer APL can completely contact and cover the second connecting electrode CNE2 exposed in the portion superimposed with the anode contact hole ACTH. Furthermore, the anode planarization layer APL can be formed to have a height that completely fills the stepped portion St included in the anode contact hole ACTH in the portion superimposed with it.

[0211] Next, a CMP process is performed. In an embodiment, a CMP process refers to a process of polishing and planarizing a surface with unevenness or curvature using, for example, chemical / mechanical components. In an embodiment, the CMP process performed in this process can be, for example, a metal CMP process.

[0212] like Figure 15 As shown, in this process, a portion of the anolyte layer APL can be polished and removed, and the anolyte layer APL can include a first surface a11 in the portion overlapping with the anode contact hole ACTH. As described above, the first surface a11 of the anolyte layer APL can have polished surface characteristics (e.g., a rough surface or a curved surface).

[0213] Because of this process, the anode planarization layer APL can fill the stepped portion St of the anode contact hole ACTH, thus planarizing the stepped portion St formed by the anode contact hole ACTH.

[0214] This process allows for the formation of multiple anode planarization layers (APLs), which can be spaced apart from each other. The APLs do not need to be located in portions not overlapping with the anode contact holes (ACTH).

[0215] The anode planarization layer APL can be separated from the dam structure BN by the first element insulating layer PDL1, and the dam structure BN can be configured to surround the anode planarization layer APL.

[0216] Next, as Figure 16 As shown, an anode electrode AE ​​is formed on the first element insulating layer PDL1 and the anode planarization layer APL. The anode electrode AE ​​can be formed integrally, and the anode electrode AE ​​can completely cover the anode planarization layer APL.

[0217] In this process, the process of forming the anode electrode AE ​​can be performed as a film-forming process (e.g., sputtering) for forming at least one of the aforementioned metallic materials.

[0218] Next, a photoresist PR3 is formed on the anode electrode AE, and a third etching process is performed. In this process, multiple photoresist PR3s can be formed, and the multiple photoresist PR3s can be disposed in the portion overlapping with the anode contact hole ACTH. In an embodiment, the third etching process can be performed as at least one of, for example, a dry etching process and a wet etching process.

[0219] In some embodiments, a wet etching process may be performed, for example, using a liquid chemical solution (such as a diluted hydrofluoric acid solution, nitric acid solution, tetramethylammonium hydroxide solution, or potassium hydroxide solution).

[0220] like Figure 17 As shown, due to this process, the anode electrode AE, which is not stacked with the photoresist PR3, can be removed, thus allowing the anode electrode AE ​​to be patterned. In this process, the first surface a11 of the anode planarization layer APL can be completely covered by the anode electrode AE.

[0221] Although not shown in the attached figures, the photoresist PR3 can be removed by an ashing process.

[0222] Figures 18 to 21 It is shown Figure 10 The sectional view of operation S300.

[0223] Reference Figures 18 to 21 The operation S300, which describes the formation of the tip of the dam structure after the insulating layer of the second element defining the opening, is defined.

[0224] First, a second element insulating layer PDL2 is formed on the anode electrode AE ​​and the first element insulating layer PDL1. In this process, the second element insulating layer PDL2 can cover the entire anode electrode AE ​​and the first element insulating layer PDL1.

[0225] Next, a photoresist PR4 is formed on the second element insulating layer PDL2, and a fourth etching process is performed. In this process, multiple photoresist PR4s can be formed, and these multiple photoresist PR4s can be disposed in portions not overlapping with the anode contact hole ACTH. In an embodiment, the fourth etching process can be performed, for example, as a dry etching process. Redundant descriptions are omitted.

[0226] like Figure 19 As shown, in this process, the second element insulating layer PDL2, which is not stacked with the photoresist PR4, can be removed, thus forming the opening OP. In other words, the opening OP can be defined by the second element insulating layer PDL2, and the second element insulating layer PDL2 can be configured to surround the opening OP. The anode electrode AE ​​can be exposed in the portion stacked with the opening OP.

[0227] Although not shown in the attached figures, the photoresist PR4 can be removed by an ashing process.

[0228] Next, a photoresist PR5 is formed on the anode electrode AE ​​and the second element insulating layer PDL2, and a fifth etching process is performed. In this process, multiple photoresist PR5s can be formed, and these multiple photoresist PR5s can be disposed in portions overlapping with the anode contact hole ACTH and / or the opening OP. In an embodiment, the fifth etching process can be performed, for example, as a dry etching process. Redundant descriptions are omitted.

[0229] like Figure 20 As shown, in this process, the second element insulating layer PDL2, the first element insulating layer PDL1, the second dam layer BN2, and the third dam layer BN3, which are not stacked with the photoresist PR5, can be removed in one step, thus defining the hole HOL2. The hole HOL2 can be defined in the portion that is not stacked with the anode contact hole ACTH. The side surfaces of the second element insulating layer PDL2 facing the hole HOL2, the side surfaces of the first element insulating layer PDL1 facing the hole HOL2, the side surfaces of the second dam layer BN2 facing the hole HOL2, and the side surfaces of the third dam layer BN3 facing the hole HOL2 can be arranged on the same line. In other words, in this process, the second element insulating layer PDL2, the first element insulating layer PDL1, the second dam layer BN2, and the third dam layer BN3, which are not stacked with the photoresist PR5, can be removed isotropically.

[0230] In this process, the first embankment layer BN1 superimposed on the hole HOL2 can be exposed.

[0231] Although not shown in the attached diagram, photoresist PR5 can be removed by an ashing process.

[0232] Next, a photoresist PR6 is formed on the anode electrode AE ​​and the second element insulating layer PDL2, and a sixth etching process is performed. In this process, multiple photoresist PR6s can be formed, and these multiple photoresist PR6s can be disposed in portions overlapping with the anode contact hole ACTH and / or opening OP. The photoresist PR6 can cover the entire top surface of the anode electrode AE ​​and the second element insulating layer PDL2. In an embodiment, the sixth etching process can be performed, for example, as a wet etching process. Redundant descriptions are omitted.

[0233] In this process, the second dam layer BN2 and the third dam layer BN3, which comprise different metallic materials, can differ in their etching selectivity. Specifically, in the same etching process, the third dam layer BN3 can have higher etching resistance than the second dam layer BN2. In other words, in the same etching process, the second dam layer BN2 can comprise a material with a higher etching rate than the third dam layer BN3.

[0234] Therefore, as Figure 21 As shown, the third dam layer BN3 may include a tip that protrudes significantly beyond the first side surface 2c of the second dam layer BN2 in the first direction DR1. The first element insulating layer PDL1 and the second element insulating layer PDL2 may be stacked on the tip of the third dam layer BN3 in the third direction DR3. Redundant descriptions are omitted.

[0235] Although not shown in the attached figures, photoresist PR6 can be removed by an ashing process.

[0236] Figures 22 to 25 It is shown Figure 10 The operation of the S400 sectional view.

[0237] Reference Figures 22 to 25 The operation S400 describes the formation of a light-emitting layer, a cathode electrode, an auxiliary electrode, and an inorganic layer of components on the anode electrode.

[0238] Next, a first light-emitting layer EL1, a cathode electrode CE, and an auxiliary electrode AX are deposited on the anode electrode AE ​​to form a first light-emitting element ED1.

[0239] In this process, the formation of the first light-emitting layer EL1 can be performed as a thermal deposition process. In this process, the material forming the first light-emitting layer EL1 can be formed not only on the anode electrode AE ​​stacked with the first emission region EA1, but also on the anode electrode AE ​​disposed in the portion stacked with the second emission region EA2 and the third emission region EA3. The first light-emitting layers EL1 disposed in the portions stacked with the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be spaced apart from each other.

[0240] Furthermore, the material forming the first light-emitting layer EL1 can also be formed on the first diaphragm layer BN1. The materials forming the first light-emitting layer EL1 disposed on the anode electrode AE ​​and the materials forming the first light-emitting layer EL1 disposed on the first diaphragm layer BN1 can be spaced apart from each other. The material forming the first light-emitting layer EL1 disposed on the first diaphragm layer BN1 can also be referred to as an organic patterned ELP.

[0241] In this process, the cathode electrode CE can be formed by thermal deposition or sputtering. The process for forming the cathode electrode CE can have higher step coverage characteristics than the process for forming the first light-emitting layer EL1. Therefore, the cathode electrode CE can cover the entire first light-emitting layer EL1.

[0242] In this process, the material forming the cathode electrode CE can be formed not only on the first light-emitting layer EL1 superimposed on the first emission region EA1, but also on the portion of the first light-emitting layer EL1 superimposed on the second emission region EA2 and the third emission region EA3. The cathode electrodes CE disposed in the portions superimposed on the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be spaced apart from each other.

[0243] Furthermore, the material forming the cathode electrode CE can be formed not only on the first light-emitting layer EL1, but also on the organic pattern ELP. The materials forming the cathode electrode CE on the first light-emitting layer EL1 and the materials forming the cathode electrode CE on the organic pattern ELP can be spaced apart from each other. The material forming the cathode electrode CE on the first diaphragm layer BN1 can also be referred to as the electrode pattern CEP.

[0244] In this process, the cathode electrode CE can contact the tip of the third dam layer BN3. Redundant descriptions are omitted.

[0245] In this process, the formation of the auxiliary electrode AX can be performed as a sputtering process. The process for forming the auxiliary electrode AX can exhibit higher step coverage characteristics than the process for forming the cathode electrode CE. Therefore, the auxiliary electrode AX can be formed integrally.

[0246] In other words, the material forming the auxiliary electrode AX can be formed not only on the cathode electrode CE, but also on the electrode pattern CEP, and the auxiliary electrode AX formed on the cathode electrode CE and the auxiliary electrode AX formed on the electrode pattern CEP can be integrated.

[0247] In this process, the material forming the auxiliary electrode AX can contact the tip of the third dam layer BN3 and the first side surface 2c of the second dam layer BN2. Redundant descriptions are omitted.

[0248] Next, an inorganic layer IO is formed on the auxiliary electrode AX. The inorganic layer IO can cover the outline of the underlying structure with a uniform thickness and can cover the entire auxiliary electrode AX.

[0249] In this process, the process of forming the inorganic layer IO of the element can be performed as a film-forming process (e.g., deposition process) for forming at least one of the above-mentioned inorganic materials.

[0250] Next, as Figure 23 and Figure 24 As shown, a photoresist PR7 is formed in the first emission region EA1 and the portion overlapping with the peripheral portion of the first emission region EA1, and the photoresist PR7 is used as a mask to perform the seventh etching process.

[0251] In this process, the materials that form the first light-emitting layer EL1, which are not stacked with the photoresist PR7, the materials that form the cathode electrode CE, which are not stacked with the photoresist PR7, the materials that form the auxiliary electrode AX, which are not stacked with the photoresist PR7, and the materials that form the element inorganic layer IO, which are not stacked with the photoresist PR7, can be removed in one step.

[0252] Therefore, the anode electrode AE ​​superimposed with the second emission region EA2 and the anode electrode AE ​​superimposed with the third emission region EA3 can be exposed again, and the element inorganic layer IO can be formed in the form of the first element inorganic layer IO1.

[0253] In this process, the organic pattern ELP and electrode pattern CEP disposed on the first diaphragm layer BN1 can be removed. Therefore, the first element inorganic layer IO1 can be spaced apart from the first diaphragm layer BN1 on the third-direction DR3.

[0254] Therefore, a first light-emitting element ED1 and a first element inorganic layer IO1 can be formed in the portion superimposed with the first emission region EA1.

[0255] Next, the above process is repeated to form a second light-emitting layer EL2, a cathode electrode CE, an auxiliary electrode AX, and an element inorganic layer IO on the anode electrode AE ​​superimposed on the second emitting region EA2. Due to this process, a second light-emitting element ED2 and a second element inorganic layer IO2 superimposed on the second emitting region EA2 can be formed.

[0256] Furthermore, the above process is repeated to form a third light-emitting layer EL3, a cathode electrode CE, an auxiliary electrode AX, and an inorganic element layer IO on the anode electrode AE ​​superimposed on the third emission region EA3. This process allows the formation of a third light-emitting element ED3 and a third inorganic element layer IO3 superimposed on the third emission region EA3.

[0257] Therefore, it can form Figure 5 The EML layer of the display element is shown stacked with the ACTH anode contact hole. Redundant descriptions are omitted.

[0258] In the display device 10 of the embodiment, the third embankment layer BN3 includes a tip, such that the first light-emitting layer EL1, the second light-emitting layer EL2 and the third light-emitting layer EL3, which are spaced apart from each other, can be formed in the portion superimposed with the first emission region EA1, the second emission region EA2 and the third emission region EA3 without the need for a separate fine metal mask.

[0259] Furthermore, in the display device 10 of the embodiment, the third dam layer BN3 includes a tip, such that the spaced-apart cathode electrodes CE can be formed in the portion superimposed with the first emission region EA1, the second emission region EA2, and the third emission region EA3 without the need for a separate fine metal mask. Therefore, the display device 10 of the embodiment can have ease of manufacture.

[0260] Furthermore, the display device 10 of the embodiment includes an anode planarization layer APL, which fills the anode contact hole ACTH in the portion overlapping with the anode contact hole ACTH, thereby planarizing the stepped portion included in the anode contact hole ACTH. Therefore, the anode electrode AE ​​can be formed with a flat surface, and thus, the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 can also be formed with a uniform thickness. Therefore, the display device 10 can solve reliability defects (e.g., light-emitting layer shading defects). Other redundant descriptions are omitted.

[0261] Figure 26 This is a block diagram of an embodiment of an electronic device.

[0262] Apart from Figures 1 to 25 In addition, refer to Figure 26The display device 10 in the embodiments can be applied to various electronic devices. The electronic device 1 in the embodiments may include the display device 10 described above, and may also include modules or devices with other additional functions besides the display device 10.

[0263] The electronic device 1 in the embodiment may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0264] The processor 12 may include at least one of a central processing unit (“CPU”), an application processor (“AP”), a graphics processing unit (“GPU”), a communication processor (“CP”), an image signal processor (“ISP”), and a controller.

[0265] The memory 13 can store the data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals are transmitted to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0266] The power module 14 may include a power module such as a power adapter or battery device and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 1.

[0267] At least one of the components of the electronic device 1 described above may be included in the display device 10 in the above embodiments. Furthermore, some of the modules functionally included in a single module may be included in the display device 10, and some other modules may be disposed separately from the display device 10. In the embodiments, the display device 10 may include a display module 11, and the processor 12, memory 13, and power module 14 may be disposed in the electronic device 1 as, for example, other devices besides the display device 10.

[0268] Figure 27 This is a schematic diagram of an embodiment of an electronic device.

[0269] Reference Figure 27 Various electronic devices using the display device 10 in the embodiments may include not only image display electronic devices (such as smartphones 1_1a, tablet PCs 1_1b, laptop computers 1_1c, televisions (“TV”) 1_1d, and desktop monitors 1_1e), but also wearable electronic devices (such as smart glasses 1_2a, head-mounted displays 1_2b, or smartwatches 1_2c) and vehicle electronic devices 1_3 (such as central information displays (“CID”) or interior mirror displays located on the dashboard, center instrument panel, and dashboard of a vehicle) containing display modules.

[0270] The disclosed embodiments should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the disclosed concepts to those skilled in the art.

[0271] Although the disclosure has been specifically shown and described with reference to the disclosed embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit or scope of the disclosure as defined by the claims.

Claims

1. A display device, the display device comprising: The substrate includes both emitting and non-emitting regions; A dam structure is disposed on the emission area of ​​the substrate and has a cantilever structure, and an anode contact hole superimposed on the emission area penetrates the dam structure; A connecting electrode is disposed between the substrate and the embankment structure in the portion overlapping with the anode contact hole; A first element insulating layer is disposed on the dam structure, stacked with the anode contact hole, and covering the side surface of the dam structure; The anode electrode is disposed on the insulating layer of the first element; An anode planarization layer is disposed between the connecting electrode and the anode electrode in the portion overlapping with the anode contact hole; as well as The second element insulating layer covers the edge of the anode electrode, defines an opening, and contacts the first element insulating layer.

2. The display device according to claim 1, wherein, The dike structure includes: First dike layer; The second dike layer is constructed on top of the first dike layer; and The third dam layer includes a tip that protrudes significantly beyond the first side surface of the second dam layer towards the non-emissive region. The anode planarization layer is stacked with the anode contact hole and penetrates the first dam layer, the second dam layer, and the third dam layer.

3. The display device according to claim 2, wherein, The anode planarization layer is spaced apart from the first dam layer, the second dam layer, and the third dam layer, and the first element insulating layer is placed between the anode planarization layer and the first dam layer to the third dam layer.

4. The display device according to claim 2, further comprising: A first light-emitting layer is disposed on the anode electrode and completely covers the insulating layer of the second element; A cathode electrode is disposed on the first light-emitting layer; as well as An auxiliary electrode is disposed on the cathode electrode and in contact with the tip of the third dam layer.

5. The display device according to claim 4, wherein, The auxiliary electrode contacts the first side surface of the second dike layer, and In the portion superimposed with the non-emission region, the auxiliary electrode is spaced apart from the first embankment in a direction perpendicular to the substrate.

6. The display device according to claim 1, wherein, The anode planarization layer contacts the anode electrode and the connecting electrode, and The anode planarization layer is electrically connected to the anode electrode and the connecting electrode.

7. The display device according to claim 6, further comprising: A transistor is disposed between the substrate and the connecting electrode. The anode electrode is connected to the transistor via the anode planarization layer and the connection electrode.

8. The display device according to claim 1, wherein, The anode planarization layer completely fills the anode contact hole.

9. The display device according to claim 1, wherein, The anode planarization layer comprises a transparent conductive material.

10. The display device according to claim 1, wherein, The anode planarization layer includes a first surface facing the anode electrode, and The first surface is completely covered by the anode electrode.

11. The display device according to claim 1, wherein, In the plan view, the first element insulating layer exposes the anode planarization layer, and In the plan view, the insulating layer of the first element completely surrounds the anode planarization layer.

12. The display device according to claim 11, wherein, In the plan view, the embankment structure is spaced apart from the anode planarization layer, and the first element insulating layer is placed between the embankment structure and the anode planarization layer. In the plan view, the embankment structure completely surrounds the anode planarization layer.

13. A method for manufacturing a display device, the method comprising the following steps: The anode contact hole is defined to penetrate the dike structure and the insulating layer of the first element; Forming an anode planarization layer and an anode electrode; The tip of the dike structure is formed after the second element insulating layer defining the opening is formed; as well as A light-emitting layer, a cathode electrode, an auxiliary electrode, and an inorganic layer of components are formed on the anode electrode.

14. The method according to claim 13, wherein, In the steps of forming the anode planarization layer and the anode electrode A portion of the anolyte planarization layer is removed by performing a chemical mechanical polishing process. The anode planarization layer includes a first surface that contacts the anode electrode, and The first surface includes a surface polished by the chemical mechanical polishing process.

15. An electronic device, the electronic device comprising: A display device includes: a substrate including an emitting region and a non-emitting region; a dam structure disposed on the emitting region of the substrate and having a cantilever structure, wherein an anode contact hole overlapping the emitting region penetrates the dam structure; a connecting electrode disposed between the substrate and the dam structure in a portion overlapping the anode contact hole; a first element insulating layer disposed on the dam structure, overlapping the anode contact hole, and covering a side surface of the dam structure; an anode electrode disposed on the first element insulating layer; an anode planarization layer disposed between the connecting electrode and the anode electrode in a portion overlapping the anode contact hole; and a second element insulating layer covering an edge of the anode electrode, defining an opening, and contacting the first element insulating layer; and At least one of a display module, a processor, a memory, and a power module is connected to the display device.

16. The electronic device according to claim 15, wherein, The dike structure includes: First dike layer; The second dike layer is constructed on top of the first dike layer; and The third dam layer includes a tip that protrudes significantly beyond the first side surface of the second dam layer towards the non-emissive region. The anode planarization layer penetrates the first dam layer, the second dam layer, and the third dam layer while being superimposed on the anode contact hole.

17. The electronic device according to claim 16, wherein, The anode planarization layer is spaced apart from the first dam layer, the second dam layer, and the third dam layer, and the first element insulating layer is placed between the anode planarization layer and the first dam layer to the third dam layer.

18. The electronic device according to claim 16, wherein, The display device further includes: A first light-emitting layer is disposed on the anode electrode and completely covers the insulating layer of the second element; A cathode electrode is disposed on the first light-emitting layer; and An auxiliary electrode is disposed on the cathode electrode and in contact with the tip of the third dam layer.

19. The electronic device according to claim 15, wherein, The anode planarization layer completely fills the anode contact hole.

20. The electronic device according to claim 15, wherein, The display device further includes: A transistor is disposed between the substrate and the connecting electrode. The anode electrode is connected to the transistor via the anode planarization layer and the connection electrode.

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