Capacitor package structure and packaging method

Abstract

The application discloses a kind of capacitor packaging structure and packaging method, it is related to the field of semiconductor chip packaging.The structure includes carrier plate, temporary bonding layer, chip and capacitor, capacitor is provided with dummy silicon far from carrier plate side, and the two are fixed by adhesive layer and form capacitor-dummy silicon composite structure, the composite structure is fixed to carrier plate by temporary bonding layer with chip, and composite structure and chip thickness are consistent.The application is balanced by adding dummy silicon counterweight constraint on the side of capacitor, the impact pressure of plastic encapsulation material in the process of plastic encapsulation is balanced, and the drift of capacitor is inhibited;Two replaceable process flows are provided simultaneously, adapt to different production line layout, can significantly improve the accuracy of capacitor position and electrical connection reliability, reduce packaging defect rate, improve production yield.

Description

Technical Field

[0001] This application relates to the field of semiconductor chip packaging, and in particular to a capacitor packaging structure and packaging method. Background Technology

[0002] In the field of semiconductor chip packaging, passive components such as chip capacitors are usually integrated into the package to achieve functions such as power filtering and signal decoupling.

[0003] Current processes typically involve temporarily bonding the chip and a surface-mount capacitor to a carrier board, followed by encapsulation with epoxy resin to form a protective package. Due to the small size and light weight of surface-mount capacitors, the flowing encapsulation material generates significant impact pressure during encapsulation. The adhesive force of the temporary bonding material alone is insufficient to effectively restrain the capacitor, easily leading to displacement or even floating within the encapsulation material. This displacement results in inaccurate alignment between the subsequent redistribution layer and the capacitor pins, with some pins even covered by the encapsulation material. This reduces electrical connection reliability, increases alignment difficulty and testing costs, and severely impacts product yield and production efficiency. Summary of the Invention

[0004] To address the technical problem that surface-mount capacitors in existing semiconductor packages are prone to positional drift due to impact from the molding compound during the molding process, leading to difficulties in subsequent rewiring layer alignment and decreased electrical connection reliability, this application provides a capacitor packaging structure and packaging method. The technical solution is as follows: On one hand, a capacitor packaging structure is provided, wherein a dummy silicon is provided on the side of the capacitor away from the carrier plate, and an adhesive layer is provided between the dummy silicon and the capacitor; the dummy silicon is fixed to the capacitor through the adhesive layer to form a capacitor-dummy silicon composite structure; The chip and the capacitor-dummy silicon composite structure are fixed to a predetermined area of ​​the carrier board by a temporary bonding layer; the thickness of the capacitor-dummy silicon composite structure is the same as the thickness of the chip. The capacitor's pins are positioned facing the carrier plate.

[0005] Optionally, the carrier plate is a glass carrier plate, a silicon carrier plate, or a steel plate; The dummy silicon is a monocrystalline silicon wafer or a recycled silicon wafer. The size of the dummy silicon is adapted to the size of the capacitor. The thickness of the dummy silicon is determined according to the capacitor height and the fluidity of the molding compound.

[0006] Optionally, the adhesive layer is a high-temperature resistant modified epoxy adhesive layer, and the thickness of the adhesive layer is 10μm~30μm.

[0007] Optionally, the temporary bonding layer is a UV-release adhesive layer, and the thickness of the temporary bonding layer is 10μm~20μm.

[0008] Optionally, an underfill is provided between the capacitor and the dummy silicon, the underfill being located in the central region of the capacitor and cured.

[0009] On the other hand, a capacitor packaging structure packaging method is provided, applicable to the capacitor packaging structure described above, the method comprising: S1, An adhesive layer is provided on the upper surface of the capacitor, and the dummy silicon is bonded and fixed to the capacitor through the adhesive layer to form a capacitor-dummy silicon composite structure. S2, a temporary bonding layer is coated on the surface of the carrier board, and the chip and the capacitor-dummy silicon composite structure are placed in a preset area of ​​the carrier board with the capacitor pins facing the carrier board. The relative positions of the chip and the capacitor-dummy silicon composite structure are determined by fixing. S3 uses a transfer molding process to inject low-viscosity, high-flow epoxy resin molding compound to encapsulate the chip, capacitor-dummy silicon composite structure, and temporary bonding layer as a whole. After heat preservation and curing, it is cooled to room temperature to form a molded body. S4. The carrier board is debonded by ultraviolet irradiation, and the carrier board and temporary bonding layer are removed to expose the capacitor leads. S5, a redistribution layer is fabricated on the surface of the plastic package, so that the redistribution layer is electrically connected to the capacitor pins and chip pads; S6, solder joints are made on the surface of the redistribution layer to cut the package into individual units.

[0010] Optionally, the step of providing an adhesive layer on the upper surface of the capacitor and bonding and fixing the dummy silicon to the capacitor through the adhesive layer to form a capacitor-dummy silicon composite structure includes: Clean the upper surface of the capacitor and coat the dummy silicon with an adhesive layer of 10μm~30μm thickness; The capacitor is attached to the adhesive layer with its top surface facing down, and pressure of 0.08MPa~0.2MPa is applied. It is then cured at high temperature for 20 to 40 minutes and cut into individual units.

[0011] Optionally, the temporary bonding layer has a coating thickness of 10μm~20μm, and the chip and capacitor-dummy silicon composite structure are fixed by vacuum adsorption and ultraviolet pre-curing. The molding process involves heat preservation and curing for 30 to 50 minutes, during which the molding compound completely covers the exposed areas of the chip, the capacitor-dummy silicon composite structure, and the temporary bonding layer.

[0012] Optionally, the process of forming a redistribution layer on the surface of the molding compound includes: A titanium / copper seed layer is deposited on the surface of the molding compound using sputtering and photolithography processes; Rewire pattern is defined by photolithography; Electroplating thickens the copper layer to 5μm~10μm; Etching removes excess seed layer, forming a rewiring layer; The solder joint is a solder ball or a copper pillar.

[0013] Optionally, the method further includes: S7. First, a temporary bonding layer is coated on the surface of the carrier board, and the chip and capacitor are placed in the preset area and temporarily fixed. S8, then apply or press an adhesive layer onto the capacitor surface, mount dummy silicon to form a composite structure, making the thickness of the composite structure consistent with the thickness of the chip; fill the middle of the capacitor with high-temperature resistant filler and cure it.

[0014] Compared with the prior art, the present invention has the following significant advantages.

[0015] The structure includes a carrier substrate, a temporary bonding layer, a chip, and a capacitor. A dummy silicon layer is located on the side of the capacitor away from the carrier substrate. The two are fixed together by an adhesive layer to form a capacitor-dummy silicon composite structure. This composite structure is fixed to the carrier substrate by the chip via the temporary bonding layer, and the thickness of the composite structure is the same as that of the chip. This invention, by adding a dummy silicon weight constraint to the capacitor side, balances the impact pressure of the molding compound during molding, suppressing capacitor drift. It also provides two interchangeable process flows to adapt to different production line layouts, significantly improving capacitor positioning accuracy and electrical connection reliability, reducing packaging defect rates, and increasing production yield. Attached Figure Description

[0016] Figure 1 This is a schematic diagram illustrating the fabrication of the capacitor-dummy silicon composite structure in an embodiment of the present invention; Figure 2 This is a schematic diagram of the temporary bonding of the chip and capacitor assembly to the carrier board in an embodiment of the present invention; Figure 3 This is a schematic diagram of the encapsulated structure in an embodiment of the present invention; Figure 4 This is a schematic diagram of the finished product structure after debonding, rewiring, and solder joint fabrication in an embodiment of the present invention. Figure 5 This is a schematic diagram showing the chip and capacitor temporarily bonded to the carrier board in an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure after dummy silicone is mounted and underfill is filled in an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure after encapsulation using the transfer molding process in an embodiment of the present invention; Figure 8This is a schematic diagram of the finished product structure after debonding, rewiring, and solder joint fabrication in an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0018] In this article, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0019] This invention adds a dummy silicon counterweight structure to the side of the capacitor away from the carrier board, forming a capacitor-dummy silicon composite structure with the same height as the chip. The rigid support and counterweight effect of the dummy silicon offsets the impact of the molding compound, suppressing capacitor drift at the source and ensuring that the pins are exposed after molding, providing a reliable foundation for accurate connection of subsequent rewiring layers.

[0020] To adapt to different production line layouts and process cycles, this invention provides two alternative process flows based on the same inventive concept. Both revolve around the core anti-drift mechanism of dummy silicon counterweight constraint and equal-height structural balance. The only difference is the sequence of processes and the bottom filling method. They do not change the core technical solution and protection scope of this invention and are parallel implementations of the same invention.

[0021] Example 1

[0022] A capacitor packaging structure includes a carrier board, a temporary bonding layer, a chip, and a capacitor. A dummy silicon layer is disposed on the side of the capacitor away from the carrier board, and an adhesive layer is disposed between the dummy silicon layer and the capacitor. The dummy silicon layer is fixed to the capacitor via the adhesive layer to form a capacitor-dummy silicon composite structure. The chip and the capacitor-dummy silicon composite structure are fixed to a predetermined area of ​​the carrier board via the temporary bonding layer. The thickness of the capacitor-dummy silicon composite structure is the same as the thickness of the chip. The leads of the capacitor are oriented towards the carrier board.

[0023] like Figure 1 As shown, the dummy silicon is directly placed on the side of the capacitor away from the carrier plate. Its rigidity and weight constrain the capacitor and counteract the lateral and longitudinal impact forces brought by the flow of molding compound. Structurally, it restricts the capacitor from displacement, warping or flipping. The adhesive layer connects the dummy silicon and the capacitor as a whole, so that the two maintain their relative position under the impact of molding compound. like Figure 2As shown, the capacitor-dummy silicon composite structure maintains the same thickness as the chip, ensuring uniform force during molding compound flow and filling. This prevents capacitor displacement caused by excessively high flow rates and uneven pressure due to height differences. It also ensures a smooth surface for the molded body after molding, providing a flat base for subsequent redistribution layer fabrication. The capacitor leads are oriented towards the carrier substrate, ensuring that the leads are directly exposed on the molded body surface after debonding and removing the carrier substrate. This prevents the leads from being covered or obstructed by the molding compound, ensuring that the redistribution layer can directly and effectively contact the leads.

[0024] This embodiment utilizes a combination of rigid counterweights, integrated composite structures, equal-height structures, and pin orientation to fundamentally suppress capacitor drift during the molding process, significantly improving capacitor positioning accuracy. This provides a stable structural foundation for the precise fabrication of redistribution layers and effectively increases packaging yield.

[0025] Example 2

[0026] Furthermore, the substrate is made of glass, silicon, or steel, all of which have high flatness, high mechanical strength, and high temperature stability. They can maintain the substrate surface without deformation throughout the temporary bonding, encapsulation, and curing process, ensuring the stability of the positioning reference for the chip and capacitor.

[0027] Dummy silicon uses monocrystalline silicon wafers or recycled silicon wafers, which are consistent with the chip material and have a highly matched coefficient of thermal expansion. This can reduce the thermal stress caused by temperature changes during molding, high-temperature testing and actual use, and avoid thermal stress from causing structural cracking, interface delamination or positional displacement.

[0028] The dummy silicon size is matched with the capacitor to ensure uniform pressure transmission and avoid local stress concentration. The dummy silicon thickness is combined with the capacitor height and the flowability of the molding compound to dynamically balance the impact of the molding compound and the constraint force of the temporary bonding layer, so that the capacitor remains stable in a strong flow environment, while the overall height is consistent with the chip to ensure the flatness of the molding compound surface.

[0029] This embodiment improves the overall structural stability, thermal reliability, and process compatibility by matching materials, adapting dimensions, and adaptively setting thickness, thereby reducing the risk of packaging failure.

[0030] Example 3

[0031] Furthermore, the adhesive layer is a high-temperature resistant modified epoxy adhesive layer, and the thickness of the adhesive layer is 10μm~30μm.

[0032] like Figure 1As shown, the high-temperature modified epoxy adhesive will not cause temporary bonding layer failure within the curing temperature range, and can be adapted to subsequent high-temperature curing and molding processes. It also has high bonding strength, high insulation and low gas emission rate, which ensures long-term stable connection between dummy silicon and capacitor, and will not release impurities at high temperatures to contaminate the chip and capacitor surface.

[0033] The thickness of the adhesive layer is controlled between 10μm and 30μm. If the thickness is too small, it will easily lead to insufficient bonding area and weak bonding force. If the thickness is too large, it will cause dimensional deviation and adhesive layer overflow to contaminate the pins. This range can provide sufficient bonding strength while maintaining dimensional accuracy and interface cleanliness.

[0034] This embodiment ensures the stability of the composite structure throughout the entire process by using high-temperature resistant materials and reasonable thickness control, avoiding capacitance drift due to bonding failure and improving structural reliability.

[0035] Example 4

[0036] Furthermore, the temporary bonding layer is a UV-release adhesive layer with a thickness of 10μm~20μm.

[0037] like Figure 2 As shown, the UV release adhesive has sufficient bonding strength before UV irradiation to resist external forces from pre-molding transport, mounting, and molding material impact, ensuring that the chip and capacitor do not shift; after UV irradiation, it quickly loses its adhesion, leaving no residue or damage during the debonding process, facilitating carrier separation and reuse.

[0038] The thickness is set between 10μm and 20μm. If the thickness is too low, the adhesion will be insufficient and it will not be able to withstand the impact of molding. If the thickness is too high, it will lead to incomplete debonding and residual adhesive layer contaminating the pins and pads. This range balances the fixing strength and the convenience of debonding, ensuring positioning accuracy and the yield of subsequent processes.

[0039] This embodiment achieves stable temporary fixation and non-destructive debonding by using UV-exfoliating materials and setting appropriate thickness, simplifying the process and improving the product qualification rate.

[0040] Example 5

[0041] Furthermore, an underfill is provided between the capacitor and the dummy silicon, and the underfill is located in the middle region of the capacitor and is cured.

[0042] like Figure 6As shown, the underfill is applied to the central area of ​​the capacitor, eliminating gaps between the capacitor and the dummy silicon and preventing molding compound from entering the gaps and creating additional pressure that could cause the capacitor to lift. After curing, the underfill forms a rigid support, further enhancing the integrity of the capacitor and the dummy silicon and improving its impact resistance. At the same time, the underfill makes the capacitor surface smooth, preventing local unevenness that could cause molded material flow disturbances, uneven redistribution layer film formation, or line breakage. The underfill uses high-temperature resistant materials, which do not affect the performance of the temporary bonding layer and adhesive layer, and are compatible with the overall process flow.

[0043] This embodiment further improves the positioning accuracy and structural stability of the capacitor and reduces the process defect rate by filling gaps, rigid reinforcement, and surface leveling.

[0044] Example 6

[0045] To further realize the aforementioned capacitor packaging structure, this embodiment provides a packaging method adapted to this structure. This method, through a process of prefabricating a capacitor dummy silicon composite structure, synchronous temporary bonding, overall molding, debonding, rewiring, and cutting, transforms the aforementioned structural features into industrially feasible process steps. This ensures that the capacitor position is stable and drift-free during molding, ultimately achieving reliable exposure of the capacitor pins and precise connection for subsequent electrical connections. The method includes: S1, An adhesive layer is provided on the upper surface of the capacitor, and the dummy silicon is bonded and fixed to the capacitor through the adhesive layer to form a capacitor-dummy silicon composite structure. S1 represents the capacitor assembly prefabrication step, such as... Figure 1 As shown, the capacitor and dummy silicon are fixed first, so that the capacitor has a rigid counterweight and overall structure before entering the subsequent bonding and molding processes. This avoids the individual capacitor from drifting due to its light weight and small force-bearing area, and establishes a stable mechanical structure in advance.

[0046] In one possible implementation, step S1 includes: S11, clean the upper surface of the capacitor and coat the dummy silicon with an adhesive layer of 10μm~30μm thickness; Among them, cleaning the upper surface of the capacitor can remove oil, dust particles and oxide layer, improve interface wettability and bonding strength, and avoid bonding failure caused by interface defects; applying a 10μm~30μm adhesive layer ensures bonding area and adhesive layer uniformity.

[0047] S12, attach the capacitor with the top surface facing down to the adhesive layer, apply a pressure of 0.08MPa~0.2MPa, cure at high temperature for 20 minutes to 40 minutes, and cut into individual units.

[0048] Applying pressure of 0.08MPa~0.2MPa ensures uniform adhesive layer thickness, removes interfacial air bubbles, and improves bonding density; high-temperature curing for 20-40 minutes allows the adhesive layer to fully cross-link, achieving maximum mechanical strength and stability; cutting into independent units ensures that each composite structure has a consistent size, facilitating automated mounting and positioning.

[0049] Thus, through a complete process of cleaning, applying adhesive, bonding, pressurizing, curing, and cutting, the high precision, high consistency, and high reliability of the capacitor-dummy silicon composite structure are ensured, providing a stable foundation for subsequent processes.

[0050] S2, a temporary bonding layer is coated on the surface of the carrier board, and the chip and the capacitor-dummy silicon composite structure are placed in a preset area of ​​the carrier board with the capacitor pins facing the carrier board. The relative positions of the chip and the capacitor-dummy silicon composite structure are determined by fixing. Among them, S2 uses the carrier plate as a unified reference, such as Figure 2 As shown, the chip and composite structure are positioned synchronously to ensure relative position accuracy. The pins facing the carrier board ensure that they are fully exposed after debonding, avoiding electrical connection failure caused by the encapsulation material, and providing conditions for precise docking of the redistribution layer.

[0051] In one possible implementation, the temporary bonding layer has a coating thickness of 10μm to 20μm, and the chip and capacitor-dummy silicon composite structure are fixed by vacuum adsorption and ultraviolet pre-curing.

[0052] The molding process involves heat preservation and curing for 30 to 50 minutes, during which the molding compound completely covers the exposed areas of the chip, the capacitor-dummy silicon composite structure, and the temporary bonding layer.

[0053] The temporary bonding layer, with a thickness of 10μm~20μm, balances adhesion and debonding effects. Vacuum adsorption eliminates interface bubbles and improves bonding tightness. UV pre-curing quickly locks in position, preventing misalignment after mounting. Figure 3 As shown, the molding compound is fully cured by heat preservation for 30-50 minutes, resulting in uniform internal stress and complete coverage of all exposed areas. This prevents the chip and capacitor from coming into contact with the external environment and improves moisture resistance, shock resistance, and temperature resistance.

[0054] Therefore, by using precise positioning processes and sufficient curing conditions, the accuracy of structural positioning and the reliability of the molded body are improved, and packaging defects are reduced.

[0055] S3 uses a transfer molding process to inject low-viscosity, high-flow epoxy resin molding compound to encapsulate the chip, capacitor-dummy silicon composite structure, and temporary bonding layer as a whole. After heat preservation and curing, it is cooled to room temperature to form a molded body. Among them, such as Figure 3As shown, the transfer molding process has stable pressure and uniform filling. The low-viscosity, high-flow epoxy resin can quickly fill the cavity without generating large impact disturbances. Heat preservation and curing allow the molding compound to fully cross-link and form a dense structure. Cooling to room temperature allows the molded body to stabilize in size and release internal stress, avoiding shrinkage deformation that could cause capacitor displacement.

[0056] S4. The carrier board is debonded by ultraviolet irradiation, and the carrier board and temporary bonding layer are removed to expose the capacitor leads. Among them, UV debonding is gentle and non-destructive, which can completely preserve the molded body, chip and capacitor structure. After removing the temporary bonding layer, the pins are clearly exposed, with no glue residue or obstruction, ensuring stable contact resistance between the redistribution layer and the pins.

[0057] S5, a redistribution layer is fabricated on the surface of the plastic package, so that the redistribution layer is electrically connected to the capacitor pins and chip pads; Among them, such as Figure 4 As shown, the redistribution layer enables circuit conduction between the chip and the capacitor, and performs electrical functions such as filtering and decoupling. A precisely aligned redistribution layer can reduce line resistance, reduce signal loss, and improve the overall electrical performance of the package.

[0058] In one possible implementation, step S5 includes: S51 uses sputtering and photolithography processes to deposit a titanium / copper seed layer on the surface of the molding compound; S52, defines the rewiring pattern through photolithography; S53, electroplating thickens the copper layer to 5μm~10μm; S54, etching to remove excess seed layer and form rewiring layer; The solder joint is a solder ball or a copper pillar.

[0059] Among them, such as Figure 4 As shown, sputtered titanium / copper seed layers improve coating adhesion and conductivity uniformity, photolithography defines patterns to ensure circuit precision and alignment accuracy; electroplated copper layers up to 5-10μm ensure sufficient current carrying capacity, mechanical strength and anti-aging performance; etching removes excess seed layers to achieve electrical isolation between circuits and avoid short circuits; solder balls or copper pillars are compatible with mainstream mounting processes, with high connection strength and good conductivity.

[0060] Therefore, by using a complete redistribution process, a low-loss, highly reliable electrical connection between the chip and the capacitor is achieved, ensuring stable package electrical performance.

[0061] S6, solder joints are made on the surface of the redistribution layer to cut the package into independent units; The solder joints provide external electrical and mechanical interfaces, and the dicing separates the wafer-level package into individual finished products, enabling mass production.

[0062] This embodiment, without altering the traditional packaging process, only adds a prefabrication composite structure step, which can significantly suppress capacitor drift, improve positional accuracy, electrical connection reliability, and production yield, making it suitable for large-scale industrial applications.

[0063] Example 7

[0064] To adapt to different production line process cycles and equipment configurations, this embodiment provides an optional process flow based on the same core principle, building upon the packaging method described in Embodiment 6. This solution continues the anti-drift design concept of dummy silicon weight constraint and equal-height structural balance, only adjusting the sequence of process steps: First, the chip and capacitor are temporarily bonded, then dummy silicon is mounted and underfill is filled. Without changing the key steps such as encapsulation, debonding, and rewiring, the process adaptability and capacitor positioning accuracy are further improved. Both the chip and capacitor are developed around the same invention purpose, providing a flexible option for actual production.

[0065] Therefore, the method further includes: S7. First, a temporary bonding layer is coated on the surface of the carrier board, and the chip and capacitor are placed in the preset area and temporarily fixed. S7 is an alternative process to replace the original S1 and S2. The original scheme was to first prepare the capacitor-dummy silicon composite structure and then perform temporary bonding. The current scheme is to first temporarily bond the chip and the capacitor separately.

[0066] like Figure 5 As shown, the carrier material, temporary bonding layer material, thickness, and UV pre-curing conditions are consistent with the original scheme. The positioning benchmark and accuracy requirements are also the same as the original scheme. The overall process architecture is not changed, only the process sequence is adjusted to adapt to different production line layouts and equipment conditions.

[0067] S8. Then apply or press an adhesive layer onto the capacitor surface and mount dummy silicon to form a composite structure, so that the thickness of the composite structure is consistent with the thickness of the chip. Among them, such as Figure 6 As shown, the S8 mounts the dummy silicon after the capacitor has completed temporary bonding and positioning. The adhesive layer can be applied by smearing or pressing, resulting in more uniform coating and tighter adhesion. After mounting, the thickness of the composite structure is strictly controlled to be consistent with the chip, continuing the advantage of equal height balance and anti-drift.

[0068] S9, fill the middle of the capacitor with high-temperature resistant filler and cure it.

[0069] Filling the middle of the capacitor with high-temperature resistant filler and curing it can further eliminate the gap between the capacitor and the dummy silicon, strengthen the rigid connection, and level the surface, making the capacitor more stable under the impact of plastic encapsulation.

[0070] like Figure 7 As shown, the process parameters, material selection, and structural requirements of the S3 molding process in this solution are consistent with the original solution. The molding compound also completely covers the chip, composite structure, and exposed area of ​​the temporary bonding layer. The subsequent S4 debonding, S5 rewiring, and S6 solder joint fabrication and cutting steps are also the same as the original solution, and the corresponding finished product structure is as follows. Figure 8 As shown, the final product structure is consistent with the original plan.

[0071] In the attached diagrams of this plan, Figures 5-8 Corresponding to this alternative plan, and the original plan Figures 1-4 Two complete process flow diagrams are formed, and the two schemes share the same structural principles and anti-drift mechanisms.

[0072] This embodiment provides a second alternative process flow, which, while retaining all the structural advantages and technical effects of the original solution, further enhances the flexibility and adaptability of the process. It can be freely selected according to the production line cycle time, equipment configuration, and capacity requirements. Both solutions can achieve precise capacitor positioning, no drift, no obstruction, and highly reliable electrical connection. At the same time, they have stronger thermal stability, better process compatibility, and more significant yield improvement, effectively reducing production costs and improving production efficiency.

[0073] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0074] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware, or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk. The above are merely optional embodiments of this application and are not intended to limit the application. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A capacitor packaging structure, characterized in that, The structure includes a carrier board, a temporary bonding layer, a chip, and a capacitor; A dummy silicon layer is provided on the side of the capacitor away from the carrier plate, and an adhesive layer is provided between the dummy silicon layer and the capacitor; the dummy silicon layer is fixed to the capacitor through the adhesive layer to form a capacitor-dummy silicon composite structure. The chip and the capacitor-dummy silicon composite structure are fixed to a predetermined area of ​​the carrier board by a temporary bonding layer; the thickness of the capacitor-dummy silicon composite structure is the same as the thickness of the chip. The capacitor's pins are positioned facing the carrier plate.

2. The capacitor packaging structure according to claim 1, characterized in that, The carrier plate is a glass carrier plate, a silicon carrier plate, or a steel plate; The dummy silicon is a monocrystalline silicon wafer or a recycled silicon wafer. The size of the dummy silicon is adapted to the size of the capacitor. The thickness of the dummy silicon is determined according to the capacitor height and the fluidity of the molding compound.

3. The capacitor packaging structure according to claim 1, characterized in that, The adhesive layer is a high-temperature resistant modified epoxy adhesive layer with a thickness of 10μm~30μm.

4. The capacitor packaging structure according to claim 1, characterized in that, The temporary bonding layer is a UV-release adhesive layer with a thickness of 10μm~20μm.

5. The capacitor packaging structure according to claim 1, characterized in that, An underfill is provided between the capacitor and the dummy silicon. The underfill is located in the middle region of the capacitor and is cured.

6. A method for packaging a capacitor packaging structure, characterized in that, The method, applicable to the capacitor packaging structure according to any one of claims 1 to 5, comprises: S1, An adhesive layer is provided on the upper surface of the capacitor, and the dummy silicon is bonded and fixed to the capacitor through the adhesive layer to form a capacitor-dummy silicon composite structure. S2, a temporary bonding layer is coated on the surface of the carrier board, and the chip and the capacitor-dummy silicon composite structure are placed in a preset area of ​​the carrier board with the capacitor pins facing the carrier board. The relative positions of the chip and the capacitor-dummy silicon composite structure are determined by fixing. S3 uses a transfer molding process to inject low-viscosity, high-flow epoxy resin molding compound to encapsulate the chip, capacitor-dummy silicon composite structure, and temporary bonding layer as a whole. After heat preservation and curing, it is cooled to room temperature to form a molded body. S4. The carrier board is debonded by ultraviolet irradiation, and the carrier board and temporary bonding layer are removed to expose the capacitor leads. S5, a redistribution layer is fabricated on the surface of the plastic package, so that the redistribution layer is electrically connected to the capacitor pins and chip pads; S6, solder joints are made on the surface of the redistribution layer to cut the package into individual units.

7. The method according to claim 6, characterized in that, The method of setting an adhesive layer on the upper surface of the capacitor and bonding and fixing the dummy silicon to the capacitor through the adhesive layer to form a capacitor-dummy silicon composite structure includes: Clean the upper surface of the capacitor and coat the dummy silicon with an adhesive layer of 10μm~30μm thickness; The capacitor is attached to the adhesive layer with its top surface facing down, and pressure of 0.08MPa~0.2MPa is applied. It is then cured at high temperature for 20 to 40 minutes and cut into individual units.

8. The packaging method according to claim 6, characterized in that, The temporary bonding layer has a coating thickness of 10μm~20μm, and the chip and the capacitor-dummy silicon composite structure are fixed by vacuum adsorption and ultraviolet pre-curing. The molding process involves heat preservation and curing for 30 to 50 minutes, during which the molding compound completely covers the exposed areas of the chip, the capacitor-dummy silicon composite structure, and the temporary bonding layer.

9. The packaging method according to claim 6, characterized in that, The process of creating a rewiring layer on the surface of the molding compound includes: A titanium / copper seed layer is deposited on the surface of the molding compound using sputtering and photolithography processes; Rewire pattern is defined by photolithography; Electroplating thickens the copper layer to 5μm~10μm; Etching removes excess seed layer, forming a rewiring layer; The solder joint is a solder ball or a copper pillar.

10. The packaging method according to claim 6, characterized in that, The method further includes: S7. First, a temporary bonding layer is coated on the surface of the carrier board, and the chip and capacitor are placed in the preset area and temporarily fixed. S8. Then apply or press an adhesive layer onto the capacitor surface and mount dummy silicon to form a composite structure, so that the thickness of the composite structure is consistent with the thickness of the chip. S9, fill the middle of the capacitor with high-temperature resistant filler and cure it.

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