Slew rate enhancement circuit and control method of slew rate enhancement circuit

Abstract

The present application relates to a slew rate enhancement circuit, comprising: a comparator comparing a first differential input voltage and a second differential input voltage and generating a dynamic current; a first boost current supply terminal mirroring the generated dynamic current and supplying the dynamic current to a main source amplifier circuit section if the dynamic current is generated; and a second boost current supply terminal additionally supplying the dynamic current to the main source amplifier circuit section based on an operation of a timing controller.

Description

Technical Field

[0001] This invention relates to a slew rate enhancement circuit and a control method for the slew rate enhancement circuit. Background Technology

[0002] Typically, display panels, especially OLED displays, require high resolution and fast response times. To achieve this, the display driver IC plays a crucial role in accurately processing input signals and transmitting them as output signals to the display panel. In this process, the rise and fall rates of the output signal, known as the slew rate, have a significant impact on display performance.

[0003] In existing technologies, various circuit designs have been proposed to detect and correct the difference between the input and output signals in order to reduce slew rate deviation. However, this technology suffers from reduced signal detection capability when the input signal changes slowly, i.e., under low slew rate conditions, resulting in insufficient correction effect of the slew rate enhancement circuit. In particular, in edge channels of displays, where the output signal transmission distance is long and the load is high, the slow rise and fall rates of the signal may lead to a decrease in output quality.

[0004] Therefore, there is a need to develop slew rate enhancement circuits that can solve these problems. Summary of the Invention

[0005] The problem that the invention aims to solve

[0006] The purpose of this invention is to provide a novel circuit and control method for correcting slew rate deviations generated in various channels of a display driver IC. In particular, the purpose is to provide a method that shortens the setup time and improves the display output quality by effectively correcting low slew rate signals generated in edge channels.

[0007] The technical problems to be solved by this invention are not limited to those mentioned above. Those skilled in the art can clearly understand other technical problems not mentioned from the following description.

[0008] Technical solutions to the problem

[0009] An embodiment of the slew rate enhancement circuit of the present invention, as a slew rate enhancement circuit for supplying current to the main source amplifier circuit section, may include: a comparator that compares a first differential input voltage and a second differential input voltage and generates a current; a first boost current supply terminal that, if the current is generated, mirrors the generated current and supplies the current to the main source amplifier circuit section; and a second boost current supply terminal that adds current to the main source amplifier circuit section based on the operation of a timing controller.

[0010] In at least one embodiment of the present invention, the comparator may include a first comparator transistor and a second comparator transistor with the first differential input voltage connected to their gates and the second differential input voltage connected to their sources. If the first differential input voltage increases, current can flow through the first comparator transistor; if the first differential input voltage decreases, current can flow through the second comparator transistor.

[0011] In at least one embodiment of the present invention, the first boost current supply terminal may include a mirror circuit that mirrors the current flowing through the first comparator transistor and the second comparator transistor to generate a mirror current, and supplies the mirror current to the common source terminal and / or common gate terminal of the main source amplifier circuit.

[0012] In at least one embodiment of the present invention, the timing controller can synchronize with the variation time of the first differential input voltage and set the current supply time of the second boost current supply terminal differently for the position of each channel of the display driver IC.

[0013] In at least one embodiment of the present invention, the second boost current supply terminal may include a first current source transistor and a second current source transistor, and the timing controller may apply a bias to the gate nodes of the first current source transistor and the second current source transistor to adjust the amount of current supplied to the common source terminal of the main source amplifier circuit.

[0014] In at least one embodiment of the present invention, the current supply time can be set in the range of 50ns to 500ns.

[0015] In at least one embodiment of the present invention, a switching circuit with an N-type transistor and a P-type transistor connected in parallel can be arranged between the terminal that receives the first differential input voltage and the gates of the first comparator transistor and the second comparator transistor.

[0016] According to an embodiment of the present invention, the control method for a slew rate enhancement circuit, as a control method for supplying dynamic current to a main source amplifier circuit section, may include: a step of comparing a first differential input voltage and a second differential input voltage and generating a current; a step of mirroring the generated current and supplying the current to the main source amplifier circuit section if the current is generated; and a step of adding current supply to the main source amplifier circuit section based on the operation of a timing controller.

[0017] In at least one embodiment of the method of the present invention, the step of generating the current may include: if the first differential input voltage increases, the current flows through the first comparator transistor, and if the first differential input voltage decreases, the current flows through the second comparator transistor.

[0018] In at least one embodiment of the method of the present invention, the step of mirroring the generated current and supplying the current to the main source amplifier circuit section may include the step of supplying the mirrored current to the common source terminal and / or common gate terminal of the main source amplifier circuit section.

[0019] In at least one embodiment of the method of the present invention, the timing controller can synchronize with the variation time of the first differential input voltage and set the current supply time of the second boost current supply terminal differently for the position of each channel of the display driver IC.

[0020] In at least one embodiment of the method of the present invention, the current supply time can be set in the range of 50ns to 500ns.

[0021] Invention Effects

[0022] According to at least one embodiment of the present invention, the slew rate deviation between the center channel and the edge channel of the display driver IC can be effectively corrected. Therefore, uniform signal quality is maintained in both the center channel and the edge channel of the display driver IC, thereby improving the overall signal transmission characteristics of the display.

[0023] The effects that can be obtained in this invention are not limited to those mentioned above. Those skilled in the art to which this invention pertains can clearly understand other effects not mentioned from the following description. Attached Figure Description

[0024] Figure 1 This is a diagram illustrating the configuration of a display device according to an embodiment of the present invention.

[0025] Figure 2 This is a diagram illustrating the configuration of a data driving device according to an embodiment of the present invention.

[0026] Figure 3 This is a block diagram of a differential amplifier according to an embodiment of the present invention.

[0027] Figure 4 This is a diagram showing the configuration of the main source amplifier circuit section according to an embodiment of the present invention.

[0028] Figure 5 This is a diagram of a slew rate enhancement circuit according to an embodiment of the present invention.

[0029] Figure 6This is a diagram showing the effect of a slew rate enhancement circuit according to an embodiment of the present invention. Detailed Implementation

[0030] This invention can be modified in various ways and can have various embodiments, which will be illustrated and described in the accompanying drawings. However, this is not intended to limit the invention to a particular embodiment, but should be understood to include all modifications, equivalents, and substitutions within the spirit and technical scope of the invention.

[0031] The suffixes “module” and “section” used in this specification are for distinguishing the names of constituent elements only and should not be construed as being distinguishable or separable in a physicochemical manner or as presupposing that they can be distinguished or separable in this way.

[0032] Terms including ordinal numbers, such as “first” and “second”, can be used to describe various constituent elements, but these constituent elements are not limited to these terms. These terms are used only in the name meaning to distinguish one constituent element from another; their sequential meaning is understood through the context of the corresponding description rather than through such names.

[0033] The term "and / or" is used to include all combinations of a plurality of items that are its objects. For example, "A and / or B" means including all three cases: "A", "B", "A and B", etc.

[0034] When it is mentioned that a constituent element is "connected" or "linked" to another constituent element, it should be understood that it can be directly connected or linked to the other constituent element, but there may be other constituent elements in between.

[0035] The terminology used in this application is for illustrative purposes only and is not intended to limit the invention. Unless the context clearly defines otherwise, singular expressions include plural expressions. In this application, terms such as "comprising" or "having" should be understood as specifying the presence of features, numbers, steps, actions, constituent elements, components, or combinations thereof as described in the specification, without precluding the presence or additional possibilities of one or more other features or numbers, steps, actions, constituent elements, components, or combinations thereof.

[0036] Unless otherwise defined, all terms used herein, including technical or scientific terms, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms commonly used, such as those defined in dictionaries, shall be interpreted as consistent with their meaning in the context of the relevant art and shall not be construed as having an ideal or excessive form of meaning unless expressly defined in this application.

[0037] Furthermore, "unit," "control unit," "control device," or "controller" are merely broad terms used to name devices that control corresponding functions, and do not refer to a generic function unit. For example, devices with these names may include communication devices that communicate with other controllers or sensors for the control of the corresponding function, computer-readable recording media that store operating systems or logical commands and input / output information, and one or more processors that perform the judgments, calculations, and decisions required to perform the control of the responsible function.

[0038] On the other hand, a processor may include at least one or more semiconductor integrated circuits and / or electronic components that perform comparison, judgment, operation, and decision-making to achieve programmed functions. For example, a processor may be one or a combination of a computer, microprocessor, CPU, ASIC, electronic circuit (circuit, logic circuit).

[0039] The processor can be electrically connected to the memory, and the processor can load and record data from the memory. The memory and processor can be integrated or physically separate.

[0040] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0041] Figure 1 This is a diagram illustrating the configuration of a display device according to an embodiment of the present invention.

[0042] Reference Figure 1 The display device 100 may include a display panel 120, a data processing device 130, a gate driving device 140, and a data driving device 110, etc.

[0043] The display panel 120 may be a liquid crystal display (LCD) panel, or a self-emissive element panel such as an OLED (Organic Light Emitting Diode) panel.

[0044] When the display panel 120 is a liquid crystal display panel, the display panel 120 may include a backlight, liquid crystal, and a common electrode, and each pixel may be equipped with a pixel electrode and a driving transistor. If a scan signal is supplied to the gate of the driving transistor, a data voltage can be supplied to the pixel electrode as the driving transistor is turned on. Furthermore, an electric field can be formed between the pixel electrode and the common electrode according to the data voltage, and the alignment direction of the liquid crystal can be changed. As a result, the transmittance of light supplied from the backlight can be changed, and the brightness of the pixel can be adjusted.

[0045] The display panel 120 may have a plurality of data lines DL and a plurality of gate lines GL arranged in a matrix. The data lines DL may be connected to the source terminals of the driving transistors of each pixel, and the gate lines GL may be connected to the gate terminals of the driving transistors of each pixel. If a scan signal SCN is supplied to the gate line GL, the data voltage VD supplied through the data lines DL may be transmitted to the pixel electrode as the driving transistor is turned on.

[0046] Parasitic capacitors can be formed on the data line DL. These parasitic capacitors can be formed between the data line DL and the common electrode, or between the data line DL and the pixel electrode. From the perspective of the data driving device 110 supplying the data voltage VD, the parasitic capacitors can be identified as loads. The larger the capacitance of the parasitic capacitors, the more electrical power the data driving device 110 needs to supply to the data line DL.

[0047] Display panel 120 can be a self-emissive element panel such as an OLED panel. In addition to OLED panels, other forms of self-emissive elements, such as micro LED panels, can also be used.

[0048] Each pixel in an OLED panel can be equipped with a scanning transistor, a driving transistor, and the OLED itself. If a scanning signal SCN is supplied to the gate of the scanning transistor, the scanning transistor can be turned on, and the data voltage VD can be supplied to the driving transistor. In the OLED panel, the data voltage VD can be supplied to the gate of the driving transistor. The magnitude of the driving transistor's on-current can be determined based on the data voltage VD, and the brightness of the OLED connected to the driving transistor can be adjusted accordingly.

[0049] The display panel 120 may have a plurality of data lines DL and a plurality of gate lines GL arranged in a matrix. The data lines DL may be connected to the source terminals of the scan transistors of each pixel, and the gate lines GL may be connected to the gate terminals of the source transistors of each pixel. If the scan signal SCN is supplied to the gate line GL, the data voltage VD supplied through the data lines DL may be transmitted to the driving transistor as the scan transistor is turned on.

[0050] Parasitic capacitors can be formed on the data line DL. These parasitic capacitors can be formed between the data line DL and the cathode electrode of the OLED, or between the data line DL and the anode electrode of the OLED. From the perspective of the data driving device 110 supplying the data voltage VD, the parasitic capacitors can be identified as loads. The larger the capacitance of the parasitic capacitors, the more power the data driving device 110 needs to supply to the data line.

[0051] The data processing device 130 can receive image data from an external device, such as a host or a device called an application processor (AP). Furthermore, it can convert the image data in the format of the external device into RGB image data in a format that the data driving device 110 can process. The data processing device 130 can then send the converted RGB image data to the data driving device 110.

[0052] Image data RGB may include pixel data representing the grayscale value of each pixel P. Pixel data for a pixel P may be, for example, 8 bits of data, which can represent a grayscale value from 0 to 255. Data processing device 130 may generate pixel data for each pixel and include the pixel data in image data RGB before sending it to data driving device 110.

[0053] The data processing device 130 can send control signals to devices involved in driving the display panel, such as the data driving device 110 and the gate driving device 140. The data processing device 130 can send a data control signal DCS to the data driving device 110 and a gate control signal GCS to the gate driving device 140.

[0054] The control signals DCS and GCS can include setting information for each device. For example, the data processing device 130 can receive setting information from an external device, confirm the setting information for each device, include the setting information in the corresponding control signal (DCS or GCS), and send it.

[0055] The control signals DCS and GCS may include timing signals for controlling each device. These timing signals may be, for example, vertical synchronization signals (Vsync) and horizontal synchronization signals (Hsync). The data drive device 110 or the gate drive device 140 can distinguish frames based on the timing signals and can distinguish different horizontal times. Regarding the timing of controlling each device, the data processing device 130 is also referred to as a timing controller.

[0056] The gate driving device 140 can supply a scan signal SCN to the pixels P arranged on the display panel 120. Furthermore, it can select the pixels to which the scan signal SCN is supplied, and supply a data voltage VD to the selected pixels.

[0057] The gate driving device 140 can supply a scan signal SCN via a gate line GL. A plurality of gate lines GL can be arranged on the display panel 120. Each gate line GL can be connected to a pixel P arranged in a column in one direction (e.g., a horizontal direction). The gate driving device 140 can supply a scan signal SCN indicating conduction to one of the plurality of gate lines GL, and can select the pixel P connected to the corresponding gate line GL. The gate driving device 140 can change the gate line GL and supply the scan signal SCN indicating conduction at each horizontal time interval.

[0058] The data driving device 110 can drive the pixels P arranged on the display panel 120.

[0059] The data driving device 110 can receive image data RGB from the data processing device 130. Furthermore, the data driving device 110 can identify the pixel data for each pixel P included in the image data RGB, generate a data voltage VD corresponding to the pixel data, and supply it to each pixel P.

[0060] Pixel data can represent the grayscale value of each pixel P, and the data driving device 110 can generate a data voltage VD corresponding to this grayscale value.

[0061] Pixel data can be stored in the latch circuit of the data driving device 110 and then output as a digital signal. Furthermore, the data driving device 110 can convert the digital signal into an analog voltage using a gamma reference voltage.

[0062] There is a difference between the grayscale corresponding to physical brightness and the grayscale corresponding to brightness recognized by humans. Correcting this difference is called gamma conversion. The data drive device 110 can also apply gamma conversion simultaneously when converting digital signals to analog voltages. For example, the data drive device 110 can use the voltage used in digital-to-analog conversion as the voltage-gamma reference voltage for applying gamma conversion, thereby enabling the simultaneous application of digital-to-analog conversion and gamma conversion.

[0063] The analog voltage has a low power level, so it may not be suitable for driving pixel P. Therefore, the data driving device 110 can amplify the analog voltage to generate a data voltage VD and supply the relatively high-power data voltage VD to pixel P.

[0064] Figure 2 This is a diagram illustrating the configuration of a data driving device according to an embodiment of the present invention.

[0065] Reference Figure 2 The data driving device 110 may include a channel circuit 210 and a gamma reference voltage generation circuit 230, etc.

[0066] The channel circuit 210 may include a latch circuit 211, a level shifter 212, a DAC (Digital-to-Analog Converter) 213, and a buffer circuit 214, etc. It can receive pixel data PXD corresponding to the gray value of the pixel and generate a data voltage VD, and supply the data voltage VD to the data line connected to the pixel.

[0067] The latch circuit 211 can sequentially store pixel data PXD received through the data bus.

[0068] The latch circuit 211 may have two latches internally. The first latch may store the pixel data to be output in the next horizontal time, and the second latch may store the pixel data to be output in the current horizontal time. If the next horizontal time arrives, the first latch may store the pixel data to be output in the next horizontal time after that, and the pixel data stored in the first latch may be moved to the second latch and stored.

[0069] The output timing of the latch circuit 211 can be determined based on the latch output signal generated at each horizontal time. The latch output signal can be synchronized with the horizontal synchronization signal. Alternatively, the latch output signal can be a signal with a different phase than the horizontal synchronization signal but the same period length.

[0070] The latch circuit 211 can transmit the pixel data PXD stored in the latch circuit 211 to the level shifter 212 according to the latch output signal.

[0071] Level shifter 212 can convert pixel data PXD into digital signal DS. Level shifter 212 can convert pixel data PXD into digital signal DS and increase the signal level.

[0072] Pixel data PXD can be a low-voltage or low-power signal. Level shifter 212 can convert pixel data PXD into a high-voltage or high-power digital signal DS.

[0073] The DAC213 can receive a digital signal DS and drive the gate of an internal switch. Furthermore, the DAC213 can convert the digital signal DS into an analog voltage AS by driving the gate of the switch.

[0074] The DAC213 may include a plurality of switches. Each switch can selectively connect to the output one of a plurality of gamma reference voltage lines supplied with a plurality of gamma reference voltages, depending on its on / off state. The voltage formed on the selected gamma reference voltage line can be an analog voltage AS. A digital signal DS can be supplied to the gate of the switch and change its on / off state.

[0075] The digital signal DS can be supplied to drive the gate of the switch. The digital signal DS is output by the level shifter 212, and from this point of view, the gate load of the switch can become part of the output load of the level shifter 212.

[0076] The data drive device 110 may include a gamma reference voltage generation circuit 230 that supplies a gamma reference voltage VGM to the DAC 213.

[0077] The channel circuit 210 may include a buffer circuit 214 disposed between the output of the DAC 213 and the pixel.

[0078] The buffer circuit 214 can amplify the output of DAC 213 and supply it to the data line connected to the pixel. The buffer circuit 214 can also amplify the analog voltage AS and generate a data voltage VD, which is then supplied to the data line.

[0079] The buffer circuit 214 may include a differential amplifier for amplifying the analog voltage AS into the data voltage VD.

[0080] The differential amplifier can be a rail-to-rail Class-A amplifier. Buffer circuit 214 can generate a data voltage VD that amplifies the analog voltage AS using this differential amplifier.

[0081] The input and output of a differential amplifier can be connected via a buffer structure. For example, the output of the differential amplifier can be connected to its negative input. Furthermore, an analog voltage AS can be supplied to the positive input of the differential amplifier.

[0082] Figure 3 This is a block diagram of a differential amplifier according to an embodiment of the present invention.

[0083] Reference Figure 3 The differential amplifier may include a main source amplifier circuit section 300 and a boost circuit section 400.

[0084] The boost circuit section 400 may include a comparator 420, a first boost current supply terminal 430, a second boost current supply terminal 440, and a timing control terminal 450.

[0085] Comparator 420 can receive the analog voltage AS of the DAC output voltage as an input signal and the output value of the amplified voltage as another input signal, comparing the voltage levels of the two signals. If there is a difference in the voltage levels of the two signals, current can flow through the first boost current supply terminal 430. The first mirror circuit and the second mirror circuit of the first boost current supply terminal 430 mirror the current and supply it to the main source amplifier circuit section 300.

[0086] The second boost current supply terminal 440 can be connected in parallel with the first boost current supply terminal 430 to supply current to the main source amplifier circuit section 300 based on the operation of the timing control terminal 450.

[0087] The timing control terminal 450 can synchronize with the timing of changes in the input signal to control the operating time of the second boost current supply terminal 440. Furthermore, the operating time can be set according to the position of each channel of the display driver IC.

[0088] For details on the main source amplifier circuit section 300 and the boost circuit section 400, please refer to... Figure 4 and Figure 5 illustrate.

[0089] Figure 4 This is a diagram showing the configuration of the main source amplifier circuit section according to an embodiment of the present invention.

[0090] Reference Figure 4 The main source amplifier circuit section 300 may include a first circuit terminal 310, a second circuit terminal 321, a third circuit terminal 322, a fourth circuit terminal 330, and a fifth circuit terminal 340.

[0091] The first circuit terminal 310, which generates a differential current based on the differential input voltage, can be referred to as the input circuit terminal. Hereinafter, the first circuit terminal 310 will be referred to as the input circuit terminal 310, and an embodiment will be described.

[0092] The second circuit terminal 321 can be a circuit that controls the gate voltage of the first output transistor MPO based on the first differential current generated at the input circuit terminal 310, and the third circuit terminal 322 can be a circuit that controls the gate voltage of the second output transistor MNO based on the second differential current generated at the input circuit terminal 310. The second circuit terminal 321 and the third circuit terminal 322 have the configuration of a current mirror circuit, and thus the two circuits can be combined and referred to as current mirror circuit terminals 321 and 322. The second circuit terminal 321 is referred to as the first current mirror circuit, and the third circuit terminal 322 is referred to as the second current mirror circuit. Hereinafter, the second circuit terminal 321 will be referred to as the first current mirror circuit 321, and the third circuit terminal 322 will be referred to as the second current mirror circuit, and an embodiment will be described.

[0093] The fourth circuit terminal 330 serves as a circuit that provides bias current and can be referred to as the bias circuit terminal. Hereinafter, the fourth circuit terminal 330 will be referred to as the bias circuit terminal 330, and an embodiment will be described.

[0094] The fifth circuit terminal 340 may include a first output transistor MPO disposed between the first voltage rail (DDVDH) and the output terminal OT, and a second output transistor MNO disposed between the second voltage rail (AVSS) and the output terminal OT. The fifth circuit terminal 340, as a circuit including the output terminal OT, may be referred to as an output circuit terminal. Hereinafter, the fifth circuit terminal 340 will be referred to as the output circuit terminal 340, and embodiments will be described.

[0095] In the main source amplifier circuit section 300, the input circuit terminal 310, the current mirror circuit terminals 321 and 322, the bias circuit terminal 330, and the output circuit terminal 340 can form a rail-to-rail Class-A amplifier.

[0096] The main source amplifier circuit section 300 may include a first voltage rail supplied with a high driving voltage DDVDH and a second voltage rail supplied with a low driving voltage AVSS. Furthermore, one side of the input circuit terminal 310, the current mirror circuit terminals 321 and 322, and the output circuit terminal 340 may be connected to the first voltage rail, and the other side may be connected to the second voltage rail.

[0097] The main source amplifier circuit section 300 can receive differential input voltages IP and IM, and supply the output voltage OT to the outside. In the main source amplifier circuit section 300, a first differential input voltage IP can be input through a first input terminal, and a second differential input voltage IM can be input through a second input terminal. Furthermore, in the main amplifier 300, the output voltage OT can be supplied to the outside through an output terminal. For ease of explanation, the reference numeral IP can be used to refer to the first differential input voltage and the first input terminal. The reference numeral IM can be used to refer to the second differential input voltage and the second input terminal. The reference numeral OT can be used to refer to the output voltage and the output terminal. The first differential input voltage IP can be called the positive input voltage, and the first input terminal can be called the positive input terminal. The second differential input voltage IM can be called the negative input voltage, and the second input terminal can be called the negative input terminal.

[0098] When the main source amplifier circuit section 300 is used as a buffer, the negative input terminal can be connected to the output terminal. Furthermore, the output voltage OT can follow the waveform of the first differential input voltage IP.

[0099] Depending on the slew rate of the main source amplifier circuit section 300, the output voltage OT may follow the waveform of the first differential input voltage IP at different speeds. In one embodiment, the main source amplifier circuit section 300 can improve its slew rate by adding a dynamic current supplied through the boost circuit section 400. The dynamic current can be generated in response to changes in the differential input voltage (especially the first differential input voltage IP). For example, a dynamic current can be generated when the first differential input voltage IP has a rising or falling waveform. When the differential input transmission (especially the first differential input voltage IP) is in a static state, no dynamic current may be generated. For example, when the first differential input voltage IP remains at a constant level, no dynamic current may be generated. With this structure, the main source amplifier circuit section 300 can improve its slew rate without consuming additional static power.

[0100] The output circuit 340 may include a first output transistor MPO disposed between the first voltage rail and the output terminal, and a second output transistor MNO disposed between the second voltage rail and the output terminal. The slew rate of the main source amplifier circuit 300 may be significantly affected by the magnitude of the current that charges / discharges the gates of the first output transistor MPO and the second output transistor MNO. For example, when adjusting the magnitude of the current flowing through the first output transistor MPO and the second output transistor MNO in accordance with the dynamic waveform of the first differential input voltage IP to raise or lower the gate voltage, if the current that charges / discharges the gate is large, the variation of the current flowing through the first output transistor MPO and the second output transistor MNO will increase, thereby improving the slew rate.

[0101] One embodiment of the main source amplifier circuit section 300 may have a structure in which a dynamic current is supplied in response to the variation of the differential input voltage, and the current used to charge / discharge the gates of the first output transistor MPO and the second output transistor MNO is increased by such dynamic current.

[0102] The charging / discharging current of the first output transistor MPO and the second output transistor MNO may be affected by the current at the input circuit terminal 310 and the current at the current mirror circuit terminals 321 and 322. The main source amplifier circuit 300 can add dynamic current to the input circuit terminal 310 and / or the current mirror circuit terminals 321 and 322 to increase the charging / discharging current of the first output transistor MPO and the second output transistor MNO.

[0103] The input circuit terminal 310 may include a first differential amplifier circuit 311 and a second differential amplifier circuit 312.

[0104] The first differential amplifier circuit 311 may include a first N-type transistor MN1 and a second N-type transistor MN2 having a common source structure. Furthermore, the sources of the first N-type transistor MN1 and the second N-type transistor MN2 can be connected to a second voltage rail supplied with a low driving voltage AVSS via a third N-type transistor MN3.

[0105] A bias voltage can be supplied to the gate of the third N-type transistor MN3, and based on this bias voltage, the third N-type transistor MN3 can be used as a bias current source.

[0106] A first differential input voltage IP can be supplied to the gate of the first N-type transistor MN1, and a second differential input voltage IM can be supplied to the gate of the second N-type transistor MN2.

[0107] If the first differential input voltage IP increases, more current can flow through the first N-type transistor MN1. This increased current flow through MN1 leads to more current flowing to the first output transistor MPO and less current flowing to the second output transistor MNO, thus increasing the output voltage OT. Conversely, if the first input voltage IP decreases, less current can flow through the first N-type transistor MN1. This decreased current flow through MN1 leads to less current flowing to the first output transistor MPO and more current flowing to the second output transistor MNO, thus decreasing the output voltage OT.

[0108] The second differential amplifier circuit 312 may include a first P-type transistor MP1 and a second P-type transistor MP2 having a common source structure. Furthermore, the sources of the first P-type transistor MP1 and the second P-type transistor MP2 can be connected to a first voltage rail supplied with a high driving voltage DDVDH via a third P-type transistor MP3.

[0109] A bias voltage can be supplied to the gate of the third P-type transistor MP3, and based on this bias voltage, the third P-type transistor MP3 can be used as a bias current source.

[0110] A first differential input voltage IP can be supplied to the gate of the first P-type transistor MP1, and a second differential input voltage IM can be supplied to the gate of the second P-type transistor MP2.

[0111] If the first differential input voltage IP increases, less current can flow through the first P-type transistor MP1. Less current flowing through MP1 results in more current flowing to the first output transistor MPO and less current flowing to the second output transistor MNO, thus increasing the output voltage OT. Conversely, if the first input voltage IP decreases, more current can flow through MP1. More current flowing through MP1 results in less current flowing to the first output transistor MPO and more current flowing to the second output transistor MNO, thus decreasing the output voltage OT.

[0112] The current mirror circuit terminals 321 and 322 may include a first current mirror circuit 321 and a second current mirror circuit 322.

[0113] The first current mirror circuit 321 may include a first reference current transistor MP4 and a first mirror current transistor MP5.

[0114] The first current mirror circuit 321 may have a common gate structure. The gate of the first reference current transistor MP4 may be connected to the gate of the first mirror current transistor MP5.

[0115] One side of the first current mirror circuit 321 can be connected to the first voltage rail of the driven high voltage DDVDH. The source of the first reference current transistor MP4 and the source of the first mirror current transistor MP5 can be connected to the first voltage rail.

[0116] The first reference current can flow through the first reference current transistor MP4, and the mirror current of the first reference current can flow through the first mirror current transistor MP5.

[0117] A first additional transistor circuit with a common gate structure may be arranged at the drain of the first reference current transistor MP4 and the drain of the first mirror current transistor MP5.

[0118] The first additional transistor circuit may include a first additional transistor MP6 connected to the drain of the first reference current transistor MP4 and a second additional transistor MP7 connected to the drain of the first mirror current transistor MP5. The first additional transistor MP6 may perform additional functions such as limiting the amount of current flowing through the first reference current transistor MP4, and the second additional transistor MP7 may perform additional functions such as limiting the amount of current flowing through the first mirror current transistor MP5.

[0119] The gate and drain of the first reference current transistor MP4 can be electrically connected to form a current mirror circuit. In normal operation, the first auxiliary transistor MP6 and the second auxiliary transistor MP7 can operate as bypass circuits; therefore, the gate of the first reference current transistor MP4 and the drain of the first auxiliary transistor MP6 can be connected.

[0120] In the first differential amplifier circuit 311 at the input circuit terminal 310, the drain of the first N-type transistor MN1 can be connected to the drain of the first mirror current transistor MP5. Furthermore, in the first differential amplifier circuit 311, the drain of the second N-type transistor MN2 can be connected to the drain of the first reference current transistor MP4.

[0121] The second current mirror circuit 322 may include a second reference current transistor MN4 and a second current mirror transistor MN5. The second current mirror circuit 322 may have a common gate structure. The gate of the second reference current transistor MN4 may be connected to the gate of the second current mirror transistor MN5.

[0122] One side of the second current mirror circuit 322 can be connected to the second voltage rail of the driven low voltage AVSS. The source of the second reference current transistor MN4 and the source of the second mirror current transistor MN5 can be connected to the second voltage rail.

[0123] The second reference current can flow through the second reference current transistor MN4, and the mirror current of the second reference current can flow through the second mirror current transistor MN5.

[0124] A second additional transistor circuit with a common gate structure can be arranged at the drain of the second reference current transistor MN4 and the drain of the second mirror current transistor MN5.

[0125] The second additional transistor circuit may include a third additional transistor MN6 connected to the drain of the second reference current transistor MN4 and a fourth additional transistor MN7 connected to the drain of the second mirror current transistor MN5. The third additional transistor MN6 may perform additional functions such as limiting the amount of current flowing through the second reference current transistor MN4, and the fourth additional transistor MN7 may perform additional functions such as limiting the amount of current flowing through the second mirror current transistor MN5.

[0126] The gate and drain of the second reference current transistor MN4 can be electrically connected to form a current mirror circuit. In normal operation, the third and fourth auxiliary transistors MN6 and MN7 can operate as bypass circuits; therefore, the gate of the second reference current transistor MN4 and the drain of the third auxiliary transistor MN6 can be connected.

[0127] In the second differential amplifier circuit 312 at the input circuit terminal 310, the drain of the first P-type transistor MP1 can be connected to the drain of the second mirror current transistor MN5. Furthermore, in the second differential amplifier circuit 312, the drain of the second P-type transistor MP2 can be connected to the drain of the second reference current transistor MN4.

[0128] A bias circuit terminal 330 may be arranged between the first current mirror circuit 321 and the second current mirror circuit 322.

[0129] The bias circuit terminal 330 may include a first bias circuit and a second bias circuit.

[0130] The first bias circuit may have a structure consisting of an N-type transistor MN8 and a P-type transistor MP8 connected in parallel. The bias current supplied by the first bias circuit can be determined based on the bias voltage supplied to the gates of the N-type transistor MN8 and the P-type transistor MP8.

[0131] The second bias circuit can have a structure consisting of another N-type transistor MN9 and another P-type transistor MP9 connected in parallel. The bias current supplied by the second bias circuit can be determined based on the bias voltage supplied to the gates of the other N-type transistor MN9 and the other P-type transistor MP9.

[0132] The first bias circuit can be electrically connected to the first reference current transistor MP4 of the first current mirror circuit 321 and the second reference current transistor MN4 of the second current mirror circuit 322 to form a current path. This path can be referred to as the reference current path. In the reference current path, the first bias current formed by the first bias circuit can flow through the first voltage rail, the first reference current transistor MP4 and the first bias circuit, and then flow out to the second voltage rail through the second reference current transistor MN4.

[0133] The second bias circuit can be electrically connected to the first current mirror transistor MP5 of the first current mirror circuit 331 and the second current mirror transistor MN5 of the second current mirror circuit 322 to form another current path. This path can be referred to as the mirror current path. In the mirror current path, the second bias current, which is essentially formed by the second bias circuit, can flow through the first voltage rail, the first current mirror transistor MP5, and the second bias circuit, and then out to the second voltage rail through the second current mirror transistor MN5.

[0134] The source of the first output transistor MPO in the output circuit 340 can be connected to the first voltage rail, and the drain can be connected to the output terminal OT. Furthermore, the gate of the first output transistor MPO can be connected to the contact nodes of the second bias circuit and the first current mirror circuit 321 in the current mirror path.

[0135] The source of the second output transistor MNO in the output circuit 340 can be connected to the second voltage rail, and the drain can be connected to the output terminal OT. Furthermore, the gate of the second output transistor MNO can be connected to the contact node of the second bias circuit and the second current mirror circuit 322 in the current mirror path.

[0136] Input circuit terminal 310 can generate differential current based on differential input voltages IP and IM. Furthermore, current mirror circuit terminals 321 and 322 can control the gate voltages of the first output transistor MPO and the second output transistor MNO based on the differential current. Additionally, boost circuit unit 400 can supply dynamic current to input circuit terminal 310 or to current mirror circuit terminals 321 and 322 in response to changes in differential input voltages IP and IM, thereby increasing the slew rate of the main source amplifier circuit unit 300.

[0137] The boost circuit section 400 can supply dynamic current to the input circuit terminal 310. The input circuit terminal 310 may include a differential amplifier circuit having a common source structure and receiving differential input voltages IP and IM through its gate. The boost circuit section 400 can supply dynamic current to the common source terminal of such differential amplifier circuit. For example, the boost circuit section 400 can supply dynamic current to the common source terminal CSN of the first differential amplifier circuit 311, or it can supply dynamic current to the common source terminal CSP of the second differential amplifier circuit 312.

[0138] The boost circuit section 400 can supply dynamic current to the current mirror circuit terminals 321 and 322. The current mirror circuit terminals 321 and 322 can include current mirror circuits with a common gate structure, and the boost circuit section 400 can supply dynamic current to the common gate terminal of such current mirror circuits. For example, the boost circuit section 400 can supply dynamic current to the common gate terminal HPC of the first current mirror circuit 321, or it can supply dynamic current to the common gate terminal HNC of the second current mirror circuit 322.

[0139] The current mirror circuit terminals 321 and 322 may include a reference current path through which a reference current flows and a mirror current path through which the mirror current flows, and the boost circuit section 400 can supply current. For example, the boost circuit section 400 can supply dynamic current to the common gate terminal HPC of the first current mirror circuit 321, and this dynamic current can flow into the reference current path through the drain of the first reference current transistor MP4. As another example, the boost circuit section 400 can supply dynamic current to the common gate terminal HNC of the second current mirror circuit 322, and this dynamic current can flow into the reference current path through the drain of the second reference current transistor MN4.

[0140] Figure 5 This is a diagram of a slew rate enhancement circuit according to an embodiment of the present invention.

[0141] Reference Figure 5 The boost circuit section 400 includes a flip circuit terminal 410, a comparator 420, a first boost current supply terminal 430, a second boost current supply terminal 440, and a timing control terminal 450.

[0142] Comparator 420 may include a first comparator transistor TN2 and a second comparator transistor TP2, with a first differential input voltage IP connected to its gate and a second differential input voltage IM connected to its source.

[0143] The boost circuit section 400 can generate and supply dynamic current based on the current flowing through the first comparator transistor TN2 and the second comparator transistor TP2.

[0144] The first comparator transistor TN2 can be an N-type transistor. If the first differential input voltage IP and the second differential input voltage IM maintain similar voltage levels, then no current may flow through the first comparator transistor TN2. Then, if the first differential input voltage IP increases (having a rising waveform), then current may flow through the first comparator transistor TN2. The first comparator transistor TN2 can be connected to the first boost current supply terminal 430.

[0145] The first boost current supply terminal 430 can mirror the current flowing through the first comparator transistor TN2 through the first mirror circuit 431, and supply the mirrored current to the common source terminal CSP of the second differential amplifier circuit 312 and / or the common gate terminal HNC of the second current mirror circuit 322.

[0146] In the first current mirror circuit 431, the current flowing through the first comparator transistor TN2 can flow to a P-type transistor TP3, and the current flowing through the P-type transistor TP3 can be mirrored by another P-type transistor TP4 and yet another P-type transistor TP5. Furthermore, the current flowing through the other P-type transistor TP4 can be supplied to the common source terminal CSP of the second differential amplifier circuit 312, and the current flowing through the other P-type transistor TP5 can be supplied to the common gate terminal HNC of the second current mirror circuit.

[0147] The second comparator transistor TP2 can be a P-type transistor. If the first differential input voltage IP and the second differential input voltage IM maintain similar voltage levels, then no current may flow through the second comparator transistor TP2. Then, if the first differential input voltage IP drops (with a pull-down waveform), then current may flow through the second comparator transistor TP2. The second comparator transistor TP2 can be connected to the first boost current supply terminal 430.

[0148] The first boost current supply terminal 430 can mirror the current flowing through the second comparator transistor TP2 through the second mirror circuit 432, and supply the mirrored current to the common source terminal CSN of the first differential amplifier circuit 311 and / or the common gate terminal HPC of the first current mirror circuit.

[0149] In the second mirror circuit 432, the current flowing through the second comparator transistor TP2 can flow to an N-type transistor TN3, and the current flowing through the N-type transistor TN3 can be mirrored by another N-type transistor TN4 and yet another N-type transistor TN5. Furthermore, the current flowing through the other N-type transistor TN4 can be supplied to the common gate terminal HPC of the first current mirror circuit, and the current flowing through the other N-type transistor TN5 can be supplied to the common source terminal CSN of the first differential amplifier circuit.

[0150] The boost circuit section 400 may also include a second boost current supply terminal 440 and a timing control terminal 450.

[0151] The second boost current supply terminal 440 can be connected in parallel with the first boost current supply terminal 430, and supply current to the common source terminal CSN of the first differential amplifier circuit or the common source terminal CSP of the second differential amplifier circuit of the main source amplifier circuit section 300 based on the operation of the timing control terminal 450.

[0152] The second boost current supply terminal 440 may include a first current source transistor TP6, which is a P-type transistor, and a second current source transistor TN6, which is an N-type transistor, capable of generating current. The current generated by the first current source transistor TP6 can be supplied to the common source terminal CSP of the second differential amplifier circuit of the main source amplifier circuit section 300, and the current generated by the second current source transistor TN6 can be supplied to the common source terminal CSN of the first differential amplifier circuit of the main source amplifier circuit section 300.

[0153] The timing control terminal 450 can synchronize with the fluctuation time of the first differential input voltage IP signal and control the operating time of the second boost current supply terminal 440, setting the operating time according to the position of each channel of the display driver IC. Furthermore, the timing control terminal 450 can supply current through the second boost current supply terminal only at the required time points based on the rise / pull-down signal, thereby saving energy and improving signal quality.

[0154] The timing control terminal 450 can control the switch included in the second boost current supply terminal according to the position of each channel of the display driver IC, apply bias to the gate nodes of the first current source transistor TP6 and the second current source transistor TN6 to adjust the current amount, and supply current to the main source amplifier circuit section 300. Even at low slew rates, a stable output waveform can be obtained.

[0155] The boost circuit section 400 may further include a switching circuit 410 consisting of an N-type transistor TN1 and a P-type transistor TP1 connected in parallel. The switching circuit 410 may be arranged between the terminal to which the first differential input voltage IP is input and the gates of the comparator transistors TN2 and TP2. The boost circuit section 400 may control the voltage supplied to the gate of the switching circuit 410 to disconnect the switching circuit 410 and not supply dynamic current.

[0156] Figure 6 This is a diagram showing the effect of a slew rate enhancement circuit according to an embodiment of the present invention.

[0157] Reference Figure 6 (a) shows the waveforms of the input and output signals when the input voltage in the edge channel of the display driver IC increases (rises). The x-axis represents time (µs), and the y-axis represents voltage (V). It can be seen that the output signal rises more slowly than the input signal when the input voltage in the edge channel of the display driver IC increases. It can be seen that the output signal of the present invention is closer to the input signal than the output signal of the comparative example (here, the comparative example refers to the case in a conventional slew rate enhancement circuit). This shows that even at low slew rates in the edge channel of the display driver IC, the stability of the output waveform in a conventional slew rate enhancement circuit can be ensured.

[0158] Reference Figure 6 Figure (b) shows the voltage curve as the input voltage in the edge channel of the display driver IC decreases (pull-down). The x-axis represents time (µs), and the y-axis represents voltage (V). It can be seen that the output signal decreases more slowly than the input signal when the input voltage in the edge channel of the display driver IC decreases (pull-down). It can be seen that the output signal of the present invention is generated more closely to the input signal compared to the output signal of the comparative example (here, the comparative example refers to the case in a conventional slew rate enhancement circuit). This demonstrates that even at low slew rates in the edge channel of the display driver IC, the stability of the output waveform in a conventional slew rate enhancement circuit can be ensured.

[0159] It will be apparent to those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit and essential features of the invention. Therefore, the detailed description above should not be construed as restrictive in all respects but should be considered exemplary. The scope of the invention should be determined by a reasonable interpretation of the appended claims, and all modifications within the equivalent scope of the invention are included within the scope of the invention.

[0160] The methods described in the above embodiments can be made into a program for running in a computer, which can be stored in a computer-readable recording medium. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage device, etc. In addition, it also includes a form implemented as a carrier wave (e.g., transmitted via the Internet).

[0161] Computer-readable recording media can be distributed across computer systems connected via a network, and computer-readable code can be stored and executed in a distributed manner. Furthermore, the functional programs, code, and code segments used to implement the above methods can be easily deduced by programmers skilled in the art to which the embodiments pertain.

[0162] It will be apparent to those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit and essential features of the invention.

[0163] Therefore, the detailed description above should not be construed as limiting in all respects but should be considered exemplary. The scope of the invention should be determined by a reasonable interpretation of the appended claims, and all modifications within the equivalent scope of the invention are included within the scope of the invention.

Claims

1. A slew rate enhancement circuit that supplies current to the main source amplifier circuit section, wherein, The slew rate enhancement circuit includes: The comparator compares the first differential input voltage and the second differential input voltage and generates a current. If the current is generated at the first boost current supply terminal, the generated current is mirrored and supplied to the main source amplifier circuit; and The second boost current supply terminal supplies additional current to the main source amplifier circuit based on the action of the timing controller.

2. The slew rate enhancement circuit according to claim 1, wherein, The comparator includes a first comparator transistor and a second comparator transistor whose gates are connected to the first differential input voltage and whose sources are connected to the second differential input voltage. If the first differential input voltage increases, current flows through the first comparator transistor; if the first differential input voltage decreases, current flows through the second comparator transistor.

3. The slew rate enhancement circuit according to claim 2, wherein, The first boost current supply terminal includes a mirror circuit that mirrors the currents flowing through the first comparator transistor and the second comparator transistor to generate a mirror current. The first boost current supply terminal supplies the mirror current to the common source terminal and / or common gate terminal of the main source amplifier circuit.

4. The slew rate enhancement circuit according to claim 1, wherein, The timing controller synchronizes with the variation time of the first differential input voltage and sets the current supply time of the second boost current supply terminal differently for each channel of the display driver IC.

5. The slew rate enhancement circuit according to claim 1, wherein, The second boost current supply terminal includes a first switch and a second switch. If the first switch and the second switch are turned on, current is supplied to the common source terminal of the main source amplifier circuit.

6. The slew rate enhancement circuit according to claim 1, wherein, The second boost current supply terminal includes a first current source transistor and a second current source transistor. The timing controller applies a bias to the gate nodes of the first current source transistor and the second current source transistor to adjust the amount of current supplied to the common source terminal of the main source amplifier circuit.

7. The slew rate enhancement circuit according to claim 4, wherein, The current supply time can be set within the range of 50ns to 500ns.

8. The slew rate enhancement circuit according to claim 2, wherein, A switching circuit with an N-type transistor and a P-type transistor connected in parallel is arranged between the terminal that receives the first differential input voltage and the gates of the first comparator transistor and the second comparator transistor.

9. A control method for a slew rate enhancement circuit, wherein a dynamic current is supplied to the main source amplifier circuit section, wherein, The control method for the slew rate enhancement circuit includes: The steps of comparing the first differential input voltage and the second differential input voltage and generating current; If the current is generated, the step of mirroring the generated current and supplying the current to the main source amplifier circuit section; and The step of supplying additional current to the main source amplifier circuit based on the action of the timing controller.

10. The control method for the slew rate enhancement circuit according to claim 9, wherein, The step of generating current includes: The steps are as follows: if the first differential input voltage increases, current flows through the first comparator transistor; if the first differential input voltage decreases, current flows through the second comparator transistor.

11. The control method for the slew rate enhancement circuit according to claim 9, wherein, The steps of mirroring the generated current and supplying the current to the main source amplifier circuit include: The step of supplying the mirrored current to the common source terminal and / or common gate terminal of the main source amplifier circuit section.

12. The control method for the slew rate enhancement circuit according to claim 9, wherein, The timing controller synchronizes with the variation time of the first differential input voltage and sets the current supply time of the second boost current supply terminal differently for each channel of the display driver IC.

13. The control method for the slew rate enhancement circuit according to claim 12, wherein, The current supply time can be set within the range of 50ns to 500ns.

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