gate pull-down to backside power rail

Abstract

A semiconductor device includes a gate metal and a gate extension disposed within a region between two transistors having opposite conductivity and connected to the gate metal. The gate extension extends toward a side of the semiconductor device having a power rail. A gate cutout is disposed within the gate metal and through the gate extension to segment the gate extension into portions that are electrically isolated from one another. Each portion of the gate extension is coupled to a backside power rail.

Description

Background Technology

[0001] The present invention relates generally to semiconductor devices and processing methods, and more specifically to connecting back-side gate contacts to back-side power rails using local interconnect structures.

[0002] Back-side power rails are provided to supply power to the transistor devices on the chip and to ground. Conventionally, one of the most convenient placement locations for back-side power rails is in the N2N space (i.e., below but between adjacent n-type field-effect transistors (NFETs)) and the P2P space (i.e., below but between adjacent p-type field-effect transistors (PFETs). This limits the placement options for the gate contacts, which are typically left in locations between the NFET-PFET (N2P) regions. This makes connecting the gate to the back-side power distribution network (BSPDN) via gate pull-down very difficult, especially considering the reduced node size.

[0003] Therefore, there is a need for alternative gate connection methods and wiring that maintain the electrical integrity of conductive components but provide efficient wiring within the constraints of ever-decreasing node sizes. Summary of the Invention

[0004] According to one embodiment of the present invention, a semiconductor device includes a gate metal and a gate extension disposed in a region between two transistors having opposite conductivity and connected to the gate metal. The gate extension extends toward a side of the semiconductor device having a power rail. A gate notch is disposed within the gate metal and extends through the gate extension to divide the gate extension into electrically isolated portions. Each portion of the gate extension is coupled to a back-side power rail.

[0005] In some embodiments, the gate extension may be disposed in a shallow trench isolation. Each portion of the gate extension may be connected to a local interconnect. The local interconnect may connect a portion of the gate extension to a corresponding back-side power rail. The gate extension may extend toward the back side of the semiconductor device, and the local interconnect may be disposed in a layer for back-side contacts. The source / drain regions connected to the top-side contacts may be separated from the local interconnect by a back-side interlayer dielectric layer. The source / drain regions of two transistors with opposite conductivity may have a gate notch disposed between them.

[0006] According to another embodiment of the present invention, a semiconductor device includes: an N-type field-effect transistor (NFET), a P-type field-effect transistor (PFET) disposed adjacent to the NFET, and a gate metal disposed in a region between the NFET and the PFET. A gate extension is disposed in the region between the NFET and the PFET and is connected to the gate metal on the back side of the semiconductor device. A gate notch is configured to pass through the gate metal and through the gate extension to divide the gate extension into a first portion and a second portion electrically isolated from each other. The first portion is coupled to a first back-side power rail, and the second portion is coupled to a second back-side power rail.

[0007] In some embodiments, the gate extension may be disposed in shallow trench isolation. A first portion of the gate extension may be connected to the supply voltage back-side power rail via a local interconnect, and a second portion of the gate extension may be connected to the ground back-side power rail via a local interconnect. A gate notch may be disposed between the source / drain regions of the NFET and PFET. An additional gate notch may be disposed between source / drain regions having the same conductivity. The first portion may be coupled to a first back-side power rail via a first local interconnect, and the second portion may be coupled to a second back-side power rail via a second local interconnect. The first and second local interconnects may be disposed within a layer for the back-side contacts. The source / drain regions connected to the top-side contacts may be separated from corresponding local interconnects in the first and second local interconnects via a back-side interlayer dielectric layer.

[0008] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: extending a gate electrode by forming a gate extension into a shallow trench isolation (STI) region at an NFET to PFET (N2P) boundary; dividing the gate extension into portions by forming a gate cut through the gate extension to separate the gate extension; forming a back-side local interconnect to connect to a portion of the gate extension; and forming a power rail to connect to the back-side local interconnect to pull down the gate electrode.

[0009] In other embodiments, back-side local interconnects can be formed by depositing conductors in openings separated by gate cutouts. This method may include forming additional gate cutouts disposed between source / drain regions having the same conductivity. The back-side local interconnects can be formed within a layer for back-side contacts, and the source / drain regions connected to the top-side contacts can be separated from their corresponding back-side local interconnects by a back-side interlayer dielectric layer.

[0010] These and other features and advantages will become clear from the following detailed description of illustrative embodiments, which should be read in conjunction with the accompanying drawings. Attached Figure Description

[0011] The following description will provide details of preferred embodiments with reference to the following figures, in which: Figure 1 The illustration shows a cross-sectional view of a semiconductor substrate with shallow trench isolation, taken at cross-sectional lines X, Y1, Y2 and Y3 as shown in the illustration, and a patterned stack of layers that may be formed or provided in one or more nanosheets, according to an embodiment of the present invention. Figure 2 A cross-sectional view of the opening for forming a gate extension into a shallow trench isolation, taken at section lines X, Y1, Y2 and Y3 according to an embodiment of the present invention, is shown. Figure 3 The diagram shows cross-sectional views taken at sections X, Y1, Y2, and Y3 after the formation of the dummy gate and the source / drain regions formed on the sacrificial occupant, according to an embodiment of the invention. Figure 4 The illustration shows cross-sectional views taken at sections X, Y1, Y2, and Y3 after forming the top interlayer dielectric layer, etching trenches, and filling the trenches to form a gate cutout (or dielectric strip) according to an embodiment of the present invention. Figure 5 The illustration shows a cross-sectional view taken at sections X, Y1, Y2 and Y3 after adding additional top interlayer dielectric material and patterning it to form intermediate process contacts, forming a subsequent process structure, applying a carrier wafer and flipping the structure to process the bottom side, according to an embodiment of the present invention. Figure 6 A cross-sectional view is shown at sections X, Y1, Y2 and Y3 after the substrate has been removed to the etch stop layer, according to an embodiment of the present invention. Figure 7 The illustration shows cross-sectional views taken at sections X, Y1, Y2, and Y3 after an opening is formed by etching the remaining portion of the semiconductor layer, according to an embodiment of the present invention. Figure 8 The diagram shows cross-sectional views taken at sections X, Y1, Y2, and Y3 after the formation of the back-side interlayer dielectric layer according to an embodiment of the present invention. Figure 9 The illustration shows cross-sectional views taken at sections X, Y1, Y2, and Y3 after etching the back-side interlayer dielectric layer to open contact holes or trenches to expose sacrificial placeholders at selected contact locations and for forming back-side local interconnects, according to an embodiment of the invention. Figure 10 The illustration shows cross-sectional views taken at sections X, Y1, Y2, and Y3 after removing exposed sacrificial occupants to expose the active region and forming contacts and local interconnects, according to an embodiment of the invention; and Figure 11The diagram shows cross-sectional views taken at sections X, Y1, Y2, and Y3 after the formation of the back-side power rails and the back-side power distribution network, according to an embodiment of the present invention. Detailed Implementation

[0012] According to embodiments of the present invention, devices and methods including connecting a gate structure to a back-side power rail are described. In a useful embodiment, a gate extension is formed in the region between an n-type field-effect transistor (NFET) and a p-type field-effect transistor (PFET) (N2P). A gate cutout or dielectric strip through the gate extension divides the gate extension into two gate extension portions. A back-side local interconnect is formed over the gate extension portions. A back-side power rail is formed and connected to the back-side local interconnect to pull down (connect) the gate. The back-side power rail provides a positive supply voltage (VDD) or a negative supply voltage (VSS) to the gates of the PFET and NFET, respectively.

[0013] In other embodiments, the semiconductor device includes a back-side local interconnect that connects the gate extension to a back-side power supply. The gate extension for the NFET and the gate extension for the PFET are separated by a dielectric strip that bifurcates or divides the gate extension. The back-side local interconnect for the NFET and the back-side local interconnect for the PFET are electrically separated by the dielectric strip to provide a compact gate connection through a tight N2P region (in which the gate extension portion is located). In one embodiment, the source / drain connected to the front-side contacts is separated from the back-side local interconnect by a back-side interlayer dielectric layer (BILD).

[0014] Now refer to the accompanying drawings (where similar numbers denote the same or similar elements and were originally referenced) Figure 1 This diagram illustrates a device according to an embodiment of the present invention and a method for manufacturing a nanosheet field-effect transistor (FET) device. The wafer 100 includes a substrate 106 having multiple layers on which the semiconductor device will be fabricated. Figure 1 The illustration depicts cross-sectional views taken at the corresponding section lines X, Y1, Y2, and Y3 in Figure 105. Figure X Y1, Y2, and Y3. Illustration 105 shows gate line 102 and active region lines 103, 104 for reference. (Through) Figures 1 to 11 The corresponding X, Y1, Y2, and Y3 views are depicted. Active region lines 103 and 104 represent the source / drain (S / D) regions of the transistor device to be formed, while gate line 102 represents such a transistor device. The transistor channel is formed on the active region lines 103 and 104 below the gate line 102. In the illustrative embodiment shown, active region line 103 is used by an NFET, while active region line 104 is used by a PFET.

[0015] Substrate 106 may include any suitable substrate structure, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and preferably includes a single-crystal semiconductor. In one example, substrate 106 may include a silicon-containing material. Illustrative examples of suitable Si-containing materials for substrate 106 may include, but are not limited to, Si, SiGe, SiGeC, SiC, and their multilayers. Although silicon is the primary semiconductor material used in wafer fabrication, alternative semiconductor materials may be used as additional layers, such as, but not limited to, germanium, gallium arsenide, gallium nitride, silicon germanium, cadmium telluride, zinc selenide, etc.

[0016] An etch stop layer 108 is formed on the substrate 106. The etch stop layer 108 may include an epitaxially grown crystal structure. The etch stop layer 108 includes a material that allows selective etching and removal of the substrate 106 in subsequent steps. In one embodiment, the etch stop layer 108 includes SiGe; however, depending on the material of the substrate 106, other materials, such as SiGeC, SiC, etc., may be selected.

[0017] The semiconductor layer 110 is epitaxially grown on the etch stop layer 108. The semiconductor layer 110 may include the same material as the substrate 106, but may use other semiconductor materials, such as SiGe, SiGeC, SiC, etc.

[0018] One or more layers are stacked onto or formed on semiconductor layer 110. In one embodiment, one or more nanosheets (NS) are applied to semiconductor layer 110. In another embodiment, the layer stack can be epitaxially grown using different chemical substances to form layers with different properties. In one embodiment, the patterned layer stack 120 includes alternating semiconductor layers 112 and 114. Semiconductor layer 112 can be selectively removed relative to semiconductor layer 114, and vice versa, for example, by a selective etching process. In one embodiment, semiconductor layer 112 comprises SiGe, where Ge can comprise, for example, 30% of a compound atom, and semiconductor layer 114 can comprise Si. It should be understood that other materials or atomic percentages can be used for semiconductor layers 112 and 114. In other embodiments, different stacking orders and numbers of layers can be used for semiconductor layers 112 and 114.

[0019] Single or multiple nanosheets or epitaxially grown layer stacks may include stack 120, which may be patterned to expose and etch semiconductor layer 110. In one embodiment, a hard mask 123 may be formed by blanket deposition of a hard mask material layer, providing a patterned photoresist on top of the hard mask material layer, and then etching the hard mask material layer to provide a hard mask pattern for etching stack 120. The patterned photoresist may be generated by applying a blanket photoresist layer to the surface of the hard mask material and exposing the photoresist layer to a radiated pattern, and then developing the pattern into the photoresist layer using a photoresist developer. The pattern in the photoresist layer is transferred to the hard mask by an etching process.

[0020] An opening 116 is formed through the stack 120 using an anisotropic etching process, such as reactive ion etching (RIE) or ion beam etching (IBE). The semiconductor layer 110 is further etched according to the opening 116 to form shallow trenches therein. Shallow trench isolation (STI) or STI 128 is formed in the etched trenches. STI 128 can be formed by depositing materials such as, for example, SiO2 or SSiO2. x N y STI 128 can be formed using dielectric materials such as SiCO or other suitable compounds. It can be deposited via chemical vapor deposition (CVD), but other deposition methods can also be used. The STI 128 can then be etched down to the level of semiconductor layer 110, for example, via RIE.

[0021] refer to Figure 2 A planarization material 129 is blanket-covered over the wafer 100. The planarization material 129 may include an organic planarization layer (OPL). The planarization material 129 is patterned to position the gate extension. In a particularly useful embodiment, the wafer 100 is processed to form a nanosheet field-effect (FET) transistor device. A gate contact opening 125 may be used for the gate extension region.

[0022] The planarization material 129 is etched to open the opening 125. The etching then continues into the STI 128 within the opening 125. The etching may include, for example, RIE or IBE.

[0023] refer to Figure 3A dummy gate material for the dummy gate 132 is blanket-coated over the wafer 100, and then a hard mask material is blanket-deposited to subsequently form a patterned hard mask 130, for example, by using photolithography patterning. The dummy gate material may include polysilicon, amorphous Si, or other selectively removable materials. The hard mask material is patterned to form the hard mask 130. The dummy gate 132 is etched using the hard mask 130. Then, a deposition process is used to form a spacer 134. The spacer 134 may include nitrides, such as, for example, SiN, SiBCN, SiOCN, SiOC, SiC, but other dielectric materials may be used.

[0024] The hard mask 130 can be used as an etching mask to etch nanosheets (e.g., stack 120) to expose the semiconductor layer 110. Regions of the nanosheets located beneath the hard mask 130 are patterned for further processing, while in other regions the nanosheets (e.g., stack 120) are completely removed.

[0025] Following nanosheet etching, the exposed sacrificial sheet of semiconductor layer 112 is indented (laterally etched), and an inner spacer (not shown) is formed and includes a dielectric material. In one embodiment, the inner spacer is formed using an exposed portion of semiconductor layer 112, which undergoes a Ge agglomeration process to form a dielectric oxide (SiO2) at the exposed portion via a thermal oxidation process. The oxidation process converts SiGe into a dielectric material and condenses Ge.

[0026] Hard mask 130 can be used as an etching mask to etch semiconductor layer 110. Semiconductor layer 110 is etched to form trenches, for example, through RIE. Sacrificial placeholders 142 are formed within the trenches etched into semiconductor layer 110. Sacrificial placeholders 142 can be epitaxially grown in the trenches of semiconductor layer 110. Sacrificial placeholders 142 may comprise SiGe or other epitaxially grown materials that can be selectively removed relative to semiconductor layer 110.

[0027] An epitaxial growth process is performed to form source and drain (S / D) regions 148 and 150. S / D regions 148 and 150 may comprise Si or SiGe and, when epitaxial growth is unrestricted, include surfaces with facets. In one embodiment, S / D regions 148 and 150 may be designated as N-type or P-type devices, respectively, wherein N-type devices may comprise, for example, Si, and P-type devices may comprise, for example, SiGe. S / D regions 148 and 150 may be appropriately doped during formation by epitaxial growth. For example, S / D region 150 may be doped by introducing a p-type dopant (e.g., B, Ga, etc.) during epitaxial formation. Similarly, S / D region 148 may be doped by introducing an n-type dopant (e.g., P, As, etc.) during epitaxial formation. P-type and N-type devices may be formed adjacent to each other.

[0028] refer to Figure 4 A dielectric layer 160, such as an interlayer dielectric (ILD), is formed on the wafer 100. The dielectric layer 160 may comprise any suitable material, for example selected from the group consisting of silicon-containing materials, such as SiO2, Si3N4, SiO2, etc. x N y SiC, SiCO, SiCOH, and SiCH compounds, wherein some or all of the Si in the above-mentioned Si-containing materials are replaced by Ge, carbon-doped oxides, inorganic oxides, inorganic polymers, mixed polymers, or organic polymers (such as polyamides or SiLK). TM Other carbon-containing materials, organic-inorganic materials (such as spin-coated glass and silsesquioxane materials), and diamond-like carbon (DLC, also known as amorphous hydride carbon, α-C:H) can be used. Dielectric layer 160 can be deposited using CVD, but other deposition methods can be employed.

[0029] The dummy gate 132 and semiconductor layer 112 are removed by etching. This can include a separate etching process. Afterward, an alternative gate metal 152 is formed, which includes a gate dielectric (such as, for example, HfO2, HfSiO2). x HfAlO x HfLaO x (etc.), one or more layers of work function metal (WFM) and conductive metal filler (such as, for example, W, Al, Ru).

[0030] Gate metal 152 is deposited into opening 125 ( Figure 2 A gate extension 126 is formed in the STI 128. The gate extension 126 extends into the STI 128 and brings the conductive material closer to the back side of the wafer 100.

[0031] According to an embodiment of the present invention, a gate notch 154 is formed to separate and provide electrical isolation between structures. The gate notch 154 is patterned using photolithographic patterning techniques. For example, photolithography can be used to pattern an etching mask (not shown). Trenches for the gate notch 154 are etched according to the etching mask, and then the gate notch 154 is filled with a dielectric material and the free surface is planarized. The gate notch 154 separates a portion of the gate extension 126 and separates the S / D regions 148, 150 from each other. The gate notch 154 can be formed down to the semiconductor layer 110. The gate notch 154 can be formed into and through the STI 128. The gate notch 154 can comprise any suitable material, for example selected from the group consisting of silicon-containing materials such as SiO2, Si3N4, SiO2, etc. x N ySiC, SiCO, SiCOH, and SiCH compounds, wherein some or all of the Si in the above-mentioned Si-containing materials are replaced by Ge, carbon-doped oxides, inorganic oxides, inorganic polymers, mixed polymers, or organic polymers (such as polyamides or SiLK). TM Other carbon-containing materials, organic-inorganic materials (such as spin-coated glass and silsesquioxane materials), and diamond-like carbon (DLC, also known as amorphous hydride carbon, α-C:H) can be used to deposit the gate notch 154, including CVD and plasma-enhanced CVD (PECVD), but other deposition methods are also possible.

[0032] refer to Figure 5 Intermediate process (MOL) contacts 162 and 164 are formed to establish connections with S / D regions 148 and 150 and gate metal 152 on the top side of wafer 100.

[0033] A dielectric layer 168 is formed on wafer 100 and planarized. Trench or via is formed in the dielectric layer 168 forming the top ILD. The trench or via exposes the active material underneath for S / D regions 148 and 150 and may expose a portion of the gate metal 152.

[0034] In a useful embodiment, a silicide liner (such as Ti, Ni, NiPt) is first deposited in the contact trench, and then a diffusion barrier layer can be formed in the contact trench before conductive filling. The diffusion barrier layer may include, for example, TiN, TaN, or similar materials.

[0035] Conductive filling is performed to fill the trenches above the diffusion barrier layer (if present). The conductive filler may include materials such as, for example, Co, Cu, Ru, Mo, Rh, W, Ir, and alloys, or combinations of these and other conductive materials. In a particularly useful embodiment, the conductive filler includes W. The conductive filler may be formed using deposition methods such as, for example, CVD, PECVD, atomic layer deposition (ALD), or any other suitable deposition method. The conductive filler is planarized by CMP to form contacts 162, 164.

[0036] Processing continues to form a back-to-office (BEOL) layer 170, which may include a metal structure and a dielectric layer to complete the top side of the device and provide electrical access to the formed device. A carrier wafer 172 may be bonded to the BEOL layer 170. The carrier wafer 172 provides support and transportability for the wafer 100 for further processing, including flipping the wafer 100 and removing portions of the bottom side of the device.

[0037] refer to Figure 6To continue processing, wafer 100 can be flipped to process features on the bottom side of the device. However, for clarity and consistency, the device will be shown in the figures with the same orientation as previously described, and the bottom / top will be consistently referenced. Substrate 106 is removed from the bottom side of the device. Substrate 106 can be removed by an etching process that stops at etch stop layer 108. In an alternative embodiment, a cleave process can be used to propagate cracks to remove substrate 106 at etch stop layer 108.

[0038] refer to Figure 7 The etch stop layer 108 is then removed by an etching process. In an alternative embodiment, a CMP process may be used. With the removal of the etch stop layer 108, the semiconductor layer 110 is exposed. The semiconductor layer 110 is removed by an etching process that selectively removes material from the semiconductor layer 110 relative to the STI 128, the sacrificial placeholder 142, or the gate metal 152 (e.g., a high-k metal). Removal of the semiconductor layer 110 forms an opening 178.

[0039] refer to Figure 8 A dielectric layer 180 is formed in the opening 178. The dielectric layer 180 includes a material that can be selectively removed relative to the material of the gate notch 154. In one embodiment, the dielectric layer 180 comprises silicon oxide. The dielectric layer 180 forms a back-side ILD (BILD).

[0040] refer to Figure 9 The back-side contacts are positioned to establish connections with the S / D regions 148 and 150 and the gate metal 152. An opening 182 is formed in the dielectric layer 180. The opening 182 can be patterned using photolithography to create an etch mask, thereby etching the opening 182 with anisotropic etching (e.g., RIE). The opening 182 exposes the underlying sacrificial placeholder 142 corresponding to the S / D regions 148, 150.

[0041] According to an embodiment of the invention, an opening 182 is etched into the dielectric layer 180, STI 128, and sacrificial placeholder 142 according to a pattern to form a back-side contact. In the region 186 where a gate pull-down is to be formed, the opening 182 extends along the side of a gate cutout 154. The gate cutout 154 allows for self-alignment of spacers between portions of region 186. Region 186 provides areas for placing local interconnects, as described below.

[0042] In the area where the sacrificial occupant 142 has been exposed, the sacrificial occupant 142 is etched to create an opening. The etching process may include dry etching or wet etching, which selectively etches the sacrificial occupant 142 relative to the S / D regions 148, STI 128, and dielectric layer 180 to complete the opening for the active region contact. The corresponding S / D regions 148, 150 are now exposed through the opening 182.

[0043] refer to Figure 10 In a useful embodiment, a silicide liner (such as Ti, Ni, NiPt) is first deposited, and then a diffusion barrier layer can be formed in the opening 182 prior to conductive filling. The diffusion barrier layer may include, for example, TiN, TaN, or similar materials. Conductive filling is performed to fill the opening 182. The conductive filler may include materials such as, for example, Cu, Ru, Mo, Rh, W, Ir, and alloys, or combinations of these and other conductive materials. In a particularly useful embodiment, the conductive filler includes Cu. The conductive filler may be formed using deposition methods such as, for example, CVD, PECVD, ALD, or any other suitable deposition method. The conductive filler is planarized by CMP to form local interconnects 190 and 192 and back-side contacts 194.

[0044] The planarization process ensures a clear boundary between local interconnects 190 and 192. This is achieved by planarizing to remove conductive material from a gate cutout 154 that separates local interconnects 190 from local interconnects 192. Local interconnect 190 serves as a gate pull-down for the NFET (S / D region 148), and local interconnect 192 serves as a gate pull-down for the PFET (S / D region 150).

[0045] refer to Figure 11 The process continues, forming a back-side interconnect layer 195, which may include a metal structure and a dielectric layer to complete the bottom side of the device and provide electrical access to the formed device. The back-side interconnect layer 195 is formed on the dielectric layer 180. A dielectric layer 202, which may include the same material as the dielectric layer 180, is deposited and may be planarized. The dielectric layer 202 is patterned using photolithography to define openings for back-side power rails 197 and 198. The back-side power rails 197 and 198 are formed using a damascene process. Conductive filling is performed using any suitable deposition process, such as physical vapor deposition (PVD), CVD, PECVD, ALD, etc. The conductive filling may include materials such as, for example, Co, Cu, Ru, Mo, Rh, W, Ir, and alloys or combinations of these and other conductive materials. The conductive filling is planarized, for example, by CMP to form the back-side power rails 197 and 198. The back-side power rails 197 and 198 are configured to contact the local interconnects 190 and 192 and the back-side contact 194.

[0046] According to an exemplary embodiment, back-side power rail 197 provides VSS to the NFET (region 148), and back-side power rail 197 provides VDD to the PFET (region 150). Local interconnect 190 is connected to back-side power rail 198, and local interconnect 192 is connected to back-side power rail 197.

[0047] A back-side power distribution network (BSPDN) 199 is fabricated on insulating layer 202, and connections are established from BSPDN 199 to back-side power rails 197 and 198. Processing continues to complete the device.

[0048] According to embodiments of the present invention, gate pull-down of NFETs and PFETs within a compact transistor-to-transistor (T2T) region is achieved without affecting wiring or top-side or bottom-side wiring structures. Furthermore, local interconnects are provided that allow direct connection to the back-side power rail via a location or region between the NFET and PFET (N2P). This embodiment makes it easy and reliable to connect gates to the back-side power distribution network (BSPDN) via gate pull-down, especially considering the reduced node size.

[0049] Exemplary applications / uses to which this invention can be applied include, but are not limited to, semiconductor devices. Semiconductor devices may include processors, memory devices, application-specific integrated circuits (ASICs), logic circuits or devices, combinations thereof, and any other circuit devices. In such devices, one or more semiconductor devices may be included in a central processing unit, a graphics processing unit, and / or a separate processor- or computing element-based controller (e.g., logic gates, etc.). Semiconductor devices may include one or more onboard memories (e.g., caches, dedicated memory arrays, read-only memory, etc.). In some embodiments, a semiconductor device may include one or more memories that may be on-board or off-board, or may be dedicated to use by a hardware processor subsystem (e.g., ROM, RAM, basic input / output system (BIOS), etc.).

[0050] In some embodiments, the semiconductor device may include and execute one or more software elements. The one or more software elements may include an operating system and / or one or more applications and / or specific code to achieve a specified result. In other embodiments, the semiconductor device may include dedicated, specialized circuitry that performs one or more electronic processing functions to achieve the specified result. Such circuitry may include one or more field-programmable gate arrays (FPGAs) and / or programmable application-programmable logic arrays (PLAs).

[0051] It should be understood that aspects of the invention will be described based on the given illustrative architecture; however, other architectures, structures, substrate materials, and process features and steps may be varied within the scope of these aspects.

[0052] It will also be understood that when an element, such as a layer, region, or substrate, is described as being "on" or "above" another element, it can be directly on the other element, or there may be intermediate elements present. In contrast, when an element is described as being "directly" on or "directly" above another element, there are no intermediate elements. It will also be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0053] This embodiment may include a design for an integrated circuit chip, which can be created using a graphical computer programming language and stored in a computer storage medium, such as a disk, magnetic tape, physical hard disk drive, or virtual hard disk drive (such as in a storage access network). If the designer does not manufacture the chip or the photomask used to manufacture the chip, the designer may transfer the resulting design directly or indirectly to such an entity by physical means (e.g., by providing a copy of the storage medium containing the design) or electronic means (e.g., via the Internet). The stored design is then converted into a suitable format (e.g., GDSII) for manufacturing the photomask, which typically includes multiple copies of the chip design in question to be formed on a wafer. The photomask is used to define areas of the wafer (and / or layers on it) to be etched or otherwise processed.

[0054] The methods described herein can be used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer either as bare dies (i.e., as a single wafer with multiple unpackaged chips) or in packages. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads for attachment to a motherboard or other more advanced carrier) or in a multi-chip package (such as a ceramic carrier with either surface-mount or buried interconnects). In either case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0055] It should also be understood that the material compounds will be described according to the listed elements, such as SiGe. These compounds include different proportions of elements within the compound; for example, SiGe includes Si. x Ge 1-x Where x is less than or equal to 1, etc. Furthermore, other elements can be included in the compound and it will still function according to the current principles. Compounds with additional elements will be referred to herein as alloys.

[0056] In this specification, references to "an embodiment," "embodiment," and other variations mean that a particular feature, structure, characteristic, etc., described in connection with that embodiment is included in at least one embodiment. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing throughout this specification, and any other variations, do not necessarily refer to the same embodiment.

[0057] It should be understood that any use of " / ", "and / or", and "at least one" below, such as in "A / B", "A and / or B", and "at least one of A and B", is intended to cover the selection of selecting only the first listed option (A), or only the second listed option (B), or both options (A and B). As a further example, in the cases of "A, B, and / or C" and "at least one of A, B, and C", this wording is intended to cover the selection of only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). As will be readily apparent to those skilled in the art and related fields, this can be extended to list as many items as possible.

[0058] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that, when used herein, the terms “comprising” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0059] Spatial relative terms, such as “below,” “under,” “lower,” “above,” “upper,” “top,” “bottom,” etc., may be used herein for descriptive purposes to describe the relationship between one element or feature shown in a figure and another element(s) or feature(s). It will be understood that, in addition to the orientation shown in the figure, spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, an element described as “below” or “under” other elements or features will be oriented as “above” other elements or features. Thus, “below” can include both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more intermediate layers.

[0060] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, the first element discussed below can be referred to as the second element without departing from the scope of this concept.

[0061] Preferred embodiments of the apparatus and method have been described (these are intended to be illustrative and not restrictive), and it should be noted that modifications and variations can be made by those skilled in the art based on the foregoing teachings. Therefore, it should be understood that changes can be made to the specific embodiments disclosed within the scope of the invention as outlined in the appended claims. Thus, having described aspects of the invention in the details and specificities required by patent law, the content claimed and desired for protection by a patent certificate is set forth in the appended claims.

Claims

1. A semiconductor device, comprising: Gate metal; A gate extension is disposed in the region between two transistors having opposite conductivity and connected to the gate metal, the gate extension extending toward the side of the semiconductor device having a power rail; A gate notch, disposed within the gate metal and extending through the gate extension, divides the gate extension into electrically isolated portions; and Each portion of the gate extension is coupled to the back-side power rail.

2. The semiconductor device according to claim 1, wherein, The gate extension is disposed within a shallow trench isolation.

3. The semiconductor device according to claim 1, wherein, Each portion of the gate extension is connected to a local interconnect.

4. The semiconductor device according to claim 3, wherein, The local interconnect connects a portion of the gate extension to the corresponding back-side power rail.

5. The semiconductor device according to claim 4, wherein, The gate extension extends toward the back side of the semiconductor device, and the local interconnect is disposed within the layer for the back side contacts.

6. The semiconductor device according to claim 4, wherein, The source / drain regions connected to the top-side contacts are separated from the local interconnect by the back-side interlayer dielectric layer.

7. The semiconductor device of claim 1, further comprising source / drain regions of two transistors having opposite conductivity, wherein the gate cutout is disposed between the source / drain regions.

8. A semiconductor device, comprising: N-type field-effect transistor (NFET); A P-type field-effect transistor (PFET) is configured to be adjacent to the NFET; A gate metal is disposed in the region between the NFET and the PFET; A gate extension is disposed in the region between the NFET and the PFET and is connected to the gate metal on the back side of the semiconductor device; as well as A gate notch is configured to pass through the gate metal and through the gate extension to divide the gate extension into a first portion and a second portion so that the first portion is electrically isolated from the second portion; and The first portion is coupled to a first back-side power rail and the second portion is coupled to a second back-side power rail.

9. The semiconductor device according to claim 8, wherein, The gate extension is disposed within a shallow trench isolation.

10. The semiconductor device according to claim 8, wherein, The first portion of the gate extension is connected to the back-side power rail of the supply voltage via a local interconnect.

11. The semiconductor device according to claim 8, wherein, The second portion of the gate extension is connected to the grounded back-side power rail via a local interconnect.

12. The semiconductor device according to claim 8, wherein, The gate notch is disposed between the source / drain regions of the NFET and the PFET.

13. The semiconductor device of claim 8 further includes an additional gate notch disposed between source / drain regions having the same conductivity.

14. The semiconductor device according to claim 8, wherein, The first portion is coupled to the first back-side power rail using a first local interconnect, and the second portion is coupled to the second back-side power rail using a second local interconnect.

15. The semiconductor device according to claim 14, wherein, The first local interconnect and the second local interconnect are disposed within the layer for the back contact.

16. The semiconductor device according to claim 14, wherein, The source / drain regions connected to the top-side contact are separated from the corresponding local interconnects in the first and second local interconnects by the back-side interlayer dielectric layer.

17. A method for manufacturing a semiconductor device, comprising: The gate electrode is extended by forming a gate extension into the shallow trench isolation (STI) region at the NFET to PFET (N2P) boundary; The gate extension is divided into portions by forming a gate cut through the gate extension to separate the gate extension; A portion of the back-side partial interconnect is formed to connect to the gate extension; as well as A power rail is formed to connect to the back-side local interconnect to pull down the gate electrode.

18. The method according to claim 17, wherein, The back-side local interconnect is formed by depositing conductors in the openings separated by the gate cutout.

19. The method of claim 17, further comprising forming an additional gate cut-out disposed between source / drain regions having the same conductivity.

20. The method of claim 17, wherein, The back-side local interconnects are formed within the layer used for the back-side contacts, and the source / drain regions connected to the top-side contacts are separated from the corresponding back-side local interconnects by a back-side interlayer dielectric layer.

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