A low power watchdog circuit
The low-power watchdog circuit designed with a three-stage oscillator and counter solves the problem of high power consumption in existing watchdog circuits in low-power applications, and realizes an extremely low-power circuit design.
Patent Information
- Application Number
- CN202610428507.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-02
- Publication Date
- 2026-07-10
Smart Images
Figure CN122363972A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a low-power watchdog circuit. Background Technology
[0002] In digital or mixed-signal circuits, watchdog circuits are frequently needed to reset signals and prevent the program from entering an abnormal state. However, ordinary watchdog circuits typically consume power in the microampere (µA) range, which can be a significant portion of power consumption in low-power applications if operating continuously. Therefore, there is a pressing need for an ultra-low-power watchdog circuit. Summary of the Invention
[0003] The purpose of this invention is to provide a low-power watchdog circuit to solve the problems in the background art.
[0004] To address the aforementioned technical problems, this invention provides a low-power watchdog circuit, comprising: An oscillator consists of a three-stage oscillator circuit, with the size of the three-stage oscillator circuit gradually increasing, and each stage driving the input capacitor of the next stage. The counter receives the clock signal generated by the oscillator and outputs a dog-feed signal. The watchdog signal circuit generates a reset signal to the reset terminals of each flip-flop in the counter under the action of the watchdog signal; when there is no watchdog signal, the reset signal is 0, the counter counts down and starts counting, and outputs a high level when it counts to 0; if the watchdog signal is valid during the counting process, the counter will be reset to 11…1.
[0005] In one feasible implementation, the first-stage oscillation circuit includes 4n PMOS transistors and 8n NMOS transistors. The 4n PMOS transistors are connected in series to form a first PMOS transistor chain, and the 8n NMOS transistors are connected in series to form a first NMOS transistor chain. The source terminal of the first PMOS transistor in the first PMOS transistor chain is connected to VDD, and the drain terminal of the last PMOS transistor in the first NMOS transistor chain is connected to the drain terminal of the first NMOS transistor in the first NMOS transistor chain. The source terminal of the last NMOS transistor in the first NMOS transistor chain is grounded. The gate terminals of the 4n PMOS transistors in the first PMOS transistor chain are interconnected and connected to a first node, and the gate terminals of the 8n NMOS transistors in the first NMOS transistor chain are interconnected and connected to a first node. The second-stage oscillation circuit includes 2n PMOS transistors and 4n NMOS transistors. The 2n PMOS transistors are connected in series to form a second PMOS transistor chain, and the 4n NMOS transistors are connected in series to form a second NMOS transistor chain. The source of the first PMOS transistor in the second PMOS transistor chain is connected to VDD, and the drain of the last PMOS transistor in the second NMOS transistor chain is connected to the drain of the first NMOS transistor in the second NMOS transistor chain. The source of the last NMOS transistor in the second NMOS transistor chain is grounded. The gates of the 2n PMOS transistors in the second PMOS transistor chain are interconnected and connected to the second node, and the gates of the 4n NMOS transistors in the second NMOS transistor chain are interconnected and connected to the second node. The third-stage oscillation circuit includes n PMOS transistors and 2n NMOS transistors. The n PMOS transistors are connected in series to form a third PMOS transistor chain, and the 2n NMOS transistors are connected in series to form a third NMOS transistor chain. The source terminal of the first PMOS transistor in the third PMOS transistor chain is connected to VDD, and the drain terminal of the last PMOS transistor is connected to the drain terminal of the first NMOS transistor in the third NMOS transistor chain. The source terminal of the last NMOS transistor in the third NMOS transistor chain is grounded. The gate terminals of the n PMOS transistors in the third PMOS transistor chain are interconnected and connected to the third node, and the gate terminals of the 2n NMOS transistors in the third NMOS transistor chain are interconnected and connected to the third node.
[0006] In one feasible implementation, the drain of the tail-end PMOS transistor in the third PMOS transistor chain and the drain of the head-end NMOS transistor in the third NMOS transistor chain are connected to the first node; the drain of the tail-end PMOS transistor in the second PMOS transistor chain and the drain of the head-end NMOS transistor in the second NMOS transistor chain are connected to the third node; and the drain of the tail-end PMOS transistor in the first PMOS transistor chain and the drain of the head-end NMOS transistor in the first NMOS transistor chain are connected to the second node.
[0007] In one feasible implementation, the individual MOS transistors in the three-stage oscillation circuit are of the same size, the size of the subsequent PMOS transistor chain is twice that of the previous PMOS transistor chain, and the size of the subsequent NMOS transistor chain is twice that of the previous NMOS transistor chain; each stage only needs to drive the input capacitor in the next stage, so that the load of each stage is relatively balanced.
[0008] In one feasible implementation, the counter comprises M flip-flops and one NOR gate; M flip-flops are connected in sequence, and the input port D of each flip-flop is connected to its own inverted output port. The clock port C of the first flip-flop is connected to the clock signal output by the oscillator, and the clock ports C of the second to Mth flip-flops are respectively connected to the output port Q of the previous flip-flop; the input of the NOR gate is connected to the output port Q of each flip-flop, and the output of the gate outputs a dog feed signal to the dog feed circuit. When the outputs of these M flip-flops are all 0, the NOR gate outputs a high level, which is a counter from M 11…1 to M 00…0.
[0009] In one feasible implementation, the dog-feeding circuit includes a delay module and an XOR gate; One input of the XOR gate is directly input to the dog feed signal, and the other input is input to the dog feed signal delayed by the delay module. The XOR gate generates a reset signal SETB which is sent to the reset terminals of each flip-flop in the counter.
[0010] This invention provides a low-power watchdog circuit, comprising an oscillator, a counter, and a watchdog signal circuit. The oscillator consists of a three-stage oscillator circuit, with the size of the three stages gradually increasing, each stage driving the input capacitor of the next stage. The counter receives the clock signal generated by the oscillator and outputs a watchdog signal. Under the action of the watchdog signal, the watchdog signal circuit generates a reset signal to the reset terminals of each flip-flop in the counter. When there is no watchdog signal, the reset signal is 0, the counter starts counting down, counts to 0, and outputs a high level. If the watchdog signal is valid during the counting process, the counter will be reset to 11…1. The oscillator and counter of this invention achieve extremely low power consumption. Attached Figure Description
[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0012] Figure 1 This is a schematic diagram of the oscillator structure provided by the present invention.
[0013] Figure 2 This is a schematic diagram of the counter structure provided by the present invention.
[0014] Figure 3 This is a schematic diagram of the dog feeding signal circuit provided by the present invention. Detailed Implementation
[0015] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0016] The serial numbers assigned to components in this application, such as "first" and "second," are merely for distinguishing the described objects and have no sequential or technical meaning. The terms "connection" and "linkage," unless otherwise specified, are not limited to physical or mechanical connections and can include electrical communication connections, whether direct or indirect. In the description of this application, it should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "middle," "between," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on this application.
[0017] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion.
[0018] This invention provides a low-power watchdog circuit, comprising three parts: an oscillator providing extremely low power for the watchdog, an extremely low-power counter, and a watchdog signal circuit.
[0019] Extremely low power oscillators such as Figure 1 As shown, it consists of a three-stage oscillation circuit: The first-stage oscillation circuit includes 4n PMOS transistors and 8n NMOS transistors. The 4n PMOS transistors are connected in series to form the first PMOS transistor chain, and the 8n NMOS transistors are connected in series to form the first NMOS transistor chain. The source of the first PMOS transistor in the first PMOS transistor chain is connected to VDD, and the drain of the last PMOS transistor in the first NMOS transistor chain is connected to the drain of the first NMOS transistor in the first NMOS transistor chain. The source of the last NMOS transistor in the first NMOS transistor chain is grounded. The gates of the 4n PMOS transistors in the first PMOS transistor chain are interconnected and connected to the first node A, and the gates of the 8n NMOS transistors in the first NMOS transistor chain are interconnected and connected to the first node A.
[0020] The second-stage oscillation circuit includes 2n PMOS transistors and 4n NMOS transistors. The 2n PMOS transistors are connected in series to form a second PMOS transistor chain, and the 4n NMOS transistors are connected in series to form a second NMOS transistor chain. The source of the first PMOS transistor in the second PMOS transistor chain is connected to VDD, and the drain of the last PMOS transistor in the second NMOS transistor chain is connected to the drain of the first NMOS transistor in the second NMOS transistor chain. The source of the last NMOS transistor in the second NMOS transistor chain is grounded. The gates of the 2n PMOS transistors in the second PMOS transistor chain are interconnected and connected to the second node B, and the gates of the 4n NMOS transistors in the second NMOS transistor chain are interconnected and connected to the second node B.
[0021] The third-stage oscillator circuit includes n PMOS transistors and 2n NMOS transistors. The n PMOS transistors are connected in series to form a third PMOS transistor chain, and the 2n NMOS transistors are connected in series to form a third NMOS transistor chain. The source of the first PMOS transistor in the third PMOS transistor chain is connected to VDD, and the drain of the last PMOS transistor is connected to the drain of the first NMOS transistor in the third NMOS transistor chain. The source of the last NMOS transistor in the third NMOS transistor chain is grounded. The gates of the n PMOS transistors in the third PMOS transistor chain are interconnected and connected to the third node C. The gates of the 2n NMOS transistors in the third NMOS transistor chain are interconnected and connected to the third node C.
[0022] Furthermore, the connection between the drain of the tail PMOS transistor in the third PMOS transistor chain and the drain of the head NMOS transistor in the third NMOS transistor chain is connected to the first node A; the connection between the drain of the tail PMOS transistor in the second PMOS transistor chain and the drain of the head NMOS transistor in the second NMOS transistor chain is connected to the third node C; and the connection between the drain of the tail PMOS transistor in the first PMOS transistor chain and the drain of the head NMOS transistor in the first NMOS transistor chain is connected to the second node B.
[0023] Looking from left to right, the individual transistors are the same size; the difference lies in the number of transistors connected in series in the chain. For example, the second stage has 4n NMOS transistors connected in series, while the first stage has 8n NMOS transistors connected in series. Therefore, the size (W / L) of the second stage is twice that of the first stage. This is mainly to achieve an optimal balance between delay, area, and power consumption. Each stage only needs to drive the input capacitor of the next stage (i.e., the parasitic capacitance of the MOS transistors), making the load of each stage relatively balanced. According to the logic effort theory, the optimal scaling factor is approximately e (2.718), but in actual designs, it is often taken as an integer multiple (such as 2 or 3) to simplify layout and calculation; here, 2 is used. Figure 1 The circuit is divided into three parts: left, middle, and right. Each part can be regarded as an inverter. In this case, the driving capability will be very weak under low power consumption. In order to gradually enhance the driving capability, the ratio of the inverter needs to remain unchanged while the subsequent circuit continues to amplify W / L until the driving capability is sufficient to drive a normal inverter.
[0024] When n is relatively large, the current of this oscillator can be compressed to tens of nA @ 180nm process.
[0025] Extremely low power counters such as Figure 2 As shown, it includes M flip-flops and one NOR gate. The M flip-flops are connected sequentially, and the input port D of each flip-flop is connected to its own inverted output port. The clock port C of the first flip-flop is connected to the clock signal output by the oscillator, and the clock ports C of the second to Mth flip-flops are respectively connected to the output port Q of the previous flip-flop; the input of the NOR gate is connected to the output port Q of each flip-flop, and the output of the gate outputs a dog feed signal to the dog feed circuit.
[0026] When the outputs of these M flip-flops are all 0, the NOR gate outputs a high level. This is a counter that ranges from M 11…1 to M 00…0.
[0027] Combined with the oscillator clock mentioned earlier, the basic module of a counter can be formed.
[0028] Dog feeding circuit, such as Figure 3 As shown, it includes a delay module and an XOR gate. One input of the XOR gate directly receives the watchdog signal, and the other input receives the watchdog signal delayed by the delay module. The XOR gate generates a reset signal SETB, which is sent to the reset terminals of each flip-flop in the counter.
[0029] The delayed watchdog signal is XORed with the watchdog signal itself and output to the reset pins of each flip-flop in the counter. When there is no watchdog signal, SETB=0, the counter starts counting down, and when it counts to 0, it outputs a high level. If the watchdog signal pulse is valid during the counting process, the counter will be reset to 11…1.
[0030] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0031] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A low-power watchdog circuit, characterized in that, include: An oscillator consists of a three-stage oscillator circuit, with the size of the three-stage oscillator circuit gradually increasing, and each stage driving the input capacitor of the next stage. The counter receives the clock signal generated by the oscillator and outputs a dog-feed signal. The watchdog signal circuit generates a reset signal to the reset terminals of each flip-flop in the counter under the action of the watchdog signal; when there is no watchdog signal, the reset signal is 0, the counter counts down and starts counting, and outputs a high level when it counts to 0; if the watchdog signal is valid during the counting process, the counter will be reset to 11…1.
2. The low-power watchdog circuit as described in claim 1, characterized in that, The first-stage oscillation circuit includes 4n PMOS transistors and 8n NMOS transistors. The 4n PMOS transistors are connected in series to form a first PMOS transistor chain, and the 8n NMOS transistors are connected in series to form a first NMOS transistor chain. The source terminal of the first PMOS transistor in the first PMOS transistor chain is connected to VDD, and the drain terminal of the last PMOS transistor in the first NMOS transistor chain is connected to the drain terminal of the first NMOS transistor chain. The source terminal of the last NMOS transistor in the first NMOS transistor chain is grounded. The gate terminals of the 4n PMOS transistors in the first PMOS transistor chain are interconnected and connected to the first node, and the gate terminals of the 8n NMOS transistors in the first NMOS transistor chain are interconnected and connected to the first node. The second-stage oscillation circuit includes 2n PMOS transistors and 4n NMOS transistors. The 2n PMOS transistors are connected in series to form a second PMOS transistor chain, and the 4n NMOS transistors are connected in series to form a second NMOS transistor chain. The source of the first PMOS transistor in the second PMOS transistor chain is connected to VDD, and the drain of the last PMOS transistor in the second NMOS transistor chain is connected to the drain of the first NMOS transistor in the second NMOS transistor chain. The source of the last NMOS transistor in the second NMOS transistor chain is grounded. The gates of the 2n PMOS transistors in the second PMOS transistor chain are interconnected and connected to the second node, and the gates of the 4n NMOS transistors in the second NMOS transistor chain are interconnected and connected to the second node. The third-stage oscillation circuit includes n PMOS transistors and 2n NMOS transistors. The n PMOS transistors are connected in series to form a third PMOS transistor chain, and the 2n NMOS transistors are connected in series to form a third NMOS transistor chain. The source terminal of the first PMOS transistor in the third PMOS transistor chain is connected to VDD, and the drain terminal of the last PMOS transistor is connected to the drain terminal of the first NMOS transistor in the third NMOS transistor chain. The source terminal of the last NMOS transistor in the third NMOS transistor chain is grounded. The gate terminals of the n PMOS transistors in the third PMOS transistor chain are interconnected and connected to the third node, and the gate terminals of the 2n NMOS transistors in the third NMOS transistor chain are interconnected and connected to the third node.
3. The low-power watchdog circuit as described in claim 2, characterized in that, The drain of the tail PMOS transistor in the third PMOS transistor chain and the drain of the head NMOS transistor in the third NMOS transistor chain are connected to the first node. The drain of the tail PMOS transistor in the second PMOS transistor chain and the drain of the head NMOS transistor in the second NMOS transistor chain are connected to the third node. The drain of the tail PMOS transistor in the first PMOS transistor chain and the drain of the head NMOS transistor in the first NMOS transistor chain are connected to the second node.
4. The low-power watchdog circuit as described in claim 2, characterized in that, In the three-stage oscillation circuit, the size of each MOS transistor is the same. The size of the subsequent PMOS transistor chain is twice that of the previous PMOS transistor chain, and the size of the subsequent NMOS transistor chain is twice that of the previous NMOS transistor chain. Each stage only needs to drive the input capacitor in the next stage, so that the load of each stage is relatively balanced.
5. The low-power watchdog circuit as described in claim 1, characterized in that, The counter comprises M flip-flops and one NOR gate; M flip-flops are connected in sequence, and the input port D of each flip-flop is connected to its own inverted output port. The clock port C of the first flip-flop is connected to the clock signal output by the oscillator, and the clock ports C of the second to Mth flip-flops are respectively connected to the output port Q of the previous flip-flop; the input of the NOR gate is connected to the output port Q of each flip-flop, and the output of the gate outputs a dog feed signal to the dog feed circuit. When the outputs of these M flip-flops are all 0, the NOR gate outputs a high level, which is a counter from M 11…1 to M 00…0.
6. The low-power watchdog circuit as described in claim 1, characterized in that, The dog-feeding circuit includes a delay module and an XOR gate; One input of the XOR gate is directly input to the dog feed signal, and the other input is input to the dog feed signal delayed by the delay module. The XOR gate generates a reset signal SETB which is sent to the reset terminals of each flip-flop in the counter.