An alternating current driving inverter adaptive fault-tolerant control method and storage medium

Abstract

This invention provides an adaptive fault-tolerant control method and storage medium for an AC drive inverter, relating to the field of power electronics control technology. The method includes: real-time monitoring of the operating status of multiple parallel inverter units; when a fault is detected in any inverter unit, its operation is disconnected online, and the number N of effective working units in the system is dynamically updated; based on the updated N value, current sharing control is performed on the remaining normal parallel inverter units to redistribute the total load current. The system includes a main control box and multiple parallel inverter units, with the main control box executing the above method. This invention achieves continuous operation of the system without shutdown through online fault diagnosis, rapid isolation of faulty units, and dynamic current sharing reconstruction based on the number of remaining units, significantly improving the reliability and fault tolerance of the parallel inverter system. This invention also discloses a computer-readable storage medium.

Description

Technical Field

[0001] This invention relates to the field of parallel technology of AC drive equipment, and in particular to an adaptive fault-tolerant control method and storage medium for AC drive inverters. Background Technology

[0002] With increasingly stringent requirements for uninterrupted power supply in critical AC loads such as metallurgical, aviation, petrochemical, and precision manufacturing production lines, and the widespread adoption of parallel expansion of multiple inverters in new energy microgrids and high-power AC drive systems, any single inverter failure must be seamlessly taken over by redundant modules within milliseconds to handle all load current.

[0003] However, the following problems still exist in the current "cold-temperature standby" transmission solutions in the industry:

[0004] 1) Speed ​​cannot be adjusted after switching to mains frequency.

[0005] 2) The switching of dual frequency converters for standby requires stopping and restarting, which causes fluctuations in motor speed.

[0006] 3) The cost of switching between frequency converter and motor backup is high, and the switching is delayed and has weak resistance to power fluctuations.

[0007] Traditional solutions have switching times ranging from several seconds to hundreds of seconds and are prone to circulating current surges, synchronization loss, and load voltage drops. They can no longer meet the requirements for high reliability, hot-swappable, and plug-and-play online adaptive fault tolerance. Therefore, there is an urgent need for an adaptive fault-tolerant control method for AC drive inverters that can achieve millisecond-level fault detection and current sharing reconstruction. Summary of the Invention

[0008] In view of the technical defects and drawbacks existing in the prior art, the present invention provides an adaptive fault-tolerant control method and storage medium for AC drive inverters to overcome the above problems or at least partially solve the above problems. The specific solution is as follows:

[0009] As a first aspect of the present invention, an adaptive fault-tolerant control method for an AC drive inverter is provided. This method is based on a system consisting of a main control box and multiple parallel inverter units, and includes:

[0010] S1. System Operation and Status Monitoring: The main control box is connected to each parallel inverter unit through the SCI high-speed optical fiber communication network, monitors the operating status of each inverter unit in real time, and dynamically determines the number N of online effective inverter units based on the monitoring results.

[0011] S2. Cooperative Control and Fault-Tolerant Decision-Making: Based on the number of online effective inverter units N, the main control box uniformly controls all normally operating parallel inverter units to perform carrier synchronization and current sharing control, and simultaneously monitors the power supply status and inverter unit status. When a power supply failure or inverter unit failure occurs, the corresponding fault-tolerant operation is triggered.

[0012] S3. Fault Handling and System Reconfiguration: When the fault-tolerant operation is triggered, if it is an inverter unit fault, the main control box controls the blocking of the pulse drive signal of the faulty unit and disconnects it from the system, and immediately performs recurrent sharing control on the remaining normal inverter units according to the updated number of online effective units N in the manner of S2; if it is a power supply fault, the control switches to the backup power supply.

[0013] In some embodiments, carrier synchronization in step S2 is achieved through the enhanced pulse width modulation module (EPWM) of the main control box, specifically as follows:

[0014] The main control box outputs a time base synchronization signal through the EPWMSYNCO pin of the enhanced pulse width modulation module (EPWM) to uniformly control the time base counters of all channels of the enhanced pulse width modulation module inside it, thereby generating multi-channel pulse width modulation waveforms with a unified carrier frequency and phase, and sending them to the corresponding parallel inverter units to drive their power switching devices to operate synchronously.

[0015] In some embodiments, the unified control of all normally operating parallel inverter units for current sharing control in step S2 is achieved through reference voltage correction based on circulating current feedback, specifically including:

[0016] S211. Status Acquisition and Circulating Current Calculation: The main control box acquires the three-phase output current value Iabc_j of each inverter unit in real time through the SCI high-speed optical fiber communication network, j=1, 2, ..., N, and calculates the circulating current error value Err_Iabc_j = Iabc_j - Iabc_avg between it and the system average current, where Iabc_avg is the ratio of the total current Iabc_total to the number of online effective units N;

[0017] S212, Adjustment amount and command generation: The circulating current error value Err_Iabc_j is input to the circulating current regulator to generate the corresponding reference voltage correction amount ΔV_ref_j; The correction amount ΔV_ref_j is superimposed on the original reference voltage setpoint V_ref_j of each inverter unit to form the corrected voltage command V_ref_j';

[0018] S213. Driving and Output: Based on the modified voltage command V_ref_j', generate the corresponding pulse width modulation waveform to drive the power switching devices of each inverter unit, so that their output current approaches the average current, thereby achieving current sharing.

[0019] In some embodiments, the circulating flow regulator is implemented using a proportional regulator;

[0020] The reference voltage correction amount ΔV_ref_j is calculated using the following control law:

[0021] ΔV_ref_j = K * Err_Iabc_j

[0022] Where K is the circulation regulation proportional coefficient.

[0023] This proportional adjustment achieves a rapid dynamic response by linearly amplifying the circulating current error into a voltage compensation amount.

[0024] In some embodiments, dynamically determining the number N of online active inverters and monitoring the power supply status and inverter unit status specifically includes:

[0025] S221. Initialization and continuous monitoring: When the system is powered on, the main control box sets the initial effective number N according to the total number of physically connected parallel inverter units; during operation, the main control box continuously collects the bus voltage Udc_j and output current Iabc_j of each inverter unit through the SCI high-speed fiber optic communication network.

[0026] S222 Fault Diagnosis and Unit Count Update: The main control box diagnoses the system status in real time based on the following criteria:

[0027] If the bus voltage deviation value Err_Udc_j = Udc_j - Udc_avg of any inverter unit continues to exceed the preset voltage threshold, the corresponding power supply is determined to be abnormal and a power switching operation is triggered.

[0028] If the amplitude or rate of change of the circulating current error value Err_Iabc_j = Iabc_j - Iabc_avg of any inverter unit continuously exceeds the preset current threshold, the inverter unit is determined to be faulty, and a faulty inverter unit disconnection operation is triggered. After the fault occurs, the main control box immediately updates the number of valid units N to N-1 and broadcasts it to all normal units through the SCI network. When the faulty inverter unit is repaired and its status is confirmed to be normal by the main control box, the main control box updates the number of valid units N to N+1 and broadcasts it through the SCI network in the same way.

[0029] Where Iabc_avg is the average output current of each inverter unit, and Udc_avg is the average bus voltage of each inverter unit.

[0030] The updated effective number of units N is used in real time to calculate the new average current Iabc_avg and average voltage Udc_avg, providing a dynamic parameter reference for current sharing control and fault-tolerant operation.

[0031] In some embodiments, the method is implemented based on a fault-tolerant control system, which adopts the following topology:

[0032] M independent power supplies are connected to a common DC bus through their respective power input contactors; the DC sides of N parallel inverter units are all connected in parallel to this common DC bus, and the AC output sides of each inverter unit are connected to the AC motor through their respective output contactors and parallel reactors; a bus contactor is connected in series on the main line of the common DC bus to control the overall DC power supply of the entire inverter system, where M≥2 and N≥2;

[0033] Based on the above topology, the fault-tolerant operations for power supply failures in steps S2 and S3 are specifically implemented as multi-power supply anti-power fluctuation switching control, including the following processes:

[0034] Power-on initialization process: After the main control box is powered on, the bus contactor and the output contactors of all normal inverter units are first engaged; then the status of each power supply is monitored: if there is a fault-free power supply, the input contactor corresponding to one of the fault-free power supplies is engaged in a delayed manner according to the preset priority order; if all power supplies report faults, no power input contactor is engaged.

[0035] Switching process during operation: During system operation, the main control box continuously monitors the current working power supply status. When the current power supply fails or the bus voltage is undervoltage, it immediately controls the disconnection of the current power supply's input contactor and, based on the preset priority strategy, switches to the next highest priority fault-free power supply within milliseconds, and engages its corresponding input contactor.

[0036] In some embodiments, the fault-tolerant operation for inverter unit failures in steps S2 and S3 is specifically implemented as the disconnection and re-current sharing control of the faulty inverter unit, and the process includes:

[0037] Fault diagnosis and isolation: The main control box monitors the operating status of each inverter unit in real time. When any inverter unit fails, it immediately stops sending pulse drive signals to the faulty inverter unit and controls the disconnection of its output contactor, physically isolating it from the parallel system.

[0038] Re-current sharing control: After the faulty unit is isolated, the main control box immediately updates the number of effective inverters N in the system to N-1, and based on the new number of units N, performs re-current sharing control on the remaining normal inverter units to ensure a smooth transition of the total output current.

[0039] In some embodiments, step S3 further includes online reconnection control after the faulty inverter unit is repaired; when the main control box receives a status confirmation signal indicating that the faulty unit has been repaired, the following reconnection control is executed:

[0040] Status integration: The main control box marks the repaired inverter unit as normal and updates the number of effective units N in the system to N+1. This updated number of units is broadcast to all inverter units via SCI high-speed fiber optic communication.

[0041] Pre-synchronization and soft input: Based on the updated number of units N, the main control box first controls the output contactor of the closed repair unit to connect its AC output side in parallel with the system; then, through current sharing control, the reference voltage setpoint of the repair unit is dynamically adjusted so that its output current rises smoothly to be consistent with the current system average current.

[0042] Once the current of the repair unit stabilizes, it will be fully integrated into the parallel system and participate in normal current sharing control.

[0043] In some embodiments, the method further includes a safety interlock logic, executed by the main control box, to prevent system failures caused by misoperation; the safety interlock logic includes:

[0044] Output contactor interlock: For any online inverter unit, the main control box is prohibited from disconnecting its own output contactor and simultaneously prohibiting the energizing of the output contactor of any other inverter unit in standby or fault state, so as to ensure that only one set of synchronized inverter units supplies power to the motor at any given time, avoiding asynchronous closing or power circulation.

[0045] Power switching interlock: Before performing a power switching operation, the main control box must first verify that the target power supply is in a fault-free state and that its bus voltage value is within the rated operating range of the system. At the same time, the absolute value of the difference between the target power supply bus voltage and the current working power supply bus voltage is within the allowable synchronous closing range before the switching command can be executed.

[0046] When any operation request or system status that violates the above interlocking conditions is detected, the main control box immediately blocks the operation and triggers a system-level fault alarm to maintain the current safe state.

[0047] As a second aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the AC drive inverter adaptive fault-tolerant control method as described in any one of the above descriptions.

[0048] The present invention has the following beneficial effects:

[0049] This invention solves the technical problem of traditional fixed-parameter control being unable to cope with system collapse caused by sudden faults by constructing a real-time monitoring and current sharing control based on a dynamic effective number of inverters N. Specifically, when any inverter unit in the system fails or goes out of service, the system can automatically update the effective number of inverters N without shutting down, and recalculate the reference current and voltage based on the new N value. This allows the remaining normal units to immediately share the load of the faulty unit, maintaining the stability of the system's total output power. This achieves millisecond-level fault self-healing and seamless power switching, significantly improving the system's availability and reliability. Attached Figure Description

[0050] Figure 1 A schematic diagram of a parallel control system for an AC drive inverter provided in an embodiment of the present invention;

[0051] Figure 2 A schematic flowchart of an adaptive fault-tolerant control method for an AC drive inverter provided in an embodiment of the present invention;

[0052] Figure 3 This is a carrier synchronization connection diagram provided in an embodiment of the present invention;

[0053] Figure 4 This is a control block diagram of a reference voltage-corrected circulating current suppression strategy provided in an embodiment of the present invention;

[0054] Figure 5 This is the inverter unit parallel adaptive fault-tolerant topology provided in the embodiments of the present invention;

[0055] Figure 6 Bus voltage RMS detection provided in this embodiment of the invention;

[0056] Figure 7 This invention provides an embodiment of output current RMS value detection.

[0057] Figure 8 The current waveform during the clearing of fault unit #1 provided in this embodiment of the invention;

[0058] Figure 9 The current waveform during the activation of fault unit #1 provided in this embodiment of the invention. Detailed Implementation

[0059] To enable those skilled in the art to better understand the technical solutions of the present invention, exemplary embodiments of the present invention are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present invention to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present invention. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0060] Where there is no conflict, the various embodiments of the present invention and the features thereof may be combined with each other.

[0061] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0062] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Terms such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0063] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having the meaning consistent with their meaning in the context of the relevant art and the invention, and will not be interpreted as having an idealized or overly formal meaning unless expressly so defined herein.

[0064] In the technical solution of this invention, the collection, storage, use, processing, transmission, provision, and disclosure of user personal information all comply with relevant laws and regulations and do not violate public order and good morals. The use of user data in this technical solution follows relevant national laws and regulations (e.g., the "Information Security Technology - Personal Information Security Specification"). For example: appropriate measures are taken for personal information access control; restrictions are imposed on the display of personal information; the purpose of using personal information does not exceed the scope of direct or reasonable association; and explicit identity targeting is eliminated when using personal information to avoid precisely locating a specific individual.

[0065] refer to Figure 1 The diagram shows a parallel control system for an AC drive inverter. The entire system is mainly divided into three parts: the main control box, the parallel inverter unit, and the parallel reactor. The main control box is the core of the entire control system; all information interaction and control command generation are completed in this part. The parallel inverter unit is the operating part of the parallel system; it receives control commands from the main control box and generates drive waveforms based on appropriate calculations. , To determine the number of inverters connected in parallel, drive the power devices to operate, and output the desired three-phase voltage value. , The number of inverters connected in parallel drives the motor. The parallel reactors mainly suppress high-frequency circulating currents caused by inconsistent drive signals from each inverter module. In the same parallel system, the parameters of the parallel reactors must be consistent. While satisfying the high-frequency circulating current suppression requirement, the parameter values ​​of the parallel reactors should be as small as possible to avoid excessive voltage drop affecting the normal control of the motor.

[0066] In parallel systems, the circulating current caused by inconsistent trigger edges of the drive signals is a high-frequency circulating current, and its suppression is particularly important for parallel control. In parallel systems, this high-frequency circulating current is generally suppressed by using parallel reactors. However, if the difference between the trigger signal pulse edges is too large (especially when the carrier waves are asynchronous, even the same pulse width between parallel modules can cause a large difference in pulse edges), a larger reactor value is required to suppress the circulating current within a certain range. In practical systems, considering that the voltage drop from the inverter output to the motor control system cannot be too large, the reactor value cannot be too large either, so certain measures need to be taken.

[0067] To address at least one of the technical problems existing in the aforementioned related technologies, this invention provides an adaptive fault-tolerant control method for AC drive inverters, which employs carrier synchronization and current sharing control to suppress high-frequency circulating currents. Figure 2 This is a flowchart illustrating an adaptive fault-tolerant control method for an AC drive inverter provided in an embodiment of the present invention. The method includes:

[0068] S1. System Operation and Status Monitoring: The main control box is connected to each parallel inverter unit through the SCI high-speed optical fiber communication network, monitors the operating status of each inverter unit in real time, and dynamically determines and broadcasts the number N of online effective inverter units of the system based on the monitoring results.

[0069] S2. Cooperative control and fault-tolerant decision-making: Based on the number N of online effective inverter units, the main control box uniformly controls all normally operating parallel inverter units to perform carrier synchronization and current sharing control, and simultaneously monitors the power supply status and inverter unit status. When a power supply fault or inverter unit fault is detected, the corresponding fault-tolerant operation is triggered.

[0070] S3. Fault Handling and System Reconfiguration: When the fault-tolerant operation is triggered, if it is an inverter unit fault, the main control box controls the blocking of the pulse drive signal of the faulty unit and disconnects it from the system, and immediately performs recurrent sharing control on the remaining normal inverter units according to the updated number of online effective units N in the manner of S2; if it is a power supply fault, the control switches to the backup power supply.

[0071] This invention solves the technical problem of traditional fixed-parameter control being unable to cope with system collapse caused by sudden faults by constructing a real-time monitoring and current sharing control based on a dynamic effective number of inverters N. Specifically, when any inverter unit in the system fails or goes out of service, the system can automatically update the effective number of inverters N without shutting down, and recalculate the reference current and voltage based on the new N value. This allows the remaining normal units to immediately share the load of the faulty unit, maintaining the stability of the system's total output power. This achieves millisecond-level fault self-healing and seamless power switching, significantly improving the system's availability and reliability.

[0072] In some embodiments, carrier synchronization in step S2 is achieved through the enhanced pulse width modulation module (EPWM) of the main control box, specifically as follows:

[0073] The main control box controls the time base counters of all channels of the enhanced pulse width modulation module (EPWM) through the time base synchronization signal output by the EPWMSYNCO pin of the enhanced pulse width modulation module (EPWM), or through the external synchronization signal locked by the EPWMSYCI pin. This generates multiple pulse width modulation waveforms with a unified carrier frequency and phase, and sends them to the corresponding parallel inverter units to drive their power switching devices to operate synchronously.

[0074] like Figure 3 As shown, the microcontroller of the main control box is a DSP28335. The EPWM module in the DSP28335 can generate a time base synchronization signal and output it through a specific pin (EPWMSYNCO). Alternatively, an external signal (EPWMSYCI) from a specific pin can be used as the actual synchronization signal for the entire module.

[0075] In some embodiments, in parallel operation of frequency converters, circulating current inevitably exists due to parameter inconsistencies. The presence of circulating current causes modules with higher loads to operate under overload conditions for extended periods, affecting their lifespan. Circulating current has multiple components; how to suppress these different components is a key issue in parallel operation technology. (Reference) Figure 4 The diagram shown is a control block diagram of a reference voltage correction circulating current suppression strategy provided in an embodiment of the present invention. The strategy specifically includes:

[0076] S211. Status Acquisition and Circulating Current Calculation: The main control box acquires the three-phase output current value Iabc_j of each inverter unit in real time through the SCI high-speed fiber optic communication network, j=1, 2, ..., N, and calculates the circulating current error value Err_Iabc_j = Iabc_j - Iabc_avg between it and the system average current, where Iabc_avg is the ratio of the total current Iabc_total to the number of effective online inverters N, and Err_Iabc_j is the three-phase circulating current value of the j-th parallel inverter unit. The specific calculation formula is as follows:

[0077]

[0078] S212, Adjustment amount and command generation: The circulating current error value Err_Iabc_j is input to the circulating current regulator to generate the corresponding reference voltage correction amount ΔV_ref_j; The correction amount ΔV_ref_j is superimposed on the original reference voltage setpoint V_ref_j of each inverter unit to form the corrected voltage command V_ref_j';

[0079] S213. Driving and Output: Based on the modified voltage command V_ref_j', generate the corresponding pulse width modulation waveform to drive the power switching devices of each inverter unit, so that their output current approaches the average current, thereby achieving current sharing.

[0080] The circulating flow regulator is implemented using a proportional regulator;

[0081] The reference voltage correction amount ΔV_ref_j is calculated using the following control law:

[0082] ΔV_ref_j = K * Err_Iabc_j

[0083] Where K is the circulation regulation proportional coefficient.

[0084] This proportional adjustment achieves a rapid dynamic response by linearly amplifying the circulating current error into a voltage compensation amount.

[0085] In some embodiments, dynamically determining the number N of online active inverters and monitoring the power supply status and inverter unit status specifically includes:

[0086] S221. Initialization and Continuous Monitoring: When the system is powered on, the main control box sets the initial effective number N based on the total number of physically connected parallel inverter units; during operation, the main control box continuously collects the bus voltage Udc_j (wherein, the bus voltage is the voltage value detected at the DC input terminal of each inverter unit connected to the common DC bus) and output current Iabc_j of each inverter unit through the SCI high-speed fiber optic communication network.

[0087] S222 Fault Diagnosis and Unit Count Update: The main control box diagnoses the system status in real time based on the following criteria:

[0088] If the bus voltage deviation value Err_Udc_j = Udc_j - Udc_avg of any inverter unit continues to exceed the preset voltage threshold, the corresponding power supply is determined to be abnormal and a power switching operation is triggered.

[0089] See Figure 6 The diagram shown is a schematic diagram of the bus voltage RMS detection provided in an embodiment of the present invention.

[0090] If the amplitude or rate of change of the circulating current error value Err_Iabc_j = Iabc_j - Iabc_avg of any inverter unit continuously exceeds the preset current threshold, the inverter unit is determined to be faulty, and a faulty inverter unit disconnection operation is triggered. After the fault occurs, the main control box immediately updates the number of valid units N to N-1 and broadcasts it to all normal units through the SCI network. When the faulty inverter unit is repaired and its status is confirmed to be normal by the main control box, the main control box updates the number of valid units N to N+1 and broadcasts it through the SCI network in the same way.

[0091] See Figure 7 The diagram shown is a schematic representation of the output current RMS value detection provided in an embodiment of the present invention.

[0092] Where Iabc_avg is the average output current of each inverter unit, and Udc_avg is the average bus voltage of each inverter unit.

[0093] The updated effective number of units N is used in real time to calculate the new average current Iabc_avg and average voltage Udc_avg, providing a dynamic parameter reference for current sharing control and fault-tolerant operation.

[0094] In some embodiments, the method is implemented based on a fault-tolerant control system, which adopts the following topology:

[0095] M independent power supplies (M≥2) are connected to a common DC bus through corresponding power input contactors (KM_P1, KM_P2, ...,KM_Pm); the DC sides of N parallel inverter units (N≥2) are all connected in parallel to this common DC bus, and the AC output side of each inverter unit is connected to the AC motor through corresponding output contactors (KM_O1, KM_O2, ...,KM_On) and then through parallel reactors; a bus contactor (KM_BUS) is connected in series on the main line of the common DC bus to control the overall DC power supply of the entire inverter system.

[0096] Based on the above topology, the fault-tolerant operations for power supply failures in steps S2 and S3 are specifically implemented as multi-power supply anti-power fluctuation switching control, including the following processes:

[0097] Power-on initialization process: After the main control box is powered on, the bus contactor KM_BUS and the output contactors of all normal inverter units are first engaged; then the fault status signals of each power supply are detected: if there is a fault-free power supply, the input contactor (KM_Px) corresponding to one of the fault-free power supplies is engaged in a delayed manner according to the preset priority order; if all power supplies report faults, no power input contactor is engaged.

[0098] Switching process during operation: During system operation, the main control box continuously monitors the current working power supply status. When it is determined that the current power supply is abnormal or the bus voltage is undervoltage according to the method in step S222, it immediately controls the disconnection of the input contactor of the current power supply, and switches to the next highest priority fault-free power supply within milliseconds based on the preset priority strategy, and engages its corresponding input contactor.

[0099] In some embodiments, the fault-tolerant operation for inverter unit failures in steps S2 and S3 is specifically implemented as the disconnection and re-current sharing control of the faulty inverter unit, and the process includes:

[0100] Fault diagnosis and isolation: The main control box monitors the operating status of each inverter unit in real time. When any inverter unit is determined to be faulty according to the method in step S22, the pulse drive signal sent to the faulty inverter unit is immediately stopped, and its output contactor (KM_Ox) is disconnected to physically isolate it from the parallel system.

[0101] Re-current sharing control: After the faulty unit is isolated, the main control box immediately updates the number of effective inverters N in the system to N-1, and based on the new number of units N, and based on the current sharing control algorithm in steps S211~S213, re-current sharing control is performed on the remaining normal inverter units to ensure a smooth transition of the total output current.

[0102] refer to Figure 5 The diagram shown illustrates a parallel adaptive fault-tolerant topology for an inverter according to an embodiment of the present invention. It includes two power supplies, two inverter units, and a main control box U01. The system startup signal command reception and processing is performed using the main control box. DI1 receives the power-on command, DI2 receives the fault signal from power supply #1, and DI3 receives the fault signal from power supply #2. Figure 5As shown, the 24V control power supply of the main control box U01 is connected first. Upon receiving the power-on command DI1, KM_BUS, KM_O1, and KM_O2 are first engaged. Then, DI2 and DI3 are checked for fault signal input. If there is no abnormality, KM_P1 is engaged by default after a 100ms delay on DI1. If DI2 has an abnormality, KM_P2 is engaged (KM_P1 is engaged by default when both power supplies are fault-free; the power supply on the fault-free side is engaged when one of them has a fault; and neither KM_P1 nor KM_P2 is engaged when both power supplies have a fault).

[0103] During the operation of the inverter fault-tolerant system: if power supply #1 is working and DI2 is detected as abnormal or the bus voltage reaches an undervoltage abnormality, immediately switch to power supply #2; if power supply #2 is working and DI3 is detected as abnormal or the bus voltage reaches an undervoltage abnormality, immediately switch to power supply #1.

[0104] like Figure 5 As shown, when inverter unit #1 fails, the main control box immediately stops sending pulse width modulation drive signals to the faulty unit, sets the fault status relay of that unit, and resets the running status relay. Simultaneously, after a 5ms delay, it disconnects the output contactor KM_O1 and its power input contactor KM_P1 of the faulty unit, and after a 50ms delay, it disconnects the bus contactor KM_BUS, thus achieving online disconnection of the faulty unit.

[0105] In some embodiments, step S3 further includes online reconnection control after the faulty inverter unit is repaired; when the main control box receives a status confirmation signal indicating that the faulty unit has been repaired, the following reconnection control is executed:

[0106] Status integration: The main control box marks the repaired inverter unit as normal and updates the number of effective units N in the system to N+1. This updated number of units is broadcast to all inverter units via SCI high-speed fiber optic communication.

[0107] Pre-synchronization and soft input: Based on the updated number of units N, the main control box first controls the output contactor of the closed repair unit to connect its AC output side in parallel with the system; then, according to the current sharing control algorithm in steps S211~S213, the reference voltage setpoint of the repair unit is dynamically adjusted through current sharing control so that its output current rises smoothly to be consistent with the current system average current.

[0108] Once the current of the repair unit stabilizes, it will be fully integrated into the parallel system and participate in normal current sharing control.

[0109] refer to Figure 5As shown, the reactivation control sequence after fault repair of inverter unit #1 is as follows: After repair completion, the switch is set (parameter is a pulse signal, time=0ms, where time represents the time interval). Then, the output contactor KM_O1 of the repaired inverter unit is closed (time=5ms). Finally, the bus contactor KM_BUS is closed (time=55ms) → the standby unit automatically starts operation. The reactivation control sequence after fault repair of inverter unit #2 is similar.

[0110] In some embodiments, the method further includes a safety interlock logic, executed by the main control box, to prevent system failures caused by misoperation; the safety interlock logic includes:

[0111] Output contactor interlock: For any online inverter unit, the main control box is prohibited from disconnecting its own output contactor and simultaneously prohibiting the energizing of the output contactor of any other inverter unit in standby or fault state, so as to ensure that only one set of synchronized inverter units supplies power to the motor at any given time, avoiding asynchronous closing or power circulation.

[0112] Power switching interlock: Before performing a power switching operation, the main control box must first verify that the target power supply is in a fault-free state and that its bus voltage value is within the rated operating range of the system. At the same time, the absolute value of the difference between the target power supply bus voltage and the current working power supply bus voltage is within the allowable synchronous closing range before the switching command can be executed.

[0113] When any operation request or system status that violates the above interlocking conditions is detected, the main control box immediately blocks the operation and triggers a system-level fault alarm to maintain the current safe state.

[0114] ,refer to Figure 5 As shown, during the operation of inverter unit #1, the engaged KM_O1 contactor must not be disconnected, and during the operation of inverter unit #2, the engaged KM_O2 contactor must not be disconnected; during the operation of inverter unit #1, the disconnected KM_O2 contactor must not be engaged, and during the operation of inverter unit #2, the disconnected KM_O1 contactor must not be engaged.

[0115] refer to Figure 8-9 As shown, the control system, through dynamic correction of the online effective number of inverters N and a collaborative fault-tolerant strategy, achieves automatic disconnection and reconnection after inverter unit failure, dual-power supply anti-power-damp switching, and contactor opening and closing operations. Throughout the switching process, the system maintains continuous operation without any fault-related shutdowns; the faulty unit can be seamlessly reconnected after repair. The output current transitions smoothly throughout the fault-tolerant process, with no inrush current, effectively achieving real-time fault detection and current sharing reconstruction, ensuring long-term stable operation of the system.

[0116] Based on the same inventive concept, embodiments of the present invention provide a computer-readable storage medium having a computer program stored thereon, wherein when the program is executed by a processor, it implements the AC drive inverter adaptive fault-tolerant control method as described in any one of the above.

[0117] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).

[0118] As is known to those skilled in the art, computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer-readable program instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technologies, portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable program instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0119] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0120] The computer program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing state information from the computer-readable program instructions. This electronic circuitry can execute the computer-readable program instructions to implement various aspects of the invention.

[0121] The computer program product described herein can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0122] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0123] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0124] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0125] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0126] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. An adaptive fault-tolerant control method for an AC drive inverter, characterized in that, This method is based on a system consisting of a main control box and multiple parallel inverter units, and includes the following: S1: The main control box is connected to each parallel inverter unit through the SCI high-speed fiber optic communication network, monitors the operating status of each inverter unit in real time, and dynamically determines the number N of online effective inverter units based on the monitoring results. S2: Based on the number of online effective inverter units N, the main control box uniformly controls all normally operating parallel inverter units to perform carrier synchronization and current sharing control, and simultaneously monitors the power supply status and inverter unit status. When a power supply failure or inverter unit failure occurs, the corresponding fault-tolerant operation is triggered. S3: When the fault-tolerant operation is triggered, if it is an inverter unit failure, the main control box controls to block the pulse drive signal of the faulty unit and disconnect it from the system, and immediately performs recurrent sharing control on the remaining normal inverter units according to the updated number of online effective units N in the manner of S2; if it is a power supply failure, it controls to switch to backup power supply.

2. The method according to claim 1, characterized in that, The carrier synchronization in step S2 is achieved through the enhanced pulse width modulation module (EPWM) of the main control box, specifically as follows: The main control box outputs a time base synchronization signal through the EPWMSYNCO pin of its enhanced pulse width modulation module (EPWM) to uniformly control the time base counters of all channels of its internal enhanced pulse width modulation module, thereby generating multi-channel pulse width modulation waveforms with a unified carrier frequency and phase, and sending them to the corresponding parallel inverter units to drive their power switching devices to operate synchronously.

3. The method according to claim 1, characterized in that, In step S2, the unified control of current sharing for all normally operating parallel inverter units is achieved through reference voltage correction based on circulating current feedback, specifically including: S211. Status Acquisition and Circulating Current Calculation: The main control box acquires the three-phase output current value Iabc_j of each inverter unit in real time through the SCI high-speed optical fiber communication network, j=1, 2, ..., N, and calculates the circulating current error value Err_Iabc_j = Iabc_j - Iabc_avg between it and the system average current, where Iabc_avg is the ratio of the total current Iabc_total to the number of online effective units N; S212, Adjustment amount and command generation: The circulating current error value Err_Iabc_j is input to the circulating current regulator to generate the corresponding reference voltage correction amount ΔV_ref_j; The correction amount ΔV_ref_j is superimposed on the original reference voltage setpoint V_ref_j of each inverter unit to form the corrected voltage command V_ref_j'; S213. Driving and Output: Based on the modified voltage command V_ref_j', generate the corresponding pulse width modulation waveform to drive the power switching devices of each inverter unit, so that their output current approaches the average current, thereby achieving current sharing.

4. The method according to claim 3, characterized in that, The circulating flow regulator is implemented using a proportional regulator; The reference voltage correction amount ΔV_ref_j is calculated using the following control law: ΔV_ref_j = K * Err_Iabc_j Where K is the circulation regulation proportional coefficient. This proportional adjustment achieves a rapid dynamic response by linearly amplifying the circulating current error into a voltage compensation amount.

5. The method according to claim 1, characterized in that, Dynamically determine the number N of online active inverters, and monitor the power supply status and inverter unit status, specifically including: S221. Initialization and continuous monitoring: When the system is powered on, the main control box sets the initial effective number N according to the total number of physically connected parallel inverter units; during operation, the main control box continuously collects the bus voltage Udc_j and output current Iabc_j of each inverter unit through the SCI high-speed fiber optic communication network. S222 Fault Diagnosis and Unit Count Update: The main control box diagnoses the system status in real time based on the following criteria: If the bus voltage deviation value Err_Udc_j = Udc_j - Udc_avg of any inverter unit continues to exceed the preset voltage threshold, the corresponding power supply is determined to be abnormal and a power switching operation is triggered. If the amplitude or rate of change of the circulating current error value Err_Iabc_j = Iabc_j - Iabc_avg of any inverter unit continuously exceeds the preset current threshold, the inverter unit is determined to be faulty, and a faulty inverter unit disconnection operation is triggered. After the fault occurs, the main control box immediately updates the number of valid units N to N-1 and broadcasts it to all normal units through the SCI network. When the faulty inverter unit is repaired and its status is confirmed to be normal by the main control box, the main control box updates the number of valid units N to N+1 and broadcasts it through the SCI network in the same way. Where Iabc_avg is the average output current of each inverter unit, and Udc_avg is the average bus voltage of each inverter unit. The updated effective number of units N is used in real time to calculate the new average current Iabc_avg and average voltage Udc_avg, providing a dynamic parameter reference for current sharing control and fault-tolerant operation.

6. The method according to claim 1, characterized in that, The method is implemented based on a fault-tolerant control system, which adopts the following topology: M independent power supplies are connected to a common DC bus through their respective power input contactors; the DC sides of N parallel inverter units are all connected in parallel to this common DC bus, and the AC output sides of each inverter unit are connected to the AC motor through their respective output contactors and parallel reactors; a bus contactor is connected in series on the main line of the common DC bus to control the overall DC power supply of the entire inverter system, where M≥2 and N≥2; Based on the above topology, the fault-tolerant operations for power supply failures in steps S2 and S3 are specifically implemented as multi-power supply anti-power fluctuation switching control, including the following processes: Power-on initialization process: After the main control box is powered on, the bus contactor and the output contactors of all normal inverter units are first engaged; then the status of each power supply is monitored: if there is a fault-free power supply, the input contactor corresponding to one of the fault-free power supplies is engaged in a delayed manner according to the preset priority order; if all power supplies report faults, no power input contactor is engaged. Switching process during operation: During system operation, the main control box continuously monitors the current working power supply status. When the current power supply fails or the bus voltage is undervoltage, it immediately controls the disconnection of the current power supply's input contactor and, based on the preset priority strategy, switches to the next highest priority fault-free power supply within milliseconds, and engages its corresponding input contactor.

7. The method according to claim 6, characterized in that, In steps S2 and S3, the fault-tolerant operation for inverter unit failure is specifically implemented as the disconnection and re-current sharing control of the faulty inverter unit. The process includes: Fault diagnosis and isolation: The main control box monitors the operating status of each inverter unit in real time. When any inverter unit fails, it immediately stops sending pulse drive signals to the faulty inverter unit and controls the disconnection of its output contactor, physically isolating it from the parallel system. Re-current sharing control: After the faulty unit is isolated, the main control box immediately updates the number of effective inverters N in the system to N-1, and based on the new number of units N, performs re-current sharing control on the remaining normal inverter units to ensure a smooth transition of the total output current.

8. The method according to claim 6, characterized in that, Step S3 also includes online reconnection control after the faulty inverter unit is repaired; when the main control box receives the status confirmation signal that the faulty unit has been repaired, the following reconnection control is executed: Status integration: The main control box marks the repaired inverter unit as normal and updates the number of effective units N in the system to N+1. This updated number of units is broadcast to all inverter units via SCI high-speed fiber optic communication. Pre-synchronization and soft input: Based on the updated number of units N, the main control box first controls the output contactor of the closed repair unit to connect its AC output side in parallel with the system; Subsequently, through current sharing control, the reference voltage setpoint of the repair unit is dynamically adjusted so that its output current smoothly rises to match the current system average current. Once the current of the repair unit stabilizes, it will be fully integrated into the parallel system and participate in normal current sharing control.

9. The method according to claim 6, characterized in that, The method also includes a safety interlock logic, executed by the main control box, to prevent system failures caused by misoperation; the safety interlock logic includes: Output contactor interlock: For any online inverter unit, the main control box is prohibited from disconnecting its own output contactor and simultaneously prohibiting the energizing of the output contactor of any other inverter unit in standby or fault state, so as to ensure that only one set of synchronized inverter units supplies power to the motor at any given time, avoiding asynchronous closing or power circulation. Power switching interlock: Before performing a power switching operation, the main control box must first verify that the target power supply is in a fault-free state and that its bus voltage value is within the rated operating range of the system. At the same time, the absolute value of the difference between the target power supply bus voltage and the current working power supply bus voltage is within the allowable synchronous closing range before the switching command can be executed. When any operation request or system status that violates the above interlocking conditions is detected, the main control box immediately blocks the operation and triggers a system-level fault alarm to maintain the current safe state.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the adaptive fault-tolerant control method for AC drive inverters as described in any one of claims 1-9.

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