Valley detection dithering circuit and method

Abstract

The application discloses a valley detection frequency jittering circuit and method. The circuit is applied to a switching power supply in a quasi-resonant mode, and comprises a zero-crossing detection module, which receives a voltage signal VS of an auxiliary winding of a transformer and generates a zero-crossing setting signal according to the voltage signal VS; a jittering delay module, which is connected with the zero-crossing detection module and is used for introducing a delay time after the zero-crossing setting signal is generated and outputting a delay setting signal; and a switch control module, which is connected with the jittering delay module and a power switch tube Q1 and is used for controlling the power switch tube Q1 to be turned on according to the delay setting signal after the zero-crossing setting signal is generated, so that the turn-on time of the power switch tube Q1 corresponds to a resonant valley bottom region of the voltage signal VS; in a plurality of switching periods, the delay time changes between at least two different delay values, so that the turn-on time of the power switch tube Q1 changes in the resonant valley bottom region, thereby causing the jittering of the working frequency of the switching power supply.

Description

Technical Field

[0001] This invention relates to the field of circuit design, and more specifically to a valley detection frequency dithering circuit and method. Background Technology

[0002] As switching power supplies evolve towards higher frequencies and smaller sizes, those employing pulse width modulation (PWM) or quasi-resonant control generate relatively steep switching waveforms during operation. These waveforms contain a large number of harmonic components concentrated at the switching frequency and its harmonics. These harmonic components easily propagate outwards through power lines, signal lines, and spatial electromagnetic fields, resulting in significant conducted and radiated interference. With the increasing demands for electromagnetic compatibility in communication equipment and digital control systems, switching power supplies must not only meet efficiency and functional requirements but also comply with stricter electromagnetic interference standards. Electromagnetic interference has gradually become a significant factor restricting the application and widespread adoption of switching power supplies.

[0003] To reduce electromagnetic interference caused by the aforementioned harmonic concentration, existing technologies propose introducing frequency jitter to vary the operating frequency of the switching power supply within a certain range. This disperses the harmonic energy originally concentrated at a single frequency point and its harmonics across a wider frequency spectrum, thereby reducing the interference peak at a single frequency point. While this method helps improve electromagnetic compatibility performance to some extent, in practical applications, the introduction of frequency jitter often needs to be coordinated with the control method of the switching power supply; otherwise, it may adversely affect the system's switching timing, efficiency, or stability. Especially in control modes with specific constraints on the switching on timing, achieving effective and controllable frequency jitter while ensuring the original control conditions still requires further improvement. Summary of the Invention

[0004] The purpose of this invention is to provide a valley detection frequency jitter circuit and method to achieve controlled jitter of the switching frequency and reduce electromagnetic interference while ensuring the stability of valley switching.

[0005] To achieve the above objectives, the present invention discloses the following technical solution: A first aspect of the present invention provides a valley detection frequency dithering circuit, applied in a quasi-resonant mode switching power supply, comprising: The zero-crossing detection module receives the voltage signal VS from the auxiliary winding of the transformer and generates a zero-crossing set signal based on the voltage signal VS. A jitter delay module, connected to the zero-crossing detection module, is used to introduce a delay time after the zero-crossing set signal is generated and output a delayed set signal; A switching control module, connected to the jitter delay module and the gate of the power switch Q1, is used to control the power switch Q1 to turn on according to the delay set signal after the zero-crossing set signal is generated, so that the turn-on time of the power switch Q1 corresponds to the resonant valley region of the voltage signal VS. In this process, the delay time varies between at least two different delay values ​​during multiple switching cycles, so that the turn-on time of the power switch Q1 changes within the resonant valley region, thereby causing fluctuations in the operating frequency of the switching power supply.

[0006] Optionally, the jitter delay module includes: An energy storage unit, connected to the zero-crossing detection module, is used to control the charging and discharging of the energy storage node according to the zero-crossing set signal, so that the energy storage node forms a time-varying energy storage node voltage. An adjustment unit, connected to the energy storage unit, is used to periodically adjust the charging and discharging path or charging and discharging intensity of the energy storage unit within multiple switching cycles, so as to change the time when the energy storage node voltage reaches a preset judgment condition. The comparison unit is connected to the energy storage unit and the regulation unit respectively, and is used to compare the voltage of the energy storage node with a preset threshold, and output the delayed set signal when the voltage of the energy storage node reaches the preset threshold.

[0007] Optionally, the energy storage unit includes a first current source I1, a first switch K1, a first resistor R1, a first capacitor C1, and a first inverter A1; The input terminal of the first current source I1 is connected to the power supply voltage, the output terminal is connected to the first terminal of the first capacitor C1, and the second terminal of the first capacitor C1 is grounded. The first end of the first resistor R1 is connected to the first end of the first capacitor C1 through the first switch K1, and the second end of the first resistor R1 is grounded. The input terminal of the first inverter A1 is connected to the zero-crossing set signal, and the output terminal is connected to the control terminal of the first switch K1.

[0008] Optionally, the adjustment unit includes a second current source I2, a third current source I3, a second switch K2, and a third switch K3; The input terminals of the second current source I2 and the third current source I3 are both connected to the power supply voltage. The output terminal of the second current source I2 is connected to the first terminal of the first capacitor C1 through the second switch K2, and the output terminal of the third current source I3 is connected to the first terminal of the first capacitor C1 through the third switch K3.

[0009] Optionally, the comparison unit includes: The first comparator CMP1 has its non-inverting input connected to the first terminal of the first capacitor C1, its inverting input connected to the first reference voltage Vref1, and its output terminal outputting the delayed set signal.

[0010] Optionally, the adjustment unit includes a fourth current source I4, a second resistor R2, a third resistor R3, a fourth resistor R4, a fourth switch K4, and a fifth switch K5; The input terminal of the fourth current source I4 is connected to the power supply voltage, and the output terminal is grounded through the second resistor R2, the third resistor R3 and the fourth resistor R4 in sequence. The first end of the fourth switch K4 is connected between the second resistor R2 and the third resistor R3, and the second end of the fourth switch K4 is connected between the third resistor R3 and the fourth resistor R4. The first end of the fifth switch K5 is connected between the third resistor R3 and the fourth resistor R4, and the second end of the fifth switch K5 is grounded.

[0011] Optionally, the comparison unit includes: The second comparator CMP2 has its non-inverting input connected to the first terminal of the first capacitor C1, its inverting input connected to the output terminal of the fourth current source I4, and its output terminal outputs the delayed set signal.

[0012] Optionally, the zero-crossing detection module includes: The third comparator CMP3 has a non-inverting input connected to the second reference voltage Vref2, an inverting input connected to the voltage signal VS of the transformer auxiliary winding, and an output that outputs the zero-crossing set signal.

[0013] Optionally, the switch control module includes a first flip-flop DFFR1, a second flip-flop DFFR2, a second inverter A2, and a fourth comparator CMP4; The input terminal of the second inverter A2 is connected to the frequency limiting parameter Fmax, and the output terminal is connected to the reset terminal of the first flip-flop DFFR1; The input terminal of the first flip-flop DFFR1 is connected to the power supply voltage VDD, the clock terminal of the first flip-flop DFFR1 is connected to the output terminal of the jitter delay module, and the output terminal of the first flip-flop DFFR1 is connected to the clock terminal of the second flip-flop DFFR2. The non-inverting input of the fourth comparator CMP4 is connected to the source of the power switch Q1, the inverting input is connected to the peak reference voltage Vocp, and the output is connected to the reset terminal of the second flip-flop DFFR2. The input terminal of the second flip-flop DFFR2 is connected to the power supply voltage VDD, and the output terminal of the second flip-flop DFFR2 is connected to the gate of the power switch Q1 to control the on / off state of the power switch Q1.

[0014] Secondly, the present invention proposes a valley detection jitter control method, applied to the valley detection jitter circuit described above, comprising the following steps: Receive the voltage signal VS from the auxiliary winding of the transformer, and generate a zero-crossing set signal based on the voltage signal VS; After the zero-crossing set signal is generated, a delay time is introduced, and a delayed set signal is generated after the delay ends. The power switch Q1 is turned on according to the delayed set signal, so that the turn-on time of the power switch Q1 corresponds to the resonant valley region of the voltage signal VS; By periodically or sequentially changing the delay time over multiple switching cycles, the conduction time of the power switch Q1 changes within the resonant valley region, thereby causing fluctuations in the operating frequency of the switching power supply.

[0015] The effects described in the invention are merely those of the embodiments, and not all the effects of the invention. One of the above technical solutions has the following advantages or beneficial effects: The valley detection frequency jitter circuit provided in this application introduces a variable delay mechanism based on zero-crossing detection, ensuring that the turn-on time of the power switch always falls within the voltage resonant valley region. Simultaneously, this turn-on time is varied over multiple switching cycles, thereby achieving frequency jittering without disrupting the valley turn-on conditions. This method effectively disperses the harmonic energy generated by a fixed switching frequency, reduces electromagnetic interference levels, and balances switching loss control with system stability, making it suitable for practical applications of quasi-resonant mode switching power supplies.

[0016] Furthermore, by setting up energy storage units, adjustment units, and comparison units, the delay generation process is completed based on the dynamic changes in the energy storage node voltage. Stable switching of the delay time between different values ​​is achieved through periodic adjustments to the charging / discharging path or charging / discharging intensity. Simultaneously, by combining multiple comparison and limiting control structures, the conduction behavior of the power switching transistors can be effectively constrained while ensuring delay accuracy and consistency. This not only improves the controllability and flexibility of the jitter process but also enhances the reliability and anti-interference capability of the circuit under different operating states, facilitating integration and engineering applications. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the principles of this application.

[0018] Figure 1 The circuit topology diagram of the valley detection circuit for switching power supplies proposed by the inventor is shown; Figure 2 It shows Figure 1 The waveform diagram of the relevant signals of the valley bottom detection circuit shown; Figure 3 A structural block diagram of a valley detection frequency dithering circuit according to an embodiment of the present invention is shown; Figure 4 A circuit topology diagram of a valley detection frequency dithering circuit according to an embodiment of the present invention is shown; Figure 5 It shows Figure 4 The waveform diagram of the relevant signal of the valley bottom detection frequency dithering circuit is shown. Figure 6 A circuit topology diagram of a jitter delay module according to an embodiment of the present invention is shown; Figure 7 A schematic diagram illustrating the linear periodic variation trend of frequency dithering according to an embodiment of the present invention is shown; Figure 8 A circuit topology diagram of a jitter delay module according to another embodiment of the present invention is shown; Figure 9 A schematic flowchart of a valley detection jitter control method according to an embodiment of the present invention is shown. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0020] It should be noted that references to "an embodiment," "embodiment," "example embodiment," etc., in this specification refer to the described embodiment including specific features, structures, or characteristics; however, not every embodiment must include these specific features, structures, or characteristics. Furthermore, such expressions do not refer to the same embodiment. Moreover, when describing specific features, structures, or characteristics in conjunction with embodiments, whether or not explicitly described, it is indicated that incorporating such features, structures, or characteristics into other embodiments is within the knowledge of those skilled in the art.

[0021] Furthermore, certain terms are used in the specification and subsequent claims to refer to specific components or parts. Those skilled in the art will understand that manufacturers may use different names or terms to refer to the same component or part. This specification and subsequent claims do not distinguish components or parts by differences in name, but rather by differences in function. The terms "comprising" and "including" used throughout the specification and subsequent claims are open-ended and should be interpreted as "including but not limited to." Additionally, the term "connection" here includes any direct and indirect electrical connection means. Indirect electrical connection means include connections made through other means.

[0022] Based on the aforementioned technical problems, the inventors first constructed a valley detection circuit for quasi-resonant mode switching power supplies during the research and development process. Its basic structure is as follows: Figure 1 As shown in the diagram, this circuit includes a zero-crossing detection module, a switch control module, a transformer primary winding NP, a power switch Q1, and a primary current sensing resistor Rcs. It is used to achieve basic operation control of the switching power supply while ensuring valley-level turn-on. VS is a voltage signal induced by the transformer auxiliary winding, used to reflect changes in the secondary output voltage. The second reference voltage Vref2 is set to near 0V to provide a reference for determining the zero-crossing of VS. The zero-crossing detection module generates a zero-crossing set signal when it detects that the VS voltage has crossed zero, and sends this signal to the switch control module.

[0023] The switching control module includes a D flip-flop (DFFR) and its associated control logic. VDD is the operating power supply, CLK is the clock signal, RB is the reset signal, and Q is the flip-flop output. The D flip-flop is a rising-edge triggered structure. When CLK has a rising edge and RB is active, output Q is set; when RB is inactive, output Q is reset to its initial state. This triggering logic controls the turn-on timing of the power switch Q1.

[0024] In addition, the circuit includes a frequency limiting parameter Fmax to limit the system's highest operating frequency. This parameter adaptively adjusts based on the load condition to constrain the operating frequency range of the switching power supply under different load conditions. The primary-side current sensing resistor Rcs is used to collect primary-side current information. When the power switch Q1 is turned on, the primary-side coil current gradually increases and stores energy. When the CS node voltage Vcs is detected to be higher than the peak reference voltage Vocp, the comparator module outputs a reset signal, resetting the corresponding trigger output and thus turning off the power switch Q1, completing one energy transfer cycle.

[0025] Figure 2 It shows Figure 1 The waveform diagram of the relevant signals from the valley bottom detection circuit is shown. Combined with... Figure 2 The waveform shown is for Figure 1 The working principle of the valley bottom detection circuit is explained below.

[0026] In this invention, the switching power supply operates in quasi-resonant (QR) mode. When the power switch Q1 is turned on and the primary winding is in the energy storage stage, the voltage signal VS induced in the auxiliary winding is negative, i.e., VS < 0V; when the power switch Q1 is turned off, the primary winding stops storing energy and energy is released to the load by the secondary winding, VS becomes positive, i.e., VS > 0V. Figure 2 It is known that a significant resonant waveform will be generated in VS at the instant of energy conversion in the transformer and the turn-on and turn-off of the power switch Q1. Since the conduction loss of the power switch Q1 is proportional to the voltage it withstands at the moment of turn-on, the higher the conduction voltage, the greater the conduction loss. Therefore, in the design of quasi-resonant switching power supplies, the power switch Q1 is usually triggered to turn on near the zero-crossing of the voltage signal VS, so that it turns on in the resonance valley region, thereby effectively reducing switching losses and improving system efficiency.

[0027] Furthermore, the specific conduction process of power switch Q1 is as follows: After the secondary coil discharges, the VS voltage drops rapidly and enters the resonant state. The second reference voltage Vref2 is set to be close to 0V. When VS drops below 0V, the zero-crossing set signal S_set output by the third comparator CMP3 changes from low to high. If the frequency limiting parameter Fmax is high at this time, the output after the second inverter A2 is low, making the reset terminal of the first flip-flop DFFR1 inactive, its output remains unchanged, the second flip-flop DFFR2 is not triggered, the switching signal SW remains low, and power switch Q1 is not turned on.

[0028] As the voltage signal VS continues to resonate, when VS crosses 0V again and enters the next negative half-cycle, the third comparator CMP3 outputs a high-level S_set signal again. If, during this period, the frequency limiting parameter Fmax has been reset to a low level and outputs a high level after passing through the second inverter A2, making the reset terminal of the first flip-flop DFFR1 valid, then when the rising edge of S_set arrives, the output of the first flip-flop DFFR1 jumps from a low level to a high level. At this time, the CS node voltage Vcs corresponding to the primary current detection signal Vcs is still less than the peak reference voltage Vocp. The fourth comparator CMP4 outputs a high level to the reset terminal of the second flip-flop DFFR2, causing the switching signal SW output by the second flip-flop DFFR2 to jump from a low level to a high level. The power switch Q1 turns on, the primary coil begins to store energy, and the primary current Ics rises accordingly.

[0029] Therefore, the frequency limiting parameter Fmax constrains the turn-on time of power switch Q1 based on the current load state, thereby limiting the system's maximum operating frequency. When the frequency limiting parameter Fmax has not yet been reset to a low level, even if the VS voltage crosses zero, power switch Q1 will not be triggered to turn on; only after the frequency limiting parameter Fmax is reset is power switch Q1 allowed to turn on near the zero-crossing of the voltage signal VS. Figure 2 As shown in the waveform, if the frequency limiting parameter Fmax has been reset to low level before the voltage signal VS drops to 0V, then at the zero-crossing moment of the voltage signal VS, the zero-crossing set signal S_set triggers the switch signal SW to go high, and the power switch Q1 turns on.

[0030] Furthermore, the disconnection process of power switch Q1 is as follows: During the conduction period of power switch Q1, the primary coil is in an energy storage state, and the current Ics on the primary current sensing resistor Rcs gradually increases over time. When the primary current reaches the preset peak value Ipeak, the voltage Vcs corresponding to the CS node exceeds the peak reference voltage Vocp, the output of the fourth comparator COMP4 flips to a low level, resetting the output switching signal SW of the second flip-flop DFFR2 to a low level, thereby turning off power switch Q1, stopping the primary coil from storing energy, and entering the energy transfer stage.

[0031] Based on the aforementioned valley detection and frequency limiting control circuit, in order to achieve frequency dithering to reduce electromagnetic interference, during the research and development process, an attempt was made to change the operating frequency by introducing dithering into the frequency limiting parameter Fmax. However, combined with... Figure 2As shown in the waveform, it can be observed that this method is difficult to achieve a stable and controllable frequency jitter effect. When the jitter delay is completed before the VS voltage crosses zero, the power switch Q1 is still turned on near the same zero-crossing point, and the actual turn-on time does not change, making it difficult to achieve the frequency jitter effect. However, when the jitter delay occurs after the VS voltage crosses zero, it is necessary to wait for the next VS voltage to cross zero before the switching signal SW can be triggered, causing the turn-on time to jump or even change across cycles, making it difficult to achieve continuous and predictable frequency modulation.

[0032] Therefore, it is evident that simply jittering the frequency limiting parameter Fmax cannot achieve precise and consistent conduction timing modulation while ensuring that the power switch Q1 still operates in the resonant valley region. The jittering effect is limited by the VS zero-crossing event itself, making it difficult to balance conduction loss control with the controllability of the jittering effect. Through further research, the inventors gradually recognized these limitations and subsequently redesigned and iterated the valley detection and switching control mechanism, ultimately proposing the technical solution adopted in this invention.

[0033] Figure 3 A structural block diagram of a valley detection frequency dithering circuit according to an embodiment of the present invention is shown. Figure 3 As shown, this valley detection frequency jitter circuit is applied in a quasi-resonant mode switching power supply and includes a zero-crossing detection module, a jitter delay module, and a switching control module. The zero-crossing detection module receives the voltage signal VS from the transformer auxiliary winding and generates a zero-crossing set signal based on VS. The jitter delay module is connected to the zero-crossing detection module and introduces a delay time after the zero-crossing set signal is generated, then outputs a delayed set signal. The switching control module is connected to the jitter delay module and the gate of the power switch Q1. After the zero-crossing set signal is generated, it controls the power switch Q1 to turn on based on the delayed set signal, so that the turn-on time of the power switch Q1 corresponds to the resonant valley region of the voltage signal VS. Specifically, the delay time varies between at least two different delay values ​​over multiple switching cycles, causing the turn-on time of the power switch Q1 to change within the resonant valley region, thereby causing jitter in the operating frequency of the switching power supply.

[0034] According to the above embodiments, by introducing a variable delay mechanism based on zero-crossing detection, the turn-on time of the power switch is always ensured to fall within the voltage resonant valley region. Simultaneously, this turn-on time is varied over multiple switching cycles, thereby achieving switching frequency jitter without disrupting the valley turn-on conditions. This method effectively disperses the harmonic energy generated by a fixed switching frequency, reduces electromagnetic interference levels, and balances switching loss control with system stability, making it suitable for practical applications of quasi-resonant mode switching power supplies.

[0035] In one embodiment, reference Figure 3The jitter delay module includes an energy storage unit, an adjustment unit, and a comparison unit. The energy storage unit, connected to the zero-crossing detection module, controls the charging and discharging of the energy storage node based on the zero-crossing set signal, causing the energy storage node voltage to vary over time. The adjustment unit, connected to the energy storage unit, periodically adjusts the charging and discharging path or intensity of the energy storage unit over multiple switching cycles to change the time it takes for the energy storage node voltage to reach a preset judgment condition. The comparison unit, connected to both the energy storage unit and the adjustment unit, compares the energy storage node voltage with a preset threshold and outputs a delayed set signal when the energy storage node voltage reaches the preset threshold.

[0036] In this embodiment, the jitter delay module does not directly modulate the switching control signal or frequency limiting parameters. Instead, it uses the zero-crossing set signal output by the zero-crossing detection module as the time starting point. By controlling the voltage evolution process of the energy storage node, an adjustable delay interval is constructed after the zero-crossing event. The length of this delay interval is determined by the charging behavior of the energy storage unit and is regularly varied within multiple switching cycles by the adjustment unit, causing the timing of the comparison unit triggering the delay set signal to shift within each switching cycle. Therefore, the conduction time of the power switch no longer corresponds to a single zero-crossing point but is controlled to vary within the time range of the resonant valley. This ensures low conduction loss characteristics while achieving jitter distribution of the operating frequency, effectively dispersing the switching spectrum energy. This implementation organically combines frequency jitter control with the valley detection process, avoiding the timing uncertainties caused by directly jittering the frequency limiting signal, making the frequency jitter effect more stable and predictable.

[0037] Figure 4 A circuit topology diagram of a valley detection frequency dithering circuit according to an embodiment of the present invention is shown. Figure 4 As shown, the zero-crossing detection module includes a third comparator CMP3. The non-inverting input of the third comparator CMP3 is connected to the second reference voltage Vref2, the inverting input is connected to the voltage signal VS of the transformer auxiliary winding, and the output terminal outputs a zero-crossing set signal.

[0038] In one embodiment, such as Figure 4As shown, the switch control module includes a first flip-flop DFFR1, a second flip-flop DFFR2, a second inverter A2, and a fourth comparator CMP4. The input of the second inverter A2 is connected to the frequency limiting parameter Fmax, and its output is connected to the reset terminal of the first flip-flop DFFR1. The input of the first flip-flop DFFR1 is connected to the power supply voltage VDD, its clock terminal is connected to the output of the jitter delay module, and its output is connected to the clock terminal of the second flip-flop DFFR2. The non-inverting input of the fourth comparator CMP4 is connected to the source of the power switch Q1, its inverting input is connected to the peak reference voltage Vocp, and its output is connected to the reset terminal of the second flip-flop DFFR2. The input of the second flip-flop DFFR2 is connected to the power supply voltage VDD, and its output is connected to the gate of the power switch Q1 to control the switching on and off of the power switch Q1.

[0039] According to the above embodiment, the valley detection frequency jitter circuit uses the voltage signal VS of the transformer auxiliary winding as a key timing reference. A zero-crossing detection module determines the voltage polarity change during energy conversion and uses this as the triggering basis for subsequent control logic. Based on the zero-crossing detection result, a jitter delay module is introduced to controllably delay the turn-on time of the power switch, so that the turn-on action is no longer strictly locked to a single zero-crossing point, but changes within the time interval corresponding to the resonant valley. Simultaneously, the switching control module, under the joint constraints of the frequency limiting parameter Fmax and the primary-side current detection signal Vcs, coordinates the turn-on and turn-off processes, thereby achieving a unification of valley turn-on and frequency jitter while ensuring stable system operation and limiting peak current. Through this circuit structure, this embodiment can embed frequency jitter behavior into the valley detection timing without introducing additional complex control logic, effectively dispersing the switching spectrum energy while maintaining low conduction losses and consistent switching behavior.

[0040] The switching control module constructs a complete turn-on and turn-off control link through a multi-level triggering and comparison mechanism. The first trigger, DFFR1, samples and synchronizes the delayed set signal output by the jitter delay module. The second trigger, DFFR2, generates the actual switching drive signal under the premise of meeting frequency limiting and current limiting conditions. The frequency limiting parameter Fmax and the primary-side current detection signal Vcs act on the reset path of the triggers, respectively, forming a dual constraint on the turn-on behavior. Through this structural configuration, the turn-on time of the power switch Q1 is uniformly scheduled by the jitter delay module, while its turn-on duration and turn-off time are jointly limited by the peak current determination and the frequency limiting parameter. This allows valley-level turn-on, frequency jittering, and current protection to be achieved collaboratively within the same control framework. This embodiment organically embeds jitter control into the switching drive link without changing the basic control logic of the quasi-resonant operating mode, avoiding the uncertainty of the turn-on timing and helping to maintain the stability and consistency of system operation while reducing electromagnetic interference.

[0041] Figure 5 It shows Figure 4 The waveform diagram of the relevant signal from the valley bottom detection frequency dithering circuit is shown. Figure 5 As shown, the zero-crossing set signal S_set is generated by the zero-crossing detection module, and its rising edge corresponds to the moment when the voltage signal VS enters the negative half-cycle. After the zero-crossing set signal S_set transitions from low to high, the jitter delay module does not immediately output a conduction signal, but instead enters a delay timing phase. During this phase, the energy storage node voltage changes with time according to a preset charging and discharging pattern. When the voltage signal reaches the judgment threshold set by the comparison unit, the comparison unit flips its output, generating the delayed set signal S_set_d. Therefore, the delayed set signal S_set_d has a delay time relative to the zero-crossing set signal S_set. This delay time is the actual control quantity for triggering the conduction.

[0042] Furthermore, the delay time over multiple consecutive switching cycles... It is not fixed, but varies sequentially among several preset delay values. When the zero-crossing set signal S_set arrives in different periods, the time required for the energy storage node to reach the decision threshold is different. Therefore, the rising edge of the delayed set signal S_set_d has different offsets relative to the zero-crossing set signal S_set. Since the power switch is triggered by the delayed set signal S_set_d, the actual turn-on time of the power switch in each period is slightly offset within the resonant valley region, thus allowing the operating frequency of the switching power supply to exhibit controlled variations within a certain range.

[0043] from Figure 5It can be seen that this delay mechanism is always based on zero-crossing detection, and the conduction behavior is always limited to the valley time window. The change in delay only changes the specific trigger position in the valley region and does not disrupt the quasi-resonant operating conditions. Thus, it is possible to controllably modulate the conduction time while ensuring the valley conduction characteristics, providing a stable and consistent implementation path for frequency jitter.

[0044] To facilitate understanding of the implementation of the jitter delay module of the present invention, the internal circuit structure will be described in detail below with reference to specific embodiments.

[0045] Example 1: Figure 6 A circuit topology diagram of a jitter delay module 20 according to an embodiment of the present invention is shown. Figure 6 As shown, the energy storage unit includes a first current source I1, a first switch K1, a first resistor R1, a first capacitor C1, and a first inverter A1. The input terminal of the first current source I1 is connected to the power supply voltage, and its output terminal is connected to the first terminal of the first capacitor C1, while the second terminal of the first capacitor C1 is grounded. The first terminal of the first resistor R1 is connected to the first terminal of the first capacitor C1 through the first switch K1, and the second terminal of the first resistor R1 is grounded. The input terminal of the first inverter A1 is connected to a zero-crossing set signal, and its output terminal is connected to the control terminal of the first switch K1.

[0046] The regulating unit includes a second current source I2, a third current source I3, a second switch K2, and a third switch K3. The input terminals of the second current source I2 and the third current source I3 are both connected to the power supply voltage. The output terminal of the second current source I2 is connected to the first terminal of the first capacitor C1 through the second switch K2, and the output terminal of the third current source I3 is connected to the first terminal of the first capacitor C1 through the third switch K3.

[0047] The comparison unit includes a first comparator CMP1. The non-inverting input of the first comparator CMP1 is connected to the first terminal of the first capacitor C1, the inverting input is connected to the first reference voltage Vref1, and the output outputs a delayed set signal.

[0048] In this embodiment, the jitter delay module uses the capacitor energy storage process as a time reference and achieves variable delay decision after a zero-crossing event by controlling the charging and discharging behavior of the energy storage node. Specifically, when the zero-crossing set signal changes, the energy storage unit switches between charging and discharging states under inverse control, causing the energy storage node voltage to exhibit a time-dependent change. Simultaneously, the adjustment unit selectively conducts multiple charging branches, changing the equivalent charging intensity of the energy storage node in different switching cycles, thus varying the time required for the energy storage node voltage to reach a comparison threshold. The comparison unit uses this energy storage node voltage as the decision object, outputting a delayed set signal when it reaches a preset threshold for subsequent switching control.

[0049] Specifically, constant current sources I1, I2, and I3 provide charging current to the energy storage capacitor C1, and resistor R1 is used to charge and discharge the energy storage capacitor C1. The first comparator CMP1 outputs a delayed set signal S_set_d based on the comparison result between the energy storage node voltage and the first reference voltage Vref1. When the zero-crossing set signal S_set is low, the corresponding transformer auxiliary winding voltage VS is in the positive voltage range. After passing through the first inverter A1, it outputs a high level, causing the first switch K1 to close. The energy storage capacitor C1 discharges through resistor R1, and the energy storage node voltage V1 remains below the first reference voltage Vref1. At this time, the delayed set signal S_set_d output by the first comparator CMP1 remains low. When the zero-crossing set signal S_set jumps to a high level, the corresponding VS enters the negative voltage range. After passing through the first inverter A1, it outputs a low level, causing the first switch K1 to open, and the energy storage capacitor C1 enters the charging state. At this time, the first constant current source I1 charges the energy storage capacitor C1, causing the energy storage node voltage V1 to gradually rise over time. When the energy storage node voltage V1 rises and reaches the first reference voltage Vref1, the comparator CMP1 flips and outputs a delayed set signal S_set_d at a high level, thereby triggering the subsequent switch control signal SW to enter the conduction state.

[0050] According to the formula for calculating capacitor voltage It can be seen that, under the condition that the capacitance of the energy storage capacitor C1 and the comparison threshold voltage remain unchanged, the time required for the energy storage node voltage to reach the decision threshold is related to the magnitude of the charging current; the larger the charging current, the shorter the time required to reach the threshold. Therefore, by changing the equivalent charging current of the energy storage capacitor C1, the delay time can be adjusted. Adjustments were made.

[0051] refer to Figure 6 Taking at least two controllable branches as an example, the regulating unit controls the connection state of the second constant current source I2 and the third constant current source I3 through the second switch K2 and the third switch K3. Within different switching cycles, the conduction combination of the second switch K2 and the third switch K3 is periodically changed, thereby changing the number of constant current sources participating in charging, and thus changing the equivalent charging current of the energy storage capacitor C1. This causes the flip-off time of the first comparator CMP1 to change within multiple switching cycles, forming a periodically varying delay time. It should be noted that, to ensure the power switch remains within the resonant valley region during conduction, a delay time is recommended. The maximum value is limited to less than a quarter of a resonant period.

[0052] In practical applications, the number and combination of the above-mentioned charging branches can be flexibly configured according to the system's requirements for delay accuracy and adjustment range.

[0053] The above structure directly links the generation of the delay to zero-crossing detection and restricts the delay variation to a time window determined by the dynamic behavior of the energy storage unit, ensuring that the power switch always conducts near the resonant valley region. Simultaneously, since the delay variation is achieved by adjusting the charging path, a controlled and repeatable jitter effect can be formed while maintaining circuit stability and consistency. This allows for effective expansion of the switching frequency without disrupting the valley conduction conditions, reducing the risk of electromagnetic interference.

[0054] Furthermore, the delay amount is determined by combining specific parameters. The implementation method will be explained. Taking a system with a maximum operating frequency of 200 kHz as an example, corresponding to a single switching cycle of 5 μs, when the jitter ratio is set to 5%, the maximum allowable delay is... The delay step is 0.25 μs. Under this condition, by setting two sets of controllable charging branches, three different equivalent charging currents can be formed, with the delay adjustment step size corresponding to each level being approximately 0.083 μs. Accordingly, the current magnitudes of each charging current source can be configured according to a predetermined ratio, for example, the ratio of the first constant current source I1, the second constant current source I2, and the third constant current source I3 is 2:3:1. Based on the target delay step size and the parameters of the energy storage capacitor C1, the first reference voltage Vref1 is preset, so that the comparator completes the switching at the corresponding time.

[0055] In the specific control process, when the set signal S_set is active, the control signals S1 of the second switch K2 and S2 of the third switch K3 are periodically combined and switched to allow different charging branches to participate in or exit the capacitor charging process sequentially in multiple consecutive cycles. In the first stage (4 consecutive cycles), S1=1 and S2=1 are maintained, allowing both charging branches to conduct simultaneously and applying the maximum charging current to capacitor C1. In the second stage (4 consecutive cycles), S1=1 and S2=0 are maintained, keeping only one charging branch conducting to form a medium charging current. In the third stage (4 consecutive cycles), S1=0 and S2=0 are maintained, both charging branches are disconnected, and only the base current branch participates in charging, forming the minimum charging current. In the fourth stage (4 consecutive cycles), S1=1 and S2=0 are maintained again. In the fifth stage (4 consecutive cycles), S1=1 and S2=1 are restored. The above five stages are executed sequentially and cyclically, causing the charging current to change periodically between the "large-medium-small-medium-large" levels. This causes the comparator flip time to shift periodically within a preset range, forming a periodic delay signal S_set_d, which in turn adjusts the on-time of the switch signal SW, achieving a controlled jitter modulation effect.

[0056] Figure 7 A schematic diagram illustrating the linear periodic variation trend of frequency dithering according to an embodiment of the present invention is shown. Figure 7 As shown, when finer frequency adjustment levels are set and the jitter center value is selected at the middle level, the system operating frequency exhibits an approximately linear periodic variation trend around this center value. The frequency offsets corresponding to each level switch sequentially according to a preset order, making the overall jitter trajectory appear as a regular, symmetrical periodic jitter pattern on the time axis. In the figure, Period represents the jitter period, the size of which is determined by the number of adjustment levels and the timing period corresponding to each level; that is, Period equals the product of the number of levels and the timing period of a single level. Through the above method, a stable and predictable jitter modulation effect can be achieved while ensuring the continuity and controllability of frequency changes.

[0057] Example 2: Figure 8 A circuit topology diagram of a jitter delay module according to another embodiment of the present invention is shown. Compared with Embodiment 1, this embodiment only adjusts the specific structure of the adjustment unit and the comparison unit, while the rest remains the same.

[0058] Specifically, the regulating unit includes a fourth current source I4, a second resistor R2, a third resistor R3, a fourth resistor R4, a fourth switch K4, and a fifth switch K5. The input terminal of the fourth current source I4 is connected to the power supply voltage, and its output terminal is grounded sequentially through the second resistor R2, the third resistor R3, and the fourth resistor R4. The first terminal of the fourth switch K4 is connected between the second resistor R2 and the third resistor R3, and the second terminal of the fourth switch K4 is connected between the third resistor R3 and the fourth resistor R4. The first terminal of the fifth switch K5 is connected between the third resistor R3 and the fourth resistor R4, and the second terminal of the fifth switch K5 is grounded.

[0059] The comparison unit includes a second comparator CMP2. The non-inverting input of the second comparator CMP2 is connected to the first terminal of the first capacitor C1, the inverting input is connected to the output of the fourth current source I4, and the output terminal outputs a delayed set signal.

[0060] In this embodiment, the fourth current source I4 forms a segmented voltage distribution through the second resistor R2, the third resistor R3, and the fourth resistor R4 connected in series, with different resistor nodes corresponding to different voltage levels. By selectively controlling the conduction states of the fourth switch K4 and the fifth switch K5, the effective segments participating in voltage division in the resistor network can be changed, thereby causing the output terminal of the fourth current source I4 to exhibit different equivalent voltage values. Thus, the adjustment unit can switch between multiple operating states, providing graded and controllable reference conditions for delay decision-making.

[0061] Based on this, the comparison unit compares the voltage signal formed on the first capacitor C1 in the energy storage unit with the aforementioned adjustable reference voltage through the second comparator CMP2. When the voltage on the first capacitor C1 reaches or exceeds the corresponding level determined by the adjustment unit, the second comparator CMP2 outputs a delay set signal. This structure makes the delay decision threshold no longer fixed, but can be dynamically adjusted according to the state changes of the adjustment unit. Thus, without changing the basic structure of the energy storage unit, fine adjustment of the delay characteristics can be achieved, providing another implementation path for jitter delay and enhancing the flexibility and scalability of the invention in terms of circuit implementation.

[0062] In summary, this embodiment also achieves jitter delay control by changing the delay decision condition, causing the generation time of the delay set signal to vary within multiple switching cycles. Compared to Embodiment 1, this embodiment differs only in the formation method of the delay decision condition; its basic working mechanism remains the same, therefore its specific working process will not be described further. Furthermore, the corresponding periodic delay signal can also be obtained by periodically changing the capacitance of the energy storage capacitor C1, which is not specifically limited here.

[0063] According to the above embodiments, by setting up an energy storage unit, an adjustment unit, and a comparison unit, the delay generation process is completed based on the dynamic changes of the energy storage node voltage. Furthermore, by periodically adjusting the charging and discharging path or the charging and discharging intensity, stable switching of the delay time between different values ​​is achieved. Simultaneously, by combining multiple comparison and limiting control structures, the conduction behavior of the power switch can be effectively constrained while ensuring delay accuracy and consistency. This not only improves the controllability and flexibility of the jitter process but also enhances the reliability and anti-interference capability of the circuit under different operating states, facilitating integration and engineering applications.

[0064] Figure 9 A schematic flowchart of a valley detection jitter control method according to an embodiment of the present invention is shown. Figure 9 As shown, the method includes the following steps: Step S100: Receive the voltage signal VS from the auxiliary winding of the transformer, and generate a zero-crossing set signal based on the voltage signal VS.

[0065] Step S200: After the zero-crossing set signal is generated, a delay time is introduced, and a delayed set signal is generated after the delay ends.

[0066] Step S300: Control the power switch Q1 to turn on according to the delayed set signal, so that the turn-on time of the power switch Q1 corresponds to the resonant valley region of the voltage signal VS.

[0067] In step S400, the delay time is changed periodically or sequentially within multiple switching cycles, so that the conduction time of the power switch Q1 changes in the resonant valley region, thereby causing the operating frequency of the switching power supply to fluctuate.

[0068] The specific implementation methods for each step in the above valley detection jitter control method refer to the relevant content of the embodiment in the above valley detection jitter control circuit, and will not be repeated here.

[0069] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0070] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A valley detection frequency dithering circuit, applied in a quasi-resonant mode switching power supply, characterized in that, include: The zero-crossing detection module receives the voltage signal VS from the auxiliary winding of the transformer and generates a zero-crossing set signal based on the voltage signal VS. A jitter delay module, connected to the zero-crossing detection module, is used to introduce a delay time after the zero-crossing set signal is generated and output a delayed set signal; A switching control module, connected to the jitter delay module and the gate of the power switch Q1, is used to control the power switch Q1 to turn on according to the delay set signal after the zero-crossing set signal is generated, so that the turn-on time of the power switch Q1 corresponds to the resonant valley region of the voltage signal VS. In this process, the delay time varies between at least two different delay values ​​during multiple switching cycles, so that the turn-on time of the power switch Q1 changes within the resonant valley region, thereby causing fluctuations in the operating frequency of the switching power supply.

2. The valley detection frequency dithering circuit according to claim 1, characterized in that, The jitter delay module includes: An energy storage unit, connected to the zero-crossing detection module, is used to control the charging and discharging of the energy storage node according to the zero-crossing set signal, so that the energy storage node forms a time-varying energy storage node voltage. An adjustment unit, connected to the energy storage unit, is used to periodically adjust the charging and discharging path or charging and discharging intensity of the energy storage unit within multiple switching cycles, so as to change the time when the energy storage node voltage reaches a preset judgment condition. The comparison unit is connected to the energy storage unit and the regulation unit respectively, and is used to compare the voltage of the energy storage node with a preset threshold, and output the delayed set signal when the voltage of the energy storage node reaches the preset threshold.

3. The valley detection frequency dithering circuit according to claim 2, characterized in that, The energy storage unit includes a first current source I1, a first switch K1, a first resistor R1, a first capacitor C1, and a first inverter A1; The input terminal of the first current source I1 is connected to the power supply voltage, the output terminal is connected to the first terminal of the first capacitor C1, and the second terminal of the first capacitor C1 is grounded. The first end of the first resistor R1 is connected to the first end of the first capacitor C1 through the first switch K1, and the second end of the first resistor R1 is grounded. The input terminal of the first inverter A1 is connected to the zero-crossing set signal, and the output terminal is connected to the control terminal of the first switch K1.

4. The valley detection frequency dithering circuit according to claim 3, characterized in that, The regulating unit includes a second current source I2, a third current source I3, a second switch K2, and a third switch K3; The input terminals of the second current source I2 and the third current source I3 are both connected to the power supply voltage. The output terminal of the second current source I2 is connected to the first terminal of the first capacitor C1 through the second switch K2, and the output terminal of the third current source I3 is connected to the first terminal of the first capacitor C1 through the third switch K3.

5. The valley detection frequency dithering circuit according to claim 4, characterized in that, The comparison unit includes: The first comparator CMP1 has its non-inverting input connected to the first terminal of the first capacitor C1, its inverting input connected to the first reference voltage Vref1, and its output terminal outputting the delayed set signal.

6. The valley detection frequency dithering circuit according to claim 3, characterized in that, The regulating unit includes a fourth current source I4, a second resistor R2, a third resistor R3, a fourth resistor R4, a fourth switch K4, and a fifth switch K5; The input terminal of the fourth current source I4 is connected to the power supply voltage, and the output terminal is grounded through the second resistor R2, the third resistor R3 and the fourth resistor R4 in sequence. The first end of the fourth switch K4 is connected between the second resistor R2 and the third resistor R3, and the second end of the fourth switch K4 is connected between the third resistor R3 and the fourth resistor R4. The first end of the fifth switch K5 is connected between the third resistor R3 and the fourth resistor R4, and the second end of the fifth switch K5 is grounded.

7. The valley detection frequency dithering circuit according to claim 6, characterized in that, The comparison unit includes: The second comparator CMP2 has its non-inverting input connected to the first terminal of the first capacitor C1, its inverting input connected to the output terminal of the fourth current source I4, and its output terminal outputs the delayed set signal.

8. The valley detection frequency dithering circuit according to claim 1, characterized in that, The zero-crossing detection module includes: The third comparator CMP3 has a non-inverting input connected to the second reference voltage Vref2, an inverting input connected to the voltage signal VS of the transformer auxiliary winding, and an output that outputs the zero-crossing set signal.

9. The valley detection frequency dithering circuit according to claim 5 or 7, characterized in that, The switch control module includes a first flip-flop DFFR1, a second flip-flop DFFR2, a second inverter A2, and a fourth comparator CMP4; The input terminal of the second inverter A2 is connected to the frequency limiting parameter Fmax, and the output terminal is connected to the reset terminal of the first flip-flop DFFR1; The input terminal of the first flip-flop DFFR1 is connected to the power supply voltage VDD, the clock terminal of the first flip-flop DFFR1 is connected to the output terminal of the jitter delay module, and the output terminal of the first flip-flop DFFR1 is connected to the clock terminal of the second flip-flop DFFR2. The non-inverting input of the fourth comparator CMP4 is connected to the source of the power switch Q1, the inverting input is connected to the peak reference voltage Vocp, and the output is connected to the reset terminal of the second flip-flop DFFR2. The input terminal of the second flip-flop DFFR2 is connected to the power supply voltage VDD, and the output terminal of the second flip-flop DFFR2 is connected to the gate of the power switch Q1 to control the power switch Q1 to turn on and off.

10. A valley detection jitter control method, applied in the valley detection jitter circuit as described in any one of claims 1-9, characterized in that, Includes the following steps: Receive the voltage signal VS from the auxiliary winding of the transformer, and generate a zero-crossing set signal based on the voltage signal VS; After the zero-crossing set signal is generated, a delay time is introduced, and a delayed set signal is generated after the delay ends. The power switch Q1 is turned on according to the delayed set signal, so that the turn-on time of the power switch Q1 corresponds to the resonant valley region of the voltage signal VS; During multiple switching cycles, the delay time is changed periodically or sequentially, causing the conduction time of the power switch Q1 to change within the resonant valley region, thereby causing fluctuations in the operating frequency of the switching power supply.

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