A power converter and a control method thereof

Abstract

The present application relates to the technical field of power electronics, in particular to a power converter and a control method thereof, the power converter is suitable for the application scene of outputting stable voltage according to wide range of input voltage, the conduction state of each switch is controlled according to the duty cycle of the power converter in a specific time region to avoid the generation of reverse current, while reducing the generation of thermal energy, the stability of the circuit and the conversion efficiency of the power converter can also be improved, secondly, the voltage value of the input voltage can be shared by setting the first capacitor Cb1 and the second capacitor Cb2, so that the duty cycle of all switches can be doubled, and the voltage stress of all switches and the setting difficulty of the corresponding control signal are further reduced.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a power converter and its control method. Background Technology

[0002] As a core component in the development of social technology, power converters require, at the technical level, reduced losses to achieve high efficiency and high power density. Currently, in many applications, there is a frequent need to convert 54V to 12V, highlighting the growing importance of this requirement. For example, in some industrial automation equipment and certain modules of communication base stations, the conversion efficiency and power density of 54V to 12V directly affect the performance, stability, and energy consumption of the equipment.

[0003] For wide-range input voltages, existing buck power converters often struggle to maintain a stable output voltage. For example, when the input voltage is between 48V and 54V, a stable 12V output can be achieved by adjusting the buck power converter's duty cycle. However, when the input voltage is between 40V and 48V, conventional buck power converters cannot maintain a stable 12V output simply by adjusting the duty cycle. Specifically, when the input voltage is below 48V, the buck power converter's duty cycle will exceed 50% to maintain a stable 12V output. In this situation, when the switch in the buck power converter changes, the series voltage of the energy storage capacitors used to store and release energy is not equal to the voltage across the input capacitor. If the series voltage of the energy storage capacitors is greater than the voltage across the input capacitor, this voltage mismatch will cause a reverse current surge. Since the input capacitor attempts to maintain its charge when the voltage changes, a large instantaneous current is generated in the circuit. This reverse current surge not only affects the stability of the circuit but also reduces the efficiency of the power conversion circuit and generates heat, thus posing a safety hazard.

[0004] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. Summary of the Invention

[0005] The technical problem to be solved by this invention is how to achieve a stable output voltage of the power converter over a wide input voltage range and avoid generating reverse current.

[0006] The present invention adopts the following technical solution:

[0007] In a first aspect, a power converter is provided, comprising: a first bridge arm composed of multiple switches, a second bridge arm composed of multiple switches, a first capacitor Cb1, a second capacitor Cb2, and an inductor assembly.

[0008] One end of the first bridge arm is connected to the first input terminal Vin+ of the power converter, and the other end is connected to the second input terminal Vin-; one end of the second bridge arm is connected to the first input terminal Vin+ of the power converter, and the other end is connected to the second input terminal Vin-; an input capacitor Cin is provided between the first input terminal Vin+ and the second input terminal Vin-;

[0009] The first bridge arm has a second node and a third node, and the second bridge arm has a first node and a fourth node; the first node, the second node, the third node, and the fourth node are respectively located on the connecting line between two adjacent switches;

[0010] The first node is connected to one end of the first capacitor Cb1; the other end of the first capacitor Cb1 is connected to the second node; the third node is connected to one end of the second capacitor Cb2; the other end of the second capacitor Cb2 is connected to the fourth node; the second node and the fourth node are respectively connected to one end of the inductor assembly, and the other end of the inductor assembly is connected to the first output terminal Vout+ of the power converter;

[0011] Specifically, based on the duty cycle of the power converter, the conduction state of each switch is controlled within a specific time region to ensure that the first capacitor Cb1 and the second capacitor Cb2 do not form a circuit with the input capacitor Cin, or that the voltages across the first capacitor Cb1 and the second capacitor Cb2 are both lower than the voltages across the input capacitor Cin.

[0012] Preferably, the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4 are connected in sequence to form the first bridge arm, and the fifth switch Q5, the sixth switch Q6, the seventh switch Q7 and the eighth switch Q8 are connected in sequence to form the second bridge arm.

[0013] One end of the first switch Q1 and one end of the fifth switch Q5 are respectively connected to the first input terminal Vin+; one end of the fourth switch Q4 and one end of the eighth switch Q8 are respectively connected to the second input terminal Vin-.

[0014] The first node between the sixth switch Q6 and the seventh switch Q7 is connected to one end of the first capacitor Cb1; the other end of the first capacitor Cb1 is connected to the second node between the third switch Q3 and the fourth switch Q4.

[0015] The third node between the second switch Q2 and the third switch Q3 is connected to one end of the second capacitor Cb2; the other end of the second capacitor Cb2 is connected to the fourth node between the seventh switch Q7 and the eighth switch Q8.

[0016] The first switch Q1 and the fifth switch Q5 share a common source, the first switch Q1 and the second switch Q2 share a common drain, and the fifth switch Q5 and the sixth switch Q6 share a common drain.

[0017] Preferably, the first bridge arm is formed by connecting the second switch Q2, the first switch Q1, the third switch Q3 and the fourth switch Q4 in sequence, and the second bridge arm is formed by connecting the sixth switch Q6, the fifth switch Q5, the seventh switch Q7 and the eighth switch Q8 in sequence.

[0018] One end of the second switch Q2 and one end of the sixth switch Q6 are respectively connected to the first input terminal Vin+; one end of the fourth switch Q4 and one end of the eighth switch Q8 are respectively connected to the second input terminal Vin-.

[0019] The first node between the fifth switch Q5 and the seventh switch Q7 is connected to one end of the first capacitor Cb1; the other end of the first capacitor Cb1 is connected to the second node between the third switch Q3 and the fourth switch Q4.

[0020] The third node between the first switch Q1 and the third switch Q3 is connected to one end of the second capacitor Cb2; the other end of the second capacitor Cb2 is connected to the fourth node between the seventh switch Q7 and the eighth switch Q8.

[0021] The first switch Q1 and the second switch Q2 share a common source, and the fifth switch Q5 and the sixth switch Q6 share a common source.

[0022] Preferably, the power converter further includes a PWM control module, which is connected to the control terminals of the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the fifth switch Q5, the sixth switch Q6, the seventh switch Q7, and the eighth switch Q8, respectively.

[0023] The PWM control module is used to send corresponding PWM control signals to the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the fifth switch Q5, the sixth switch Q6, the seventh switch Q7 and the eighth switch Q8 respectively, so as to control the on / off state of each switch at different times.

[0024] Preferably, the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the fifth switch Q5, the sixth switch Q6, the seventh switch Q7, and the eighth switch Q8 have the same switching frequency.

[0025] Preferably, the power converter further includes an input inductor Lin, an output inductor Ls, and an output capacitor Cout; one end of the input inductor Lin is connected to the first input terminal Vin+ of the power converter, and the other end of the input inductor Lin is connected to one end of the input capacitor Cin, one end of the first switch Q1, and one end of the fifth switch Q5, respectively.

[0026] One end of the output inductor Ls is connected to the other end of the inductor assembly, and the other end of the output inductor Ls is connected to the first output terminal Vout+ of the power converter; one end of the output capacitor Cout is connected to the first output terminal Vout+ of the power converter, and the other end of the output capacitor Cout is connected to the second output terminal Vout- of the power converter.

[0027] Preferably, the inductor assembly is a discrete inductor, comprising a first inductor Lq1 and a second inductor Lq2; one end of the first inductor Lq1 is connected to the second node, and the other end of the first inductor Lq1 is connected to the first output terminal Vout+ of the power converter; one end of the second inductor Lq2 is connected to the fourth node, and the other end of the second inductor Lq2 is connected to the first output terminal Vout+ of the power converter.

[0028] Preferably, the inductor assembly is a coupled inductor, comprising a third inductor Lq1' and a fourth inductor Lq2'. One end of the third inductor Lq1' is connected to the second node, and the other end of the third inductor Lq1' is connected to the first output terminal Vout+ of the power converter. One end of the fourth inductor Lq2' is connected to the fourth node, and the other end of the fourth inductor Lq2' is connected to the first output terminal Vout+ of the power converter. The third inductor Lq1' and the fourth inductor Lq2' are wound on the same magnetic core assembly, and the polarities of the third inductor Lq1' and the fourth inductor Lq2' are opposite. The absolute value of the coupling coefficient between the third inductor Lq1' and the fourth inductor Lq2' ranges from 0 to 1.

[0029] In a second aspect, a control method for a power converter is provided, the control method being implemented in the power converter as described in the first aspect, comprising:

[0030] When the duty cycle of the power converter is less than or equal to a preset threshold, a first timing control diagram corresponding to each switch is constructed, and a corresponding PWM control signal is generated according to the first timing control diagram to control the closing or opening of each switch; wherein, the first switch Q1 and the fifth switch Q5 remain in the on state;

[0031] When the duty cycle of the power converter is greater than a preset threshold, a second timing control diagram is constructed for each switch, and a corresponding PWM control signal is generated according to the second timing control diagram to control the closing or opening of each switch; wherein, during the time period when a reverse current surge occurs, the first switch Q1 or the fifth switch Q5 is controlled to open to avoid the generation of reverse current.

[0032] Preferably, the first bridge arm includes a first switch Q1, a second switch Q2, a third switch Q3, and a fourth switch Q4, and the second bridge arm includes a fifth switch Q5, a sixth switch Q6, a seventh switch Q7, and an eighth switch Q8, in the first timing control diagram:

[0033] The sixth control signal on the sixth switch Q6 is in phase with the third control signal on the third switch Q3; the second control signal on the second switch Q2 is in phase with the seventh control signal on the seventh switch Q7; the sixth control signal on the sixth switch Q6 is phase-shifted by 180 degrees with the fourth control signal on the fourth switch Q4; the second control signal on the second switch Q2 is phase-shifted by 180 degrees with the eighth control signal on the eighth switch Q8; the sixth control signal on the sixth switch Q6 is phase-shifted by 180 degrees with the second control signal on the second switch Q2; the fourth control signal on the fourth switch Q4 is phase-shifted by 180 degrees with the eighth control signal on the eighth switch Q8; the first switch Q1 and the fifth switch Q5 remain in the on state.

[0034] Preferably, the first bridge arm includes a first switch Q1, a second switch Q2, a third switch Q3, and a fourth switch Q4, and the second bridge arm includes a fifth switch Q5, a sixth switch Q6, a seventh switch Q7, and an eighth switch Q8, in the second timing control diagram:

[0035] The seventh control signal on the seventh switch Q7 is in phase with the fourth control signal on the fourth switch Q4; the third control signal on the third switch Q3 is in phase with the eighth control signal on the eighth switch Q8; the sixth control signal on the sixth switch Q6 is 180 degrees phase-shifted with the seventh control signal on the seventh switch Q7; the seventh control signal on the seventh switch Q7 is also 180 degrees phase-shifted with the third control signal on the third switch Q3; the third control signal on the third switch Q3 is 180 degrees phase-shifted with the second control signal on the second switch Q2.

[0036] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0037] The power converter proposed in this invention can output a stable voltage based on a wide range of input voltages, making it suitable for applications requiring low-stability voltage outputs based on a wide range of input voltages. By controlling the conduction state of each switch within a specific time region according to the duty cycle of the power converter, reverse current generation can be avoided. This reduces heat generation while improving circuit stability and power converter conversion efficiency. Furthermore, by setting the first capacitor Cb1 and the second capacitor Cb2 to share the input voltage value, the duty cycle of all switches can be doubled, further reducing the voltage stress on all switches and the difficulty of setting the corresponding control signals. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of a power converter with recoil current provided in an embodiment of the present invention;

[0040] Figure 1a This is a waveform diagram of a recoil current provided in an embodiment of the present invention;

[0041] Figure 2 This is a schematic diagram of a specific structure of a power converter provided in an embodiment of the present invention;

[0042] Figure 2a This is a schematic diagram of another power converter provided in an embodiment of the present invention;

[0043] Figure 2b This is a schematic diagram of the drive power supply and drive circuit of a power converter provided in an embodiment of the present invention;

[0044] Figure 2c This is a schematic diagram of the drive power supply and drive circuit of another power converter provided in an embodiment of the present invention;

[0045] Figure 2d This is a waveform diagram of an embodiment of the present invention that does not generate a backflush current;

[0046] Figure 3 This is another specific structural schematic diagram of a power converter provided in an embodiment of the present invention;

[0047] Figure 4 This is a flowchart illustrating a control method for a power converter provided in an embodiment of the present invention;

[0048] Figure 5 This is a switching control timing diagram of a power converter with a duty cycle of less than or equal to 50%, provided by an embodiment of the present invention.

[0049] Figure 6 This is a switching control timing diagram of a power converter with a duty cycle greater than 50%, provided by an embodiment of the present invention.

[0050] Figure 7 This is one of the embodiments provided by the present invention. Figure 5 The switching control timing diagram is a schematic diagram of the modal circuit within t0-t1;

[0051] Figure 8 This is one of the embodiments provided by the present invention. Figure 5 The switching control timing diagram is a schematic diagram of the modal circuit within t1-t2;

[0052] Figure 9 This is one of the embodiments provided by the present invention. Figure 5 The switching control timing diagram is a schematic diagram of the modal circuit within t2-t3;

[0053] Figure 10 This is one of the embodiments provided by the present invention. Figure 5 The switching control timing diagram is a schematic diagram of the modal circuit within t3-t4;

[0054] Figure 11 This is one of the embodiments provided by the present invention. Figure 5 The switching control timing diagram is a schematic diagram of the modal circuit within t4-t5;

[0055] Figure 12 This is one of the embodiments provided by the present invention. Figure 5 The switching control timing diagram is a schematic diagram of the modal circuit within t5-t6;

[0056] Figure 13 This is one of the embodiments provided by the present invention. Figure 5 The switching control timing diagram is a schematic diagram of the modal circuit within t6-t7;

[0057] Figure 14 This is one of the embodiments provided by the present invention. Figure 5 The switching control timing diagram is a schematic diagram of the modal circuit within t7-t8;

[0058] Figure 15 This is one of the embodiments provided by the present invention. Figure 6 The switching control timing diagram is a schematic diagram of the modal circuit within t0-t1;

[0059] Figure 16 This is one of the embodiments provided by the present invention. Figure 6 The switching control timing diagram is a schematic diagram of the modal circuit within t1-t2;

[0060] Figure 17 This is one of the embodiments provided by the present invention. Figure 6 The switching control timing diagram is a schematic diagram of the modal circuit within t2-t3;

[0061] Figure 18 This is one of the embodiments provided by the present invention. Figure 6 The switching control timing diagram is a schematic diagram of the modal circuit within t3-t4;

[0062] Figure 19 This is one of the embodiments provided by the present invention. Figure 6 The switching control timing diagram is a schematic diagram of the modal circuit within t4-t5;

[0063] Figure 20 This is one of the embodiments provided by the present invention. Figure 6 The switching control timing diagram is a schematic diagram of the modal circuit within t5-t6;

[0064] Figure 21 This is one of the embodiments provided by the present invention. Figure 6 The switching control timing diagram is a schematic diagram of the modal circuit within t6-t7;

[0065] Figure 22 This is one of the embodiments provided by the present invention. Figure 6 The switching control timing diagram is a schematic diagram of the modal circuit within t7-t8;

[0066] Figure 23 This is one of the embodiments provided by the present invention. Figure 6 The switching control timing diagram is a schematic diagram of the modal circuit within t8-t9;

[0067] Figure 24 This is one of the embodiments provided by the present invention. Figure 6 The switching control timing diagram is a schematic diagram of the modal circuit within t9-t10. Detailed Implementation

[0068] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0069] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as openly inclusive, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples; that is, although they may be incorporated into embodiments or examples using the above terms for reasons such as order and position, it does not limit them to be incorporated in combination by a single embodiment or example.

[0070] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, for example, the description may use the prefix "A" or "B" to describe the same type of nouns as two independent entities. In this case, the corresponding features defined with "A" and "B" are used only to distinguish between similar entities and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0071] In describing some embodiments, the terms "coupled," "coupled," and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "connected" or "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other, such as "optical coupling," "wireless connection," etc. The embodiments disclosed herein are not necessarily limited to the scope of this invention.

[0072] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0073] Example 1:

[0074] Before providing a detailed description of the power converter proposed in this invention, this embodiment first presents a buck power converter, such as... Figure 1 As shown, this buck converter can convert a 54V input voltage to a stable 12V output voltage. Compared with traditional buck circuits, its duty cycle can be doubled, allowing for more efficient voltage conversion within the same timeframe. Secondly, this buck converter significantly reduces the effective value of the current, thereby reducing energy loss in the circuit. Simultaneously, the stress on the power switches in the circuit is also significantly reduced, extending the lifespan of the power switching components and improving the overall reliability of the circuit. It is worth noting that... Figure 1 The reference numerals in this document are for illustrative purposes only and do not conflict with the reference numerals in the accompanying drawings in the following embodiments.

[0075] The applicant discovered through research that for a wide range of input voltages, the buck power converter often struggles to maintain a stable output voltage. For example, when the input voltage fluctuates between 48V and 54V, a stable 12V output can be achieved by adjusting the buck power converter's duty cycle. However, when the input voltage fluctuates between 40V and 48V, conventional buck power converters can no longer achieve a stable 12V output by adjusting the duty cycle. Specifically, when the input voltage is below 48V, the buck power converter's duty cycle will exceed 50% to maintain a stable 12V output. In this case, when the switch in the buck power converter is switched, the series voltage of the energy storage capacitors used to store and release energy is not equal to the voltage across the input capacitor. If the series voltage of the energy storage capacitors is greater than the voltage across the input capacitor, this voltage mismatch will cause a reverse current surge. Since the input capacitor attempts to maintain its charge when the voltage changes, a large instantaneous current is generated in the circuit. In one embodiment, such as... Figure 1a As shown, the horizontal axis represents time, and the vertical axis represents the current value of capacitor cb1 or capacitor cb2. The waveform of the backflow current is displayed within the dashed box. This backflow current not only affects the stability of the circuit but also reduces the efficiency of the power conversion circuit and generates heat, thus posing a safety hazard.

[0076] To address the issue of backflow current generated by the aforementioned buck converter during the process of outputting a stable voltage based on a wide range of input voltages, which affects circuit stability, this embodiment proposes another power converter.

[0077] In one embodiment, the system includes: a first bridge arm composed of multiple switches, a second bridge arm composed of multiple switches, a first capacitor Cb1, a second capacitor Cb2, and an inductor assembly; one end of the first bridge arm is connected to the first input terminal Vin+ of the power converter, and the other end is connected to the second input terminal Vin-; one end of the second bridge arm is connected to the first input terminal Vin+ of the power converter, and the other end is connected to the second input terminal Vin-; an input capacitor Cin is disposed between the first input terminal Vin+ and the second input terminal Vin-; the first bridge arm has a second node (denoted by B) and a third node (denoted by C), the second... The bridge arm has a first node (denoted by A) and a fourth node (denoted by D); the first node, the second node, the third node, and the fourth node are respectively located on the connection line between two adjacent switches; the first node is connected to one end of the first capacitor Cb1; the other end of the first capacitor Cb1 is connected to the second node; the third node is connected to one end of the second capacitor Cb2; the other end of the second capacitor Cb2 is connected to the fourth node; the second node and the fourth node are respectively connected to one end of the inductor assembly, and the other end of the inductor assembly is connected to the first output terminal Vout+ of the power converter.

[0078] Specifically, based on the duty cycle of the power converter, the conduction state of each switch is controlled within a specific time region to ensure that the first capacitor Cb1 and the second capacitor Cb2 do not form a circuit with the input capacitor Cin, or that the voltages across the first capacitor Cb1 and the second capacitor Cb2 are both lower than the voltages across the input capacitor Cin.

[0079] Based on the connection relationship between the switches, this embodiment proposes at least two circuit structures for power converters. In one embodiment, the circuit structure of the first power converter is as follows: Figure 2As shown, the bridge includes: a first switch Q1, a second switch Q2, a third switch Q3, and a fourth switch Q4 connected in sequence to form a first bridge arm; a fifth switch Q5, a sixth switch Q6, a seventh switch Q7, and an eighth switch Q8 connected in sequence to form a second bridge arm; one end of the first switch Q1 and one end of the fifth switch Q5 are respectively connected to the first input terminal Vin+; one end of the fourth switch Q4 and one end of the eighth switch Q8 are respectively connected to the second input terminal Vin-; a first node between the sixth switch Q6 and the seventh switch Q7 is connected to one end of the first capacitor Cb1; the other end of the first capacitor Cb1 is connected to a second node between the third switch Q3 and the fourth switch Q4; a third node between the second switch Q2 and the third switch Q3 is connected to one end of the second capacitor Cb2; the other end of the second capacitor Cb2 is connected to a fourth node between the seventh switch Q7 and the eighth switch Q8; the first switch Q1 and the fifth switch Q5 share a common source, the first switch Q1 and the second switch Q2 share a common drain, and the fifth switch Q5 and the sixth switch Q6 share a common drain.

[0080] In one embodiment, the circuit structure of the second power converter is as follows: Figure 2a As shown, the bridge includes: a second switch Q2, a first switch Q1, a third switch Q3, and a fourth switch Q4 connected in sequence to form a first bridge arm; a sixth switch Q6, a fifth switch Q5, a seventh switch Q7, and an eighth switch Q8 connected in sequence to form a second bridge arm; one end of the second switch Q2 and one end of the sixth switch Q6 are respectively connected to the first input terminal Vin+; one end of the fourth switch Q4 and one end of the eighth switch Q8 are respectively connected to the second input terminal Vin-; a first node between the fifth switch Q5 and the seventh switch Q7 is connected to one end of the first capacitor Cb1; the other end of the first capacitor Cb1 is connected to a second node between the third switch Q3 and the fourth switch Q4; a third node between the first switch Q1 and the third switch Q3 is connected to one end of the second capacitor Cb2; the other end of the second capacitor Cb2 is connected to a fourth node between the seventh switch Q7 and the eighth switch Q8; the first switch Q1 and the second switch Q2 share a common source, and the fifth switch Q5 and the sixth switch Q6 share a common source.

[0081] In this embodiment, when the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the fifth switch Q5, the sixth switch Q6, the seventh switch Q7, and the eighth switch Q8 are all MOS switches, and all MOS switches are N-type MOS switches (the same applies to P-type MOS switches, which will not be discussed in detail in this embodiment), each switch has a corresponding PWM control module. The PWM control module is connected to the gate and source of the MOS switch. The PWM control module includes a drive circuit (represented by Driver) and a drive power supply (represented by VCC). The drive power supply is used to provide energy to the drive circuit, and the drive circuit is used to provide drive signals to the MOS switches (first switch Q1 to eighth switch Q8). When multiple MOS switches are connected with a common source, multiple drive circuits can share the same drive power supply to provide drive signals to multiple MOS switches.

[0082] In one embodiment, refer to Figure 2 and Figure 2b It can be seen that the first switch Q1 and the fifth switch Q5 share a common source, the first switch Q1 and the second switch Q2 share a common drain, and the fifth switch Q5 and the sixth switch Q6 share a common drain. At this time, the second switch Q2 uses a single drive power supply VCC1, the third switch Q3 uses a single drive power supply VCC2, the sixth switch Q6 uses a single drive power supply VCC3, the seventh switch Q7 uses a single drive power supply VCC4, the fourth switch Q4 and the eighth switch Q8 share the same drive power supply VCC5, and the first switch Q1 and the fifth switch Q5 share the same drive power supply VCC6. Figure 2b It can be seen that the circuit structure of the first type of power converter uses a total of 6 driving power supplies.

[0083] In one embodiment, such as Figure 2a and Figure 2c As shown, the first switch Q1 and the second switch Q2 share a common source, and the fifth switch Q5 and the sixth switch Q6 share a common source. In this case, the first switch Q1 and the second switch Q2 share the same driving power supply VCC1, the third switch Q3 uses its own driving power supply VCC2, the fifth switch Q5 and the sixth switch Q6 share the same driving power supply VCC3, the seventh switch Q7 uses its own driving power supply VCC4, and the fourth switch Q4 and the eighth switch Q8 share the same driving power supply VCC5. Figure 2c It can be seen that a total of 5 driving power supplies are used.

[0084] In conclusion, compared to Figure 2 The circuit structure of the first power converter shown is as follows: Figure 2a The circuit structure of the second power converter shown uses one less drive power supply. Saving the number of drive power supplies simplifies circuit design, reduces product costs, and increases power density.

[0085] The following embodiments will further illustrate the power converter using the circuit structure of the first type of power converter. In one embodiment, such as Figure 2 As shown, it includes: a first bridge arm consisting of a first switch Q1, a second switch Q2, a third switch Q3 and a fourth switch Q4 connected in sequence; a second bridge arm consisting of a fifth switch Q5, a sixth switch Q6, a seventh switch Q7 and an eighth switch Q8 connected in sequence; a first capacitor Cb1; a second capacitor Cb2; and an inductor assembly.

[0086] One end of the first switch Q1 and one end of the fifth switch Q5 are respectively connected to the first input terminal Vin+ of the power converter; one end of the fourth switch Q4 and one end of the eighth switch Q8 are respectively connected to the second input terminal Vin- of the power converter; an input capacitor Cin is provided between the first input terminal Vin+ and the second input terminal Vin-.

[0087] The first node (represented by A in the figure) between the sixth switch Q6 and the seventh switch Q7 is connected to one end of the first capacitor Cb1; the other end of the first capacitor Cb1 is connected to the second node (represented by B in the figure) between the third switch Q3 and the fourth switch Q4; the third node (represented by C in the figure) between the second switch Q2 and the third switch Q3 is connected to one end of the second capacitor Cb2; the other end of the second capacitor Cb2 is connected to the fourth node (represented by D in the figure) between the seventh switch Q7 and the eighth switch Q8; the second node and the fourth node are respectively connected to one end of the inductor assembly, and the other end of the inductor assembly is connected to the first output terminal Vout+ of the power converter.

[0088] In practical applications, based on the duty cycle of the power converter, the conduction state of each switch is controlled within a specific time region to ensure that the first capacitor Cb1 and the second capacitor Cb2 do not form a circuit with the input capacitor Cin, or that the voltages across the first capacitor Cb1 and the second capacitor Cb2 are both lower than the voltage across the input capacitor Cin, thereby avoiding backflow current. In one embodiment, such as... Figure 2d As shown, the horizontal axis represents time, and the vertical axis represents... Figure 2 or Figure 2a The current value of the first capacitor Cb1 or the second capacitor Cb2 in the circuit structure of the power converter shown is compared to Figure 1a If the recoil current disappears, it proves that this embodiment can effectively eliminate the recoil voltage and maintain the stability of the power converter. For a more specific implementation process, please refer to the following embodiment.

[0089] In one embodiment, when the duty cycle of the power converter is less than or equal to a preset threshold, a first timing control diagram corresponding to each switch is constructed, and a corresponding PWM control signal is generated according to the first timing control diagram to control the off or on state of each switch; wherein, the first switch Q1 and the fifth switch Q5 remain on. When the duty cycle of the power converter is greater than the preset threshold, a second timing control diagram corresponding to each switch is constructed, and a corresponding PWM control signal is generated according to the second timing control diagram to control the off or on state of each switch; wherein, during the period when a reverse current surge occurs, the first switch Q1 or the fifth switch Q5 is controlled to be on to avoid the generation of reverse current. A more specific control method will be described in detail in Embodiment 2.

[0090] The second input terminal Vin- and the second output terminal Vout- of the power converter are grounded terminals.

[0091] In one embodiment, refer to Figure 2 The input voltage Vin is a wide-range input voltage provided by the back-end circuit, ranging from 40V to 60V (i.e., 40V, 60V, or any value between 40V and 60V). The output voltage Vout is a stable voltage provided to the electrical load, ranging from 10V to 15V (i.e., 10V, 15V, or any value between 10V and 15V). The first capacitor Cb1 and the second capacitor Cb2 share the input voltage Vin, allowing the duty cycle of all switching power components in the power converter to be doubled, further reducing the voltage stress on all switching power components and the difficulty of setting the corresponding control signals.

[0092] In one embodiment, the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the fifth switch Q5, the sixth switch Q6, the seventh switch Q7, and the eighth switch Q8 are all MOSFETs or transistors.

[0093] Reference Figure 2When the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the fifth switch Q5, the sixth switch Q6, the seventh switch Q7, and the eighth switch Q8 are all MOSFETs, the source of the first switch Q1 is connected to the first input terminal Vin+ of the power converter, the drain of the first switch Q1 is connected to the drain of the second switch Q2, the source of the second switch Q2 is connected to the drain of the third switch Q3, the source of the third switch Q3 is connected to the drain of the fourth switch Q4, and the fourth switch Q4... The sources of the five switches are connected to the second input terminal Vin- and the second output terminal of the power converter, respectively. The source of the fifth switch Q5 is connected to the first input terminal Vin+ of the power converter. The drain of the fifth switch Q5 is connected to the drain of the sixth switch Q6. The source of the sixth switch Q6 is connected to the drain of the seventh switch Q7. The source of the seventh switch Q7 is connected to the drain of the eighth switch Q8. The source of the eighth switch Q8 is connected to the second input terminal Vin- and the second output terminal of the power converter, respectively.

[0094] In one embodiment, the power converter further includes a PWM control module (not shown in the figure). The PWM control module is connected to the control terminals (i.e., the gates of each switch) of the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the fifth switch Q5, the sixth switch Q6, the seventh switch Q7, and the eighth switch Q8, respectively. The PWM control module is used to send corresponding PWM control signals to the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the fifth switch Q5, the sixth switch Q6, the seventh switch Q7, and the eighth switch Q8, respectively, to control the on / off state of each switch at different times.

[0095] In one embodiment, such as Figure 2 As shown, the power converter also includes an input inductor Lin, an output inductor Ls, and an output capacitor Cout; one end of the input inductor Lin is connected to the first input terminal Vin+ of the power converter, and the other end of the input inductor Lin is connected to one end of the input capacitor Cin, one end of the first switch Q1, and one end of the fifth switch Q5, respectively.

[0096] One end of the output inductor Ls is connected to the other end of the inductor assembly, and the other end of the output inductor Ls is connected to the first output terminal Vout+ of the power converter; one end of the output capacitor Cout is connected to the first output terminal Vout+ of the power converter, and the other end of the output capacitor Cout is connected to the second output terminal Vout- of the power converter.

[0097] The input inductor Lin, the input capacitor Cin, the output inductor Ls, and the output capacitor Cout are used to smooth the input voltage or current, the output voltage or current, and for energy storage and filtering, respectively. The specific implementation principles are not detailed in this embodiment.

[0098] In one embodiment, the inductor component is a discrete inductor or a coupled inductor; such as Figure 2 As shown, the inductor assembly is a discrete inductor, comprising a first inductor Lq1 and a second inductor Lq2; one end of the first inductor Lq1 is connected to the second node, and the other end of the first inductor Lq1 is connected to the first output terminal Vout+ of the power converter; one end of the second inductor Lq2 is connected to the fourth node, and the other end of the second inductor Lq2 is connected to the first output terminal Vout+ of the power converter.

[0099] In this configuration, as discrete inductors, the first inductor Lq1 and the second inductor Lq2 operate independently, primarily responsible for energy storage and filtering, as well as providing a continuous current path during switching to reduce current surges and thus lower electromagnetic interference. Discrete inductors offer greater flexibility and design freedom, allowing optimization for different application needs. They can be independently selected to meet specific current and voltage requirements and are easy to heat dissipate and integrate.

[0100] In one embodiment, such as Figure 3 As shown, the inductor assembly is a coupled inductor, comprising a third inductor Lq1' and a fourth inductor Lq2'. One end of the third inductor Lq1' is connected to the second node, and the other end of the third inductor Lq1' is connected to the first output terminal Vout+ of the power converter. One end of the fourth inductor Lq2' is connected to the fourth node, and the other end of the fourth inductor Lq2' is connected to the first output terminal Vout+ of the power converter. The third inductor Lq1' and the fourth inductor Lq2' are wound on the same magnetic core assembly, and the polarities of the third inductor Lq1' and the fourth inductor Lq2' are opposite. The absolute value of the coupling coefficient between the third inductor Lq1' and the fourth inductor Lq2' ranges from 0 to 1.

[0101] The switching on and off of the switch causes the inductor component to be in a charging or discharging state, thereby achieving the voltage reduction function. The specific implementation principle will not be explained in detail in this embodiment.

[0102] Reference Figure 3 The first end of the third inductor Lq1' has the opposite polarity to the first end of the fourth inductor Lq2', meaning the second end of the third inductor Lq1' has the same polarity as the fourth inductor Lq2' (both are indicated by black dots). In one embodiment, the third inductor Lq1' and the fourth inductor Lq2' can be wound on the same magnetic core assembly to form a coupled inductor. The higher the absolute value of the coupling coefficient, the tighter the magnetic coupling between the two inductors, the less magnetic flux leakage, and the higher the energy transfer efficiency. For coupled inductors, the absolute value of the coupling coefficient needs to satisfy the following relationship: when the coupling coefficient is close to 1, the magnetic coupling between the two inductors is the strongest, meaning that the magnetic flux between the third inductor Lq1' and the fourth inductor Lq2' almost completely passes through each other's magnetic core, thereby achieving efficient magnetic energy conversion. Coupled inductors achieve mutual coupling of magnetic flux by sharing a magnetic core, which can more effectively utilize the magnetic core material and improve energy conversion efficiency. Coupled inductors can reduce the required magnetic core material, thereby reducing volume and weight, while improving the utilization efficiency of magnetic energy.

[0103] In one embodiment, the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the fifth switch Q5, the sixth switch Q6, the seventh switch Q7, and the eighth switch Q8 have the same switching frequency.

[0104] When the duty cycle of the power converter is less than or equal to 50%, no reverse current surge will occur; therefore, the first switch Q1 and the fifth switch Q5 will remain on. When the duty cycle of the power converter is greater than 50%, relative to... Figure 1 The power converter shown, by adding the switching control of the first switch Q1 and the fifth switch Q5, keeps only one branch (the first or second bridge arm) in the conducting state during the period when current surges may occur, thus preventing reverse current surges. The specific implementation principle will be explained in detail in the following embodiments.

[0105] In one embodiment, the first switch Q1 and the fifth switch Q5 can be used as current control switches. Current control switches are respectively installed on the first bridge arm and the second bridge arm. This method has the following advantages compared to installing current control switches on the main road:

[0106] (1) Switching frequency: When the current control switch is set on the main line, its switching frequency will be twice that of the current control switches set on the two bridge arms. The higher switching frequency will bring more switching losses and higher requirements for the switching elements, which will shorten the service life of the elements. By setting the current control switch on the first and second bridge arms, excessively high switching frequencies are avoided, and switching losses and stress on the elements are reduced.

[0107] (2) Circuit stability: Stability is a crucial indicator in power converters. The current control switches on the bridge arms, by controlling their conduction state within specific time periods, ensure that no reverse current surges occur under different duty cycles, thus improving circuit stability. For example, when the duty cycle D is less than or equal to 50%, the first switch Q1 and the fifth switch Q5 will remain on, preventing reverse current surges during any time period. When the duty cycle D is greater than 50%, by increasing the switching control of the first switch Q1 and the fifth switch Q5, only one branch (the first or second bridge arm) is kept on during the period when a current surge occurs, effectively avoiding reverse current surges.

[0108] (3) Reduction of heat generation: Reduction of heat generation can be divided into two aspects: First, the switching losses of the switches are reduced due to the lower switching frequency, thus reducing the heat generation of individual switches. Second, by distributing the switches on the main circuit to the branch circuits, the original drive losses of the switches are distributed to the two drivers on the two branch circuits. This significantly reduces the heat generation of the switch drivers. Higher switching frequencies lead to more heat generation, which not only reduces the conversion efficiency of the power converter but also affects the safety and reliability of the circuit. Placing the current control switch on the first and second bridge arms, due to the lower switching frequency, can reduce the heat generation of the power converter and improve the safety of power converter operation.

[0109] In summary, placing the current control switch on the first and second bridge arms has advantages over placing it on the main line, such as lower switching frequency, simpler control, higher circuit stability, and less heat generation.

[0110] The power converter proposed in this embodiment can output a stable voltage based on a wide range of input voltages, making it suitable for applications requiring low-stability voltage outputs based on a wide range of input voltages. By controlling the conduction state of each switch within a specific time region based on the power converter's duty cycle, reverse current generation is avoided. This reduces heat generation while improving circuit stability and power converter conversion efficiency. Furthermore, by setting the first capacitor Cb1 and the second capacitor Cb2 to share the input voltage, the duty cycle of all switches can be doubled, further reducing the voltage stress on all switches and the difficulty of setting their corresponding control signals.

[0111] Example 2:

[0112] In Example 1, a power converter was proposed. In this example, a control method for the power converter will be proposed, such as... Figure 4 As shown, it includes:

[0113] Step 101: When the duty cycle of the power converter is less than or equal to a preset threshold, construct a first timing control diagram for each switch, and generate a corresponding PWM control signal according to the first timing control diagram to control the closing or opening of each switch; wherein, the first switch Q1 and the fifth switch Q5 remain in the on state.

[0114] In one embodiment, such as Figure 5 As shown, in the first timing control diagram: the sixth control signal on the sixth switch Q6 is in phase with the third control signal on the third switch Q3; the second control signal on the second switch Q2 is in phase with the seventh control signal on the seventh switch Q7; the sixth control signal on the sixth switch Q6 is phase-shifted by 180 degrees with the fourth control signal on the fourth switch Q4; the second control signal on the second switch Q2 is phase-shifted by 180 degrees with the eighth control signal on the eighth switch Q8; the sixth control signal on the sixth switch Q6 is phase-shifted by 180 degrees with the second control signal on the second switch Q2; the fourth control signal on the fourth switch Q4 is phase-shifted by 180 degrees with the eighth control signal on the eighth switch Q8; the first switch Q1 and the fifth switch Q5 remain in the on state.

[0115] The preset threshold can be 50%. The first timing control diagram is designed based on the actual input voltage range and specific output voltage requirements. The switching on and off of the switch causes the inductor to be in a charging and discharging state, thus achieving the voltage reduction function. Within one switching cycle, when the switch is on, the inductor current rises linearly, storing energy; when the switch is off, the inductor freewheels through other switches, and the current decreases linearly, releasing energy. The charging and discharging process of the inductor and the energy transfer method determine the basic timing of each switch. Secondly, the first capacitor Cb1 and the second capacitor Cb2 in the circuit are used for filtering and stabilizing the output voltage. The charging and discharging process of the switch under different states is also closely related to the switching timing. When the switch is off, the capacitor discharges to the load to maintain the stability of the output voltage, requiring the switching timing to match the charging and discharging characteristics of the capacitor.

[0116] To achieve a stable output voltage based on different input voltages and avoid reverse current, precise control of the duty cycle of each switch is required. By controlling the duty cycle, the charging and discharging times of the inductor can be adjusted, thereby controlling the output voltage. Based on the preset output voltage and the actual input voltage, the control circuit calculates a suitable duty cycle and generates a timing diagram for the switches accordingly. By adjusting the pulse width of the PWM signal, i.e., the duty cycle, the turn-on and turn-off times of the switches can be controlled, thus obtaining a timing control diagram that meets the circuit requirements.

[0117] When the duty cycle of the power converter is less than or equal to 50%, according to the first timing control diagram, there will be no reverse current surge at any time. Therefore, both the first switch Q1 and the fifth switch Q5 will remain on (i.e., Figure 2 or Figure 3 The circuit diagram shown is equivalent to the following at this time: Figure 1 (The circuit diagram is shown). The specific state of each switch at each moment and the equivalent circuit will be explained in detail below.

[0118] Step 102: When the duty cycle of the power converter is greater than a preset threshold, construct a second timing control diagram for each switch, and generate a corresponding PWM control signal according to the second timing control diagram to control the closing or opening of each switch; wherein, during the time period when a reverse current surge occurs, control the first switch Q1 to open or the fifth switch Q5 to open to avoid the generation of reverse current.

[0119] In one embodiment, such as Figure 6As shown, in the second timing control diagram: the seventh control signal on the seventh switch Q7 is in phase with the fourth control signal on the fourth switch Q4; the third control signal on the third switch Q3 is in phase with the eighth control signal on the eighth switch Q8; the sixth control signal on the sixth switch Q6 is phase-shifted by 180 degrees with the seventh control signal on the seventh switch Q7; the seventh control signal on the seventh switch Q7 is also phase-shifted by 180 degrees with the third control signal on the third switch Q3; the third control signal on the third switch Q3 is phase-shifted by 180 degrees with the second control signal on the second switch Q2.

[0120] When the duty cycle of the power converter is greater than 50%, compared to the power converter proposed in Example 1, due to the addition of the switching control of the first switch Q1 and the fifth switch Q5, only one branch (the first bridge arm or the second bridge arm) control switch is kept in the conducting state during the period when current surges may occur, thus preventing reverse current surges. The specific state of each switch at each moment and the equivalent circuit will be described in detail below.

[0121] It is worth noting that, in Figure 5 and Figure 6 In the process of switching between conduction states, to prevent simultaneous conduction of switches, a first dead time Td1 and a second dead time Td2 are set to reserve gap time for accurate switching between conduction states. For example, during the time period t0-t1, the third switch Q3 and the sixth switch Q6 are in the conduction state, and the fourth switch Q4 is in the off state; the time period t1-t2 is the aforementioned first dead time Td1; during the time period t2-t3, the third switch Q3 and the sixth switch Q6 are in the off state, and the fourth switch Q4 is in the conduction state.

[0122] The first dead time Td1 and the second dead time Td2 can be obtained based on experience. Specifically, they can be set according to different operating frequencies of the circuit, different switch models, and other conditions. More specific details will not be explained in this embodiment.

[0123] In one embodiment, after obtaining the first dead time Td1 and the second dead time Td2, the duty cycle D and the switching period Ts of the power converter are determined respectively, and the corresponding first timing control diagram (e.g.) can be obtained. Figure 5 (as shown) and the second timing control diagram (as shown) Figure 1 (As shown).

[0124] By combining the duty cycle, the first timing control diagram, and the second timing control diagram to control each switch, it is possible to ensure that the first capacitor Cb1 and the second capacitor Cb2 do not form a circuit with the input capacitor Cin, or that the voltages across the first capacitor Cb1 and the second capacitor Cb2 are both lower than the voltages across the input capacitor Cin, thereby avoiding the generation of reverse current.

[0125] In one embodiment, such as Figure 2 and Figure 5 As shown, the first control signal PWM1, the second control signal PWM2, the third control signal PWM3, the fourth control signal PWM4, the fifth control signal PWM5, the sixth control signal PWM6, the seventh control signal PWM7, and the eighth control signal PWM8 are used to control the conduction state of the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the fifth switch Q5, the sixth switch Q6, the seventh switch Q7, and the eighth switch Q8, respectively.

[0126] exist Figure 5 In the first timing control diagram, a switching cycle Ts can be divided into multiple time periods, specifically including t0-t1, t1-t2, t2-t3, t3-t4, t4-t5, t5-t6, t6-t7, and t7-t8. The modal circuit diagrams for each time period in chronological order are as follows: Figures 7 to 14 As shown.

[0127] Within a switching cycle Ts, taking t0 to t8 as an example, the time intervals t0-t1 and t4-t5 are equal to D*Ts, t1-t2, t3-t4, t5-t6, and t7-t8 are equal to Td1, t0-t4 is equal to 1 / 2*Ts, and t2-t7 is equal to (1-D)*Ts-2*Td1. The control signal levels for each time interval are as follows: Figure 5 As shown, a high level indicates that the corresponding switch is turned on, and a low level indicates that the corresponding switch is turned off.

[0128] To further illustrate the changes in the voltage across the first capacitor Cb1 and the second capacitor Cb2 after different combinations of control signals in each time period, as well as the impact on the output voltage Vout, please refer to the modal circuit diagrams for each time period from t0 to t8.

[0129] In one embodiment, Figure 7 for Figure 5 The first timing control diagram is the modal circuit diagram within t0-t1. (Reference) Figure 5 and Figure 7Within the range t0-t1, the sixth control signal PWM6, the third control signal PWM3, the eighth control signal PWM8, the fifth control signal PWM5, and the first control signal PWM1 are turn-on control signals (i.e., high level), while the second control signal PWM2, the sixth control signal PWM6, and the fourth control signal PWM4 are turn-off control signals (i.e., low level). In this mode, the first capacitor Cb1 receives half of the input voltage Vin, and the output voltage Vout satisfies Vout=1 / 2Vin*D. The voltage across the first capacitor Cb1 does not exceed the voltage across the input capacitor Cin, therefore no reverse surge current is generated.

[0130] In one embodiment, Figure 8 for Figure 5 The first timing control diagram is the modal circuit diagram within t1-t2. (Reference) Figure 5 and Figure 8 During the period t1-t2, the eighth control signal PWM8, the fifth control signal PWM5, and the first control signal PWM1 are the turn-on control signals, while the sixth control signal PWM6, the second control signal PWM2, the seventh control signal PWM7, the third control signal PWM3, and the fourth control signal PWM4 are the turn-off control signals. In this mode, the first capacitor Cb1 and the second capacitor Cb2 do not form a loop with the input capacitor Cin, so no reverse surge current will be generated.

[0131] In one embodiment, Figure 9 for Figure 5 The first timing control diagram is the modal circuit diagram within t2-t3. (Reference) Figure 5 and Figure 9 During the period t2-t3, the eighth control signal PWM8, the fourth control signal PWM4, the fifth control signal PWM5, and the first control signal PWM1 are the turn-on control signals, while the sixth control signal PWM6, the second control signal PWM2, the seventh control signal PWM7, and the third control signal PWM3 are the turn-off control signals. In this mode, the first capacitor Cb1 and the second capacitor Cb2 do not form a loop with the input capacitor Cin, so no reverse surge current will be generated.

[0132] In one embodiment, Figure 10 for Figure 5 The first timing control diagram is the modal circuit diagram within t3-t4. Please refer to it. Figure 5 and Figure 10During the period t3-t4, the fourth control signal PWM4, the fifth control signal PWM5, and the first control signal PWM1 are the turn-on control signals, while the sixth control signal PWM6, the second control signal PWM2, the seventh control signal PWM7, the third control signal PWM3, and the eighth control signal PWM8 are the turn-off control signals. In this mode, the first capacitor Cb1 and the second capacitor Cb2 do not form a loop with the input capacitor Cin, so no reverse surge current will be generated.

[0133] In one embodiment, Figure 11 for Figure 5 The first timing control diagram is the modal circuit diagram within t4-t5. Please refer to it. Figure 5 and Figure 11 During the period t4-t5, the second control signal PWM2, the seventh control signal PWM7, the fourth control signal PWM4, the fifth control signal PWM5, and the first control signal PWM1 are the turn-on control signals, while the sixth control signal PWM6, the third control signal PWM3, and the eighth control signal PWM8 are the turn-off control signals. In this mode, the second capacitor Cb2 receives half of the input voltage Vin, and the output voltage Vout satisfies Vout=1 / 2Vin*D. Since the voltage across the second capacitor Cb2 does not exceed the voltage across the input capacitor Cin, no reverse surge current will be generated.

[0134] In one embodiment, Figure 12 for Figure 5 The first timing control diagram is the modal circuit diagram within t5-t6. Please refer to it. Figure 5 and Figure 12 During the period t5-t6, the fourth control signal PWM4, the fifth control signal PWM5, and the first control signal PWM1 are the turn-on control signals, while the sixth control signal PWM6, the second control signal PWM2, the seventh control signal PWM7, the third control signal PWM3, and the eighth control signal PWM8 are the turn-off control signals. In this mode, the first capacitor Cb1 and the second capacitor Cb2 do not form a loop with the input capacitor Cin, so no reverse surge current will be generated.

[0135] In one embodiment, Figure 13 for Figure 5 The first timing control diagram is the modal circuit diagram within t6-t7. Please refer to it. Figure 5 and Figure 13During the period t6-t7, the eighth control signal PWM8, the fourth control signal PWM4, the fifth control signal PWM5, and the first control signal PWM1 are the turn-on control signals, while the sixth control signal PWM6, the second control signal PWM2, the seventh control signal PWM7, and the third control signal PWM3 are the turn-off control signals. In this mode, the first capacitor Cb1 and the second capacitor Cb2 do not form a loop with the input capacitor Cin, so no reverse surge current will be generated.

[0136] In one embodiment, Figure 14 for Figure 5 The first timing control diagram is the modal circuit diagram within t7-t8. Please refer to it. Figure 5 and Figure 14 Within t7-t8, the eighth control signal PWM8, the fifth control signal PWM5, and the first control signal PWM1 are the turn-on control signals, while the sixth control signal PWM6, the second control signal PWM2, the seventh control signal PWM7, the third control signal PWM3, and the fourth control signal PWM4 are the turn-off control signals. In this mode, the first capacitor Cb1 and the second capacitor Cb2 do not form a loop with the input capacitor Cin, so no reverse surge current will be generated.

[0137] In summary, based on the working principle of the modal circuit diagram during each time stage from t0 to t8, it can be seen that when the duty cycle D is less than or equal to 50%, there will be no reverse current surge.

[0138] exist Figure 6 In the second timing control diagram, a switching cycle Ts can be divided into multiple time periods, specifically including t0-t1, t1-t2, t2-t3, t3-t4, t4-t5, t5-t6, t6-t7, t7-t8, t8-t9, and t9-t10. The modal circuit diagrams for each time period in chronological order are as follows: Figures 15 to 24 As shown.

[0139] Reference Figure 6 When the duty cycle D of the power converter is greater than 50%, take t0 to t10 as an example within one switching cycle Ts. The time occupied by t0-t6 and t4-t10 is equal to D*Ts, the time occupied by t1-t2, t4-t5, t6-t7 and t9-t10 is equal to Td1, the time occupied by t1-t3 and t6-t8 is equal to Td2, the time occupied by t0-t5 is equal to 1 / 2*Ts, and the time occupied by t6-t10 is equal to (1-D)*Ts-2*Td1.

[0140] To further illustrate the changes in the voltage across the first capacitor Cb1 and the second capacitor Cb2 after different combinations of control signals in each time period, as well as the impact on the output voltage Vout, please refer to the modal circuit diagrams for each time period from t0 to t10.

[0141] In one embodiment, Figure 15 for Figure 6 The second timing control diagram is the modal circuit diagram within t0-t1. Please refer to... Figure 6 and Figure 15 Within the range t0-t1, the sixth control signal PWM6, the second control signal PWM2, the fifth control signal PWM5, and the first control signal PWM1 are the turn-on control signals, while the seventh control signal PWM7, the third control signal PWM3, the eighth control signal PWM8, and the fourth control signal PWM4 are the turn-off control signals. In this mode, the first capacitor Cb1 and the second capacitor Cb2 each receive half of the input voltage Vin, and the output voltage Vout satisfies Vout=1 / 2Vin*D. The voltages across the first capacitor Cb1 and the second capacitor Cb2 do not exceed the voltage across the input capacitor Cin, so no reverse surge current will be generated.

[0142] Figure 16 for Figure 6 The second timing control diagram is the modal circuit diagram within t1-t2. Please refer to it. Figure 6 and Figure 16 During the period t1-t2, the sixth control signal PWM6 and the first control signal PWM1 are the turn-on control signals, while the second control signal PWM2, the seventh control signal PWM7, the third control signal PWM3, the eighth control signal PWM8, the fourth control signal PWM4, and the fifth control signal PWM5 are the turn-off control signals. In this mode, the first capacitor Cb1 receives half of the input voltage Vin, and the output voltage Vout satisfies Vout=1 / 2Vin*D. The voltage across the first capacitor Cb1 does not exceed the voltage across the input capacitor Cin, so no reverse surge current will be generated.

[0143] Figure 17 for Figure 6 The second timing control diagram is the modal circuit diagram within t2-t3. Please refer to it. Figure 6 and Figure 17During the period t2-t3, the sixth control signal PWM6, the third control signal PWM3, the eighth control signal PWM8, and the first control signal PWM1 are the turn-on control signals, while the second control signal PWM2, the seventh control signal PWM7, the fourth control signal PWM4, and the fifth control signal PWM5 are the turn-off control signals. In this mode, the first capacitor Cb1 receives half of the input voltage Vin, and the output voltage Vout satisfies Vout=1 / 2Vin*D. The voltage across the first capacitor Cb1 does not exceed the voltage across the input capacitor Cin, so no reverse surge current is generated.

[0144] Figure 18 for Figure 6 The second timing control diagram is the modal circuit diagram within t3-t4. Please refer to it. Figure 6 and Figure 18 During the period t3-t4, the sixth control signal PWM6, the third control signal PWM3, the eighth control signal PWM8, the fifth control signal PWM5, and the first control signal PWM1 are the turn-on control signals, while the second control signal PWM2, the seventh control signal PWM7, and the fourth control signal PWM4 are the turn-off control signals. In this mode, the first capacitor Cb1 receives half of the input voltage Vin, and the output voltage Vout satisfies Vout=1 / 2Vin*D. The voltage across the first capacitor Cb1 does not exceed the voltage across the input capacitor Cin, so no reverse surge current is generated.

[0145] Figure 19 for Figure 6 The second timing control diagram is the modal circuit diagram within t4-t5. Please refer to it. Figure 6 and Figure 19 During the period t4-t5, the sixth control signal PWM6, the fifth control signal PWM5, and the first control signal PWM1 are the turn-on control signals, while the second control signal PWM2, the seventh control signal PWM7, the third control signal PWM3, the eighth control signal PWM8, and the fourth control signal PWM4 are the turn-off control signals. In this mode, the first capacitor Cb1 receives half of the input voltage Vin, and the output voltage Vout satisfies Vout=1 / 2Vin*D. The voltage across the first capacitor Cb1 does not exceed the voltage across the input capacitor Cin, so no reverse surge current is generated.

[0146] Figure 20 for Figure 6 The second timing control diagram is the modal circuit diagram within t5-t6. Please refer to it. Figure 6 and Figure 20Within t5-6, the sixth control signal PWM6, the second control signal PWM2, the fifth control signal PWM5, and the first control signal PWM1 are the turn-on control signals, while the seventh control signal PWM7, the third control signal PWM3, the eighth control signal PWM8, and the fourth control signal PWM4 are the turn-off control signals. In this mode, the first capacitor Cb1 and the second capacitor Cb2 each receive half of the input voltage Vin, and the output voltage Vout satisfies Vout=1 / 2Vin*D. The voltages across the first capacitor Cb1 and the second capacitor Cb2 do not exceed the voltage across the input capacitor Cin, so no reverse surge current will be generated.

[0147] Figure 21 for Figure 6 The second timing control diagram is the modal circuit diagram within t6-t7. Please refer to it. Figure 6 and Figure 21 During the period t6-t7, the second control signal PWM2 and the fifth control signal PWM5 are the turn-on control signals, while the sixth control signal PWM6, the seventh control signal PWM7, the third control signal PWM3, the eighth control signal PWM8, the fourth control signal PWM4, and the first control signal PWM1 are the turn-off control signals. In this mode, the second capacitor Cb2 receives half of the input voltage Vin, and the output voltage Vout satisfies Vout=1 / 2Vin*D. The voltage across the second capacitor Cb2 does not exceed the voltage across the input capacitor Cin, so no reverse surge current is generated.

[0148] Figure 22 for Figure 6 The second timing control diagram is the modal circuit diagram within t7-t8. Please refer to it. Figure 6 and Figure 22 During the period t7-t8, the second control signal PWM2, the seventh control signal PWM7, the fourth control signal PWM4, and the fifth control signal PWM5 are the turn-on control signals, while the sixth control signal PW6, the third control signal PWM3, the eighth control signal PWM8, and the first control signal PWM1 are the turn-off control signals. In this mode, the second capacitor Cb2 receives half of the input voltage Vin, and the output voltage Vout satisfies Vout=1 / 2Vin*D. The voltage across the second capacitor Cb2 does not exceed the voltage across the input capacitor Cin, so no reverse surge current is generated.

[0149] Figure 23 for Figure 6 The second timing control diagram is the modal circuit diagram within t8-t9. Please refer to it. Figure 6 and Figure 23Within t8-t9, the second control signal PWM2, the seventh control signal PWM7, the fourth control signal PWM4, the fifth control signal PWM5, and the first control signal PWM1 are the turn-on control signals, while the sixth control signal PWM6, the third control signal PWM3, and the eighth control signal PWM8 are the turn-off control signals. In this mode, the second capacitor Cb2 receives half of the input voltage Vin, and the output voltage Vout satisfies Vout=1 / 2Vin*D. The voltage across the second capacitor Cb2 does not exceed the voltage across the input capacitor Cin, therefore no reverse surge current will be generated.

[0150] Figure 24 for Figure 6 The second timing control diagram is the modal circuit diagram within t9-t10. Please refer to it. Figure 3 and Figure 24 During the period t9-t10, the second control signal PWM2, the fifth control signal PWM5, and the first control signal PWM1 are the turn-on control signals, while the sixth control signal PWM6, the seventh control signal PWM7, the third control signal PWM3, the eighth control signal PWM8, and the fourth control signal PWM4 are the turn-off control signals. In this mode, the second capacitor Cb2 receives half of the input voltage Vin, and the output voltage Vout satisfies Vout=1 / 2Vin*D. The voltage across the first capacitor Cb1 does not exceed the voltage across the input capacitor Cin, so no reverse surge current is generated.

[0151] In summary, based on the working principle of the modal circuit diagram during each time period from t0 to t10, when the duty cycle D is greater than 50%, due to the addition of the switching control of the first switch Q1 and the fifth switch Q5, only one branch (the first or second bridge arm) is kept in the conducting state during the time period when current surges may occur (t1-t3 and t6-t8), thus preventing reverse current surges.

[0152] In summary, by setting the first switch Q1 and the fifth switch Q5, reverse current surges can be prevented; by avoiding the generation of reverse surge current, unnecessary energy loss is reduced. When the input voltage is below 48V and the duty cycle of the power converter is greater than 50%, reverse current can still be avoided, maintaining the stability of the power converter and achieving the goal of outputting a stable voltage based on a wide range of input voltages.

[0153] For the specific structure of the power converter, please refer to Embodiment 1, which will not be repeated in this embodiment.

[0154] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A power converter, characterized in that, include: A first bridge arm consisting of multiple switches, a second bridge arm consisting of multiple switches, a first capacitor Cb1, a second capacitor Cb2, and an inductor assembly; One end of the first bridge arm is connected to the first input terminal Vin+ of the power converter, and the other end is connected to the second input terminal Vin-; one end of the second bridge arm is connected to the first input terminal Vin+ of the power converter, and the other end is connected to the second input terminal Vin-; an input capacitor Cin is provided between the first input terminal Vin+ and the second input terminal Vin-; The first bridge arm has a second node and a third node, and the second bridge arm has a first node and a fourth node; the first node, the second node, the third node, and the fourth node are respectively located on the connecting line between two adjacent switches; The first node is connected to one end of the first capacitor Cb1; the other end of the first capacitor Cb1 is connected to the second node; the third node is connected to one end of the second capacitor Cb2; the other end of the second capacitor Cb2 is connected to the fourth node; the second node and the fourth node are respectively connected to one end of the inductor assembly, and the other end of the inductor assembly is connected to the first output terminal Vout+ of the power converter; Specifically, based on the duty cycle of the power converter, the conduction state of each switch is controlled within a specific time region to ensure that the first capacitor Cb1 and the second capacitor Cb2 do not form a circuit with the input capacitor Cin, or that the voltages across the first capacitor Cb1 and the second capacitor Cb2 are both lower than the voltages across the input capacitor Cin.

2. The power converter according to claim 1, characterized in that, include: The first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4 are connected in sequence to form the first bridge arm, and the fifth switch Q5, the sixth switch Q6, the seventh switch Q7 and the eighth switch Q8 are connected in sequence to form the second bridge arm. One end of the first switch Q1 and one end of the fifth switch Q5 are respectively connected to the first input terminal Vin+; one end of the fourth switch Q4 and one end of the eighth switch Q8 are respectively connected to the second input terminal Vin-. The first node between the sixth switch Q6 and the seventh switch Q7 is connected to one end of the first capacitor Cb1; the other end of the first capacitor Cb1 is connected to the second node between the third switch Q3 and the fourth switch Q4. The third node between the second switch Q2 and the third switch Q3 is connected to one end of the second capacitor Cb2; the other end of the second capacitor Cb2 is connected to the fourth node between the seventh switch Q7 and the eighth switch Q8. The first switch Q1 and the fifth switch Q5 share a common source, the first switch Q1 and the second switch Q2 share a common drain, and the fifth switch Q5 and the sixth switch Q6 share a common drain.

3. The power converter according to claim 1, characterized in that, include: The second switch Q2, the first switch Q1, the third switch Q3 and the fourth switch Q4 are connected in sequence to form the first bridge arm, and the sixth switch Q6, the fifth switch Q5, the seventh switch Q7 and the eighth switch Q8 are connected in sequence to form the second bridge arm. One end of the second switch Q2 and one end of the sixth switch Q6 are respectively connected to the first input terminal Vin+; one end of the fourth switch Q4 and one end of the eighth switch Q8 are respectively connected to the second input terminal Vin-. The first node between the fifth switch Q5 and the seventh switch Q7 is connected to one end of the first capacitor Cb1; the other end of the first capacitor Cb1 is connected to the second node between the third switch Q3 and the fourth switch Q4. The third node between the first switch Q1 and the third switch Q3 is connected to one end of the second capacitor Cb2; the other end of the second capacitor Cb2 is connected to the fourth node between the seventh switch Q7 and the eighth switch Q8. The first switch Q1 and the second switch Q2 share a common source, and the fifth switch Q5 and the sixth switch Q6 share a common source.

4. The power converter according to claim 2 or 3, characterized in that, The power converter further includes a PWM control module, which is connected to the control terminals of the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the fifth switch Q5, the sixth switch Q6, the seventh switch Q7 and the eighth switch Q8, respectively. The PWM control module is used to send corresponding PWM control signals to the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the fifth switch Q5, the sixth switch Q6, the seventh switch Q7 and the eighth switch Q8 respectively, so as to control the on / off state of each switch at different times.

5. The power converter according to claim 2 or 3, characterized in that, The first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the fifth switch Q5, the sixth switch Q6, the seventh switch Q7, and the eighth switch Q8 have the same switching frequency.

6. The power converter according to claim 2 or 3, characterized in that, The power converter also includes an input inductor Lin, an output inductor Ls, and an output capacitor Cout; one end of the input inductor Lin is connected to the first input terminal Vin+ of the power converter, and the other end of the input inductor Lin is connected to one end of the input capacitor Cin, one end of the first switch Q1, and one end of the fifth switch Q5, respectively. One end of the output inductor Ls is connected to the other end of the inductor assembly, and the other end of the output inductor Ls is connected to the first output terminal Vout+ of the power converter; one end of the output capacitor Cout is connected to the first output terminal Vout+ of the power converter, and the other end of the output capacitor Cout is connected to the second output terminal Vout- of the power converter.

7. The power converter according to claim 2 or 3, characterized in that, The inductor assembly is a discrete inductor, comprising a first inductor Lq1 and a second inductor Lq2; one end of the first inductor Lq1 is connected to the second node, and the other end of the first inductor Lq1 is connected to the first output terminal Vout+ of the power converter; one end of the second inductor Lq2 is connected to the fourth node, and the other end of the second inductor Lq2 is connected to the first output terminal Vout+ of the power converter.

8. The power converter according to claim 2 or 3, characterized in that, The inductor assembly is a coupled inductor, comprising a third inductor Lq1' and a fourth inductor Lq2'. One end of the third inductor Lq1' is connected to the second node, and the other end of the third inductor Lq1' is connected to the first output terminal Vout+ of the power converter. One end of the fourth inductor Lq2' is connected to the fourth node, and the other end of the fourth inductor Lq2' is connected to the first output terminal Vout+ of the power converter. The third inductor Lq1' and the fourth inductor Lq2' are wound on the same magnetic core assembly, and the polarities of the third inductor Lq1' and the fourth inductor Lq2' are opposite. The absolute value of the coupling coefficient between the third inductor Lq1' and the fourth inductor Lq2' ranges from 0 to 1.

9. A control method for a power converter, characterized in that, The control method is implemented in the power converter as described in any one of claims 1-8, comprising: When the duty cycle of the power converter is less than or equal to a preset threshold, a first timing control diagram corresponding to each switch is constructed, and a corresponding PWM control signal is generated according to the first timing control diagram to control the closing or opening of each switch; wherein, the first switch Q1 and the fifth switch Q5 remain in the on state; When the duty cycle of the power converter is greater than a preset threshold, a second timing control diagram is constructed for each switch, and a corresponding PWM control signal is generated according to the second timing control diagram to control the closing or opening of each switch; wherein, during the time period when a reverse current surge occurs, the first switch Q1 or the fifth switch Q5 is controlled to open to avoid the generation of reverse current.

10. The control method for the power converter according to claim 9, characterized in that, The first bridge arm includes a first switch Q1, a second switch Q2, a third switch Q3, and a fourth switch Q4; the second bridge arm includes a fifth switch Q5, a sixth switch Q6, a seventh switch Q7, and an eighth switch Q8, as shown in the first timing control diagram: The sixth control signal on the sixth switch Q6 is in phase with the third control signal on the third switch Q3; the second control signal on the second switch Q2 is in phase with the seventh control signal on the seventh switch Q7; the sixth control signal on the sixth switch Q6 is phase-shifted by 180 degrees with the fourth control signal on the fourth switch Q4; the second control signal on the second switch Q2 is phase-shifted by 180 degrees with the eighth control signal on the eighth switch Q8; the sixth control signal on the sixth switch Q6 is phase-shifted by 180 degrees with the second control signal on the second switch Q2; the fourth control signal on the fourth switch Q4 is phase-shifted by 180 degrees with the eighth control signal on the eighth switch Q8; the first switch Q1 and the fifth switch Q5 remain in the on state.

11. The control method for the power converter according to claim 9, characterized in that, The first bridge arm includes a first switch Q1, a second switch Q2, a third switch Q3, and a fourth switch Q4; the second bridge arm includes a fifth switch Q5, a sixth switch Q6, a seventh switch Q7, and an eighth switch Q8, as shown in the second timing control diagram: The seventh control signal on the seventh switch Q7 is in phase with the fourth control signal on the fourth switch Q4; the third control signal on the third switch Q3 is in phase with the eighth control signal on the eighth switch Q8; the sixth control signal on the sixth switch Q6 is 180 degrees phase-shifted with the seventh control signal on the seventh switch Q7; the seventh control signal on the seventh switch Q7 is also 180 degrees phase-shifted with the third control signal on the third switch Q3; the third control signal on the third switch Q3 is 180 degrees phase-shifted with the second control signal on the second switch Q2.

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