Millimeter wave low phase error distributed attenuator based on symmetric cell

Abstract

This invention discloses a millimeter-wave low-phase-error distributed attenuator based on symmetrical units, consisting of five attenuation units cascaded in series. The attenuation of the five attenuation units is the largest in the middle and decreases asymmetrically towards both sides. Each attenuation unit consists of a transmission line, two transistors, and two bias resistors. The transmission lines of the five attenuation units are connected sequentially, and the two transistors of each attenuation unit are symmetrically arranged at both ends of their transmission lines, connected to a sensing line through their drains, grounded at their sources, and their gates are each connected to one end of a bias resistor. The other ends of the two bias resistors are connected to a common control voltage signal. This invention, based on silicon-based technology, solves the technical problem of balancing phase error, chip area, and bandwidth performance in existing attenuators, achieving a harmonious balance between wide attenuation range, low insertion loss, low phase error, and compact size, meeting the application requirements of high-performance millimeter-wave phased array systems.

Description

Technical Field

[0001] This invention relates to the field of attenuator technology, and in particular to a millimeter-wave low-phase-error distributed attenuator based on symmetrical units. Background Technology

[0002] With the continuous development of next-generation wireless communication, high-resolution imaging radar and vehicle-mounted radar technologies, the demand for millimeter-wave phased array systems is becoming increasingly prominent.

[0003] As a key gain control module in a phased array system, the phase change of the attenuator directly affects the scanning accuracy, beam gain, and multi-channel calibration difficulty of the phased array system. Therefore, attenuators with a wide attenuation range and low phase error are crucial for high-performance millimeter-wave phased array systems.

[0004] To compensate for phase changes in attenuators, various solutions have been proposed in the prior art: For switched T / π type attenuators, phase compensation is achieved by adding additional parallel / series capacitors or inductors to introduce new zeros and poles, but this type of method faces great challenges in broadband multi-bit attenuator design; For distributed attenuators, phase compensation is usually achieved by adding additional inductors or transmission lines in the parallel branches, however, the introduction of these additional components will significantly increase the chip area of ​​the attenuator.

[0005] In summary, existing technologies are insufficient to meet the requirements of high-performance millimeter-wave phased array systems for wide bandwidth, low loss, small size, and low phase error. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings and defects of the prior art and provide a millimeter-wave low-phase-error distributed attenuator based on symmetrical units. It aims to solve the technical problem that it is difficult to balance phase error, chip area and bandwidth performance of existing attenuators based on silicon-based process / semiconductor on-chip integration process, and achieve an organic unity of wide attenuation range, low insertion loss, low phase error and compact size, so as to meet the application requirements of high-performance millimeter-wave phased array system.

[0007] This invention is achieved through the following technical solution:

[0008] A millimeter-wave low-phase-error distributed attenuator based on symmetrical units is composed of five attenuation units cascaded in series. The attenuation of the five attenuation units is the largest in the middle and decreases asymmetrically to both sides. Each attenuation unit consists of a transmission line, two transistors, and two bias resistors. The transmission lines of the five attenuation units are connected in sequence. The two transistors of each attenuation unit are symmetrically arranged at both ends of their transmission lines, connected to the sensing line through the drain, grounded, and the gates of each transistor are connected to one end of a bias resistor. The other ends of the two bias resistors are connected to a control voltage signal.

[0009] Preferably, the attenuation amount of adjacent attenuation units is related by a preset ratio, and the attenuation amount of two symmetrical attenuation units has the same ratio, which is at least 2 times.

[0010] Preferably, the attenuation of the front-end attenuation unit on the input side is less than the attenuation of the end attenuation unit on the output side.

[0011] Preferably, the attenuation amounts of the five attenuation units are 0.4dB, 3.2dB, 6.4dB, 1.6dB, and 0.8dB, respectively.

[0012] Preferably, the transistor is a MOSFET transistor.

[0013] Preferably, the bias resistors have the same resistance value.

[0014] Preferably, the bias resistor is a high-precision resistor with a resistance of 10KΩ.

[0015] Preferably, the control voltage signal is in the range of 0-3.3V.

[0016] Preferably, the input terminal of the front-end attenuation unit is connected to the GSG input probe, and the GSG output probe is connected to the output terminal of the end attenuation unit.

[0017] The present invention relates to a millimeter-wave low-phase-error distributed attenuator based on symmetrical units. Each attenuation unit of the circuit adopts a transistor symmetrical structure. The two symmetrical transistors introduce a second-order phase correction term, which has little impact on the transmission phase of the attenuated state. The second-order phase correction term improves the phase of the reference state, thereby greatly reducing the phase error. Using symmetrical transistors to compensate for the phase does not increase the overall circuit area compared to traditional transmission lines and inductors. The symmetrical path introduced by the symmetrical structure transistors reduces the size of the required transistors and improves the performance of the attenuator in the millimeter-wave band. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the pull-out three-dimensional card packaging box of the present invention. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0020] In an exemplary embodiment of this application, the millimeter-wave low-phase-error distributed attenuator based on symmetric units, such as Figure 1As shown, it can be formed based on silicon-based integrated circuit / on-chip semiconductor integrated circuit process, consisting of five attenuation units connected in series. The attenuation of the five attenuation units is the largest in the middle and decreases asymmetrically to both sides. Each attenuation unit consists of a transmission line, two transistors, and two bias resistors. The transmission lines of the five attenuation units are connected in sequence. The two transistors of each attenuation unit are symmetrically arranged at both ends of their transmission lines, connected to the sensing line through the drain, grounded, and the gates of each are connected to one end of a bias resistor. The other ends of the two bias resistors are connected to a control voltage signal.

[0021] Specifically, this millimeter-wave low-phase-error distributed attenuator based on symmetrical units consists of 5 transmission lines (TL) and 10 MOSFET transistors. MOSFET transistors are symmetrically distributed at both ends of the transmission lines of each attenuation unit, forming a symmetrical transistor structure. The attenuation amounts of adjacent attenuation units are related by a preset ratio, and the attenuation ratios of two symmetrical attenuation units are identical, at least twice. More preferably, the attenuation amount of the attenuation unit on the input side is less than that of the attenuation unit on the output side.

[0022] In one embodiment, the attenuation amounts of the five symmetrical attenuation units are 0.4dB, 0.8dB, 1.6dB, 3.2dB, and 6.4dB, respectively. This is only one specific embodiment and is not limited to it. Other amounts can also be arranged according to this pattern.

[0023] In this embodiment of the application, the attenuation unit based on a symmetrical structure is used to... Figure 1 Taking a 0.4dB attenuation unit as an example, it includes a transmission line TL1, two symmetrically distributed second-order phase correction transistors M1 and M2, two bias resistors R1 and R2, and a control signal V1.

[0024] Compared to traditional distributed attenuators, the symmetrical unit-based distributed attenuator, due to the additional mirrored attenuation path introduced by transistor M2, forms two mirrored attenuation paths. This results in an admittance required to reach the same attenuation state that is approximately half that of the traditional method. The transmission phase error of both methods exhibits the same first-order term. However, the symmetrical structure attenuator introduces a second-order phase compensation term due to transistor M2. This compensation term, being the difference between the equivalent turn-on resistance and the turn-on capacitor impedance, has minimal impact on the transmission phase in the attenuated state. For the reference state transmission phase, it introduces a quadratic term determined by the equivalent turn-off capacitance, significantly reducing the attenuator's transmission phase difference. Furthermore, the introduction of the transistor does not increase the overall circuit area.

[0025] Specifically, the attenuator of this application comprises each attenuation unit consisting of a transmission line TL, two symmetrically distributed transistors, two gate bias resistors, and a control signal. Specifically, the transmission line TL1, transistors M1 and M2, bias resistors R1 and R2, and control signal V1 constitute a 0.4dB attenuation unit; the transmission line TL2, transistors M3 and M4, bias resistors R3 and R4, and control signal V2 constitute a 3.2dB attenuation unit; the transmission line TL3, transistors M5 and M6, bias resistors R5 and R6, and control signal V3 constitute a 6.4dB attenuation unit; the transmission line TL4, transistors M7 and M8, bias resistors R7 and R8, and control signal V4 constitute a 1.6dB attenuation unit; and the transmission line TL5, transistors M9 and M10, bias resistors R9 and R10, and control signal V5 constitute a 0.8dB attenuation unit.

[0026] In this attenuation unit, the source S of each transistor M1, M3, M5, M7, and M9 is grounded, the drain D is connected to the left end of transmission lines TL1-TL5, and the gate G is connected to control signals V1-V5 through bias resistors R1, R3, R5, R7, and R9; the source S of transistors M2, M4, M6, M8, and M10 is grounded, the drain D is connected to the right end of transmission lines TL1-TL5, and the gate G is connected to control signals V1-V5 through bias resistors R2, R4, R6, R8, and R10; the gate control signals of the transistors in the same attenuation unit in this application are synchronized to achieve synchronous conduction or cutoff; in the semiconductor on-chip integration process, the transmission lines TL1-TL5 can all use the thickest second-layer metal to form the signal path, which can reduce the loss effect of metal traces.

[0027] In this application, the cascading order is determined based on the return loss of each attenuation unit. The 0.4dB and 0.8dB attenuation units, which require smaller transistor sizes, have lower parasitic capacitance, and exhibit excellent return loss performance, are placed at both ends for input-output matching. The 6.4dB attenuation unit, which requires larger transistor sizes, has higher parasitic capacitance, and exhibits poorer return loss performance, is placed at the very center of the overall circuit. The 3.2dB and 1.6dB attenuation units, due to their similar return loss to 6.4dB, are distributed on either side of it. Ultimately, five attenuation units are connected in series via a signal cascading path in the order of "0.4dB→3.2dB→6.4dB→1.6dB→0.8dB". The input port GSG input probe is connected to the signal input terminal of the 0.4dB attenuation unit, and the signal output terminal of the 0.8dB attenuation unit is connected to the output port GSG output probe. The GSG input / output probe is used to input external signals or output attenuated signals; the S terminal is for inputting and outputting signals, and the G terminal is grounded.

[0028] In one embodiment, the two bias resistors of each attenuation unit constitute a bias circuit, specifically including ten high-precision bias resistors R1-R10 with a resistance of 10KΩ. One end of each bias resistor is connected to the gate of each transistor M1-M10, and the other end is connected to the control signal of the circuit. Each control signal is a voltage of 0-3.3V. By controlling the potential of the control voltages V1-V5, the conduction and turn-off of the transistors of the five attenuation units are controlled, thereby achieving 5-bit control, 0.4dB increments, and an attenuation range of 12.8dB.

[0029] The millimeter-wave low phase error distributed attenuator based on symmetrical units in this application can also be implemented using circuit board level technology, that is, on a substrate or PCB, and is not limited to on-chip integration.

[0030] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. It will be apparent to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention.

[0031] Therefore, the embodiments should be regarded as exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of the equivalents of the claims be included within the invention.

[0032] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A millimeter-wave low-phase-error distributed attenuator based on symmetrical elements, characterized in that, It consists of five attenuation units connected in series. The attenuation of the five attenuation units is the largest in the middle and decreases asymmetrically to both sides. Each attenuation unit consists of a transmission line, two transistors, and two bias resistors. The transmission lines of the five attenuation units are connected in sequence. The two transistors of each attenuation unit are symmetrically arranged at both ends of their transmission lines, connected to the sensing line through the drain, grounded, and the gates of each transistor are connected to one end of a bias resistor. The other ends of the two bias resistors are connected to a control voltage signal.

2. The millimeter-wave low-phase-error distributed attenuator according to claim 1, characterized in that, The attenuation amounts of adjacent attenuation units are related by a preset ratio, and the attenuation amounts of two symmetrical attenuation units have the same ratio, which is at least twice.

3. The millimeter-wave low-phase-error distributed attenuator according to claim 1, characterized in that, The attenuation of the front-end attenuation unit on the input side is less than the attenuation of the end attenuation unit on the output side.

4. The millimeter-wave low-phase-error distributed attenuator according to claim 1, characterized in that, The attenuation values ​​of the five attenuation units are 0.4dB, 3.2dB, 6.4dB, 1.6dB, and 0.8dB, respectively.

5. The millimeter-wave low-phase-error distributed attenuator according to claim 1, characterized in that, The transistor is a MOSFET transistor.

6. The millimeter-wave low-phase-error distributed attenuator according to claim 1, characterized in that, The bias resistors all have the same resistance value.

7. The millimeter-wave low-phase-error distributed attenuator according to claim 5, characterized in that, The bias resistor is a high-precision resistor with a resistance of 10KΩ.

8. The millimeter-wave low-phase-error distributed attenuator according to claim 1, characterized in that, The control voltage signal is in the range of 0-3.3V.

9. The millimeter-wave low-phase-error distributed attenuator according to claim 1, characterized in that, The input terminal of the front-end attenuation unit is connected to the GSG input probe, and the GSG output probe is connected to the output terminal of the end attenuation unit.

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