Adjustable frequency clock signal generator and method thereof

Abstract

A clock signal generator includes an oscillation circuit and a charge transfer capacitor. The oscillation circuit is configured to generate a clock signal and includes a comparator and a resistor-capacitor circuit, wherein the resistor-capacitor circuit includes a capacitor. The charge transfer capacitor is connected to the resistor-capacitor circuit. The frequency of the clock signal is adjusted by injecting or extracting charge associated with the resistor-capacitor circuit through the charge transfer capacitor.

Description

Technical Field

[0001] This application relates to a clock signal generator and a frequency adjustment method, and more particularly to a clock signal generator and a frequency adjustment method capable of adjusting the clock frequency with high resolution. Background Technology

[0002] Unless otherwise stated, the methods described in this section are not prior art within the scope of the claims of this application and are not recognized as prior art by virtue of their inclusion in this section.

[0003] U.S. Patent No. 11,943,585 or Application No. 19 / 035,763 discloses a gas pulse generating device that can be used as a sound generating device. As described in No. 11,943,585 or 19 / 035,763, the operating frequency of the gas pulse generating device affects the sound pressure level (SPL). Specifically, the SPL depends on how close the operating frequency is to the resonant frequency.

[0004] However, the resonant frequency of the gas pulse generator can vary due to process variations. Therefore, the operating frequency must be precisely calibrated to match the specific resonant frequency of each individual gas pulse generator.

[0005] Therefore, an adjustable frequency clock signal generator is needed to compensate for these variations and ensure optimal performance. Summary of the Invention

[0006] Therefore, the main objective of this application is to provide a clock signal generator and frequency adjustment method capable of adjusting the clock frequency with high resolution.

[0007] One embodiment of this application discloses a clock signal generator, which includes an oscillation circuit for generating a clock signal. The clock signal includes a comparator and a resistor-capacitor circuit, wherein the resistor-capacitor circuit includes a capacitor and a charge-moving capacitor connected to the resistor-capacitor circuit. The frequency of the clock signal is adjusted by injecting or extracting charge associated with the resistor-capacitor circuit via the charge-moving capacitor.

[0008] Another embodiment of this application discloses a frequency adjustment method for a clock signal generator, used to adjust the frequency of a clock signal of the clock signal generator. The method includes injecting or extracting charge associated with a resistor-capacitor circuit; wherein the clock signal generator includes an oscillation circuit, and the oscillation circuit includes a comparator and the resistor-capacitor circuit; wherein the oscillation circuit generates the clock signal. Attached Figure Description

[0009] Figure 1This is a schematic diagram of an adjustable frequency clock signal generator according to Embodiment 1 of the present invention.

[0010] Figure 2 Draw a schematic diagram of an oscillating circuit and its related waveforms.

[0011] Figure 3 A schematic diagram of an adjustable frequency clock signal generator and its associated waveforms is shown.

[0012] Figure 4 Draw another (relaxation) oscillator or an oscillating circuit and its corresponding waveform.

[0013] Figure 5 A schematic diagram of an adjustable frequency clock signal generator is shown.

[0014] Figure 6 A schematic diagram of an adjustable frequency clock signal generator is shown.

[0015] Figure 7 This is a schematic diagram of an oscillating circuit and its operation.

[0016] Figure 8 This is a schematic diagram of an adjustable frequency clock signal generator according to Embodiment 1 of the present invention.

[0017] Figure 9 Draw the waveforms of the clock signal and the capacitor voltage.

[0018] Figure 10 Draw Figure 8 The charge-moving capacitance in the figure is realized by an equivalent charge-moving capacitance.

[0019] Figure 11 This is a schematic diagram of an adjustable frequency clock signal generator according to Embodiment 1 of the present invention.

[0020] List of reference numerals

[0021] 10, 20, 30, 10b, 40, 50: Adjustable frequency clock signal generators

[0022] 12, 22, 32, 42: Oscillating circuits

[0023] 14, 24, 34, 44: Resistor-capacitor circuit

[0024] 16, 26, 36, 46: Comparators

[0025] C IE Charge transfer capacitance

[0026] V C Capacitor voltage

[0027] CLK: Clock signal

[0028] Vo: Output voltage

[0029] C, C T1 C T2 C1, C2: Capacitors

[0030] T D During discharge

[0031] T C During charging

[0032] PS: Signal

[0033] t di Delay time

[0034] bp, bp1, bp2: Sudden wave

[0035] V op V on V C1 V C2 V DD V GND V1, V2: Voltage

[0036] DE, DE1, DE2: Delay elements

[0037] CLK d Delayed clock signal

[0038] 43: Switching circuit

[0039] A, B: Nodes

[0040] R1, R2: Resistors

[0041] T1, T2: Time Complementary clock signal Delayed complementary clock signal ΔV1, ΔV2: Voltage changes C IE,(e) Equivalent charge transfer capacitance SW1, SW2: Switches Detailed Implementation

[0042] This invention proposes an adjustable frequency clock signal generator. Furthermore, frequency adjustment is achieved through a charge injection / extraction mechanism, wherein the amount of injected / extracted charge and / or delay time are used as control parameters. The clock frequency can be monotonically adjusted to provide high-resolution compensation for the aforementioned process variations.

[0043] Figure 1This is a schematic diagram of an adjustable frequency clock signal generator 10 according to an embodiment of the present invention. The adjustable frequency clock signal generator 10 includes an oscillation circuit 12 and a charge-moving capacitor C. IE The oscillation circuit 12 can be a relaxation oscillator, which includes a resistor-capacitor circuit 14 and a comparator 16. The output of the comparator 16 is typically fed back to the oscillation circuit 12 to switch between charging and discharging states / phases. The resistor-capacitor circuit 14 can perform charging or discharging operations, causing a capacitor voltage V to... C The voltage V rises (during charging) or falls (during discharging). C When the value rises or falls to cross a threshold, comparator 16 changes state and generates a clock signal CLK.

[0044] For example, Figure 2 (a) shows a schematic diagram of an oscillating circuit 22. Figure 2 Figure (b) shows an output voltage Vo and a capacitor voltage V. C The waveform. Figure 2 Excerpted from https: / / www.ti.com / lit / pdf / snoa998. The oscillation circuit 22 includes a resistor-capacitor circuit 24 and a comparator 26. The oscillation circuit 22 includes a capacitor C, which, during a discharge period T... D Internally, the output voltage Vo is at a low potential, and capacitor C is discharging, causing the capacitor voltage V to... C The voltage drops. Once the capacitor voltage V... C When the voltage drops to the first position, comparator 26 is triggered and changes state, causing the output voltage Vo to transition to a high level, and during a charging period T... C Start. During charging, T C Inside, capacitor C is charged and the capacitor voltage V C Rise. Once the capacitor voltage V C When the second bit is reached, comparator 26 is triggered and changes state again (to a low potential state), during another discharge period T. D start.

[0045] Depend on Figure 2 As can be seen, through the charging and discharging of the capacitor, the oscillation circuit 22 can output a square wave Vo (which can be used as a clock signal). The frequency of the clock is entirely determined by the RC time constant of the resistor-capacitor circuit, which cannot be adjusted.

[0046] To enable frequency adjustment, a charge-moving capacitor can be added.

[0047] Figure 3Figure (a) shows a schematic diagram of an adjustable frequency clock signal generator 20. In addition to the oscillation circuit 22, the adjustable frequency clock signal generator 20 also includes a charge-moving capacitor C. IE Charge transfer capacitance C IE One end is coupled to the resistor-capacitor circuit 24 or its internal capacitor C. The charge-moving capacitor C IE The second terminal receives a signal PS. Generally, the signal PS may include a rising edge or a falling edge, wherein the rising edge may be located during the discharge period, or the falling edge may be located during the charging period. Figure 3 In one embodiment, the falling edge is located during charging.

[0048] For example, Figure 3 (b) shows the pulse signal PS. (1) PS (2) PS (3) and capacitor voltage V C(1) V C(2) V C(3) The waveform, in which the pulse signal PS (1) PS (2) PS (3) Corresponding to different responsibilities / delay times t d,(1) , t d,(2) , t d,(3) And capacitor voltage V C(1) V C(2) V C(3) Corresponding to pulse signal PS (1) PS (2) PS (3) Pulse signal PS (1) PS (2) PS (3) It includes a falling edge located during the charging period of capacitor C. This is due to the movement of charge across capacitor C. IE It receives the pulse signal PS through its second terminal. (1) / PS (2) / PS (3) At the time (point) corresponding to the falling edge, charge can travel via charge transfer capacitor C. IE Extracted from capacitor C, capacitor voltage V C(1) / V C(2) / V C(3) The voltage drops slightly during charging, thus the capacitor voltage V C(1) / V C(2) / V C(3)The waveform will contain spikes (bp) that are oriented toward negative values ​​or have negative polarity. Therefore, due to charge extraction, the charging period is extended, and the clock frequency is adjusted to a lower value.

[0049] Figure 4 The diagram illustrates another (relaxation) oscillator or oscillator circuit 32 and its corresponding waveform, excerpted from "A Low-Power, Differential Relaxation Oscillator With the Self-Threshold-Tracking and Swing-Boosting Techniques in 0.18-μm CMOS" by S.-Y. Lu and Y.-T. Liao, published in [Journal Name]. IEEE Journal of Solid-State Circuits Journal, Volume 54, Issue 2, pp. 392-402, February 2019. The oscillation circuit 32 includes a resistor-capacitor circuit 34 and a comparator 36 (based on an inverter). The resistor-capacitor circuit 34 includes a capacitor C. T1 C T2 Similar to oscillating circuit 22, at (output) voltage V op / V on During the high / low potential state, capacitor C T1 / C T2 The charging and discharging processes are performed alternately. The clock frequency of the oscillator circuit 32 can be determined by the RC time constant, and it is not frequency adjustable.

[0050] Figure 5 A schematic diagram of an adjustable frequency clock signal generator 30 is shown. In addition to the oscillation circuit 32, the adjustable frequency clock signal generator 30 also includes a charge-moving capacitor C. IE,(1) C IE,(2) Charge transfer capacitance C IE,(1) C IE,(2) One of the first ends can be coupled to capacitor C T1 C T2 Charge transfer capacitance C IE,(1) C IE,(2) One of the second terminals can receive a signal containing a rising / falling edge to inject charge into the capacitor C in the resistor-capacitor circuit 34. T1 / C T2 Or extract charge from it.

[0051] In this invention, "signal containing rising / falling edges" generally means that the signal contains a (sudden) voltage change from a first voltage to a second voltage.

[0052] In one embodiment, the second terminal of the charge-moving capacitor may receive another clock signal. In one embodiment, this other clock signal may be a delayed version of a clock signal output by the oscillation circuit of an adjustable frequency clock signal generator.

[0053] Figure 6 A schematic diagram of an adjustable frequency clock signal generator 10b is shown. Clock signal generator 10b is similar to clock signal generator 10. In addition to clock signal generator 10, clock signal generator 10b further includes a delay element DE, which is coupled to oscillation circuit 12 (actually the output of comparator 16) and charge-moving capacitor C. IE Between the second and third terminals. The delay element DE can be used to generate a delayed clock signal CLK. d To charge transfer capacitor C IE The second end, while the delayed clock signal CLK d It is generated based on the clock signal CLK. Regarding the delayed clock signal CLK... d The detailed operation method will be discussed later.

[0054] Figure 7 (a) is a schematic diagram of an oscillator circuit 42. The oscillator circuit 42 can be used to generate a clock signal CLK. The oscillator circuit 42 includes a switching circuit 43, a resistor-capacitor circuit 44, and a comparator 46. Figure 7 Excerpted from "An Ultra-Low-Noise Swing-Boosted Differential Relaxation Oscillator in 0.18-μm CMOS" by J. Lee, A.K. George, and M. Je, published in [Journal Name]. IEEE Journal of Solid-State Circuits Journal, Volume 55, Issue 9, pp. 2489-2497, September 2020.

[0055] Switching circuit 43 is connected to nodes A and B. Figure 7 In embodiment (a), the switching circuit 43 is also connected to a power supply terminal (to receive a first voltage, such as V). DD and a grounding terminal (to receive a second / ground voltage, such as V) GND However, it is not limited to this. During a first period (e.g., a first state corresponding to the clock signal CLK, such as a high-level state), the switching circuit provides a first voltage (e.g., V from the power supply). DD ) to node A, and provide a second voltage (such as V from the ground terminal) GND ) to node B. During a second period (e.g., a second state corresponding to clock signal CLK, such as a low-potential state), the switching circuit provides a second voltage (e.g., V from ground). GND) to node A, and provide a first voltage (such as V from the power supply terminal) DD ) to node B.

[0056] The resistor-capacitor circuit 44 includes capacitors C1 and C2 and resistors R1 and R2. Capacitor C1 and resistor R1 are connected in a first series connection; capacitor C2 and resistor R2 are connected in a second series connection. The first and second series connections are connected in parallel between nodes A and B.

[0057] It is worth noting that the resistors R1 and R2 and capacitors C1 and C2 inside the resistor-capacitor circuit 44 of the present invention are for illustrative purposes only, and any component having resistance and capacitance values ​​can be used to replace R1, R2, C1, and C2 inside the resistor-capacitor circuit 44 of the present invention. That is to say, the resistors and capacitors of the present invention are symbolic representations of components having resistance and capacitance values, and can represent not only physical resistors and capacitors, but also any component having equivalent resistance or capacitance.

[0058] The comparator 46 includes a first input terminal (indicated by "+") and a second input terminal (indicated by "-"). The first input terminal is coupled between capacitor C1 and resistor R1, and the second input terminal is coupled between capacitor C2 and resistor R2.

[0059] The operation mode of oscillator circuit 42 is illustrated in the diagram. Figure 7 In (b) of the above. During a time period T1, the clock signal CLK is at a low level (or the comparator 46 outputs a low level), and node B receives voltage V. DD And node A receives voltage V GND Assume V DD > V GND Current flows from node B to node A. Capacitor C2 is discharging while capacitor C1 is charging. Voltage V C2 The voltage V drops C1 The rise. Time T1 can be regarded as the charging period of capacitor C1 or the discharging period of capacitor C2.

[0060] Once the critical condition (such as V) is reached... C1 = V C2 When comparator 46 switches to a high level (or clock signal CLK switches to a high level), node A switches to voltage V. DD And node B switches to voltage V GND Within a time interval T2, given V DD > V GND Current flows from node A to node B. Capacitor C1 is discharging and capacitor C2 is charging. Voltage V C1 The voltage V drops C2 The rise continues until the critical condition (such as V) is met again.C1 = V C2 Until then. Time T2 can be considered as the discharge period of capacitor C1 or the charging period of capacitor C2.

[0061] Figure 7 The frequency of the clock signal CLK generated by the oscillator circuit 42 shown is entirely determined by the resistance and capacitance of the resistor-capacitor circuit. Once the resistance or capacitance of the resistor-capacitor circuit is selected, the frequency of the clock signal CLK is fixed / constant.

[0062] However, for certain applications, an adjustable frequency clock signal generator is necessary. For example, an adjustable frequency clock generator can be used to generate a uniform clock signal to drive a circuit that can drive the air pulse generating device disclosed in U.S. Patent No. 11,943,585 or Application No. 19 / 035,763 as a sound generating device, where the sound pressure level (SPL) is affected by its operating frequency, as described in U.S. Patent Application Nos. 19 / 289,091 and / or 19 / 287,761. Specifically, the SPL depends on how close the operating frequency is to the resonant frequency. Since the resonant frequency of the air pulse generating device can vary due to process variations, an adjustable frequency clock signal generator needs to be designed to compensate for these variations and ensure optimal performance.

[0063] The purpose of this invention is to provide an adjustable frequency clock signal generator.

[0064] Figure 8 This is a schematic diagram of an adjustable frequency clock signal generator 40 according to Embodiment 1 of the present invention. In addition to the oscillation circuit 42, the clock signal generator 40 further includes a charge transfer capacitor C. IE,1 and C IE,2 It is coupled to the first and second input terminals of comparator 46 or to capacitors C1 and C2. Charge transfer capacitor C IE,1 / 2 It can be used to inject or extract charge into the capacitor associated with the resistor-capacitor circuit 44, thereby extending the charging and discharging period and adjusting the frequency of the clock signal.

[0065] In other words, the charge transfer capacitance C IE,1 / C IE,2 One end is coupled to the resistor-capacitor circuit 44 and / or comparator 46. Charge-moving capacitor C IE,1 / C IE,2 One of the second terminals can receive / experience a sudden (or short) voltage rise to inject charge into the resistor-capacitor circuit 44; or can receive / experience a sudden (or short) voltage drop to extract charge from the resistor-capacitor circuit 44.

[0066] In one embodiment, the charge-moving capacitor C IE,1 / C IE,2 The second terminal can receive a signal including a rising edge for a brief moment during the discharge period to inject charge into the resistor-capacitor circuit 44. In one embodiment, the charge-moving capacitor C IE,1 / C IE,2 The second terminal can receive a signal containing a falling edge for a brief moment during charging to extract charge from the resistor-capacitor circuit 44.

[0067] In one embodiment, the charge-moving capacitor C IE,1 The second terminal can receive a delayed version (or a delayed clock signal) CLK. d The charge transfer capacitance C IE,2 The second end can receive a delayed version of a complementary clock signal (or a delayed complementary clock signal). Among them, complementary clock signals The clock signal CLK is the complement of the clock signal CLK, which is output from the first output terminal of comparator 46, while the complementary clock signal is... It is output from the second output terminal of comparator 46, such as Figure 7 and Figure 8 As shown.

[0068] exist Figure 8 In this embodiment, the (adjustable frequency) clock signal generator 40 includes delay elements DE1 and DE2. Delay element DE1 is coupled to the charge transfer capacitor C. IE,1 Between the first output terminal (indicated by "-") of comparator 46 and the delay element DE2 coupled to the charge-moving capacitor C. IE,2 Between the second output terminal (indicated by "+") of comparator 46 and the delay element DE1, the delayed clock signal CLK can be generated. d To charge transfer capacitor C IE,1 The delay element DE2 can generate a delayed complementary clock signal. To charge transfer capacitor C IE,2 .

[0069] In one embodiment, the delay element DE1 generates a delay time relative to the clock signal CLK (e.g., t di The delayed clock signal CLK d To charge transfer capacitor C IE,1 Furthermore, the delay element DE2 generates a signal relative to the complementary clock signal. With a delay time (e.g.) t di () delayed complementary clock signal To charge transfer capacitor C IE,2It should be noted that the delay time used for the delay element DE1... t di With the delay time used for delay element DE2 t di Whether they are the same or different, both situations fall within the scope of this invention.

[0070] Clock signals CLK, CLK d , and capacitor voltage V C1 V C2 The waveform is shown in Figure 9 It should be noted that both the adjustable frequency clock signal generators 30 and 40 can be used to generate the capacitor voltage V. C1 V C2 The waveform.

[0071] During time T1, the clock signal CLK is at a low level while the complementary clock signal... The voltage is high. Capacitor C1 is charging and capacitor C2 is discharging. T1 can be considered as the charging period of capacitor C1 and / or the discharging period of capacitor C2.

[0072] Due to the complementary delay clock signal During the discharge period of capacitor C2, there is a rising edge with a charge amount ΔV2. C IE,2 The charge moves through the charge-moving capacitor C IE,2 The injected capacitor C2, at voltage V C2 This creates a spike bp2 (with positive polarity) on the waveform. On the other hand, due to the delayed clock signal CLK... d During the charging period of capacitor C1, there is a falling edge with a charge amount ΔV1. C IE,1 The charge moves through the charge-moving capacitor C IE,1 Extracted from capacitor C1, its voltage V C1 A spike bp1 (with negative polarity) is created on the waveform.

[0073] In other words, the waveform of the capacitor voltage can be viewed as containing an exponentially decreasing surge (such as bp2) superimposed during the discharge of the capacitor (such as C2), or containing an exponentially increasing surge (such as bp1) superimposed during the charging of the capacitor (such as C1).

[0074] During time T2, the clock signal CLK is at a high level while the complementary clock signal... The potential is low. Capacitor C1 is discharging and capacitor C2 is charging. T2 can be considered as the discharging period of capacitor C1 and / or the charging period of capacitor C2.

[0075] Due to the delayed clock signal CLK d During the discharge period of capacitor C1, there is a rising edge with a charge amount ΔV1. C IE,1 The charge moves through the charge-moving capacitor C IE,1 The injected capacitor C1, at voltage V C1 This creates a spike (with positive polarity) on the waveform. On the other hand, due to the delayed complementary clock signal... During the charging period of capacitor C2, there is a falling edge with a charge amount ΔV2. C IE,2 The charge moves through the charge-moving capacitor C IE,1 Extracted from capacitor C2, its voltage V C2 A spike (with negative polarity) is created on the waveform.

[0076] Due to charge injection / extraction or surges (such as bp1 or bp2), the charging / discharging periods T1 / T2 can be extended. Therefore, the frequency of the clock signal CLK can be adjusted and reduced accordingly.

[0077] It is worth noting that the frequency adjustment can be determined by ΔV1 or ΔV2 (the voltage change at the second terminal of the charge-moving capacitor) and the charge-moving capacitor C. IE,1 Or C IE,2 The capacitance value and delay time t di That's for you to decide.

[0078] exist Figure 9 In the embodiments, unless otherwise stated, ΔV1 = ΔV2 = V DD In another embodiment, the charge-moving capacitor C IE,1 Or C IE,2 The second terminal can receive another clock signal or another signal containing a step function, meaning it contains a sudden voltage change ΔV1 or ΔV2. In this case, ΔV1 or ΔV2 will become a control variable / parameter for frequency adjustment.

[0079] Charge transfer capacitance C IE,1 Or C IE,2 The capacitance value can be another control variable / parameter for frequency adjustment. As mentioned above, the capacitor of the present invention can be replaced by any component with a capacitance value. In this respect, the charge-moving capacitor C IE,1 Or C IE,2 The capacitance value can be adjusted. For example, please refer to... Figure 10 , Figure 8 The charge-moving capacitance C in IE,1 Or C IE,2 can be Figure 10 The equivalent charge-moving capacitance C shownIE,(e) To achieve this, where the equivalent charge-moving capacitance C IE,(e) The internal switch can be configured to adjust the equivalent charge moving capacitor C. IE,(e) The capacitance value is crucial. A larger capacitance value results in a longer charging and discharging period, thus lowering the adjusted clock frequency. In other words, a larger capacitance value leads to a longer charging and discharging period, thereby reducing the adjusted clock frequency.

[0080] Delay time t di It is also a control variable / parameter for frequency adjustment, and it is adjustable. Since the charging / discharging current decreases monotonically (exponentially) with respect to time, given a certain amount of charge injected / extracted, if the delay time... t di The larger the value, the weaker the charging and discharging current and the longer the charging and discharging period, resulting in a lower adjusted clock frequency. In other words, a longer delay time. t di This results in longer charging and discharging periods, which in turn reduces the adjusted clock frequency.

[0081] Assuming the charging and discharging behavior of a resistor-capacitor circuit is monotonic (exponential), as charge moves across the capacitor (e.g., C...), the capacitor... IE,1 Or C IE,2 The capacitance value or delay time (e.g.) t di As the clock frequency increases, the adjusted clock frequency will decrease monotonically. In this respect, the adjustable frequency clock signal generator (such as 40) of the present invention can achieve very high resolution in clock frequency adjustment.

[0082] The adjustable frequency clock signal generator (e.g., 40) of the present invention has several advantages. One of these advantages is that the amount of injected / extracted charge is fixed or controllable, provided that the charge transfer capacitor (e.g., C) is constant. IE If the capacitance value of the charge transfer capacitor and the voltage change (such as ΔV1 or ΔV2) at the second terminal of the charge transfer capacitor remain constant, the amount of charge injected / extracted will also remain constant.

[0083] Another advantage is that the adjustable frequency clock signal generator of the present invention contains minimal active circuitry, thereby minimizing interference from the active circuitry. Even if a delay element is included, this delay element will indirectly cause jitter.

[0084] Another advantage is that the charge-moving capacitance (such as C) IE The capacitance value will isolate some interference, and there is no active circuit connected to the resistor-capacitor circuit.

[0085] Furthermore, this invention provides a reliable frequency adjustment method. The adjusted clock frequency is relative to the charge-moving capacitor (e.g., C). IE The capacitance value or delay time (e.g.) t di It is monotonous and can achieve very high frequency tuning resolution.

[0086] The foregoing are merely embodiments and not limitations of the present invention. Any modifications, equivalent substitutions, and improvements following the spirit and principles of the present invention should be included within the scope of the present invention.

[0087] For example, Figure 11 This is a schematic diagram of an adjustable frequency clock signal generator 50 according to Embodiment 1 of the present invention. Figure 11 In the middle, the charge transfer capacitance C IE,1 / C IE,2 The second terminal can receive a voltage V1 / V2 through a switch SW1 / SW2. Switches SW1 / SW2 can be used to move the charge on capacitor C. IE,1 / C IE,2 The second terminal provides a sudden voltage change to voltage V1 / V2, which also falls within the scope of this invention.

[0088] In summary, the adjustable frequency clock signal generator of this invention provides a high-resolution solution for accurately correcting the operating frequency to match the specific resonant frequency of individual air pulse generating devices. Through the charge injection / extraction mechanism of a charge-moving capacitor, the charging and discharging of the resistive-capacitive oscillation circuit can be monotonically adjusted with high precision. This method not only ensures reliable frequency adjustment to compensate for process variations but also provides significant advantages such as low-interference operation, reduced jitter, and improved signal isolation by minimizing reliance on active circuitry directly connected to the resistive-capacitive timing path. Therefore, the proposed invention enables air pulse generating devices to achieve optimal sound pressure level performance in sound generation applications while maintaining stable and predictable oscillation behavior.

[0089] The foregoing outlines the features of several embodiments, enabling those skilled in the art to fully understand the various aspects of the invention. Those skilled in the art should recognize that the invention provides a basis for designing or modifying other processes and structures to achieve substantially the same functionality and / or results as the embodiments described above. Furthermore, such equivalent configurations do not depart from the spirit and scope of the invention, and various changes, substitutions, and modifications can be made without departing from that spirit and scope.

Claims

1. A clock signal generator, comprising: An oscillating circuit is used to generate a clock signal. The oscillating circuit includes a comparator and a resistor-capacitor circuit. The resistor-capacitor circuit includes a capacitor; and A charge-moving capacitor is connected to the resistor-capacitor circuit; The frequency of the clock signal is adjusted by injecting or extracting charge associated with the resistor-capacitor circuit via the charge-moving capacitor.

2. The clock signal generator as claimed in claim 1, wherein the resistor-capacitor circuit comprises: A resistor is connected to the capacitor.

3. The clock signal generator as described in claim 2, in, The resistor and the capacitor are connected between a first node and a second node; The oscillation circuit includes a switching circuit coupled to the first node and the second node; During a first period, the switching circuit provides a first voltage to the first node and a second voltage to the second node; During a second period, the switching circuit provides the second voltage to the first node and the first voltage to the second node.

4. The clock signal generator as described in claim 1, in, A first terminal of the charge-moving capacitor is coupled to the resistor-capacitor circuit. In this process, the second terminal of the charge-moving capacitor is switched from a second voltage to a first voltage.

5. The clock signal generator as described in claim 4, in, The second terminal of the charge-moving capacitor receives a first signal containing a rising edge.

6. The clock signal generator as described in claim 5, in, The second terminal of the charge-moving capacitor receives the first signal containing the rising edge during a discharge period.

7. The clock signal generator as described in claim 4, in, The second terminal of the charge-moving capacitor receives a second signal containing a falling edge.

8. The clock signal generator as described in claim 7, in, The second terminal of the charge-moving capacitor receives the second signal containing the falling edge during a charging period.

9. The clock signal generator as claimed in claim 1, comprising: A delay element is coupled between the comparator and the charge-moving capacitor.

10. The clock signal generator as described in claim 9, in, The delay element generates a delayed clock signal to the charge-moving capacitor based on the clock signal output by the comparator.

11. The clock signal generator as described in claim 10, in, The delay element generates the delayed clock signal, which has a delay time relative to the clock signal.

12. The clock signal generator of claim 11, wherein the delay time is adjustable.

13. The clock signal generator as described in claim 11, in, The frequency of the clock signal is adjusted by adjusting the delay time or the capacitance value of the charge-moving capacitor.

14. The clock signal generator as described in claim 13, in, By adjusting the delay time to be longer, the frequency of the clock signal is adjusted to be lower.

15. The clock signal generator as described in claim 13, in, By adjusting the capacitor value to a higher value, the frequency of the clock signal is adjusted to a lower value.

16. The clock signal generator as described in claim 1, in, The waveform of the capacitor voltage at this capacitor contains a spike.

17. The clock signal generator as described in claim 16, in, The surge occurs after a delay following the transition of the oscillating circuit.

18. The clock signal generator as described in claim 16, in, The waveform of the capacitor voltage includes a surge superimposed on an exponentially decreasing voltage during a discharge period of the capacitor.

19. The clock signal generator as described in claim 16, in, The waveform of the capacitor voltage includes a surge superimposed on an exponential increase during a charging period of the capacitor.

20. The clock signal generator of claim 1, wherein the resistor-capacitor circuit comprises: A first capacitor is coupled to a first input terminal of the comparator; and A second capacitor is coupled to a second input terminal of the comparator.

21. The clock signal generator of claim 20, comprising: A first charge-moving capacitor, coupled to the first capacitor; and A second charge-moving capacitor is coupled to the second capacitor.

22. The clock signal generator of claim 21, comprising: A first delay element is coupled between a first output terminal of the comparator and the first charge-moving capacitor; and A second delay element is coupled between a second output terminal of the comparator and the second charge-moving capacitor.

23. The clock signal generator as described in claim 22, in, The first delay element generates a delayed clock signal to the first charge-moving capacitor based on the clock signal output from the first output terminal of the comparator. The second delay element generates a delayed complementary clock signal to the charge-moving capacitor based on a complementary clock signal output from the second output terminal of the comparator.

24. The clock signal generator as described in claim 23, in, The delayed clock signal has a delay time relative to the clock signal; The delayed complementary clock signal has the delay time relative to the complementary clock signal.

25. The clock signal generator as described in claim 20, in, A first waveform of a first capacitor voltage at the first capacitor includes a first spike of a first polarity superimposed on an exponentially decreasing voltage during a discharge period of the first capacitor. Wherein, a second waveform of a second capacitor voltage at the second capacitor includes a second spike with a second polarity superimposed on an exponentially increasing voltage during a charging period of the second capacitor; The first polarity and the second polarity are opposite to each other; The discharge period of the first capacitor coincides with the charging period of the second capacitor.

26. A frequency adjustment method for a clock signal generator, used to adjust the frequency of a clock signal of the clock signal generator, the method comprising: Injecting or extracting charge associated with a resistor-capacitor circuit; in, The clock signal generator includes an oscillation circuit, and the oscillation circuit includes a comparator and the resistor-capacitor circuit. The oscillation circuit generates the clock signal.

27. The frequency adjustment method as described in claim 26, comprising: Charge associated with the resistor-capacitor circuit is injected or extracted via a charge-moving capacitor connected to the resistor-capacitor circuit.

28. The frequency adjustment method of claim 27, wherein the step of injecting the charge via the charge-moving capacitor comprises: During a discharge period of one capacitor in the resistor-capacitor circuit, the voltage at one end of the charge-moving capacitor is increased.

29. The frequency adjustment method of claim 27, wherein the step of extracting the charge via the charge-moving capacitor comprises: During a charging period of a capacitor in the resistor-capacitor circuit, the voltage at one end of the capacitor is reduced by the charge transfer.

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