Non-scannable flip-flop for scannable digital circuits

Abstract

The implementations described herein relate to non-scannable flip-flops used within scannable digital circuits. For example, one illustrative method includes: determining that a first propagation delay of a first stage of combinational logic is greater than a delay threshold, the first stage preceding a first scannable flip-flop within a scannable digital circuit design; and based on this determination, modifying the scannable digital circuit design to integrate a multiplexing function controlled by a scan enable signal into the first stage, and converting the first scannable flip-flop to a non-scannable flip-flop. The method further includes: determining that a second propagation delay of a second stage of combinational logic is less than a delay threshold, the second stage preceding a second scannable flip-flop within a scannable digital circuit design; and based on this determination, retaining the second scannable flip-flop in the circuit design. Corresponding methods, circuits, media, and other implementations are also disclosed.

Description

Background Technology

[0001] Microscopic digital circuit systems, such as those found within processors (e.g., central processing units (CPUs), graphics processing units (GPUs), microprocessors, etc.) or other integrated circuits (e.g., application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), etc.), can be so small and complex that verifying the correctness and reliability of the circuit system without special configuration is virtually impossible. Therefore, scanable digital circuits refer to those digital circuits that have been designed with specific features to enhance their testability. For example, scan chains can be integrated into circuit systems to improve the controllability and observability of the circuit's internal states, thereby facilitating efficient and effective testing of complex digital circuit systems. Summary of the Invention

[0002] To test complex digital circuit systems (e.g., CPUs, GPUs, other processors, and / or complex integrated circuits) for proper functionality and reliability, scan chains and / or other specific features can be integrated into the circuit system to enable and / or facilitate testing. For example, registers and other synchronous memory components within a design can be implemented using flip-flops, which can be configured to operate in either a normal mode (for the circuit system's regular functionality) or a scan mode (for testing the circuit system). While such flip-flops offer significant benefits to the circuit (e.g., allowing for robust testing), they can also incur significant costs, especially when they are located on timing-critical paths (e.g., paths where digital signals propagate from one flip-flop through a series of combinational logic steps to the next flip-flop over nearly a full clock cycle). Therefore, the methods and apparatus described herein relate to how certain flip-flops within a digital circuit design can be converted into non-scanned flip-flops that do not present the same timing and / or power consumption challenges as fully scanned digital circuits, while retaining all the benefits of fully scanned digital circuitry.

[0003] In some aspects, the technology described herein relates to a scanable digital circuit comprising: a first stage of combinational logic configured to perform a multiplexing function controlled by a scan enable signal at the output of the first stage; a first flip-flop configured to receive the output of the first stage after the multiplexing function is performed, the first flip-flop being a non-scanable flip-flop; a second stage of combinational logic; and a second flip-flop configured to receive the output of the second stage, the second flip-flop being a scanable flip-flop configured to perform the multiplexing function controlled by a scan enable signal.

[0004] In some aspects, the techniques described herein relate to a method comprising: determining that a first propagation delay of a first stage of combinational logic is greater than a delay threshold, the first stage preceding a first scannable flip-flop within a scannable digital circuit design; modifying the scannable digital circuit design based on determining that the first propagation delay is greater than the delay threshold to: integrate a multiplexing function controlled by a scan enable signal into the first stage at the output of the first stage, and convert the first scannable flip-flop to a non-scannable flip-flop; determining that a second propagation delay of a second stage of combinational logic is less than a delay threshold, the second stage preceding a second scannable flip-flop within the scannable digital circuit design; and retaining the second scannable flip-flop in the scannable digital circuit design based on determining that the second propagation delay is less than the delay threshold.

[0005] In some aspects, the techniques described herein relate to a non-transitory computer-readable medium storing instructions that, when executed, cause a processor of a computing device to perform the following processes: determining that a first propagation delay of a first stage of combinational logic is greater than a delay threshold, the first stage preceding a first scannable flip-flop within a scannable digital circuit design; modifying the scannable digital circuit design based on determining that the first propagation delay is greater than the delay threshold to: integrate a multiplexing function controlled by a scan enable signal into the first stage at the output of the first stage and convert the first scannable flip-flop to a non-scannable flip-flop; determining that a second propagation delay of a second stage of combinational logic is less than a delay threshold, the second stage preceding a second scannable flip-flop within the scannable digital circuit design; and retaining the second scannable flip-flop in the scannable digital circuit design based on determining that the second propagation delay is less than the delay threshold.

[0006] Other implementations may perform similar functions as described above and / or may use other types of hardware to perform the functions. Some implementations may involve systems, apparatuses, circuits, media, and / or combinations thereof employing scannable digital circuits as described herein and / or techniques used to design such circuits.

[0007] Details of these and other implementations are set forth in the accompanying drawings and the description below. Other features will also become apparent from the following description, drawings, and claims. Attached Figure Description

[0008] Figure 1 This paper illustrates how illustrative scannable digital circuits can be modified according to the principles described herein to replace certain aspects of scannable flip-flops with non-scannable flip-flops.

[0009] Figures 2A to 2C The functional aspects of a scannable flip-flop based on the principles described herein are illustrated, along with several alternative ways to produce the desired behavior of a scannable flip-flop within a scannable digital circuit.

[0010] Figure 3 An illustrative method for implementing a non-scannable flip-flop within a scannable digital circuit is shown, based on the principles described herein.

[0011] Figure 4 A first example modification of a scannable digital circuit, based on the principles described herein, is shown for replacing a scannable flip-flop with a non-scannable flip-flop.

[0012] Figures 5A to 5D An illustrative logic gate based on the principles described herein is shown. Figure 4 In the example modification, the logic gate can be overloaded to be used concurrently for both executing logical functions and reusing functions.

[0013] Figure 6 Additional example modifications to a scannable digital circuit, based on the principles described herein, are shown for replacing scannable flip-flops with non-scannable flip-flops.

[0014] Figure 7 Two scanned digital circuits are shown, based on the principles described herein, for comparing a scanned digital circuit design that relies solely on scanned flip-flops with a scanned digital circuit design that incorporates at least one non-scanned flip-flop.

[0015] Figures 8A to 8B An illustrative application of the principles described herein for a scannable digital circuit employing a non-scannable flip-flop is shown.

[0016] Figure 9 An illustrative computing device is shown that can be incorporated into and / or used for designing scannable digital circuits employing non-scannable flip-flops, based on the principles described herein. Detailed Implementation

[0017] This paper describes methods and apparatus related to scannable digital circuit systems employing non-scannable flip-flops. Scannable flip-flops are typically deployed throughout the design of scannable digital circuits to enable and facilitate circuit testing. However, the scannable nature of such flip-flops, compared to non-scannable flip-flops, results in longer set-time requirements, which may limit the maximum clock frequency that the circuit design can support if the flip-flops are used on relatively critical paths. Therefore, the implementation described herein involves replacing scannable flip-flops with non-scannable flip-flops on certain critical paths of the circuit design, while maintaining full scannability throughout the design.

[0018] Various types of processors and other complex digital electronic devices can comprise microscopic circuit systems so small and complex that it is virtually impossible to verify their correctness and reliability without special setups for testing to support the design. This concept is sometimes referred to as Design for Testability (DFT) and can be applied to central processing units (CPUs), graphics processing units (GPUs), other types of processors (e.g., microprocessors), and other complex digital electronic devices (e.g., application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), etc.). As used herein, digital circuits designed to have specific features to enhance their testability (e.g., using DFT principles and methods described herein) are called scannable digital circuits.

[0019] A tool that can be integrated into digital circuits based on the DFT principle is called a scan chain. Scan chains can be integrated into processors or other complex synchronous designs to improve the controllability and observability of the circuit's internal states, thereby facilitating efficient and effective testing of the circuit system. Scan chains can be included within synchronous digital circuit designs, such as processors and other circuits mentioned above.

[0020] As used herein, a digital circuit can be referred to as synchronous when a digital signal within a circuit is configured to propagate through combinational logic during a clock cycle and then latched at a specific portion of each clock cycle (e.g., on each rising edge of the clock signal, on each falling edge of the clock signal, etc.) by a memory element called a flip-flop. A flip-flop is a one-bit memory or storage element configured to latch (e.g., capture and store) the binary state of a digital signal as high (e.g., a logic value of "1") or low (e.g., a logic value of "0") when a specific portion of the clock signal is detected (e.g., a rising edge or a falling edge).

[0021] To insert a scan chain into a synchronous design, flip-flops within the design can be configured to operate not only in a normal operating mode (where the flip-flops facilitate the desired functional operation of the digital circuitry) but also in a scan mode that facilitates testing of the digital circuitry. The scan mode can be enabled when a general signal, called the scan enable signal, is in a state (e.g., high), otherwise the normal mode is enabled (e.g., in this example, when the scan enable signal is low). When the scan enable signal puts the digital circuitry into scan mode, the flip-flops within the circuitry can be interconnected to form a long shift register (called a scan chain). In this way, a data pattern can be passed through all the flip-flops in the scan chain by shifting data into the scan chain at a specific scan input point (e.g., a flip-flop at the beginning of the scan chain) and reading the data at the scan output point (a flip-flop at the end of the scan chain).

[0022] In this way, by inserting known data patterns into the scan chain and verifying the expected data patterns read from the scan chain, a large number of flip-flops (e.g., thousands, millions, or billions of flip-flops in some designs) can be functionally tested. In this way, the scan chain within a digital design allows for both: 1) controllability of the circuit (e.g., setting the state of flip-flops by shifting data into the scan chain to effectively control the inputs of combinational logic), and 2) observability of the circuit (e.g., detecting the state of flip-flops by removing data from the scan chain to effectively observe the outputs of combinational logic and the results of logical operations performed by the circuit). Therefore, scan chains can be useful for at least the following: 1) testing highly complex digital circuits (e.g., CPUs, GPUs, etc.) with potentially billions of transistors where exhaustive testing in other ways (e.g., by trying to test every possible combination of inputs) is impractical; 2) performing fault detection for difficult-to-detect problems—such as stuck-at faults (where signal lines are fixed at logic 0 or 1), bridging faults (where two signal lines are shorted together), and / or other manufacturing defects); and 3) implementing automated test patterns and test vectors, etc.

[0023] While scanable flip-flops can offer significant benefits to synchronous digital circuits (e.g., allowing circuits to implement scan chains that facilitate robust testing, as described above), certain technical problems can also arise from their use. One technical problem associated with scanable flip-flops involves the timing and power limitations they may impose on circuit designs, as will now be described.

[0024] As mentioned above, synchronous digital circuit design includes stages of combinational logic separated by flip-flops (e.g., logic gates through which digital signals propagate), which are configured to capture and store (i.e., latch) signals at the same point in each clock cycle. Thus, for example, at the first rising edge of a general clock signal provided to a set of flip-flops in the design (e.g., within a specific clock domain within a design that may include multiple clock domains associated with different clocks), a digital signal can be latched by a first flip-flop and begin propagating through the first stage of the combinational logic. When the second rising edge of the clock signal (i.e., the rising edge immediately following the first rising edge) arrives, the signal may have already propagated through the first stage of the logic, allowing a second flip-flop to latch the signal. The signal will then begin propagating through the second stage of the combinational logic so that it is latched at a third flip-flop when the third rising edge of the clock signal occurs, and so on.

[0025] To be correctly latched at a specific flip-flop, a signal must reach a stable level or value (e.g., high or low) by the specific settling time associated with the flip-flop. For example, if a flip-flop has a 30 picosecond (ps) settling time, the signal must have propagated through the combinational logic stages preceding the flip-flop at least 30 ps before the clock edge that will latch the signal at the flip-flop (in order to reach a stable high or low value). If the combinational logic stages prevent the signal from meeting this settling time requirement, an incorrect value may be latched, and various problems may occur (e.g., the circuit may not function as expected). Therefore, part of the design of synchronous circuits involves analyzing every possible path that a digital signal can take from one flip-flop to another (e.g., through various different stages of combinational logic) to determine the longest possible path that can be taken within a given clock domain. If the longest path through the various stages of combinational logic (also known as the critical path) takes T... PD (Propagation delay time) is a time interval of units, and the set time of the trigger after the level has T. S If the set time of the trigger is in units, then the time period used to synchronize the clock signal for this clock domain should not be less than T. PD and T S The sum of all values. For example, if the critical path has a propagation delay of 950 picoseconds (ps) (T... PD The trigger has a 50ps settling time (T). sIf the clock period is not less than 950 ps + 50 ps = 1000 ps = 1.0 nanosecond (ns), then the clock period should be no less than 950 ps + 50 ps = 1000 ps = 1.0 nanosecond (ns). In other words, the clock frequency of the clock signal used to synchronize this logic level with this flip-flop should not be faster than 1.0 gigahertz (GHz) (because a 1.0 GHz clock has a 1.0 ns period). It should be understood that certain other details of the flip-flop (e.g., hold time, propagation delay through the flip-flop itself, clock skew, and jitter considerations, etc.) are ignored or incorporated into the example values ​​given for the purposes of this example.

[0026] Generally, it may be desirable to clock the logic at or near its maximum frequency while still ensuring that settling times and other requirements are met. For example, the faster the processor is clocked, the more operations it can perform in a given amount of time, thereby optimizing processor performance. Then, conventionally, critical paths in the design can be identified, allowing modification of combinational logic to reduce the total length of those paths (while still meeting settling times). For example, referring to the numerical example above, if the T value on the most critical path is 950 ps... PD If it can be reduced by 25 ps to 925 ps, then the clock period can be reduced because 925 ps (T PD ) + 50 ps (T S = 975 ps. In this example, the maximum clock frequency can therefore be increased by approximately 25 MHz to 1.025 GHz without any risk of the setup times on these critical paths not being met.

[0027] Typically, the settling time of scannable flip-flops is fixed (based on the design of the scannable flip-flop template or cell used throughout the design), necessitating changes to the combinational logic across various logic levels to increase the maximum clock frequency (called the clock's F). MAX However, once the combinational logic has been modified to be as compact and efficient as possible (e.g., to achieve the shortest possible critical path while still achieving the desired functionality), further reducing the minimum time interval (or equivalently, increasing F) is acceptable. MAX This becomes a technical problem. In other words, there may be timing-related technical problems where the circuitry cannot be reliably clocked faster than allowed by the constraints imposed by the critical path of the combinational logic.

[0028] To some extent, digital circuit systems (e.g., combinational logic and / or flip-flops) can be made to operate faster by implementing transistors with lower threshold voltages that switch more quickly. However, as the speed of transistor state transitions increases and the voltage threshold decreases, another technical problem arises related to the power consumed by the circuit system. Lower threshold voltages are not only associated with higher speeds but also with more leakage current, which means that at the typically high maximum clock frequency (F... MAX There is a certain degree of trade-off between the design constraints described above and the generally expected low power consumption. Therefore, the technical problems caused by the design constraints described above can be framed as time-dependent problems (e.g., increasing F without increasing power consumption once the conventional path associated with shortening the critical path through combinational logic is exhausted). MAX The challenges) and power-related issues (e.g., once those same conventional pathways have been fully explored, without reducing F) MAX The challenge of reducing power consumption in the context of either or both.

[0029] At least one technical solution to these technical problems involves implementing non-scannable flip-flops within a scannable digital circuit according to the principles described herein. While DFT parameters and requirements may necessitate full scannability in a design, the methods and techniques described herein allow scannable flip-flops commonly used to implement the scan chains described above to be replaced with non-scannable flip-flops without affecting the functionality of the scan chain. One technical effect of this replacement is that non-scannable flip-flops can have significantly less set-time than similar scannable flip-flops (e.g., scannable flip-flops consuming approximately the same power or having approximately the same threshold voltage). Therefore, implementing non-scannable flip-flops for certain critical paths (but not all paths) within a scannable digital circuit design can serve as a technical solution to the above-described technical problems because critical set-time can be reduced rather than propagation delay time (or critical set-time can be reduced in addition to propagation delay time after techniques outside the scope of this disclosure have been used to make the propagation delay time as efficient as possible).

[0030] For example, referring back to the numerical example provided above, if the propagation delay through the critical path of combinational logic may not be less than 950 ps, ​​the implementation described in this paper can allow a non-scannable flip-flop with a settling time of only 20 ps to replace a scannable flip-flop with a settling time of 50 ps. For example, if this flip-flop transition results in only a 5 ps increase in propagation delay at the combinational logic level, the scan chain can remain unchanged, and the power consumption of the circuit can remain approximately the same (because the threshold voltage is not changed in this example); however, the clock duration and F... MAX The T that it depends on PD and T SThe sum can be reduced to the same amount of time mentioned in the example above (e.g., 955 ps + 20 ps = 975 ps). Therefore, again as in the example above, F MAX It is safe to increase the MHz by 25 to reach 1.025 GHz.

[0031] As will be described in detail herein, by deconstructing the scan characteristics of the trigger and integrating the scan characteristics with the preceding combinational logic level in a way that reduces settling time more than the added combinational propagation delay time, non-scannable triggers can replace scannable triggers even while maintaining scannable functionality. For example, as will be described and illustrated below, one or more gates at the output of the combinational logic level can be overloaded to perform both their logical functions (the functions these gates are used for in the logic level) and the multiplexed functions that would otherwise be performed by the scannable triggers. By configuring one or more gates to concurrently perform multiple roles in this way, the overall critical path can be slightly shortened, making T... PD + T S The overall value is reduced. As another example, by removing logic from a non-scannable flip-flop responsible for multiplexing functions and adding that logic to a combinational logic level, certain logic gates (e.g., those responsible for buffering functions that may no longer be needed) can be eliminated in a similar way, shortening the critical path. In these and other examples, at least one technical effect of shortening the most critical path within a design can be that the F-value associated with clocking the circuit can be increased. MAX This can reduce the power consumption of the circuit (e.g., by using transistors with higher threshold voltages), or a combination of these two benefits can be pursued to best serve the goals of the circuit design.

[0032] Various implementations will now be described in more detail with reference to the accompanying drawings. It should be understood that the specific implementations described below are provided as non-limiting examples and can be used in various situations. Furthermore, it should be understood that other implementations not expressly described herein may also fall within the scope of the claims set forth below. Non-scannable flip-flops implemented for scannable digital circuits in the manner described herein can produce any or all of the technical effects mentioned above, as well as various additional and / or alternative beneficial technical effects described below and / or becoming apparent.

[0033] Figure 1 This illustrates how illustrative scannable digital circuits, based on the principles described herein, can be modified to replace certain aspects of scannable flip-flops with non-scannable flip-flops. More specifically, such as Figure 1As shown, a portion of the scannable digital circuit 102-A shown above the dashed line can be modified according to the principles described herein to become the analog portion of the scannable digital circuit 102-B, which exhibits the same functionality and overall behavior as the scannable digital circuit 102-A, but with improved timing and / or power characteristics, as will be further described below. While in Figure 1 Only a small part of the corresponding scannable digital circuitry is shown (e.g., two flip-flops on the critical path and the combinational logic between them), but it should be understood that the same or similar principles described in this part about scannable digital circuitry can be more broadly applied to multiple critical paths (e.g., dozens, hundreds, or thousands of paths) to achieve the goal of a particular implementation.

[0034] As shown, the scannable digital circuit 102-A includes a stage 104-A of combinational logic preceding the flip-flop 106-A. The illustration at the top of the figure (Key) (will be understood as applicable to this disclosure) Figure 1 As indicated by the illustrations in the other figures described further below, flip-flop 106-A can be implemented as a scannable flip-flop that includes not only a data input (D_In) and a data output (D_Out), but also a special configuration for testability using the techniques already described (e.g., scan chains and / or other DFT capabilities). More specifically, as shown, flip-flop 106-A includes a scan input (S_In) for receiving inputs provided by a previous flip-flop (not shown explicitly in this figure) within the scan chain and a scan enable (S_En) for selecting whether flip-flop 106-A latches and outputs either: 1) the data input D_In (for use during normal mode, which facilitates the functional operation of the circuit), or 2) the scan input S_In (for use during scan mode, which facilitates the testing of the circuit in the manner described above). Flip-flop 106-A is also shown to include a clock input (marked with a triangle at the bottom of the flip-flop) that controls when the flip-flop captures / latches new data for storage.

[0035] like Figure 1As shown in the implementation of the scannable digital circuit 102-A, the data input (D_In) of flip-flop 106-A receives the digital signal that has been propagated through stage 104-A, the clock input receives the digital clock signal (CLK), the scan input (S_In) receives the SCAN_IN signal from another flip-flop (not shown), which will be assumed to have a less critical path than the path represented by stage 104-A, and the scan enable input (S_En) receives the SCAN_EN signal, which is generalizable throughout the circuit (and therefore not as helpful as the digital input signal for any critical timing path). The data output (D_Out) will be understood as providing a path that can propagate through additional stages of combinational logic to subsequent flip-flops. Figure 1 The output signal (not shown in the image).

[0036] As further illustrated in the scannable digital circuit 102-A, in the entire data flow (which in this example will be understood as moving from left to right), flip-flop 108 may precede stage 104-A of combinational logic, which precedes flip-flop 106-A. As indicated by the illustration (“Other Flip-Flops”), this flip-flop 108 may represent any suitable one or more flip-flops (e.g., one or more scannable flip-flops, non-scannable flip-flops, etc.) that provide a digital signal propagating through stage 104-A and ultimately latched by flip-flop 106-A. Implementation details of flip-flop 108 are not detailed in the provided text. Figure 1 The details are shown here because they may be irrelevant to the analysis of stage 104-A and flip-flop 106-A being described. However, note that in this example, flip-flop 108 is shown to be clocked by the same clock signal as flip-flop 106-A, thus indicating that these flip-flops are in the same clock domain.

[0037] The brackets above stage 104-A and flip-flop 106-A indicate specific timing parameters that can be determined for these components. For example, if the scannable digital circuit 102-A is in the design phase, these timing parameters can be determined by measuring similar circuits, simulating delays in design software, based on known timing parameters of the cells used in the design, or in other suitable ways. More specifically, as shown, the propagation delay of the digital signal through stage 104-A can be determined by the parameter T. PD_A This indicates that the settling time for trigger 106-A can be determined by parameter T. S_A As stated above, in order for the scannable digital circuit 102-A to function correctly, the clock signal used for clocking flip-flops 106-A and 108 should have a maximum frequency (F) corresponding to a clock period not longer than the sum of the propagation delay through combinational logic and the set-off time of the flip-flops. MAX (that is, F) MAXThe time period should be less than or equal to T. PD_A + T S_A In other words, if we assume the flip-flop is configured to latch on the rising edge of the clock signal (CLK), then the digital signal must be set for at least the time T before the next rising edge after the first rising edge. S_A The propagation must pass through stage 104-A of the combinational logic to reach stability at flip-flop 106-A.

[0038] Similarly, the scannable digital circuit 102-B in Figure 1 The diagram shows stage 104-B, which includes combinational logic preceding flip-flop 106-B. As indicated in the legend, and in contrast to flip-flop 106-A, flip-flop 106-B can be implemented as a non-scannable flip-flop. This non-scannable flip-flop includes a data input (D_In), a data output (D_Out), and a clock input (represented by a triangle), but does not include the scan input and scan enable provided by the scannable flip-flop 106-A for the testability configuration described above. As already described, this non-scannable flip-flop 106-B has the advantage of a significantly reduced settling time. In other words, the settling time T of flip-flop 106-B is significantly reduced. S_B It can be less than the set time T of trigger 106-A. S_A However, it may still be expected that trigger 106-B will be included within the scan chain, supporting the scannability and testability features already described. Therefore, as... Figure 1 As shown and further described below, the logic required to support scannable features (e.g., including multiplexing functions for selecting between data input signals and scan input signals) can be deconstructed and extracted from the scannable flip-flop unit, and then implemented together with stage 104-B or as part of stage 104-B. For example, as represented by multiplexer 110 in scannable digital circuitry 102-B, the multiplexing function associated with scannable flip-flop 106-A can be extracted from the scannable flip-flop, making it possible to use non-scannable flip-flop 106-B instead.

[0039] As will be described in more detail below, this modification from a scannable digital circuit 102-A with a scannable flip-flop 106-A to a scannable digital circuit 102-B with a non-scannable flip-flop 106-B can reduce the total propagation time and allow the circuit system of the scannable digital circuit 102-B to potentially operate at a higher frequency (i.e., a larger F) than the circuit system of the scannable digital circuit 102-A. MAXThis is performed in a clock-processed manner. For illustration, the brackets above stage 104-B and flip-flop 106-B indicate the corresponding timing parameters that can be determined for these elements (in a similar manner to those described above for the scannable digital circuit 102-A). For example, the propagation delay of the digital signal from flip-flop 108 through stage 104-B and multiplexer 110 can be determined by parameter T. PD_B This indicates that the settling time for trigger 106-B can be determined by parameter T. S_B This means, as described above, that in order for the scannable digital circuit 102-B to function correctly, the clock signal used for clocking flip-flops 106-B and 108 should have a maximum frequency (F) corresponding to a clock period no longer than the sum of the propagation delay through combinational logic and the set-off time of the flip-flops. MAX (that is, F) MAX The time period should be less than or equal to T. PD_B + T S_B In other words, if we assume the flip-flop is configured to latch on the rising edge of the clock signal (CLK), then the digital signal must be set for at least the time T before the next rising edge after the first rising edge. S_B The propagation occurs through the combinational logic of stage 104-B and the multiplexer 110 (in some examples, the multiplexer can be considered part of stage 104-B) before stabilizing at flip-flop 106-B.

[0040] Modifications to the circuitry used to extract multiplexing functionality from flip-flops (e.g., scannable flip-flop 106-A) and implement that multiplexing functionality in a preceding logic level (e.g., multiplexer 110 associated with level 104-B) can be performed in a manner that improves the overall timing. For example, as indicated by the markings on the dashed lines separating scannable digital circuitry 102-A and scannable digital circuitry 102-B, the circuitry can be "MODIF[IED]" such that: (T PD_A + T S_A ) > (T PD_B +T S_B Therefore, before modifying the scannable digital circuit design (e.g., the design of scannable digital circuit 102-A), the scannable digital circuit design is configured to be clocked at the maximum frequency (F). MAX It can be compared with a specific delay threshold and the set time (T) for scannable triggers. S_A The sum of the first time intervals corresponds to a longer duration, and after modifying the scannable digital circuit design (e.g., the design of scannable digital circuit 102-B), the scannable digital circuit design is configured to be clocked at the maximum frequency (F). MAX() shorter than or equal to the delay threshold and the settling time (T) for the scannable trigger S_A The second time period corresponds to the sum of () and (). For example, the second time period can be equal to T. PD_B and T S_B The sum, as mentioned above, can be less than T. PD_A and T S_A The sum of . In some examples, this difference can allow the scannable digital circuit 102-B to meet a target delay threshold that the scannable digital circuit 102-A cannot meet, as will be further described below.

[0041] To illustrate using the number of examples from the numerical examples above, in a particular implementation, T PD_A It can be 950 ps, ​​while T S_A It can be 50 ps. In this example, the minimum time interval (i.e., T) PD_A and T S_A The sum of these values ​​would therefore be 1000 ps (i.e., 1.0 ns), and the F-switches used in the scannable digital circuit 102-A would be... MAX It will be 1 GHz. However, after modifications to the design used to generate the scannable digital circuit 102-B, the propagation delay T of stage 104-B and multiplexer 110... PD_B It can be slightly increased to 955 ps, while the settling time T of the non-scannable trigger can be increased. S_B This is significantly reduced to 20 ps. Therefore, the overall minimum time period (i.e., T) PD_B and T S_B The sum of these parameters can be reduced to 975 ps (i.e., 0.975 ns), and the F-switches used in the scannable digital circuit 102-A can be reduced to 975 ps (i.e., 0.975 ns). MAX It can be increased to 1.025 GHz. These values ​​will be understood to be provided for illustrative purposes only, and in other implementations, F MAX The increase can be less or more.

[0042] Even when the timing conditions are improved to allow for an increase in the maximum frequency (e.g., from 1.0 GHz to 1.025 GHz in the numerical example above), it should be noted that the functions of both scannable digital circuits 102-A and 102-B can be identical. For example, while the SCAN_IN and SCAN_EN signals can be input to the scannable flip-flop 106-A in scannable digital circuit 102-A, these signals can instead be input to a multiplexer 110 outside the non-scannable flip-flop 106-B in scannable digital circuit 102-B. In both cases, the multiplexing function can be performed to achieve the same result (e.g., the scan chain and scannability functions described above), but the timing parameters are shown to be improved for scannable digital circuit 102-B compared to scannable digital circuit 102-A.

[0043] It should also be understood that, as mentioned above, the advantageous timing parameters implemented by the scannable digital circuit 102-B can be additionally or alternatively applied to achieve more advantageous power parameters (e.g., in a particular implementation, power consumption is higher than F). MAX (In cases of more significant design constraints). For example, before modifying a scannable digital circuit design (e.g., the design of scannable digital circuit 102-A), the scannable digital circuit design could be configured to generate a first power consumption when clocked at a specific maximum frequency. Then, after modifying the scannable digital circuit design (e.g., the design of scannable digital circuit 102-B), the scannable digital circuit design could be configured to generate a second power consumption when clocked at the same maximum frequency, where the second power consumption is lower than the first power consumption. In other words, timing can be improved, but instead of applying the improvement to the maximum frequency, the improvement can be applied to power consumption by using, for example, different transistors that implement the same logic and flip-flops but have higher threshold voltages (thus trading timing improvement for power consumption improvement). In some examples, improvements that can be implemented in this way can be applied to both the timing and power consumption of the circuit.

[0044] To illustrate how scannable digital circuits such as 102-A and 102-B can maintain the same functionality even with different timing and / or power consumption characteristics (e.g., transistor threshold voltages, etc.), Figures 2A to 2C A scannable trigger is shown. Figure 2A Regarding the functionality of the scannable flip-flop, and several alternative ways to generate the expected behavior of the scannable flip-flop by using logic gates at the output of the combinational logic level preceding the non-scannable flip-flop, the following points are considered. Figure 2B and Figure 2C ).

[0045] Figure 2AThe circuit system 202-A is shown, which includes DATA_IN, SCAN_IN, and SCAN_EN signals provided from a combinational logic stage (to the left of the dashed line, as labeled) to a scanable flip-flop 204-A (to the right of the dashed line, as labeled). Figure 1 As indicated by the illustration, the scanable flip-flop 204-A can be similar to the flip-flop 106-A described above. Figure 206 illustrates the functionality of the circuit system 202-A. More specifically, for each possible combination of the SCAN_EN, DATA_IN, and SCAN_IN inputs (assuming these are each digital signals that can only be in a high or low state), Figure 206 shows the DATA_OUT signal that the scanable flip-flop 204-A can latch and output.

[0046] As shown, the SCAN_EN signal can act as a multiplexer select signal to select between DATA_IN and SCAN_IN. Specifically, when SCAN_EN is low (i.e., scan mode is off, allowing the circuit to operate in normal mode), the DATA_OUT signal follows the DATA_IN signal, regardless of the SCAN_IN signal. Conversely, when SCAN_EN is high (i.e., scan mode is on, allowing the circuit to operate in scan mode), the DATA_OUT signal follows the SCAN_IN signal, regardless of the DATA_IN signal.

[0047] Figure 2B The circuit system 202-B is shown, which includes the same DATA_IN, SCAN_IN, and SCAN_EN signals processed within a stage of combinational logic (on the left side of the dashed lines, as marked) before reaching the non-scannable flip-flop 204-B (to the right of the dashed line, as labeled). Figure 1 As indicated by the diagram, the non-scannable trigger 204-B can be similar to the trigger 106-B described above. Figure 2B The text also shows information about... Figure 2AThe same diagram 206 is described. This shows that the logic implementation in circuit system 202-B is a multiplexed function of the same logic inside the scannable flip-flop 204-A in circuit system 202-A. More specifically, for each possible combination of the SCAN_EN, DATA_IN, and SCAN_IN inputs (assuming these are each digital signals that can only be high or low), diagram 206 again shows that the DATA_OUT output signal, latched and output by the non-scannable flip-flop 204-B, can follow DATA_IN when SCAN_EN is low, and can follow SCAN_IN when SCAN_EN is high. It should be understood that the ~SCAN_EN signal is the inverted signal of the SCAN_EN signal.

[0048] Figure 2C The circuit system 202-C is shown, which includes the same DATA_IN, SCAN_IN, and SCAN_EN signals processed by different gates (on the left side of the dashed lines, as labeled) within a stage of combinational logic before reaching the non-scannable flip-flop 204-C (on the right side of the dashed line, as labeled) to achieve the same result. The non-scannable flip-flop 204-C can be similar to the non-scannable flip-flop 204-B and flip-flop 106-B described above (see [link to diagram]). Figure 1 (Legend in the diagram), and in Figure 2C The text again shows the connection to what was previously discussed. Figure 2A and Figure 2B The same diagram 206 is described. More specifically, diagram 206 again shows how the logic in circuit system 202-C implements the same multiplexing function as the logic implemented inside the scannable flip-flop 204-A in circuit system 202-A and the combinational logic implemented outside the non-scannable flip-flop 204-B in circuit system 202-B.

[0049] Instead of two AND gates and one OR gate (as used in circuit system 202-B), the example of circuit system 202-C uses three NAND gates, which can be implemented more efficiently using semiconductor technology. In any case, Figures 2A to 2C The combination illustrates that the same function can be achieved in multiple ways using different types of flip-flops and different types of combinational logic (e.g., different combinations of logic gates). Although Figure 2B and Figure 2C Each of these illustrates how non-scannable flip-flops can be combined with combinational logic to functionally replace scannable flip-flops (such as...). Figure 2AThe examples of circuit systems 202-B and 202-C (such as the scannable flip-flop 204-A) are provided as examples of potential implementations, but it should be understood that these examples do not exhaust the various ways in which a circuit logically equivalent to circuit 202-A can be implemented. Various other types and / or combinations of logic gates (e.g., AND, NAND, OR, NOR, XOR, XNOR, etc.) can also be used.

[0050] Figure 3 An illustrative method 300 for implementing a non-scannable flip-flop within a scannable digital circuit, based on the principles described herein, is shown. For example, method 300 can be executed by a computing system including a processor that executes some or all of the instructions configured to implement operations 302 to 310 of method 300. In other words, in some implementations, method 300 can be performed entirely as an automated process. In other implementations, one or more operations in the process can be performed manually or with assistance, for example, by other manufacturing equipment and / or personnel (e.g., the designer of the scannable digital circuit).

[0051] Although Figure 3 Illustrative operations according to a particular implementation are shown; however, it should be understood that other implementations of this method may omit, add, reorder, and / or modify any operation explicitly stated in method 300. Furthermore, although the operations of method 300 are shown with arrows indicating the order of operations, it should be understood that one or more operations in method 300 may be performed concurrently (e.g., in parallel). As will be described in more detail below, operations 302 to 308 of method 300 may relate to planning and designing scannable digital circuits and may be performed by a computing system executing design software under the guidance of a designer or other user. Operation 310 may then relate to manufacturing, fabricating, constructing, or otherwise implementing the design created using operations 302 to 308. Thus, this operation may relate to computer-aided manufacturing equipment, such as a semiconductor fabrication system. Method 300 will now be described in more detail.

[0052] At operation 302, the computing system (which can execute digital circuit design software) can determine that a first propagation delay of the first stage of the combinational logic is greater than a delay threshold. For example, the first stage of the combinational logic may precede a first scannable flip-flop within a scannable digital circuit design. The delay threshold may be associated with a target propagation delay of the data path within a specific clock domain for the scannable digital circuit being designed. For example, to use the quantitative example mentioned above, it might be desirable to use a scannable flip-flop cell with a settling time equal to 50 ps to propagate F... MAXThe frequency is set to 1.025 GHz. Therefore, the propagation delay for each combinational logic stage between the two scannable flip-flops in the design can be targeted to be no more than 925 ps, since the sum of 925 ps and 50 ps will correspond to a target minimum clock period of 975 ps to produce the desired maximum frequency of 1.025 GHz. In this example, the delay threshold can therefore be 925 ps, and at operation 302, the computational system can determine that certain stages of the combinational logic within the design (including the first stage of the combinational logic) have a propagation delay greater than this threshold. In other words, in this example, the first propagation delay of the first stage can be determined to be 950 ps or some other delay longer than 925 ps. It should be understood that operation 302 can be performed after other techniques for optimizing the circuit system have been exhausted, such that even after attempts have been made to make the combinational logic as compact and optimal as possible using conventional techniques, the first propagation delay still exceeds the delay threshold.

[0053] At operation 304, the computing system can modify the scannable digital circuit design based on the determination that the first propagation delay at operation 302 is greater than a delay threshold. As already described, this modification can include at least two aspects, which are represented in method 300 as sub-operations 304-1 and 304-2 of operation 304. Specifically, as a first aspect of the design modification, sub-operation 304-1 instructs the computing system to integrate a multiplexed function controlled by a scan enable signal into the first stage of combinational logic at the output of the first stage. For example, as shown in the examples of circuit systems 202-B and 202-C above, logic gates can be added to the combinational logic stage before the flip-flops to replicate... Figure 2A The scannable flip-flop 204-A is shown in the diagram, which is a multiplexed function. Then, as a second aspect of the design modification, sub-operation 304-2 instructs the computing system to convert the first scannable flip-flop into a non-scannable flip-flop (e.g., as shown in the non-scannable flip-flops 204-B and 204-C following the multiplexed logic of the corresponding circuit systems 202-B and 202-C above). As used herein, this conversion of the flip-flop can be achieved by replacing the scannable flip-flop with a non-scannable flip-flop in the design.

[0054] As mentioned above Figure 1The modification to the scannable digital circuit design at operation 304 can be performed by improving the timing and / or power consumption of the scannable digital circuit in some way. For example, if conventional techniques are insufficient to reduce the first propagation delay of the first stage of the combinational logic below a delay threshold, the modification to the scannable digital circuit can reduce the set-off time of the flip-flop (by converting it from a scannable flip-flop to a non-scannable flip-flop) sufficiently to compensate for the difference between the first propagation delay and the target delay threshold. This can also be true even if the integration of the multiplexing function at sub-operation 304-1 results in an increase in the first propagation delay. For example, referring again to the quantitative example already given, the integration of the multiplexing function at sub-operation 304-1 can increase the first propagation delay from 350 ps to 355 ps, while converting the first scannable flip-flop to a non-scannable flip-flop at sub-operation 304-2 can reduce the flip-flop set-off time from 50 ps to 20 ps. Then, in the final analysis, the sum of the first propagation delay and the set-off time can be reduced overall to allow the target maximum frequency. Specifically, in this example, the sum of 355 ps and 20 ps (for the non-scannable trigger set time) satisfies the target of 375 ps clock segment, but the sum of 350 ps and 50 ps (for the scannable trigger set time) fails to satisfy.

[0055] At operation 306, the computational system can determine that the second propagation delay of the second stage of the combinational logic is less than a delay threshold. Similar to the example of the first stage above, the second stage of the combinational logic can precede the second scannable flip-flop within the scannable digital circuit design. However, in this case, the digital signal must propagate through the combinational logic within the second stage short enough that the second propagation delay is less than the delay threshold. For example, using the example delay threshold of 925 ps described above, the second propagation delay of the second stage can be determined to be only 900 ps or some other suitable value less than the threshold. Then, in this example, the target maximum frequency can be implemented using a scannable flip-flop with a longer settling time (e.g., 50 ps in the quantitative example above).

[0056] Therefore, at operation 308, based on the determination that the second propagation delay at operation 306 is less than the delay threshold, the computing system can retain the second scannable flip-flops in the scannable digital circuit design. Thus, modifications to the scannable digital circuit design at operation 304 can provide certain benefits for more critical data paths, such as those through the first stage of combinational logic, and for such paths, the effort and cost may be worthwhile. However, for less critical data paths, such as those through the second stage of combinational logic, operation 308 shows that the effort required to perform the modification can be avoided, and the original design (using scannable flip-flops) can be used. In scannable digital circuit designs with millions or billions of scannable flip-flops and associated combinational logic stages between them, it may be desirable to make the effort to modify the circuit system only for the most critical data paths, rather than for all scannable flip-flops, in the manner of operation 304. For example, if the computing system determines that 99% of the propagation delay in the design is less than the delay threshold (as in the case of the second propagation delay) and the remaining 1% of the propagation delay in the design is greater than the delay threshold (as in the case of the first propagation delay), then only the circuit modification of operation 304 can be performed to address that 1% propagation delay, while the scannable flip-flops can be retained for the other 99% of the propagation delay.

[0057] At operation 310, the computing system can provide a scannable digital circuit design that allows the scannable digital circuit to be fabricated (e.g., by a chip fabrication system such as those mentioned above). For example, based on the scannable digital circuit design generated using operations 302-308, the fabrication system performing operation 310 can construct the scannable digital circuit as including at least a (modified) first stage of combinational logic, a non-scannable flip-flop, a (unmodified) second stage of combinational logic, and a second scannable flip-flop.

[0058] In some implementations, methods such as method 300 can be embodied as in-memory processes. For example, method 300 can be embodied by instructions stored in storage facilities (e.g., memory) described and illustrated herein. More specifically, a non-transitory computer-readable medium can store instructions that, when executed, cause a processor of a computing device to perform a process embodying method 300. Specifically, when executing instructions on a non-transitory computer-readable medium, the processor can: 1) determine that a first propagation delay of a first stage of combinational logic is greater than a delay threshold, the first stage preceding a first scannable flip-flop within a scannable digital circuit design; 2) modify the scannable digital circuit design based on the determination that the first propagation delay is greater than the delay threshold to: integrate a multiplexing function controlled by a scan enable signal into the first stage at the output of the first stage and convert the first scannable flip-flop to a non-scannable flip-flop; 3) determine that a second propagation delay of a second stage of combinational logic is less than a delay threshold, the second stage preceding a second scannable flip-flop within the scannable digital circuit design; and 4) retain the second scannable flip-flop in the scannable digital circuit design based on the determination that the second propagation delay is less than the delay threshold.

[0059] Now will describe Figures 4 to 6 This provides more detailed examples of how modifications, such as those described regarding Operation 304, can be made to achieve the technical benefits already outlined. Figure 4 A first example modification of a scannable digital circuit is shown, utilizing a non-scannable flip-flop instead of a scannable one. (Combined with...) Figure 4 , Figures 5A to 5D Illustrative logic gates are shown that can be overloaded to be used concurrently for both performing logical functions and reusing functions. Then, Figure 6 An additional example modification of a scannable digital circuit is shown for replacing a scannable flip-flop with a non-scannable flip-flop.

[0060] exist Figure 4In this context, design 402-A is shown as being transformed into a modified design 402-B through modification 404, such as that described above with respect to operation 304 of method 300. More specifically, as shown, design 402-A includes a stage 406-A of combinational logic that may represent a relatively critical data path (e.g., such that the propagation delay associated with stage 406-A may exceed a delay threshold such as those described above). As shown within stage 406-A, the output of stage 406-A may include a specific gate 408. For example, as will be described in more detail below, gate 408 may be any suitable logic gate, such as an AND gate, OR gate, NAND gate, NOR gate, XOR gate, XNOR gate, etc. As shown, gate 408 is located at the output of stage 406-A in such a sense that gate 408 is the last gate (but not the only gate) through which the digital signal can propagate before being latched for the next clock cycle. This is because it should be understood that stage 406-A may include various other gates in the combinational logic that are not explicitly shown.

[0061] For this latch, design 402-A is further shown as including a scannable flip-flop 410-A that receives the DATA_IN signal not only from gate 408 of stage 406-A (and from other logic and flip-flops preceding it, not explicitly shown in the figure), but also the CLK, SCAN_IN, and SCAN_EN signals already described. Scannable flip-flop 410-A is shown as outputting the DATA_OUT signal already described. For example, the DATA_OUT signal may follow the behavior shown above with respect to Figure 206.

[0062] Following modification 404, the modified design 402-B shows a combinational logic stage 406-B feeding its output into a non-scannable flip-flop 410-B that does not possess the same scannable characteristics as the scannable flip-flop 410-A. However, as shown, specific logic 412 can be integrated into stage 406-B to implement the same multiplexing function previously performed by the scannable flip-flop before modification 404. For example, as shown, logic 412 can implement a multiplexer that selects between the DATA_IN and SCAN_IN signals based on the SCAN_EN signal, all of which can be the same as those received by the scannable flip-flop 410-A in design 402-A. As shown, gate 408 can be incorporated into or otherwise integrated within logic 412 to concurrently perform or assist at least two functions: 1) any logic function performed by gate 408 in stage 406-A, and 2) the multiplexing function performed by logic 412.

[0063] In some cases, this integration may involve modifying gate 408 to accept more inputs or to perform different logical functions depending on additional logic 412 added. For example, before modifying the scannable digital circuit design 402-A (at modification 404), stage 406-A may include logic gate 408 at the stage output, which is configured to perform a logical function with respect to the first digital signal and the second digital signal (not shown in the original text). Figure 4 (Explicitly shown in the diagram). Then, after modification 404, the multiplexing function of the scanable flip-flop 410-A can be integrated into the combinational logic stage (now becoming stage 406-B) by introducing logic 412 at the stage output as a replacement and incorporating multiple logic gates with logic gate 408. These multiple logic gates can be configured to perform both the multiplexing function and the logic function previously performed individually by gate 408. For example, gate 408 can represent one of the gates shown in circuit system 202-B or circuit system 202-C above, which can be modified (e.g., to accept a third input, etc.) to continue performing the logic function it previously performed, while also being used to perform the logic function related to... Figures 2A to 2C The described reuse function. In this way, stage 406-B can have a similar propagation delay as stage 406-A before modification 404, and any increase in delay compared to scannable trigger 410-A can be completely offset by the savings in setup time of non-scannable trigger 410-B.

[0064] Gate 408 can be implemented by any suitable type of logic gate in design 402-A, and can remain unchanged or be replaced by one or more suitable types of logic gates that satisfy the criteria described above to continue performing the same logical function while also performing the multiplexed function already extracted from the scanable flip-flop. Several examples illustrating how gate 408 can be implemented are provided below. Figures 5A to 5D An illustrative logic gate is shown, which, after modification 404, can be overloaded to be used concurrently to perform both the illustrated logic function and the multiplexed function already described.

[0065] For example, Figure 5AAn implementation is illustrated in which logic gate 408 is an AND gate 502-A that accepts a first digital signal (IN_1) and a second digital signal (IN_2) and is configured to produce an output signal (OUT) representing: 1) a logic high value when both the first and second digital signals represent logic high values; and 2) a logic low value otherwise. This logic function is illustrated by diagram 504-A, which shows that the OUT signal is low for each combination of IN_1 and IN_2, except when both IN_1 and IN_2 are high. Therefore, if the OUT signal is equivalent to the DATA_IN signal in design 402-A, modification 404 could include adding a third input to AND gate 502-A for the ~SCAN_EN signal, and then feeding the OUT signal into an OR gate that also receives the output of the AND gate, which performs an AND operation on the SCAN_IN and SCAN_EN signals together. An example of this type is given above regarding... Figure 2B An explanation was given, the difference being... Figure 2B The DATA_IN signal will instead be implemented as IN_1 and IN_2 signals, which are ANDed together with the ~SCAN_EN signal in a three-input AND gate.

[0066] As another example, Figure 5B An implementation is illustrated in which logic gate 408 is an OR gate 502-B that accepts a first digital signal (IN_1) and a second digital signal (IN_2) and is configured to produce an output signal (OUT) representing: 1) a logic low value when both the first and second digital signals represent logic low values; and 2) a logic high value otherwise. This logic function is illustrated by diagram 504-B, which shows that the OUT signal is high for each combination of IN_1 and IN_2, except when both IN_1 and IN_2 are low. Therefore, if the OUT signal is equivalent to the DATA_IN signal of design 402-A, modification 404 may include logic that adds a third input to OR gate 502-B and / or changes the output in any suitable manner, such that the same OR operation of the first and second digital signals occurs, while also implementing a multiplexing function in which the OUT signal or the SCAN_IN signal is selected based on the SCAN_EN signal.

[0067] As another example, Figure 5CAn implementation is illustrated in which logic gate 408 is a NAND gate 502-C that accepts a first digital signal (IN_1) and a second digital signal (IN_2) and is configured to produce an output signal (OUT) that represents: 1) a logic low value when both the first and second digital signals represent logic high values; 2) a logic high value otherwise. This logic function is illustrated by diagram 504-C, which shows that the OUT signal is high for each combination of IN_1 and IN_2, except when both IN_1 and IN_2 are high. Therefore, if the OUT signal is equivalent to the DATA_IN signal in design 402-A, modification 404 can include logic that adds a third input to NAND gate 502-C and / or changes the output in any suitable way, such that the same NAND operation occurs between the first and second digital signals, while also implementing a multiplexing function in which the OUT signal or the SCAN_IN signal is selected based on the SCAN_EN signal.

[0068] As yet another example, Figure 5D An implementation is illustrated in which logic gate 408 is a NOR gate 502-D that accepts a first digital signal (IN_1) and a second digital signal (IN_2) and is configured to produce an output signal (OUT) that represents: 1) a logic high value when both the first and second digital signals represent logic low values; 2) a logic low value otherwise. This logic function is illustrated by diagram 504-D, which shows that the OUT signal is low for each combination of IN_1 and IN_2, except when both IN_1 and IN_2 are low. Therefore, if the OUT signal is equivalent to the DATA_IN signal in design 402-A, modification 404 may include logic that adds a third input to the NOR gate 502-D and / or changes the output in any suitable manner such that the same NOR operation occurs between the first and second digital signals, while also implementing a multiplexing function in which the OUT signal or the SCAN_IN signal is selected based on the SCAN_EN signal.

[0069] As mentioned above, Figure 6 Additional example modifications to a scannable digital circuit, based on the principles described herein, are shown for replacing scannable flip-flops with non-scannable flip-flops. Figure 6In this context, design 602-A is shown as being transformed into modified design 602-B through modification 604, such as that described above with respect to operation 304 of method 300. More specifically, as shown, design 602-A includes a stage 606-A of combinational logic that may represent a relatively critical data path (e.g., such that the propagation delay associated with stage 606-A may exceed a delay threshold such as those described above). As shown within stage 606-A, the output of the stage may include buffer 608. For example, buffer 608 may be implemented as a non-inverting buffer (as shown) or an inverting buffer (or a NOT gate, not shown in this example). As shown, buffer 608 is located at the output of stage 606-A in such a sense that buffer 608 is the last gate (but not the only gate) through which a digital signal can propagate before being latched for the next clock cycle. It should be understood that stage 606-A may include various other gates in combinational logic that are not explicitly shown.

[0070] For this latch, design 602-A is further shown as including a scannable flip-flop 610-A that receives not only the DATA_IN signal from buffer 608 of stage 606-A, but also the CLK, SCAN_IN, and SCAN_EN signals already described. Scannable flip-flop 610-A is shown as outputting the DATA_OUT signal already described. For example, the DATA_OUT signal may follow the behavior shown above with respect to Figure 206.

[0071] Following modification 604, the modified design 602-B shows a combinational logic stage 606-B feeding its output into a non-scannable flip-flop 610-B that does not possess the same scannable characteristics as the scannable flip-flop 610-A. However, as shown, additional logic 612 can be integrated into stage 606-B to implement the same multiplexing function previously performed by the scannable flip-flop before modification 604. For example, as shown, logic 612 can implement a multiplexer that selects between the DATA_IN and SCAN_IN signals based on the SCAN_EN signal, all of which can be received by the same scannable flip-flop 610-A in design 602-A. In a similar manner to how gate 408 is incorporated into or otherwise integrated into logic 412 in the example described above, the buffering function of buffer 608 can be performed by the same logic 612 now included to perform the multiplexing function previously handled by the scannable flip-flop 610-A in design 602-A. Therefore, additional logic 612 can replace buffer 608 and can eliminate any latency particularly associated with buffer 608, as it is combined with the latency associated with the multiplexing function (which occurs regardless of whether a scannable or non-scannable flip-flop is used).

[0072] The buffering function performed by buffer 608 in stage 606-A and logic 612 in stage 606-B can prepare the digital signal to be latched by the scannable flip-flop (e.g., the DATA_IN signal in this example) in any suitable manner. For example, the buffering function can involve boosting the digital signal to ensure sufficient drive strength and acceptable voltage for the input requirements of the flip-flop, improving signal integrity (e.g., cleaning the signal or removing noise that may have been introduced into the signal), and / or otherwise buffering the signal to ensure that the signal to be latched by the flip-flop meets design requirements. Therefore, Figure 6 The diagram illustrates that, prior to the modification of the scannable digital circuit design 602-A (in modification 604), stage 606-A could include at least one logic gate (e.g., an inverting buffer, a non-inverting buffer, multiple such buffer gates, etc.) at the stage output, configured to perform a buffering function to prepare a digital signal to be latched by the scannable flip-flop 610-A. Then, after modification 604, the multiplexing function of the scannable flip-flop 610-A can be integrated into the combinational logic stage (now stage 606-B) by introducing multiple logic gates at the output of stage 606-B (i.e., in place of buffer 608). These multiple logic gates can be configured, for example, to perform both multiplexing and buffering functions. In this way, stage 606-B can have a similar propagation delay to stage 606-A prior to modification 604, and any increase in delay compared to the scannable flip-flop 610-A can be completely offset by the savings in settling time of the non-scannable flip-flop 610-B.

[0073] Figure 7 Two scanned digital circuits are shown for comparing a scanned digital circuit design that relies solely on scanned flip-flops with a scanned digital circuit design that incorporates at least one non-scanned flip-flop, based on the principles described herein. More specifically, as shown, the first scanned digital circuit 702-A is shown as multiple stages of combinational logic (including stages 704-1A, 704-2A, and other similar stages indicated by ellipses) preceding the respective scanned flip-flops (including scanned flip-flop 706-1A after stage 704-1A, scanned flip-flop 706-2A after stage 704-2A, and other scanned flip-flops after other stages of combinational logic as indicated by ellipses).

[0074] In this first scanable digital circuit 702-A, each stage of the combinational logic (e.g., stages 704-1A, 704-2A, etc.) is shown to process digital signals provided by at least one preceding flip-flop in the design (e.g., flip-flop 708-1 providing digital signals propagating through stage 704-1A, flip-flop 708-2 providing digital signals propagating through stage 704-2A, etc.). Additionally, logic stages 704-1A, 704-2A, etc., are also shown to each have an output latched by a scanable flip-flop (e.g., scanable flip-flops 706-1A, 706-2A, etc.), which receives not only data inputs from the respective logic stage but also the already described SCAN_IN and SCAN_EN signals. In other words, as shown, the scanable digital circuit 702-A may include a first stage of combinational logic (e.g., stage 704-1A); a first scanable flip-flop (scanable flip-flop 706-1A) configured to receive the output of the first stage and perform a multiplexing function controlled by a scan enable signal; a second stage of combinational logic (stage 704-2A); a second scanable flip-flop (e.g., scanable flip-flop 706-2A) configured to receive the output of the second stage and perform a multiplexing function controlled by a scan enable signal, and so on for any number of other stages of combinational logic and associated scanable flip-flops.

[0075] like Figure 7 The diagram further illustrates that the second scanable digital circuit 702-B is shown as including multiple stages of combinational logic (including stages 704-1B, 704-2B, and other similar stages indicated by ellipses) preceding corresponding flip-flops of different types (e.g., non-scanable flip-flop 706-1B after stage 704-1B, scanable flip-flop 706-2B after stage 704-2B, and other scanable and / or non-scanable flip-flops following other stages of combinational logic as indicated by ellipses). In other words, while the first scanable digital circuit 702-A may represent a more typical or conventional scanable digital circuit (with dedicated scanable flip-flops), the second scanable digital circuit 702-B will be understood as representing a scanable digital circuit comprising a combination of both scanable and non-scanable flip-flops according to the principles described herein.

[0076] In this second scanable digital circuit 702-B, each stage of the combinational logic (e.g., stages 704-1B, 704-2B, etc.) is shown to process digital signals provided by at least one preceding flip-flop in the design (e.g., the same flip-flops 708-1 and 708-2 described above). Additionally, logic stages 704-1B, 704-2B, etc., are also shown to each have an output latched by a flip-flop (e.g., a non-scanable flip-flop 706-1B, a scanable flip-flop 706-2B, etc.) that receives data input from the corresponding logic stage, but may or may not receive the already described SCAN_IN and SCAN_EN signals. More specifically, as shown, the scanable digital circuit 702-A may include a first stage of combinational logic (e.g., stage 704-1B) configured to perform a multiplexing function controlled by a scan enable signal at the output of the first stage (represented by a multiplexer shown as being integrated within stage 704-1B); a non-scanable flip-flop (e.g., non-scanable flip-flop 706-1B) configured to receive the output of the first stage after performing the multiplexing function; a second stage of combinational logic (e.g., stage 704-2B); and a scanable flip-flop (e.g., scanable flip-flop 706-2B) configured to receive the output of the second stage and perform the multiplexing function controlled by a scan enable signal.

[0077] As already described, scannable digital circuit designs can include two types of logic levels and flip-flops that are convenient for meeting timing and / or power consumption targets. For example, referring to scannable digital circuit 702-B, it should be understood that logic levels with integrated multiplexing functions and corresponding non-scannable flip-flops (e.g., similar to level 704-1B and non-scannable flip-flop 706-1B) can be included throughout the design to address various critical paths whose delay thresholds are difficult to meet using conventional techniques. Simultaneously, it should also be understood that logic levels without integrated multiplexing functions and corresponding scannable flip-flops (e.g., similar to level 704-2B and scannable flip-flop 706-2B) can also be included throughout the design to more efficiently and conveniently handle less critical paths whose delay thresholds can be met using conventional techniques.

[0078] Figures 8A to 8B An illustrative application of a scannable digital circuit employing a non-scannable flip-flop, based on the principles described herein, is shown. More specifically, Figure 8AAn implementation of a second scanable digital circuit 702-B is shown, which is implemented within a central processing unit (CPU) 802 and configured to operate based on a scan enable signal (e.g., SCAN_EN) in either of the following modes: 1) a normal mode that facilitates the functional operation of the CPU 802, or 2) a scan mode that facilitates testing of the CPU 802. As shown, the SCAN_EN signal can be a global input to the CPU 802, which will be understood as a fan-out function driving the scan enable input of all scanable flip-flops and a corresponding multiplexed function of non-scanable flip-flops. The SCAN_IN signal is also shown as an input to the CPU 802 and will be understood as representing a scan input for the first flip-flop in the scan chain shift register.

[0079] Similarly, Figure 8B An implementation of a second scannable digital circuit 702-B is shown, which is implemented within a graphics processing unit (GPU) 804 and configured to operate based on a scan enable signal (e.g., SCAN_EN) in either of the following modes: 1) a normal mode that facilitates the functional operation of the GPU 804, or 2) a scan mode that facilitates testing of the GPU 804. Similar to the description above regarding the CPU 802, the SCAN_EN signal can be a global input to the GPU 804, which will be understood as a fan-out function driving the scan enable input of all scannable flip-flops and the corresponding multiplexed function of non-scannable flip-flops. The SCAN_IN signal is then an input to the GPU 804, which will be understood as representing a scan input for the first flip-flop in the scan chain shift register. While the CPU 802 and GPU 804 are shown as specific examples of scannable digital circuitry employing non-scannable flip-flops, it should be understood that such circuitry can be implemented in a variety of other (i.e., non-CPU and non-GPU) applications, such as the digital circuitry system already described.

[0080] As already mentioned, the various methods and processes described herein can be implemented, at least in part, as instructions embodied in a non-transitory computer-readable medium and executable by one or more computing devices. Generally, a processor (e.g., a microprocessor) receives instructions from a non-transitory computer-readable medium (e.g., memory, etc.) and executes those instructions, thereby performing one or more operations such as those described herein. Such instructions can be stored and / or transmitted using any of the various known computer-readable media.

[0081] Computer-readable media (also known as processor-readable media) include any non-transitory medium that contributes to providing data (e.g., instructions) that can be read by a computer (e.g., by the computer's processor). Such media can take many forms, including but not limited to non-volatile and / or volatile media. Non-volatile media can include, for example, optical discs or magnetic disks, and other permanent storage devices. Volatile media can include, for example, dynamic random access memory (DRAM), which typically constitutes main memory.

[0082] Figure 9 An illustrative computing device 900 is shown, which can be incorporated into and / or used for designing scannable digital circuits employing non-scannable flip-flops, based on the principles described herein. Figure 9 As shown, the computing device 900 may include a communication interface 902, a processor 904 (which may represent an implementation of CPU 802), a storage device 906, and an input / output (I / O) module 908, all communicatively connected via a communication infrastructure 910. Although Figure 9 An illustrative computing device 900 is shown, but Figure 9 The components shown are not intended to be limiting. Additional or alternative components may be used in other embodiments. A more detailed description will now follow. Figure 9 The components of the computing device 900 shown in the figure.

[0083] Communication interface 902 can be configured to communicate with one or more computing devices. Examples of communication interface 902 include, but are not limited to, wired network interfaces (such as network interface cards), wireless network interfaces (such as wireless network interface cards), modems, audio / video connections, and any other suitable interfaces.

[0084] Processor 904 generally refers to any type or form of processing unit capable of processing data or interpreting, executing, and / or directing the execution of one or more of the instructions, procedures, and / or operations described herein. Processor 904 may direct the execution of operations according to one or more applications 912 or other computer-executable instructions, such as those that may be stored in storage device 906 or other computer-readable media.

[0085] Storage device 906 may include one or more data storage media, devices, or configurations, and may take any type, form, and combination of data storage media and / or devices. For example, storage device 906 may include, but is not limited to, hard disk drives, network drives, flash drives, magnetic disks, optical disks, RAM, dynamic RAM, other non-volatile and / or volatile data storage units, or combinations or sub-combinations thereof. Electronic data, including the data described herein, may be temporarily and / or permanently stored in storage device 906. For example, data representing one or more executable applications 912 configured to direct processor 904 to perform any of the operations described herein may be stored in storage device 906. In some examples, data may be arranged in one or more databases residing within storage device 906.

[0086] I / O module 908 may include one or more I / O modules configured to receive user input and provide user output. One or more I / O modules may be used to receive input for a single virtual experience. I / O module 908 may include any hardware, firmware, software, or combinations thereof that support input and output capabilities. For example, I / O module 908 may include hardware and / or software for capturing user input, including but not limited to a keyboard or keypad, a touchscreen component (e.g., a touchscreen display), a receiver (e.g., an RF or infrared receiver), a motion sensor, and / or one or more input buttons.

[0087] I / O module 908 may include one or more means for presenting output to a user, including but not limited to a graphics engine, a display (e.g., a screen), one or more output drivers (e.g., display drivers), one or more audio speakers, and one or more audio drivers. In a particular embodiment, I / O module 908 is configured to provide graphical data to the display for presentation to the user. The graphical data may represent one or more graphical user interfaces and / or any other graphical content that may serve a particular implementation.

[0088] The following clauses describe the implementation of a non-scannable flip-flop for scannable digital circuits based on the principles described herein.

[0089] Clause 1. A scanable digital circuit comprising: a first stage of combinational logic configured to perform a multiplexing function controlled by a scan enable signal at an output of the first stage; a first flip-flop configured to receive an output of the first stage after the multiplexing function is performed, the first flip-flop being a non-scanable flip-flop; a second stage of combinational logic; and a second flip-flop configured to receive an output of the second stage, the second flip-flop being a scanable flip-flop configured to perform the multiplexing function controlled by the scan enable signal.

[0090] Clause 2. The scannable digital circuit as described in Clause 1, wherein: the multiplexing function is performed by the first stage at the output of the first stage using a plurality of logic gates, the plurality of logic gates being further configured to perform a buffering function to prepare a first digital signal to be latched by the first flip-flop; and the second stage includes a logic gate at the output of the second stage, the logic gate being configured to perform the buffering function to prepare a second digital signal to be latched by the second flip-flop.

[0091] Clause 3. The scannable digital circuitry as described in Clause 1, wherein the scannable digital circuitry is implemented within a central processing unit (CPU) and configured to operate in either of the following modes based on the scan enable signal: a normal mode that facilitates the functional operation of the CPU, or a scan mode that facilitates the testing of the CPU.

[0092] Clause 4. The scannable digital circuitry as described in Clause 1, which is implemented within a graphics processing unit (GPU) and configured to operate in either of the following modes based on the scan enable signal: a normal mode that facilitates the functional operation of the GPU, or a scan mode that facilitates the testing of the GPU.

[0093] Clause 5. A method comprising: determining that a first propagation delay of a first stage of combinational logic is greater than a delay threshold, the first stage preceding a first scannable flip-flop within a scannable digital circuit design; modifying the scannable digital circuit design based on determining that the first propagation delay is greater than the delay threshold to: integrate a multiplexing function controlled by a scan enable signal into the first stage at the output of the first stage, and convert the first scannable flip-flop to a non-scannable flip-flop; determining that a second propagation delay of a second stage of combinational logic is less than the delay threshold, the second stage preceding a second scannable flip-flop within the scannable digital circuit design; and retaining the second scannable flip-flop in the scannable digital circuit design based on determining that the second propagation delay is less than the delay threshold.

[0094] Clause 6. The method as described in Clause 5, wherein: prior to modifying the scannable digital circuit design, the first stage includes a logic gate at the output of the first stage, the logic gate being configured to perform a buffering function to prepare a digital signal to be latched by the first scannable flip-flop; and the multiplexing function is integrated into the first stage by replacing the logic gate with a plurality of logic gates at the output of the first stage, the plurality of logic gates being configured to perform both the multiplexing function and the buffering function.

[0095] Clause 7. The method as described in Clause 5, wherein: prior to modifying the scannable digital circuit design, the first stage includes a logic gate at the output of the first stage, the logic gate being configured to perform a logic function relating to a first digital signal and a second digital signal; and the multiplexing function is integrated into the first stage by introducing a plurality of logic gates at the output of the first stage in place of the logic gates, the plurality of logic gates being configured to perform both the multiplexing function and the logic function.

[0096] Clause 8. The method as described in Clause 7, wherein the logic gate is configured to produce an AND gate representing an output signal that is a logic high value when both the first digital signal and the second digital signal represent a logic high value, and otherwise a logic low value.

[0097] Clause 9. The method as described in Clause 7, wherein the logic gate is a NAND gate configured to produce an output signal that is a logic low value when both the first digital signal and the second digital signal represent a logic high value; and otherwise, a logic high value.

[0098] Clause 10. The method as described in Clause 7, wherein the logic gate is configured to produce an OR gate representing an output signal that is a logic low value when both the first digital signal and the second digital signal represent a logic low value, and otherwise a logic high value.

[0099] Clause 11. The method as described in Clause 7, wherein the logic gate is configured to produce an NOR gate representing an output signal that is a logic high value when both the first digital signal and the second digital signal represent a logic low value; and otherwise represents the logic low value.

[0100] Clause 12. The method as described in Clause 5, wherein: before modifying the scannable digital circuit design, the scannable digital circuit design is configured to have a maximum frequency for clocking corresponding to a first time period longer than the sum of the delay threshold and the setup time for the first scannable trigger; and after modifying the scannable digital circuit design, the scannable digital circuit design is configured to have the maximum frequency for clocking corresponding to a second time period shorter than or equal to the sum of the delay threshold and the setup time.

[0101] Clause 13. The method as described in Clause 5, wherein: before modifying the scannable digital circuit design, the scannable digital circuit design generates a first power consumption when clocked at the maximum frequency; and after modifying the scannable digital circuit design, the scannable digital circuit design generates a second power consumption when clocked at the maximum frequency, the second power consumption being lower than the first power consumption.

[0102] Clause 14. The method of Clause 5 further comprises: constructing a scannable digital circuit based on the scannable digital circuit design, the scannable digital circuit including a first stage of combinational logic, the non-scannable flip-flop, a second stage of combinational logic, and a second scannable flip-flop.

[0103] Clause 15. The method as described in Clause 14, wherein the scanable digital circuitry is implemented within a central processing unit (CPU) and configured to operate in either of the following modes based on the scan enable signal: a normal mode that facilitates the functional operation of the CPU, or a scan mode that facilitates the testing of the CPU.

[0104] Clause 16. The method as described in Clause 14, wherein the scanable digital circuitry is implemented within a graphics processing unit (GPU) and configured to operate based on the scan enable signal in either a normal mode that facilitates the functional operation of the GPU, or a scan mode that facilitates testing of the GPU.

[0105] Clause 17. A non-transitory computer-readable medium storing instructions, which, when executed, cause a processor of a computing device to perform the following processes: determining that a first propagation delay of a first stage of combinational logic is greater than a delay threshold, the first stage preceding a first scannable flip-flop within a scannable digital circuit design; modifying the scannable digital circuit design based on determining that the first propagation delay is greater than the delay threshold to: integrate a multiplexing function controlled by a scan enable signal into the first stage at the output of the first stage, and convert the first scannable flip-flop to a non-scannable flip-flop; determining that a second propagation delay of a second stage of combinational logic is less than the delay threshold, the second stage preceding a second scannable flip-flop within the scannable digital circuit design; and retaining the second scannable flip-flop in the scannable digital circuit design based on determining that the second propagation delay is less than the delay threshold.

[0106] Clause 18. A non-transitory computer-readable medium as described in Clause 17, wherein: prior to modification of the scannable digital circuit design, the first stage includes a logic gate at the output of the first stage, the logic gate being configured to perform a buffering function to prepare a digital signal to be latched by the first scannable flip-flop; and the multiplexing function is integrated into the first stage by introducing a plurality of logic gates at the output of the first stage in place of the logic gates, the plurality of logic gates being configured to perform both the multiplexing function and the buffering function.

[0107] Clause 19. A non-transitory computer-readable medium as described in Clause 17, wherein: prior to modification of the scannable digital circuit design, the first stage includes a logic gate at the output of the first stage, the logic gate being configured to perform a logical function relating to a first digital signal and a second digital signal; and the multiplexing function is integrated into the first stage by replacing the logic gate with a plurality of logic gates at the output of the first stage, the plurality of logic gates being configured to perform both the multiplexing function and the logical function.

[0108] Clause 20. A non-transitory computer-readable medium as described in Clause 17, wherein: prior to modification of the scannable digital circuit design, the scannable digital circuit design is configured to be clocked at a maximum frequency corresponding to a first time period longer than the sum of the delay threshold and the setup time for the first scannable trigger; and after modification of the scannable digital circuit design, the scannable digital circuit design is configured to be clocked at the maximum frequency corresponding to a second time period shorter than or equal to the sum of the delay threshold and the setup time.

[0109] Various implementations of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, specially designed ASICs (Application-Specific Integrated Circuits), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system, which includes at least one programmable processor, which may be dedicated or general-purpose, and is coupled to receive and transmit data and instructions from and to a storage system, at least one input device, and at least one output device.

[0110] Various implementations have been described. However, it will be understood that various modifications can be made without departing from the spirit and scope of the specification and claims. Furthermore, the logical flow depicted in the figures does not require the desired result to be achieved in the specific order or sequence shown. Additionally, other steps may be provided, or steps may be removed from the described flow, and other components may be added to or removed from the described system. Therefore, other implementations are within the scope of the appended claims.

[0111] The specific structural and functional details disclosed in this article are representative only for the purpose of describing the example implementation. However, the example implementation can be embodied in many alternative forms and should not be construed as being limited to the implementation described in this article.

[0112] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. A first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the implementations of this disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0113] The terminology used herein is for the purpose of describing a particular implementation only and is not intended to limit the implementation. As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” are intended to include the plural forms as well. It should be further understood that the terms “comprises, comprising, includes, and / or including” as used in this specification specify the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0114] It should be understood that when an element is referred to as being “coupled” to, “connected” to, or “in response to” or “on” another element, the element may be directly coupled to, connected to, or in response to, or on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being “directly coupled” to, “directly connected” to, or “directly in response to” another element or “directly on” another element, there are no intermediate elements present. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0115] For ease of description, spatially relative terms such as “below,” “under,” “down,” “above,” and “above” may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. It should be understood that spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those depicted in the figures. For example, if the device in the figures is flipped, then an element described as “below” or “under” other elements or features would be oriented as “above” other elements or features. Therefore, the term “below” can encompass both above and below orientations. The device may be oriented in other ways (rotated 130 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0116] Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which these concepts belong. It should further be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0117] In addition to the description above, users can be provided with controls that allow them to choose whether and when the system, program, or feature described herein enables the collection of user information (e.g., information about the user's social networks, social actions or activities, occupation, user preferences, or the user's current location) and whether to send content or communications to the user from the server. Furthermore, some data may be processed in one or more ways before it is stored or used, resulting in the removal of personally identifiable information. For example, user identity may be processed to the point that the user's personally identifiable information cannot be determined, or the user's geographic location may be generalized, or location information (such as down to the city, zip code, or state level) may be obtained, making it impossible to determine the user's specific location. Therefore, users can control what information is collected, how that information is used, and what information is provided to the user.

[0118] While certain features of the described implementations have been exemplified as described herein, many modifications, substitutions, alterations, and equivalents will occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover such modifications and alterations falling within the scope of the implementations. It should be understood that they are presented by way of example only and not limitation, and various changes in form and detail are possible. Any part of the apparatus and / or method described herein can be combined in any combination, except for mutually exclusive combinations. The implementations described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different implementations described. Therefore, the scope of this disclosure is not limited to the specific combinations claimed below, but is instead extended to cover any combination of features or example implementations described herein, regardless of whether that specific combination has been specifically enumerated in the appended claims at this time.

Claims

1. A scannable digital circuit, comprising: The first stage of the combinational logic is configured to perform a multiplexing function controlled by a scan enable signal at the output of the first stage; A first trigger, configured to receive the output of the first stage after the multiplexing function is performed, wherein the first trigger is a non-scannable trigger; The second level of combinational logic; and The second trigger, configured to receive the output of the second stage, is a scannable trigger configured to perform the multiplexing function controlled by the scan enable signal.

2. The scannable digital circuit as claimed in claim 1, wherein: The multiplexing function is performed by the first stage at the output of the first stage using a plurality of logic gates, the plurality of logic gates being further configured to perform a buffering function to prepare a first digital signal to be latched by the first flip-flop; and The second stage includes a logic gate at its output, the logic gate being configured to perform the buffering function to prepare a second digital signal to be latched by the second flip-flop.

3. The scannable digital circuit of claim 1, wherein the scannable digital circuit is implemented within a central processing unit (CPU) and configured to operate based on the scan enable signal under any of the following conditions: Normal mode that facilitates the functional operation of the CPU, or A scan mode that facilitates the testing of the CPU.

4. The scannable digital circuit of claim 1, wherein the scannable digital circuit is implemented within a graphics processing unit (GPU) and configured to operate based on the scan enable signal under any of the following conditions: Normal mode that facilitates the functional operation of the GPU, or A scanning mode that facilitates the testing of the GPU.

5. A method comprising: The first propagation delay of the first stage of the combinational logic is determined to be greater than a delay threshold, and the first stage precedes the first scannable flip-flop in the scannable digital circuit design. Based on determining that the first propagation delay is greater than the delay threshold, the scannable digital circuit design is modified to: At the output of the first stage, the multiplexing function controlled by the scan enable signal is integrated into the first stage, and Convert the first scannable trigger to a non-scannable trigger; The second propagation delay of the second stage of the combinational logic is determined to be less than the delay threshold, and the second stage precedes the second scannable flip-flop within the scannable digital circuit design; as well as The second scannable trigger in the scannable digital circuit design is retained based on the determination that the second propagation delay is less than the delay threshold.

6. The method of claim 5, wherein: Before modifying the scannable digital circuit design, the first stage includes a logic gate at the output of the first stage, the logic gate being configured to perform a buffering function to prepare a digital signal to be latched by the first scannable flip-flop. and The multiplexing function is integrated into the first stage by introducing multiple logic gates at the output of the first stage to replace the logic gates. The multiple logic gates are configured to perform both the multiplexing function and the buffering function.

7. The method of claim 5, wherein: Before modifying the scannable digital circuit design, the first stage included a logic gate at its output, the logic gate being configured to perform a logical function relating to a first digital signal and a second digital signal; and The multiplexing function is integrated into the first stage by introducing multiple logic gates at the output of the first stage to replace the logic gates, and the multiple logic gates are configured to perform both the multiplexing function and the logic function.

8. The method of claim 7, wherein, The logic gate is an AND gate configured to generate an output signal, the output signal being: When both the first digital signal and the second digital signal represent a logic high value, the logic high value is represented. as well as The logic low value is represented when at least one of the first digital signal and the second digital signal represents a logic low value.

9. The method of claim 7, wherein, The logic gate is a NAND gate configured to generate an output signal, the output signal being: When both the first digital signal and the second digital signal represent a logic high value, it represents a logic low value; as well as When at least one of the first digital signal and the second digital signal represents the logic low value, it represents the logic high value.

10. The method of claim 7, wherein, The logic gate is an OR gate configured to generate an output signal, the output signal being: When both the first digital signal and the second digital signal represent a logic low value, the logic low value is represented. as well as The logic high value is represented when at least one of the first digital signal and the second digital signal represents a logic high value.

11. The method of claim 7, wherein, The logic gate is a NOR gate configured to generate an output signal, the output signal being: When both the first digital signal and the second digital signal represent a logic low value, it represents a logic high value; as well as When at least one of the first digital signal and the second digital signal represents the logic high value, it represents the logic low value.

12. The method of claim 5, wherein: Before modifying the scannable digital circuit design, the scannable digital circuit design was configured such that the maximum frequency of clock processing corresponds to a first time period, which is longer than the sum of the delay threshold and the setup time for the first scannable trigger. and After modifying the scannable digital circuit design, the scannable digital circuit design is configured such that the maximum frequency of the clock processing corresponds to a second time period, the second time period being shorter than or equal to the sum of the delay threshold and the set time.

13. The method of claim 5, wherein: Before modifications to the scannable digital circuit design, the scannable digital circuit design generates a first power consumption when clocked at the maximum frequency. and After modifying the scannable digital circuit design, when clocking at the maximum frequency, the scannable digital circuit design generates a second power consumption, which is lower than the first power consumption.

14. The method of claim 5, further comprising: Based on the aforementioned scannable digital circuit design, a scannable digital circuit is constructed, which includes a first stage of combinational logic, the non-scannable flip-flop, a second stage of combinational logic, and a second scannable flip-flop.

15. The method of claim 14, wherein, The scannable digital circuitry is implemented within a central processing unit (CPU) and configured to operate based on the scan enable signal under any of the following conditions: Normal mode that facilitates the functional operation of the CPU, or A scan mode that facilitates the testing of the CPU.

16. The method of claim 14, wherein, The scannable digital circuitry is implemented within a graphics processing unit (GPU) and configured to operate based on the scan enable signal under any of the following conditions: Normal mode that facilitates the functional operation of the GPU, or A scanning mode that facilitates the testing of the GPU.

17. A non-transitory computer-readable medium storing instructions, which, when executed, cause a processor of a computing device to perform a process comprising: The first propagation delay of the first stage of the combinational logic is determined to be greater than a delay threshold, and the first stage precedes the first scannable flip-flop in the scannable digital circuit design. Based on determining that the first propagation delay is greater than the delay threshold, the scannable digital circuit design is modified to: At the output of the first stage, the multiplexing function controlled by the scan enable signal is integrated into the first stage, and Convert the first scannable trigger to a non-scannable trigger; The second propagation delay of the second stage of the combinational logic is determined to be less than the delay threshold, and the second stage precedes the second scannable flip-flop within the scannable digital circuit design; and The second scannable trigger in the scannable digital circuit design is retained based on the determination that the second propagation delay is less than the delay threshold.

18. The non-transitory computer-readable medium of claim 17, wherein: Before modifying the scannable digital circuit design, the first stage includes a logic gate at the output of the first stage, the logic gate being configured to perform a buffering function to prepare a digital signal to be latched by the first scannable flip-flop. and The multiplexing function is integrated into the first stage by introducing multiple logic gates at the output of the first stage to replace the logic gates. The multiple logic gates are configured to perform both the multiplexing function and the buffering function.

19. The non-transitory computer-readable medium of claim 17, wherein: Before modifying the scannable digital circuit design, the first stage included a logic gate at its output, the logic gate being configured to perform a logical function relating to a first digital signal and a second digital signal; and The multiplexing function is integrated into the first stage by introducing multiple logic gates at the output of the first stage to replace the logic gates, and the multiple logic gates are configured to perform both the multiplexing function and the logic function.

20. The non-transitory computer-readable medium of claim 17, wherein: Before modifying the scannable digital circuit design, the scannable digital circuit design was configured such that the maximum frequency of clock processing corresponds to a first time period, which is longer than the sum of the delay threshold and the setup time for the first scannable trigger. and After modifying the scannable digital circuit design, the scannable digital circuit design is configured such that the maximum frequency of the clock processing corresponds to a second time period, the second time period being shorter than or equal to the sum of the delay threshold and the set time.

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