A sar adc capacitor array digital self-calibration circuit and method

Abstract

This invention relates to the field of integrated circuit manufacturing technology and discloses a digital self-calibration circuit and method for a SAR ADC capacitor array. In the process of integrated circuit manufacturing and on-chip analog-to-digital conversion circuit implementation, by causing the target capacitor to generate excitations with opposite polarities and corresponding amplitudes in odd-numbered and even-numbered calibration cycles, the DC offset components of the comparator cancel each other out during the difference calculation. By generating bit decisions through multiple statistical methods for the comparison results of each bit of the sub-ADC, the disturbance of thermal noise to the final calibration result is reduced at the bit decision level. By alternating between odd and even calibration cycles and performing pairing and difference calculation in a short time, the influence of flicker noise in adjacent calibrations is reduced. By solving the capacitor weights of each bit sequentially from low to high bits, the propagation of errors at each level is reduced. By digitally reconstructing the output result after all weights have been solved, the final output of the SAR ADC is made closer to the actual capacitor array weight relationship.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a SAR ADC capacitor array digital self-calibration circuit and method. Background Technology

[0002] An analog-to-digital converter (ADC) is a device that converts analog signals into digital signals. Successive approximation ADCs (SAR ADCs) are widely used in low-power and high-precision integrated circuits due to their relatively simple structure, low power consumption, and strong digital compatibility. Examples include wearable chips, portable electronic product chips, sensor interface chips, and other on-chip mixed-signal systems. Especially in the field of integrated circuit manufacturing, as CMOS process platforms continue to develop towards higher integration, lower power consumption, and higher precision, SAR ADCs, as typical on-chip data conversion circuits, have become an important interface unit between analog front-ends and digital processing circuits. SAR ADCs need to achieve high resolution within a small area and with low power consumption; therefore, the weighting accuracy of the capacitor array and the decision accuracy of the comparator are particularly important.

[0003] However, as the resolution of SAR ADCs continues to improve, the area of ​​the capacitor array, which forms the core of its digital-to-analog conversion, typically increases significantly, and the capacitor mismatch problem caused by manufacturing processes becomes more prominent. It's easy to understand that when the actual weights of the capacitors in the array deviate from their ideal design values, the weighting relationships relied upon by the SAR ADC during successive approximation will shift, leading to errors in the mapping between the output code and the actual input signal. These errors ultimately manifest as differential nonlinearity, integral nonlinearity, and a decrease in the overall effective number of bits. Therefore, for high-precision SAR ADCs, how to effectively calibrate the capacitor array is one of the important issues that the industry has long focused on.

[0004] In existing technologies, various solutions have been proposed to address the capacitor array mismatch problem. For example, LMS calibration typically approximates the optimal weights through iterative calculations, but this method often requires significant computational resources and a long convergence time, making it more suitable for off-chip or long-term background processing. While auxiliary capacitor calibration can improve calibration accuracy to some extent, it introduces additional area and parasitics, and its accuracy is often limited by the minimum implementation granularity of the auxiliary capacitors. Histogram calibration methods often require a large amount of sampling data and numerous repetitive calculations, making it difficult to balance accuracy, area, and speed in many low-power scenarios. As for front-end self-calibration schemes that utilize the SAR ADC's own structure, although they have advantages in on-chip implementation, their calibration results may still deviate from the true weights if comparator offset and noise effects are not fully considered.

[0005] Furthermore, in SAR ADCs, a certain DC offset typically exists at the comparator input. This DC offset mainly originates from factors such as device mismatch, process deviations, layout asymmetry, and manufacturing fluctuations. When the two inputs of the comparator actually receive the same voltage signal, due to the DC offset, the comparator output may not correspond to the ideal zero point, but will exhibit a certain digital offset. In other words, the comparator DC offset introduces an additional bias term into the overall quantization result. If this bias term is not eliminated during capacitor array calibration, the error component related to the DC offset will be directly superimposed on the calibrated weight values. More seriously, since the weighting of higher-order capacitors usually depends on the calibrated results of lower-order capacitors, the lower-order calibration error will continue to propagate to higher orders, resulting in a phenomenon where the error increases with each higher order.

[0006] Based on this, even if a scheme is adopted to perform two opposite-direction calibrations on the same capacitor and eliminate DC offset by difference or averaging, it is still difficult to obtain sufficiently stable and accurate weight values ​​without further consideration of the effects of thermal noise and flicker noise during the calibration process. Specifically, thermal noise introduces random disturbances in each decision of the comparator. These disturbances do not only affect a single complete conversion result, but are gradually coupled into subsequent bit decisions during the bit-by-bit decision process of the sub-ADC. Flicker noise has obvious low-frequency drift characteristics, and its influence may accumulate in the final weight estimation when the calibration time is long. If the results of multiple complete calibrations are simply averaged, it is difficult to completely offset the coupling and propagation effects of the above noise, especially when the comparator noise is large, the number of bits in the sub-ADC is large, and the number of bits to be calibrated is high.

[0007] Therefore, in the process of integrated circuit manufacturing and on-chip analog-to-digital conversion circuit implementation, how to provide a SAR ADC capacitor array digital self-calibration circuit and method that does not require additional complex analog auxiliary structures, can complete calibration using the SAR ADC's own capacitor array, and can also eliminate DC offset and reduce the effects of thermal noise and flicker noise has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0008] This invention provides a digital self-calibration circuit and method for a SAR ADC capacitor array. By constructing odd-numbered and even-numbered calibration cycles for the same target capacitor, the target capacitor generates signal voltage changes of equal magnitude but opposite signs in the two types of cycles. Furthermore, by using multiple comparisons on each bit of the sub-ADC to reduce the influence of thermal noise, and by combining the classification, averaging, and difference processing of the odd-even cycle results, the DC offset and flicker noise of the comparator are suppressed, thereby obtaining more accurate capacitor weight parameters and further obtaining the calibrated final output data.

[0009] To achieve the above objectives, the present invention provides a SAR ADC capacitor array digital self-calibration circuit, comprising: a sampling switch, a capacitor array, a comparator, a SAR control logic module, and a digital self-calibration calculation module; The capacitor array includes multiple non-binary weighted capacitor units. The input of the comparator is connected to the output node of the capacitor array. The input of the SAR control logic module is connected to the output of the comparator. The SAR control logic module is used to generate control signals to control the switching of the lower plates of each capacitor in the capacitor array. The digital self-calibration calculation module is used to calculate the capacitor weights and the final output data based on the conversion results. The sampling switch is configured to connect a first voltage to the upper and lower plates of the capacitor array during the sampling phase to complete the reset, and then restore the capacitor array to a predetermined initial state based on the result stored in the digital self-calibration calculation module. The SAR control logic module includes a forced set circuit, which is configured to control the target capacitor to connect its lower plate from a first voltage to a second voltage in odd-numbered calibration cycles and to connect its lower plate from the first voltage to a third voltage different from the second voltage in even-numbered calibration cycles when calibrating any target capacitor. At the same time, other capacitors below the target capacitor are used to form a sub-ADC with the comparator for conversion. The digital self-calibration calculation module is configured to generate a digital output based on the odd-numbered calibration cycles corresponding to the target capacitance. and the digital output generated by an even number of calibration cycles Calculate the first number output respectively Second digital output and output based on the first number With the second digital output The difference determines the weight value W of the target capacitor, where: ; ; ; In the formula, m represents the complete statistical count corresponding to the odd-numbered calibration cycles and the even-numbered calibration cycles respectively; The digital output representing each odd-numbered calibration cycle corresponding to the target capacitor; The digital output representing each even-numbered calibration cycle corresponding to the target capacitor; This represents the average digital output of the odd-numbered calibration cycles corresponding to the target capacitor; The value represents the average digital output of an even number of calibration cycles corresponding to the target capacitor; W represents the weight value of the target capacitor.

[0010] Optionally, the first voltage is an intermediate voltage located between the second voltage and the third voltage, and the first voltage is the arithmetic mean of the second voltage and the third voltage, so that the target capacitor generates signal voltage changes of equal magnitude and opposite sign in odd-numbered calibration cycles and even-numbered calibration cycles.

[0011] Optionally, the capacitor array is a differential capacitor array, including multiple capacitors located in the positive differential branch and multiple capacitors located in the negative differential branch. Two capacitors in the same position in the positive and negative differential branches form a pair of matched capacitors and share the same weight value. The positive and negative input terminals of the comparator are respectively connected to the two output nodes of the differential capacitor array to compare the differential voltage formed after the target capacitor is switched.

[0012] Optionally, in the odd-numbered calibration cycles and the even-numbered calibration cycles, the SAR control logic module is configured to control the switching of each capacitor of the sub-ADC bit by bit, and after each capacitor is switched, the comparator performs multiple comparisons on the current comparison state, and the digital self-calibration calculation module determines the next capacitor to be connected to the second voltage or the third voltage based on the number of logic 1s in the multiple comparison results; wherein, the number of multiple comparisons is set according to the comparator noise level.

[0013] Optionally, when the number of comparisons increases to the point that all bit capacitor switching of the sub-ADC cannot be completed within a conversion cycle, the digital self-calibration calculation module is configured to record the switching state of the capacitor array after the last comparison of the conversion cycle, and restore the switching state before the start of the next conversion cycle with the same parity, so as to continue to complete the calibration cycle corresponding to the current target capacitor, until the least bit capacitor is compared and a complete digital output is obtained.

[0014] Optionally, the digital self-calibration calculation module is configured to calculate the weight value of each target capacitor sequentially from the low-order capacitor to the high-order capacitor, and when calibrating the higher-order target capacitor, substitute the weight of the low-order capacitor that has been calibrated into the corresponding calibration calculation process; after all the capacitors to be calibrated have been calibrated, the digital self-calibration calculation module is configured to reconstruct the output data of the SAR ADC using the obtained capacitor weights to obtain the final calibrated output data.

[0015] Furthermore, to achieve the above objectives, the present invention also provides a digital self-calibration method for a SAR ADC capacitor array, used in the digital self-calibration circuit of the SAR ADC capacitor array as described in any of the preceding claims, comprising the following steps: S1: Obtain the calibration digital output data corresponding to the target capacitor, and classify and store it according to the odd-numbered calibration cycle digital output and the even-numbered calibration cycle digital output; S2: Perform statistical processing on the comparison results of each bit in each calibration cycle, generate the decision result of the corresponding bit according to the number of logic 1s in each comparison result, and form the complete calibration cycle digital output accordingly; S3: Perform cumulative averaging on the digital outputs of odd-numbered calibration cycles and even-numbered calibration cycles respectively to obtain the first digital output and the second digital output; S4: Calculate the weight value of the target capacitor based on the difference between the first digital output and the second digital output; S5: Write the weight value of the target capacitor into the weight data set, and output the calibration result based on the updated weight data set.

[0016] Optionally, step S2: Perform statistical processing on the comparison results of each bit in each calibration cycle, generate the decision result of the corresponding bit based on the number of logic 1s in each comparison result, and form the complete digital output of the calibration cycle accordingly, specifically including: S21: Count the multiple comparison results of the current bit to obtain the number of occurrences of logic 1, compare the number of occurrences of logic 1 with a preset threshold, and generate the decision result of the current bit; S22: Determine the data ownership or switching direction of the next bit based on the decision result of the current bit; S23: After all bit decision results are generated, combine the decision results of each bit to obtain a complete calibration cycle digital output.

[0017] Optionally, step S4: Calculate the weight value of the target capacitor based on the difference between the first digital output and the second digital output, specifically including: S41: Digital output for odd-numbered calibration cycles Perform cumulative averaging to obtain the first numerical output. ; S42: Even-numbered calibration cycle digital output Perform cumulative averaging to obtain the second numerical output. ; S43: Calculate the weight value W of the target capacitor according to the following formula: ; ; ; Where m is the number of times the statistics are performed; The average result of an odd number of calibration cycles; The result is the average of an even number of calibration cycles; W is the weight value of the target capacitance.

[0018] Optionally, step S5: Write the weight value of the target capacitor into the weight data set, and output the calibration result based on the updated weight data set, specifically including: S51: Write the obtained target capacitor weights into the weight data set in sequence according to the capacitor position order; S52: In the calibration process corresponding to the higher-order capacitor, the written lower-order capacitor weights are called. After the weights of all capacitors to be calibrated are written, the SAR ADC conversion result is weighted and reconstructed according to the weight data set. S53: Outputs calibrated digital results that match the actual capacitor array weights.

[0019] The beneficial effects of this invention are as follows: It proposes a digital self-calibration circuit and method for a SAR ADC capacitor array. During integrated circuit manufacturing and on-chip analog-to-digital conversion circuit implementation, by creating excitations with opposite polarities and corresponding amplitudes for the target capacitor in odd and even calibration cycles, the DC offset components of the comparator can be mutually canceled during the difference calculation. By generating bit decisions through multiple statistical methods for the comparison results of each bit of the sub-ADC, the disturbance of thermal noise on the final calibration result can be reduced at the bit decision level. By alternating between odd and even calibration cycles and pairing and calculating differences within a short time, the influence of flicker noise in adjacent calibrations can be reduced. By solving the capacitor weights of each bit sequentially from low to high bits and calling the already calibrated low-bit weights during high-bit calibration, the problem of error propagation at each level can be reduced. By digitally reconstructing the output results after all weights have been solved, the final output of the SAR ADC can more closely approximate the actual capacitor array weight relationship. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the SAR ADC capacitor array digital self-calibration circuit according to an embodiment of the present invention.

[0021] Figure 2 This is a schematic diagram illustrating the digital self-calibration principle of the SAR ADC capacitor array in an embodiment of the present invention.

[0022] Figure 3 This is a schematic diagram of the working process of the calibration sub-ADC in an embodiment of the present invention.

[0023] Figure 4 This is a schematic diagram of the algorithm logic for obtaining the weight of each capacitor to be calibrated in an embodiment of the present invention.

[0024] Figure 5 This is a flowchart illustrating the digital self-calibration method for a SAR ADC capacitor array according to an embodiment of the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0026] It should be noted that in this embodiment of the invention, the comparator's DC offset, thermal noise, and flicker noise are all objectively existing error sources in the actual operation of the SAR ADC. Specifically, DC offset refers to the fact that when the same signal is received at both inputs of the comparator, the comparator's decision result still deviates from the ideal zero point due to factors such as process mismatch and device deviation. Thermal noise refers to random noise caused by the thermal motion of charge carriers, which manifests as rapidly changing random disturbances in each comparison. Flicker noise is a noise component with low-frequency drift characteristics, which changes slowly in a short time, but can affect the result when the calibration time is long. During the capacitor array calibration process, if the above three types of error sources cannot be taken into account simultaneously, the final weight value may have systematic deviations or random fluctuations, thereby affecting the linearity and accuracy of the SAR ADC after calibration.

[0027] like Figure 1-4 As shown, this embodiment of the invention provides a SAR ADC capacitor array digital self-calibration circuit, including: a sampling switch, a capacitor array, a comparator, a SAR control logic module, and a digital self-calibration calculation module.

[0028] The capacitor array includes multiple non-binary weighted capacitor units. The input of the comparator is connected to the output node of the capacitor array. The input of the SAR control logic module is connected to the output of the comparator. The SAR control logic module is used to generate control signals to control the switching of the lower plates of each capacitor in the capacitor array. The digital self-calibration calculation module is used to calculate the capacitor weights and the final output data based on the conversion results. The sampling switch is configured to connect a first voltage to the upper and lower plates of the capacitor array during the sampling phase to complete the reset, and then restore the capacitor array to a predetermined initial state based on the result stored in the digital self-calibration calculation module. The SAR control logic module includes a forced set circuit, which is configured to control the lower plate of any target capacitor to be connected from a first voltage to a second voltage in odd-numbered calibration cycles and from the first voltage to a third voltage different from the second voltage in even-numbered calibration cycles when calibrating any target capacitor. At the same time, other capacitors below the target capacitor are used to form a sub-ADC with the comparator for conversion. The digital self-calibration calculation module is configured to generate a digital output based on the odd number of calibration cycles corresponding to the target capacitance. and the digital output generated by an even number of calibration cycles Calculate the first number output respectively Second digital output and output based on the first number With the second digital output The difference determines the weight value W of the target capacitor, where: ; ; ; In the formula, m represents the complete statistical count corresponding to the odd-numbered calibration cycles and the even-numbered calibration cycles respectively; The digital output representing each odd-numbered calibration cycle corresponding to the target capacitor; The digital output representing each even-numbered calibration cycle corresponding to the target capacitor; This represents the average digital output of the odd-numbered calibration cycles corresponding to the target capacitor; The value represents the average digital output of an even number of calibration cycles corresponding to the target capacitor; W represents the weight value of the target capacitor.

[0029] In a preferred embodiment, the first voltage is an intermediate voltage located between the second voltage and the third voltage, and the first voltage is the arithmetic mean of the second voltage and the third voltage, so that the target capacitor produces signal voltage changes of equal magnitude and opposite sign in odd-numbered calibration cycles and even-numbered calibration cycles. For example, the first voltage is a common-mode voltage, the second voltage is a reference high voltage, and the third voltage is ground voltage.

[0030] Optionally, the capacitor array is a differential capacitor array, including multiple capacitors located in the positive differential branch and multiple capacitors located in the negative differential branch. Two capacitors in the same position in the positive and negative differential branches form a pair of matched capacitors and share the same weight value. The positive and negative input terminals of the comparator are respectively connected to the two output nodes of the differential capacitor array to compare the differential voltage formed after the target capacitor is switched.

[0031] Optionally, in the odd-numbered calibration cycles and the even-numbered calibration cycles, the SAR control logic module is configured to control the switching of each capacitor of the sub-ADC bit by bit, and after each capacitor is switched, the comparator performs multiple comparisons on the current comparison state, and the digital self-calibration calculation module determines the next capacitor to be connected to the second voltage or the third voltage based on the number of logic 1s in the multiple comparison results; wherein, the number of multiple comparisons is set according to the comparator noise level.

[0032] Optionally, when the number of comparisons increases to the point that all bit capacitor switching of the sub-ADC cannot be completed within a conversion cycle, the digital self-calibration calculation module is configured to record the switching state of the capacitor array after the last comparison of the conversion cycle, and restore the switching state before the start of the next conversion cycle with the same parity, so as to continue to complete the calibration cycle corresponding to the current target capacitor, until the least bit capacitor is compared and a complete digital output is obtained.

[0033] Optionally, the digital self-calibration calculation module is configured to calculate the weight value of each target capacitor sequentially from the low-order capacitor to the high-order capacitor, and when calibrating the higher-order target capacitor, substitute the weight of the low-order capacitor that has been calibrated into the corresponding calibration calculation process; after all the capacitors to be calibrated have been calibrated, the digital self-calibration calculation module is configured to reconstruct the output data of the SAR ADC using the obtained capacitor weights to obtain the final calibrated output data.

[0034] To explain the present invention more clearly, a detailed explanation of each component of the SAR ADC capacitor array digital calibration circuit is provided below.

[0035] Specifically, the sampling switch is used to connect the set voltage to the upper and lower plates of the capacitor array during the sampling phase, complete the reset, and restore the capacitor array to the predetermined initial state according to the results stored in the digital self-calibration calculation module before the start of each calibration cycle or during cycle switching; the capacitor array is used to form a voltage change related to its weight when the target capacitor is switched; the comparator is used to detect the polarity of the differential voltage formed by the output node of the capacitor array; the SAR control logic module is used to control the switching of the lower plate of each capacitor according to the bit-by-bit approximation rule; the digital self-calibration calculation module is used to receive the conversion result, statistically analyze the odd-even calibration cycle output, solve for the weight of each capacitor, and complete the final output data reconstruction.

[0036] Furthermore, in one executable implementation, the capacitor array is a differential capacitor array. That is, the capacitor array may include multiple capacitors located in the positive differential branch and multiple capacitors located in the negative differential branch. Two capacitors in the same position in the positive and negative branches together form a pair of matched capacitors and share the same weight value. It is easy to understand that this differential implementation is beneficial for improving the system's ability to suppress common-mode disturbances and makes the differential voltage change formed by the target capacitor switching clearer. Specifically, in the differential structure, the positive and negative input terminals of the comparator are connected to the output nodes of the positive and negative differential branches, respectively. When a target capacitor performs complementary switching in the positive and negative branches, a corresponding differential voltage change is formed across the comparator, and the comparator then provides a decision result. It should be noted that this invention does not limit the specific number of bits, nor does it limit the capacitor array to strictly binary weights, or the specific implementation method of the capacitor array, such as whether it is segmented or not. As long as it can participate in successive approximation and calibration processing according to the predetermined weight relationship, this invention is applicable.

[0037] In this embodiment of the invention, the SAR control logic module includes a forced set circuit. This forced set circuit plays a crucial role in the technical solution of the invention because it is directly responsible for performing a forced switching of positive and negative complementary voltages on the target capacitor during calibration. Specifically, when calibrating any target capacitor, the forced set circuit controls the target capacitor to connect its lower plate to a second voltage from a first voltage in odd-numbered calibration cycles; and to connect its lower plate to a third voltage different from the second voltage from the first voltage in even-numbered calibration cycles. Thus, the charge redistribution direction of the target capacitor is opposite in odd-numbered and even-numbered calibration cycles, thereby forming two types of signal voltage changes of equal magnitude but opposite signs at the comparator input. Furthermore, in a typical implementation, the first voltage can be a common-mode voltage Vcm, the second voltage can be a reference high voltage Vref, and the third voltage can be ground voltage GND; in another executable implementation, other three DC voltages that satisfy the intermediate potential relationship can also be selected, as long as the first voltage is between the second and third voltages, and the target capacitor forms symmetrical excitation in the odd and even cycles.

[0038] It is worth noting that this invention does not require the calibration of every single capacitor in the capacitor array. It is easy to understand that, to balance hardware complexity and calibration benefits, typically only the lowest few bits of capacitors need to be calibrated, while the lower-order capacitors are used as sub-ADCs. Specifically, when a target capacitor enters the calibration phase, the lower-order capacitors below it, together with the comparator, constitute the calibration sub-ADC to quantize the voltage change caused by the target capacitor switching. The advantage of this approach is that it eliminates the need for an additional auxiliary ADC, allowing the existing capacitor array and comparator to directly form an internal quantization path, thereby reducing area and implementation complexity. Simultaneously, after the lower-order target capacitors have completed weight calibration, when calibrating higher-order target capacitors, these known lower-order weights can continue to participate in new quantization and calculations, forming a bit-by-bit recursive calibration mechanism.

[0039] In a more specific embodiment of the present invention, the calibration process can start from the least significant target capacitor and proceed bit by bit to higher bits. Before calibration begins, the sampling switch restores the upper and lower plates of the capacitor array to the first voltage to complete initialization and reset. Subsequently, the SAR control logic module outputs the enable control signal for the current target capacitor and temporarily excludes higher-order capacitors from this calibration. Then, in the odd-numbered calibration cycles, the forced set circuit switches the lower plate of the current target capacitor from the first voltage to the second voltage. At this time, the comparator input forms a first polarity signal voltage change corresponding to the weight of the target capacitor. The sub-ADC then switches and quantizes this voltage change bit by bit under the control of the SAR control logic module, finally obtaining a complete odd-numbered calibration cycle digital output. After this output is completed, the sampling switch is reset again. In the subsequent even-numbered calibration cycles, the forced set circuit switches the lower plate of the same target capacitor from the first voltage to the third voltage. At this time, the comparator input generates a second polarity signal voltage change with opposite polarity. The sub-ADC quantizes this voltage change again to obtain a complete even-numbered calibration cycle digital output. Thus, the odd and even calibration cycles appear in pairs and alternate.

[0040] From a mathematical perspective, considering the effects of comparator DC offset, thermal noise, and flicker noise, for the same target capacitor, in odd-numbered calibration cycles, the k-th complete digital output can be represented as a digital quantity with the same sign as the target capacitor weight, plus the DC offset, thermal noise, and flicker noise terms. In even-numbered calibration cycles, the k-th complete digital output can be represented as a digital quantity with the opposite sign to the target capacitor weight, also plus the DC offset, thermal noise, and flicker noise terms. Based on this structure, this invention does not directly use the single result as the target capacitor weight, but instead averages the results of odd-numbered and even-numbered calibration cycles respectively to obtain... and Then, the weight value W of the target capacitor is obtained using the following formula: ; ; ; In the formula, m represents the complete statistical count corresponding to the odd-numbered calibration cycles and the even-numbered calibration cycles respectively; The digital output representing each odd-numbered calibration cycle corresponding to the target capacitor; The digital output representing each even-numbered calibration cycle corresponding to the target capacitor; This represents the average digital output of the odd-numbered calibration cycles corresponding to the target capacitor; The value represents the average digital output of an even number of calibration cycles corresponding to the target capacitor; W represents the weight value of the target capacitor.

[0041] It is easy to understand that, since DC offset is superimposed in the same direction in both odd-numbered and even-numbered calibration cycles, while the target capacitance weighting term appears in opposite directions in both types of cycles, therefore... In the process, the DC offset component will be effectively canceled out.

[0042] However, simply using parity calculation is insufficient to completely solve the noise problem. Therefore, this invention further introduces a multiple comparison mechanism during the bit-by-bit conversion process of the sub-ADC. Specifically, after each capacitor in the sub-ADC completes its current bit switching, the next capacitor's switching method is not immediately determined based on a single comparison result. Instead, the comparator performs multiple comparisons on the current state, and the digital self-calibration calculation module counts the number of logic 1s in the multiple comparison results, determining whether the next capacitor is connected to the second or third voltage. It's easy to understand that this statistical processing essentially introduces a majority decision approach at the bit-level decision stage. This prevents random disturbances from thermal noise in a single comparison from directly determining the switching direction of the next bit. Instead, the bit decision is generated through the overall statistical results after multiple samplings, making it less sensitive to thermal noise. Especially when the comparator's thermal noise amplitude is relatively large, there may be many accidental flips in a single comparison. Taking the logic majority after multiple comparisons significantly improves the stability of the bit decision.

[0043] It should be noted that the number of comparisons is not a fixed value for all chips or all scenarios. More specifically, in practical applications, the number of comparisons can be preset or dynamically adjusted based on factors such as the comparator's thermal noise level, the required system accuracy, the allowable calibration time, and the clock cycle. If the comparator noise is high, the number of comparisons can be appropriately increased to improve statistical reliability; if the system prioritizes calibration speed, the number of comparisons can be reduced while still meeting accuracy requirements. Therefore, this invention does not limit the specific value of the number of comparisons, but emphasizes using a mechanism of multiple comparisons and statistical decision-making to mitigate the impact of thermal noise.

[0044] Furthermore, in some high-resolution SAR ADCs, due to the large number of bits in the sub-ADC and the need for multiple comparisons per bit, it may be impossible to complete a full odd-numbered calibration cycle or a full even-numbered calibration cycle within a single conversion cycle. To address this issue, this invention proposes recording the switching state of the capacitor array in the digital self-calibration calculation module and restoring this state before the start of subsequent conversion cycles of the same parity, thus enabling a complete calibration cycle to be completed by multiple conversion cycles consecutively. Specifically, when the current conversion cycle reaches a bit before all low-order bit comparisons are completed, the digital self-calibration calculation module records the current capacitor array switching state at the end of that cycle. After sampling and resetting in the next conversion cycle of the same parity, before continuing the conversion, the previously recorded capacitor array state is restored, and comparisons and bit decisions are continued from the unfinished positions until the least significant bit capacitor is compared and a complete digital output is obtained. Therefore, the conversion cycle and complete calibration cycle described in this invention do not necessarily correspond one-to-one; a complete calibration cycle can be achieved by concatenating multiple conversion cycles of the same parity.

[0045] In this embodiment of the invention, the alternating timing of odd and even calibration cycles is specifically utilized to reduce the impact of flicker noise. It is easy to understand that flicker noise differs from thermal noise; its changes are slower over short timescales. If odd-numbered calibration cycles and their corresponding even-numbered calibration cycles are alternated within a short time interval, the flicker noise values ​​in adjacent cycles are usually quite close. In this case, when the difference between the odd-numbered and even-numbered average results is calculated, the flicker noise term, which is superimposed on both types of results and has a similar amplitude, will also cancel each other out to some extent. In other words, this invention, through a combination of positive and negative complementary excitation, short-time alternating execution, and odd-even difference calculation, can not only offset DC offset but also effectively reduce flicker noise. It should be noted that the flicker noise in adjacent cycles is not required to be absolutely equal; as long as they are sufficiently close, the residual term after the difference will be significantly reduced.

[0046] In a specific example, assuming the capacitor to be calibrated is a mid-position capacitor, such as C5, then its subsequent capacitors C4 to C0 can be used as sub-ADCs. In the first odd-numbered calibration cycle, the SAR control logic module switches the lower plate of C5 from common-mode voltage to a reference high voltage through a forced set circuit, causing the comparator input to form a first polarity differential voltage corresponding to the weight of C5. Subsequently, C4 to C0 are switched bit by bit under the control of the SAR control logic module, and multiple comparisons are performed after each switch. The digital self-calibration calculation module determines the switching direction of the next bit based on the statistical results of logic 1. When the least significant bit is completed, a complete odd-numbered calibration cycle output is obtained. Next, in the first even-numbered calibration cycle, the lower plate of C5 is switched from common-mode voltage to ground voltage to form a differential voltage with the opposite polarity to that of the previous cycle. The same bit-by-bit comparison and statistical processing are then used to obtain the output of a complete even-numbered calibration cycle. Then repeat the odd / even pairing process described above until both are obtained. as well as Then, the digital self-calibration calculation module calculates the calibration weight W of C5 according to the aforementioned formula.

[0047] After completing the weight calculation for the current lower-order target capacitors, this invention continues to calibrate towards higher-order capacitors. Furthermore, when higher-order target capacitors enter the calibration stage, the digital self-calibration calculation module substitutes the previously solved lower-order capacitor weights into the new calibration calculation process. This serves two purposes: firstly, the lower-order weights, after previous calibration, are closer to the true values, thus providing a more accurate benchmark for the quantization and solution of higher-order capacitors; secondly, this bit-by-bit recursive approach reduces the overall tendency for errors to accumulate from lower-order to higher-order capacitors. It is readily understood that the preferred calibration sequence in this invention is to progressively advance from lower-order capacitors to higher-order capacitors, but without violating the fundamental principles, appropriate adjustments can be made based on the specific capacitor array configuration and system timing requirements.

[0048] After all the weight values ​​of the capacitors to be calibrated have been calculated, the digital self-calibration calculation module uses these calibrated weights to digitally reconstruct the output of the SAR ADC during the normal conversion phase. Specifically, in normal conversion mode, the SAR ADC still obtains the decision results for each bit using a bit-by-bit approximation method, but its final output is no longer simply summed using ideal weights, but reconstructed using the weights of each bit obtained from actual calibration. In this way, the error caused by the actual weights of the capacitor array deviating from the ideal values ​​can be compensated in the digital domain, thus making the final output result more consistent with the actual characteristics of the circuit. It is easy to understand that this digital reconstruction can be implemented in the on-chip digital logic or in the subsequent digital processing link, and this invention does not limit it in this way.

[0049] In another feasible embodiment, such as Figure 5 As shown, this embodiment of the invention also provides a SAR ADC capacitor array digital self-calibration method for the SAR ADC capacitor array digital self-calibration circuit as described in any of the preceding claims, comprising the following steps: S1: Obtain the calibration digital output data corresponding to the target capacitor, and classify and store it according to the odd-numbered calibration cycle digital output and the even-numbered calibration cycle digital output; S2: Perform statistical processing on the comparison results of each bit in each calibration cycle, generate the decision result of the corresponding bit according to the number of logic 1s in each comparison result, and form the complete calibration cycle digital output accordingly; S3: Perform cumulative averaging on the digital outputs of odd-numbered calibration cycles and even-numbered calibration cycles respectively to obtain the first digital output and the second digital output; S4: Calculate the weight value of the target capacitor based on the difference between the first digital output and the second digital output; S5: Write the weight value of the target capacitor into the weight data set, and output the calibration result based on the updated weight data set.

[0050] In a preferred embodiment, step S2: Perform statistical processing on the comparison results of each bit in each calibration cycle, generate a decision result for the corresponding bit based on the number of logic 1s in each comparison result, and form a complete calibration cycle digital output accordingly, specifically including: S21: Count the multiple comparison results of the current bit to obtain the number of occurrences of logic 1, compare the number of occurrences of logic 1 with a preset threshold, and generate the decision result of the current bit; S22: Determine the data ownership or switching direction of the next bit based on the decision result of the current bit; S23: After all bit decision results are generated, combine the decision results of each bit to obtain a complete calibration cycle digital output.

[0051] In a preferred embodiment, step S4: calculating the weight value of the target capacitor based on the difference between the first digital output and the second digital output, specifically includes: S41: Digital output for odd-numbered calibration cycles Perform cumulative averaging to obtain the first numerical output. ; S42: Even-numbered calibration cycle digital output Perform cumulative averaging to obtain the second numerical output. ; S43: Calculate the weight value W of the target capacitor according to the following formula: ; ; ; Where m is the number of times the statistics are performed; The average result of an odd number of calibration cycles; The result is the average of an even number of calibration cycles; W is the weight value of the target capacitance.

[0052] In a preferred embodiment, step S5: writing the weight value of the target capacitor into a weighted data set, and outputting the calibration result based on the updated weighted data set, specifically includes: S51: Write the obtained target capacitor weights into the weight data set in sequence according to the capacitor position order; S52: In the calibration process corresponding to the higher-order capacitor, the written lower-order capacitor weights are called. After the weights of all capacitors to be calibrated are written, the SAR ADC conversion result is weighted and reconstructed according to the weight data set. S53: Outputs calibrated digital results that match the actual capacitor array weights.

[0053] To explain the present invention more clearly, a detailed explanation of each step in the SAR ADC capacitor array digital calibration method is provided below.

[0054] Specifically, this invention first acquires the odd-numbered and even-numbered calibration cycle digital outputs corresponding to the target capacitor and stores them accordingly; then, it performs statistical processing on the comparison results of each bit in each calibration cycle, forming a decision result for each bit based on the number of logic 1s, and combines these decision results to form the complete calibration cycle digital output; next, it accumulates and averages the results of the odd-numbered and even-numbered calibration cycles respectively to obtain the first digital output and the second digital output; subsequently, according to... The target capacitance weight is obtained by determining the relationship between the target capacitance weight and the weight data set. Finally, the target capacitance weight is written into the weight data set, and the calibration result is output based on the updated weight data set.

[0055] Furthermore, in the method implementation of the present invention, the statistical processing of each comparison result is not limited to simple counting itself, but also includes threshold judgment, bit decision generation, complete output combination, and cross-cycle data concatenation in actual execution. Specifically, for multiple comparison results of each bit, the number of occurrences of logic 1 is first counted, and then the number is compared with a preset threshold to determine the decision result of the current bit; subsequently, the data assignment or switching direction required for the next bit is generated according to the decision result of the current bit; when all bits are completed, the decision results of each bit are combined into a complete calibration cycle digital output; if the current conversion cycle has not completed all bits, the result obtained in this cycle is concatenated with the result of the subsequent cycle with the same parity until a complete output is formed.

[0056] It should be further noted that the various parts of the technical solution of this invention are not limited to a single, unique implementation. For example, the sampling switch can adopt different switching circuit structures depending on the chip implementation method; the capacitor array can adopt different forms (e.g., segmented or not), different bit configurations, and different non-binary weighted weight distributions; the comparator can adopt any suitable comparison structure that meets the requirements of decision speed and noise; the SAR control logic module can adopt hard-wired logic, finite state machine, or other digital control structures; the digital self-calibration calculation module can also be implemented in the form of dedicated calculation logic, timing multiplexing logic, or sharing resources with other digital processing logic. As long as these implementation methods can complete the functions required by this invention, such as target capacitor positive and negative complementary calibration, sub-ADC quantization, multiple comparison statistics, odd-even grouping difference calculation, and weight reconstruction, they should all be considered to fall within the protection scope of this invention.

[0057] It should also be noted that, in practical applications, this invention is particularly suitable for high-resolution, low-power, or area-constrained SAR ADC design scenarios. On one hand, this invention eliminates the need for an additional high-precision auxiliary ADC or a large auxiliary capacitor structure; instead, it directly utilizes the existing capacitor array and comparator to form the calibration path, thus facilitating control over area and power consumption. On the other hand, this invention, through a combination of odd-even complementary switching and digital processing, simultaneously addresses DC offset cancellation and noise suppression, making it more robust than calibration schemes that only consider one type of error source. Furthermore, because this invention uses digital processing to define the method portion, it also possesses good digital implementation flexibility, facilitating portability and integration across different process platforms and system architectures.

[0058] In summary, this invention introduces a complementary switching relationship between odd-numbered and even-numbered calibration cycles during the target capacitor calibration process. By performing multiple comparative statistical processing bit-by-bit on the sub-ADC, combined with odd-even group averaging and difference calculations, the influence of comparator DC offset, thermal noise, and flicker noise on the weighting solution is significantly suppressed. This results in more accurate capacitor array weight parameters and further enables digital reconstruction of the final output of the SAR ADC. Therefore, it improves the overall conversion accuracy and linearity of the SAR ADC, demonstrating significant practical value and potential for widespread application.

[0059] Other embodiments or specific implementations of the SAR ADC capacitor array digital self-calibration method of the present invention can be referred to the above-described circuit embodiments, and will not be repeated here.

[0060] It is understood that in the description of this specification, references to terms such as "one embodiment," "another embodiment," "other embodiments," or "first embodiment to Nth embodiment," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0061] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0062] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A SAR ADC capacitor array digital self-calibration circuit, characterized in that, include: Sampling switch, capacitor array, comparator, SAR control logic module and digital self-calibration calculation module; The capacitor array includes multiple non-binary weighted capacitor units. The input of the comparator is connected to the output node of the capacitor array. The input of the SAR control logic module is connected to the output of the comparator. The SAR control logic module is used to generate control signals to control the switching of the lower plates of each capacitor in the capacitor array. The digital self-calibration calculation module is used to calculate the capacitor weights and the final output data based on the conversion results. The sampling switch is configured to connect a first voltage to the upper and lower plates of the capacitor array during the sampling phase to complete the reset, and then restore the capacitor array to a predetermined initial state based on the result stored in the digital self-calibration calculation module. The SAR control logic module includes a forced set circuit, which is configured to control the target capacitor to connect its lower plate from a first voltage to a second voltage in odd-numbered calibration cycles and to connect its lower plate from the first voltage to a third voltage different from the second voltage in even-numbered calibration cycles when calibrating any target capacitor. At the same time, other capacitors below the target capacitor are used to form a sub-ADC with the comparator for conversion. The digital self-calibration calculation module is configured to generate a digital output based on the odd-numbered calibration cycles corresponding to the target capacitance. and the digital output generated by an even number of calibration cycles Calculate the first number output respectively Second digital output and output based on the first number With the second digital output The difference determines the weight value W of the target capacitor.

2. The SAR ADC capacitor array digital self-calibration circuit as described in claim 1, characterized in that, The first voltage is an intermediate voltage located between the second voltage and the third voltage, and the first voltage is the arithmetic mean of the second voltage and the third voltage, so that the target capacitor generates signal voltage changes of equal magnitude and opposite sign in odd-numbered calibration cycles and even-numbered calibration cycles.

3. The SAR ADC capacitor array digital self-calibration circuit as described in claim 1, characterized in that, The capacitor array is a differential capacitor array, including multiple capacitors located in the positive differential branch and multiple capacitors located in the negative differential branch. Two capacitors in the same position in the positive and negative differential branches form a pair of matched capacitors and share the same weight value. The positive and negative input terminals of the comparator are respectively connected to the two output nodes of the differential capacitor array to compare the differential voltage formed after the target capacitor is switched.

4. The SAR ADC capacitor array digital self-calibration circuit as described in claim 1, characterized in that, In the odd-numbered calibration cycles and the even-numbered calibration cycles, the SAR control logic module is configured to control the switching of each capacitor of the sub-ADC bit by bit, and after each capacitor is switched, the comparator performs multiple comparisons on the current comparison state, and the digital self-calibration calculation module determines the next capacitor to be connected to the second voltage or the third voltage based on the number of logic 1s in the multiple comparison results; wherein, the number of multiple comparisons is set according to the comparator noise level.

5. The SAR ADC capacitor array digital self-calibration circuit as described in claim 4, characterized in that, When the number of comparisons increases to the point that the switching of all bit capacitors of the sub-ADC cannot be completed within a conversion cycle, the digital self-calibration calculation module is configured to record the switching state of the capacitor array after the last comparison of the conversion cycle, and restore the switching state before the start of the next conversion cycle with the same parity, so as to continue to complete the calibration cycle corresponding to the current target capacitor, until the least bit capacitor is compared and a complete digital output is obtained.

6. The SAR ADC capacitor array digital self-calibration circuit as described in claim 1, characterized in that, The digital self-calibration calculation module is configured to calculate the weight value of each target capacitor in the order from the low-order capacitor to the high-order capacitor, and when calibrating the higher-order target capacitor, substitute the weight of the low-order capacitor that has been calibrated into the corresponding calibration calculation process. After all capacitors to be calibrated have been calibrated, the digital self-calibration calculation module is configured to reconstruct the output data of the SAR ADC using the obtained capacitor weights to obtain the final calibrated output data.

7. A digital self-calibration method for a SAR ADC capacitor array, used in the SAR ADC capacitor array digital self-calibration circuit as described in any one of claims 1-6, characterized in that, Includes the following steps: S1: Obtain the calibration digital output data corresponding to the target capacitor, and classify and store it according to the odd-numbered calibration cycle digital output and the even-numbered calibration cycle digital output; S2: Perform statistical processing on the comparison results of each bit in each calibration cycle, generate the decision result of the corresponding bit according to the number of logic 1s in each comparison result, and form the complete calibration cycle digital output accordingly; S3: Perform cumulative averaging on the digital outputs of odd-numbered calibration cycles and even-numbered calibration cycles respectively to obtain the first digital output and the second digital output; S4: Calculate the weight value of the target capacitor based on the difference between the first digital output and the second digital output; S5: Write the weight value of the target capacitor into the weight data set, and output the calibration result based on the updated weight data set.

8. The SAR ADC capacitor array digital self-calibration method as described in claim 7, characterized in that, Step S2: Perform statistical processing on the comparison results of each bit in each calibration cycle, generate the decision result for the corresponding bit based on the number of logic 1s in each comparison result, and form the complete digital output of the calibration cycle accordingly, specifically including: S21: Count the multiple comparison results of the current bit to obtain the number of occurrences of logic 1, compare the number of occurrences of logic 1 with a preset threshold, and generate the decision result of the current bit; S22: Determine the data ownership or switching direction of the next bit based on the decision result of the current bit; S23: After all bit decision results are generated, combine the decision results of each bit to obtain a complete calibration cycle digital output.

9. The SAR ADC capacitor array digital self-calibration circuit as described in claim 7, characterized in that, Step S4: Calculate the weight value of the target capacitor based on the difference between the first digital output and the second digital output, specifically including: S41: Digital output for odd-numbered calibration cycles Perform cumulative averaging to obtain the first numerical output. ; S42: Even-numbered calibration cycle digital output Perform cumulative averaging to obtain the second numerical output. ; S43: Calculate the weight value W of the target capacitor according to the following formula: ； ； ； Where m is the number of times the statistics are performed; The average result of an odd number of calibration cycles; The result is the average of an even number of calibration cycles; W is the weight value of the target capacitance.

10. The SAR ADC capacitor array digital self-calibration circuit as described in claim 7, characterized in that, Step S5: Write the weight value of the target capacitor into the weight data set, and output the calibration result based on the updated weight data set, specifically including: S51: Write the obtained target capacitor weights into the weight data set in sequence according to the capacitor position order; S52: In the calibration process corresponding to the higher-order capacitor, the written lower-order capacitor weights are called. After the weights of all capacitors to be calibrated are written, the SAR ADC conversion result is weighted and reconstructed according to the weight data set. S53: Outputs calibrated digital results that match the actual capacitor array weights.

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