integrated circuit

Abstract

An integrated circuit is disclosed. The integrated circuit includes: a first decoupling capacitor cell having a first discharge path; and a second decoupling capacitor cell having a second discharge path, wherein the first discharge path is formed in an external region of the first decoupling capacitor cell, and the second discharge path is formed in an internal region of the second decoupling capacitor cell.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2025-0002882, filed on January 8, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to integrated circuits. Background Technology

[0003] The semiconductor device may include circuit blocks that perform logic functions, and the circuit blocks may include unit circuits that perform predetermined functions and capacitors that supply a stable power supply voltage and remove noise. The capacitors may be, for example, decoupling capacitors. Summary of the Invention

[0004] In some examples, decoupling capacitors can remove high-frequency noise entering the power supply voltage, or directly provide the power supply voltage required by internal components when the circuit block operates at high frequencies, thereby eliminating the inductive component that may appear when connected to an external power supply and reducing impedance from the power supply perspective. Here, it is desirable to remove plasma charges that occur during the operation of the semiconductor device.

[0005] This disclosure provides a cell structure capable of discharging plasma charge in a cell including a decoupling capacitor.

[0006] In general, in some aspects, this disclosure provides an integrated circuit, the integrated circuit comprising: a first decoupling capacitor unit having a first discharge path; and a second decoupling capacitor unit having a second discharge path, wherein the first discharge path is formed as an external region of the first decoupling capacitor unit, and the second discharge path is formed as an internal region of the second decoupling capacitor unit.

[0007] In general, in some aspects, this disclosure provides an integrated circuit comprising: a plurality of cell arrays, wherein the plurality of cell arrays includes: a first decoupling capacitor cell array including a plurality of first decoupling capacitor cells; and a second decoupling capacitor cell array including a plurality of second decoupling capacitor cells, wherein each of the plurality of first decoupling capacitor cells includes a top metal line forming a first path for discharging charges appearing in each of the plurality of first decoupling capacitor cells, and each of the plurality of second decoupling capacitor cells includes a second junction region forming a second path for discharging charges appearing in each of the plurality of second decoupling capacitor cells.

[0008] In general, in some aspects, this disclosure provides an integrated circuit comprising: a plurality of cell arrays; and an input / output (I / O) pad configured to input / output signals applied to the plurality of cell arrays, wherein the I / O pad includes a first discharge path configured to discharge plasma charges formed by the plurality of cell arrays. Attached Figure Description

[0009] Figure 1 This is a diagram showing an integrated circuit that includes multiple unit cells.

[0010] Figure 2 This is a diagram showing the connection relationship between the input / output pads and decoupling capacitor cells in an integrated circuit.

[0011] Figure 3 This is a plan view showing the connection relationship between the first decoupling capacitor unit and the input / output pad.

[0012] Figure 4 It is along Figure 3 The sectional view taken from line A-A' of the plan view.

[0013] Figure 5 It is along Figure 3 The sectional view taken from line B-B' of the plan view.

[0014] Figure 6 This is a plan view of the second decoupling capacitor unit.

[0015] Figure 7 It is along Figure 6 Example of a cross-sectional view taken from line C-C' of the second decoupling capacitor unit.

[0016] Figure 8 This is another example of a cross-sectional view of the second decoupling capacitor unit.

[0017] Figure 9 This is another example of a cross-sectional view of the second decoupling capacitor unit.

[0018] Figure 10 This is another example of a cross-sectional view of the first decoupling capacitor cell.

[0019] Figures 11A to 11D This is a diagram illustrating examples of components that may be included in an integrated circuit.

[0020] Figure 12 This is a flowchart illustrating a method for manufacturing integrated circuits.

[0021] Figure 13 This is a block diagram showing the system-on-a-chip.

[0022] Figure 14 This is a block diagram illustrating a computing system that includes a memory containing a stored program. Detailed Implementation

[0023] Various embodiments are described below with reference to the accompanying drawings.

[0024] Here, the X-axis and Y-axis directions can be referred to as the first direction (or first horizontal direction) and the second direction (or second horizontal direction), respectively, and the Z-axis direction can be referred to as the vertical direction or the third direction. The plane formed by the X-axis and Y-axis can be referred to as the horizontal plane, and a component located in the +Z-axis direction relative to other components can be referred to as being located on top of other components, and a component located in the -Z-axis direction relative to other components can be referred to as being located below other components. Furthermore, the area of ​​a component can represent the size occupied by the component in a plane parallel to the horizontal plane, and the width of a component can represent the length of the component in a direction orthogonal to the direction in which the component extends. The surface exposed in the +Z direction can be referred to as the top surface, the surface exposed in the -Z direction can be referred to as the bottom surface, and the surface exposed in the ±X or ±Y directions can be referred to as the side surface. A pattern including conductive material (e.g., a pattern of interconnect layers) can be referred to as a conductive pattern, or simply a pattern. Furthermore, a pattern extending in one direction can be referred to as a line.

[0025] In the accompanying drawings of this specification, only some layers may be depicted for ease of explanation, and for the sake of understanding, the vias connecting the upper and lower patterns may be indicated even if the vias are located below the upper pattern.

[0026] Figure 1 This is a diagram showing an integrated circuit 10 comprising multiple unit cells.

[0027] Reference Figure 1 Integrated circuit 10 may include a cell array region CA in which multiple cells are arranged, and an outer region PA. In some examples, multiple metal lines and multiple circuit devices connected to the multiple metal lines may be arranged in the cell array region CA. The outer region PA may be a peripheral region surrounding the cell array region CA. In some examples, a cell array 20 including multiple cells may be arranged in the cell array region CA. The cell array 20 may include multiple unit cells. Figure 1 As shown, the cell array 20 comprises 4×4 unit cells, but this is shown for illustrative purposes, and the cell array 20 may comprise tens to hundreds or thousands of unit cells.

[0028] A portion of the multiple cells included in cell array 20 may be standard cells. A standard cell is a layout unit included in integrated circuit 10 and may be simply referred to as a cell in this specification. In some examples, a standard cell may be a functional cell or logic cell that provides Boolean logic or storage functionality. For example, a logic cell may be a NAND, AND, NOR, OR, XOR, inverter, adder, flip-flop, or latch. Integrated circuit 10 may include a number of different logic cells. Standard cells may have a structure conforming to predetermined specifications and may be arranged in multiple rows.

[0029] In some examples, a portion of the multiple cells included in cell array 20 may be decoupling capacitor cells. In some examples, a decoupling capacitor cell may represent the smallest unit cell including at least one decoupling capacitor and including a discharge path to the outside or to the inside. In some examples, a decoupling capacitor cell may represent the smallest unit cell capable of performing the following functions: removing high-frequency noise entering the power supply voltage, directly providing the power supply voltage required by the internal device when the circuit block operates at high frequencies, or eliminating the inductive component that appears when connected to an external power supply. In some examples, according to some embodiments, a decoupling capacitor array including multiple decoupling capacitor cells may be arranged in cell array region CA to maintain the stability of the power supply applied to the memory cell array included in integrated circuit 10 and prevent sudden changes in current. Furthermore, each decoupling capacitor cell may include a discharge path that can discharge plasma charges generated during circuit operation through a junction structure. Thus, unwanted charges can be discharged stably, which has the effect of ensuring circuit stability. The detailed structure of the decoupling capacitor cell is described below.

[0030] Reference Figure 1Integrated circuit 10 may include multiple input / output (I / O) pads (or solder pads) 31, 32, 33, 34, and 35. In some examples, the multiple I / O pads 31, 32, 33, 34, and 35 may be pads that can transmit signals provided from the outside to internal cells. In some examples, the multiple I / O pads 31, 32, 33, 34, and 35 may be pads that can transmit signals generated in internal cells to the outside. In some examples, each of the multiple I / O pads 31, 32, 33, 34, and 35 may include buffer circuitry. Each of the multiple I / O pads 31, 32, 33, 34, and 35 may be arranged in an edge region of integrated circuit 10, and various circuits included in integrated circuit 10 may receive power, data, or signals through the multiple I / O pads 31, 32, 33, 34, and 35. According to some examples, multiple I / O pads 31, 32, 33, 34 and 35 can be connected to the circuitry that supplies power, and can send the power supply voltages VDD and VSS to the cell array 20.

[0031] According to some embodiments, the decoupling capacitor cell can be connected to an I / O pad, allowing the discharge path to be controlled in the direction of the I / O pad. According to some embodiments, the decoupling capacitor cell can be connected to a junction inside the decoupling capacitor cell, allowing the discharge path to be controlled in the inward direction of the capacitor cell. The connection structure of the decoupling capacitor cell is described in detail below with reference to the accompanying drawings.

[0032] Figure 2 This is a diagram illustrating the connection relationship between the I / O pads and decoupling capacitor cells in an integrated circuit 10 according to some embodiments.

[0033] exist Figure 2 The description omits references to the above. Figure 1 The description given is the same as the description given, and for ease of description, only some metals are shown and vias are omitted.

[0034] according to Figure 2 Some implementations include a 4×4 array of cells in cell array 20 that may include multiple first decoupling capacitor cells DC1 and multiple second decoupling capacitor cells DC2. Figure 2 In the description, the number of first decoupling capacitor units DC1 is shown to be the same as the number of second decoupling capacitor units DC2, but this is for ease of description, and the number of first decoupling capacitor units DC1 and second decoupling capacitor units DC2 included in the unit array 20 can be varied.

[0035] In some examples, a first decoupling capacitor cell array DC11 including a first decoupling capacitor cell DC1 and a second decoupling capacitor cell array DC22 including a second decoupling capacitor cell DC2 are disclosed. In one example, a plurality of I / O pads can transmit signals to at least one of the first and second decoupling capacitor cells and receive signals from at least one of the first and second decoupling capacitor cells.

[0036] According to some embodiments, each of the first decoupling capacitor unit DC1 and the second decoupling capacitor unit DC2 may include a first metal line MT1 and a second metal line MT2. In some examples, the first metal line MT1 may be a metal line formed to extend in a first direction (X-axis direction), and the second metal line MT2 may be a metal line formed to extend in a second direction (Y-axis direction). According to some embodiments, the first metal line MT1 may be a line disposed above the second metal line MT2. In some examples, the first metal line MT1 may represent a metal line disposed in the top metal layer of the integrated circuit 10. In some examples, a smaller number indicated before the metal line may indicate a metal line disposed in the upper metal layer. In some embodiments, the first metal line MT1 may be a metal line disposed in the top metal layer, and the fifth metal line MT5 may be a metal line disposed in the bottom metal layer.

[0037] Return to reference Figure 2 First metal lines MT1a, MT1b, and MT1c, arranged on the top metal layer of a plurality of first decoupling capacitor cells DC1 included in the first decoupling capacitor cell array DC11, can extend to the upper region of a portion of the plurality of I / O pads. In addition to the top metal layer of the plurality of first decoupling capacitor cells DC1 included in the first decoupling capacitor cell array DC11, a second metal line MT2 may be provided with a length that is not electrically connected to adjacent decoupling capacitor cells. With this structure, the plurality of first decoupling capacitor cells DC1 included in the first decoupling capacitor cell array DC11 can be connected to cells other than their corresponding cells via the first metal lines MT1a, MT1b, and MT1c, which serve as top metal lines. According to some examples, the first decoupling capacitor cell array DC11 can be connected to I / O pads 33 and 34 via the first metal lines MT1a, MT1b, and MT1c, and thus, charged particles (e.g., plasma charges) appearing in each of the first decoupling capacitor cells can be discharged outward in the direction of the I / O pads, thereby forming a first discharge path. This will refer to... Figures 3 to 5 To describe in more detail.

[0038] Reference Figure 2The first metal lines MT1d, MT1e, MT1f, and MT1g arranged on the top metal layer of the plurality of second decoupling capacitor units DC2 included in the second decoupling capacitor unit array DC22 may not be connected to the plurality of I / O pads 31, 32, and 33. According to some embodiments, the second metal line MT2 included in the plurality of second decoupling capacitor units DC2 in the second decoupling capacitor unit array DC22 may extend in a second direction, and the length of the second metal line MT2 in the second direction may be greater than the length of a single second decoupling capacitor unit DC2 in the second direction. That is, the plurality of second decoupling capacitor units DC2 included in the second decoupling capacitor unit array DC22 may share the second metal line MT2. Due to this structure, the connected metal area in the second decoupling capacitor unit DC2 can be increased, and therefore the effect of plasma charge can be significant. The second decoupling capacitor unit DC2 can discharge charged particles (e.g., plasma charge) in a different manner than the first decoupling capacitor unit DC1 by forming a second discharge path inside the second decoupling capacitor unit DC2.

[0039] According to some examples, a first decoupling capacitor cell may be distinguished from a second decoupling capacitor cell based on where the path for discharging the plasma charge appearing in the decoupling capacitor cell is formed. In some examples, the first and second decoupling capacitor cells may have different structures. In one example, the first decoupling capacitor cell may not include a junction region, while the second decoupling capacitor cell may include a junction region. In some examples, the first and second decoupling capacitor cells may have different structures in the front-end process (FEOL) region and the back-end process (BEOL) region. In one example, the FEOL region of the first decoupling capacitor cell may not include a junction region, while the FEOL region of the second decoupling capacitor cell may include a junction region. In another example, the BEOL region of the first decoupling capacitor cell may include a top metal line connected to an I / O pad, and the BEOL region of the second decoupling capacitor cell may not be connected to a top metal line and an I / O pad. In some examples, the dimensions of the first and second decoupling capacitor cells may be the same. The structures of the first and second decoupling capacitor cells are described below with reference to the accompanying drawings.

[0040] Figure 3 This is a plan view showing the connection relationship between the first decoupling capacitor unit DC1 and the I / O pad according to some embodiments.

[0041] Reference Figure 3The first decoupling capacitor unit DC1 may include a plurality of first metal lines MT1, which extend in a first direction (e.g., the X-axis direction) and are formed separately from each other in a second direction (e.g., the Y-axis direction). The first decoupling capacitor unit DC1 may include a second metal line MT2, which extends in the second direction (e.g., the Y-axis direction) and is formed separately from each other in the first direction (e.g., the X-axis direction). In some examples, the first metal lines MT1 may be arranged above the second metal lines MT2. In some examples, the first metal lines MT1 may be metal lines arranged on the top metal layer of the first decoupling capacitor unit DC1.

[0042] In some examples, the first decoupling capacitor unit DC1 may also include a via VIA that physically connects the first metal line MT1 to the second metal line MT2 in a third direction (e.g., the Z-axis direction).

[0043] In some examples, at least one of the first metal lines MTA1 included in the first decoupling capacitor unit DC1 may extend in a first direction to have a length extending beyond the boundary of the first decoupling capacitor unit DC1. The first metal line MTA1 may extend in the first direction and extend to the upper region of the first I / O pad 310. The first metal line MTA1 may be physically connected to the first I / O pad 310 via a via VIA.

[0044] Reference Figure 3 In this example, the first I / O pad 310 and the first decoupling capacitor unit DC1 may share a first metal line MTA1 and can be physically connected via the first metal line MTA1. Plasma charges appearing in the first decoupling capacitor unit DC1 can move towards the first I / O pad 310 via the first metal line MTA1 and be discharged. The corresponding structure is described in detail with reference to the following figures.

[0045] Figure 4 It is along Figure 3 The sectional view taken by line A-A' of the plan view, and Figure 5 It is along Figure 3 The sectional view taken from line B-B' of the plan view.

[0046] Reference Figure 4The first decoupling capacitor unit DC1 may include a substrate Sub, multiple gates, a first metal line MT1, a second metal line MT2, a third metal line MT3, a fourth metal line MT4, and a fifth metal line MT5, and may include multiple vias VIA, which can physically connect the metal lines to the multiple gates respectively in a third-party direction. In one example, an insulating material Iso may be connected between the multiple gates and the substrate Sub. The active region that can be combined with the multiple gates to form a metal-oxide-semiconductor (MOS) capacitor may be formed on the substrate Sub, but not on the substrate Sub. Figure 4 and Figure 5 The cross-sectional view is shown. In some examples, multiple MOS capacitors, each corresponding to a plurality of gates included in the first decoupling capacitor cell DC1, may be formed on the substrate Sub. In some examples, the MOS capacitors may be implemented as NFETs or PFETs, but are not limited thereto.

[0047] Reference Figure 4 The first metal wire MT1, the third metal wire MT3, and the fifth metal wire MT5 may extend in a first direction. Each of the first metal wire MT1, the third metal wire MT3, and the fifth metal wire MT5 may be arranged separately from each other in a second direction in a metal layer on which each metal wire is arranged.

[0048] Reference Figure 4 The lengths of the third metal wire MT3 and the fifth metal wire MT5 in the first direction may differ from the length of the first decoupling capacitor unit DC1 in the first direction. The length D2 of the third metal wire MT3 and the fifth metal wire MT5 in the first direction may be less than the length D1 of the first decoupling capacitor unit DC1 in the first direction. In some examples, the length D2 of the third metal wire MT3 and the fifth metal wire MT5 in the first direction may differ from the length D3 of the first metal wire MT1 in the first direction.

[0049] The length D3 of the first metal line MT1 in the first direction may be greater than the length D2 of the third metal line MT3 and the fifth metal line MT5 in the first direction and the length D1 of the first decoupling capacitor unit DC1 in the first direction.

[0050] Reference Figure 4 The length D2 of the lower metal lines, other than the first metal line MT1 which serves as the top metal layer, in the first direction can be less than the length D1 of the first decoupling capacitor unit DC1 in the first direction. Therefore, the other metal layers, besides the top metal layer, can be used for wiring within the first decoupling capacitor unit DC1 and can be unconnected to other external units.

[0051] Reference Figure 5The lengths of the second metal wire MT2 and the fourth metal wire MT4 in the second direction can be D4. In some examples, the lengths of the second metal wire MT2 and the fourth metal wire MT4 in the second direction may differ from the length D1' of the first decoupling capacitor unit DC1 in the second direction. In some examples, the lengths D4 of the second metal wire MT2 and the fourth metal wire MT4 in the second direction may have a value smaller than the length D1' of the first decoupling capacitor unit DC1 in the second direction.

[0052] Reference Figure 4 and Figure 5 Among the multiple metal lines included in the first decoupling capacitor unit DC1, the lengths of the second metal line MT2, the third metal line MT3, the fourth metal line MT4, and the fifth metal line MT5, arranged in the remaining metal layers excluding the first metal line MT1 disposed in the top metal layer, may be provided to a length not exceeding the boundary of the first decoupling capacitor unit DC1. In some examples, the length D1 of the first decoupling capacitor unit DC1 in the first direction may be greater than the length D2 of the third metal line MT3 and the fifth metal line MT5 extending in the first direction in the first direction, and the length D1' of the first decoupling capacitor unit DC1 in the second direction may be greater than the length D4 of the second metal line MT2 and the fourth metal line MT4 extending in the second direction in the second direction. Thus, the remaining metal lines, excluding the first metal line MT1, can be used only for wiring within the first decoupling capacitor unit DC1.

[0053] In the first decoupling capacitor cell DC1 according to some examples, the remaining lower metal lines, other than the first metal line MT1, can be offset inward from the boundary of the first decoupling capacitor cell DC1, thereby maintaining the capacitance of the cell while allowing the lower metal lines to be wired only inside.

[0054] Return to reference Figure 4 A discharge path for discharging plasma charges appearing in the first decoupling capacitor unit DC1 can be generated in the first I / O pad 310. The first I / O pad 310 may include a first junction region 311 formed on the substrate Sub, and the first junction region 311 may be physically connected to the fifth metal line MT5 via a first via VIA1. The first I / O pad 310 may include a fifth metal line MT5, a fourth metal line MT4, a third metal line MT3, and a second metal line MT2 separated from each other in the Z-axis direction, and the metal lines may be connected to each other in the third direction via via VIA. The second metal line MT2 may be connected to the first metal line MT1 in the third direction via via VIA.

[0055] The first I / O pad 310 can form a first discharge path DCPATH1 through the first junction region 311. The first junction region 311 of the first I / O pad 310 can be a diode with an np junction having a p-type well and an n-type diffusion, or a diode with an np junction having an n-type well and a p-type diffusion. In some embodiments, the first junction region 311 can be implemented in other ways.

[0056] When the first junction region 311 and the first metal line MT1 form the first discharge path DCPATH1, plasma charge or noise signals appearing in the first decoupling capacitor cell DC1 can be directed to the first I / O pad 310. This prevents the charge appearing in the first decoupling capacitor cell DC1 from being applied to the transistors inside the first decoupling capacitor cell DC1, thereby protecting the transistors inside the first decoupling capacitor cell DC1 and preventing the analog circuitry including the internal transistors from being degraded by micro-noise. Furthermore, in some examples, because the first junction region 311 formed on the first I / O pad 310 is connected to the first metal line MT1 as the top metal for discharge, no new junction region is added, and therefore no new region is added for discharge, which can be advantageous in terms of area.

[0057] Reference Figures 3 to 5 For example, because the first decoupling capacitor cell DC1 forms a first discharge path in the direction of the I / O pad, the interior of the first decoupling capacitor cell DC1 may not include a junction region, and all gates included in the first decoupling capacitor cell DC1 may be configured to be connected to a metal line.

[0058] exist Figure 4 and Figure 5 The image shows an example where the metal layers comprise a total of five layers. In some implementations, the first decoupling capacitor unit DC1 may include N metal layers. N can be a natural number greater than or equal to 2.

[0059] Figure 6 This is a plan view of the second decoupling capacitor unit DC2 according to some embodiments.

[0060] Reference Figure 6 The second decoupling capacitor unit DC2 may include multiple first metal lines MT1 and multiple second metal lines MT2. The multiple first metal lines MT1 extend in a first direction and are arranged separately from each other in a second direction, and the multiple second metal lines MT2 extend in the second direction and are arranged separately from each other in the first direction. In one example, the multiple second metal lines MT2 may be arranged below the first metal lines MT1.

[0061] Multiple first metal lines MT1 and multiple second metal lines MT2 formed in different layers can be physically connected via vias VIA extending upwards in a third layer. In some examples, the second decoupling capacitor cell DC2 may not be physically connected to the I / O pad. The structure and discharge path in the second decoupling capacitor cell DC2 are described in detail below with cross-sectional views.

[0062] Figure 7 It is intercepted along line C-C'. Figure 6 A cross-sectional view of each example of the second decoupling capacitor unit DC2.

[0063] Reference Figure 7 The second decoupling capacitor unit DC2 may include a first metal line MT1, a third metal line MT3, and a fifth metal line MT5 extending in a first direction. The second decoupling capacitor unit DC2 may also include a second metal line MT2 and a fourth metal line MT4 extending in a second direction, and the multiple metal lines can be physically connected vias VIA extending vertically. In one example, an insulating material Iso may be connected between multiple gates and the substrate Sub. An active region that can be combined with multiple gates to form a MOS capacitor may be formed on the substrate Sub, but not on... Figures 7 to 9 As shown in the cross-sectional view. In some examples, multiple MOS capacitors, each corresponding to a plurality of gates included in the second decoupling capacitor unit DC2, may be formed on the substrate Sub.

[0064] according to Figure 7 For example, the substrate Sub of the second decoupling capacitor unit DC2 may include a second junction region JC2 and a third junction region JC3. The second junction region JC2 and the third junction region JC3 may be a diode with an np junction having a p-type well and an n-type diffusion, or a diode with an np junction having an n-type well and a p-type diffusion. In some embodiments, the second junction region JC2 and the third junction region JC3 may be implemented in other ways.

[0065] Reference Figure 7 The second junction region JC2 may be formed in the substrate Sub. The second junction region JC2 may be physically connected to the fifth metal line MT5 of the bottom metal layer of the second decoupling capacitor unit DC2 via the second via VIA2. According to some embodiments, the length of the plurality of metal lines included in the second decoupling capacitor unit DC2 may have a value equal to the length of the boundary of the second decoupling capacitor unit DC2.

[0066] According to some embodiments, the lengths of the first metal wire MT1, the third metal wire MT3, and the fifth metal wire MT5 included in the second decoupling capacitor unit DC2 in the first direction may be the same as the length D5 of the second decoupling capacitor unit DC2 in the first direction. The lengths of the second metal wire MT2 and the fourth metal wire MT4 included in the second decoupling capacitor unit DC2 in the second direction may be the same as the length of the second decoupling capacitor unit DC2 in the second direction. Multiple metal wires included in the second decoupling capacitor unit DC2 may share metal wires with adjacent decoupling capacitor units.

[0067] Because the second decoupling capacitor unit DC2 may have a structure that shares a metal wire with the adjacent decoupling capacitor unit, and it is necessary to discharge the plasma charge appearing in the corresponding capacitor unit inside the decoupling capacitor unit, the second decoupling capacitor unit DC2 can discharge the plasma charge appearing in the second decoupling capacitor unit DC2 through the second junction region JC2. This allows the formation of a second discharge path DCPATH2. In some embodiments, a discharge path can be formed inside the second decoupling capacitor unit DC2 through the fifth metal wire MT5 as the bottom metal wire and the second junction region JC2.

[0068] In some examples, the second decoupling capacitor unit DC2 may include multiple junction regions JC2 and JC3, at least a portion of which may be connected to a bottom metal line. In some examples, the bottom metal line may represent a metal line located at the height closest to the gate in a third-order upward direction, and... Figures 7 to 9 In this configuration, the bottom metal line can be a fifth metal line MT5. In some implementations, the second decoupling capacitor unit DC2 may include two or more second junction regions, and at least one of the two or more second junction regions may be configured to be physically connected to metal lines above the plurality of gates.

[0069] according to Figure 7 For example, the second decoupling capacitor unit DC2 may include multiple junction regions JC2 and JC3, and wherein the second junction region JC2 may be physically connected to the fifth metal line MT5 through a second via VIA2 to form a second discharge path DCPATH2.

[0070] Figure 8 and Figure 9 This is another example of a cross-sectional view of the second decoupling capacitor unit DC2.

[0071] According to some implementation methods Figure 8 and Figure 9 The sectional view is taken along the direction extending along the X-axis. Figure 6 A cross-sectional view of the second decoupling capacitor unit DC2. In some examples, Figure 8 and Figure 9 The location of the via shown is not included in Figure 6 The via layout in the second decoupling capacitor unit DC2 corresponds to the via structure. However, for ease of description, this is shown by omitting the via structure of the second decoupling capacitor unit DC2, and is configured to be consistent with... Figure 8 and Figure 9 The second decoupling capacitor unit DC2 corresponding to the location of the via shown can be disclosed.

[0072] According to some implementation methods, refer to Figure 8 For example, the second decoupling capacitor unit DC2 may include multiple junction regions JC2 and JC3, and the third junction region JC3 among the multiple junction regions JC2 and JC3 may be physically connected to the fifth metal line MT5 through a third via VIA3. Thus, a third discharge path DCPATH3 can be formed.

[0073] According to some implementation methods, refer to Figure 9 For example, the second decoupling capacitor unit DC2 may include multiple junction regions JC2 and JC3. The second junction region JC2 of the multiple junction regions JC2 and JC3 is physically connected to the fifth metal line MT5 through a second via VIA2, and the third junction region JC3 of the multiple junction regions JC2 and JC3 is physically connected to the fifth metal line MT5 through a third via VIA3. Thus, a second discharge path DCPATH2 and a third discharge path DCPATH3 can be formed.

[0074] Reference Figures 7 to 9 As an example, the second decoupling capacitor cell DC2 may include a junction region capable of forming one or more discharge paths in a substrate Sub within the cell. By connecting the junction region to a bottom metal wire via vias, one or more discharge paths can be formed, allowing plasma charges generated within the second decoupling capacitor cell DC2 to be discharged within the cell via the one or more discharge paths.

[0075] According to some implementation methods Figures 7 to 9 The second junction region JC2 and the third junction region JC3 shown can correspond to the guard ring structure.

[0076] Figure 10 This is another example of a cross-sectional view of a first decoupling capacitor cell according to some implementations.

[0077] exist Figure 10 The description omits references to the above. Figure 4 The component being described is the same as the component being described.

[0078] Reference Figure 10The first metal line MT1 of the first decoupling capacitor unit may extend to the I / O pad 320 in a first direction. In some examples, the I / O pad 320 may include a first junction region 321 formed in the substrate Sub. The first junction region 321 may be physically connected to the first metal line MT1 via a through-silicon via (TSV, or through-silicon via) TSV1. That is, various structures may be configured to connect the first junction region 321 to the first metal line MT1 in a third direction.

[0079] According to some implementations, a first decoupling capacitor unit can be applied when the effect of the capacitor is relatively insignificant and the IR drop is strong, and a second decoupling capacitor unit can be applied when the capacitor is used as an RC circuit in an analog circuit to quickly handle the discharge.

[0080] Figures 11A to 11D This is a diagram illustrating an example of a component that may be included in an integrated circuit, based on the example.

[0081] For example, Figure 11A FinFET 11a is shown. Figure 11B This shows a fully all-around gate field-effect transistor (GAAFET) 11b. Figure 11C This illustrates a multi-bridge channel field-effect transistor (MBCFET) 11c, and... Figure 11D A vertical field-effect transistor (VFET) 11d is shown. For ease of illustration, Figures 11A to 11C This shows the state where one of the two source / drain regions has been removed, and Figure 11D A cross-section of VFET 11d is shown, taken along a plane parallel to the planes of the Y and Z axes and passing through the channel CH of VFET 11d.

[0082] Reference Figure 11A FinFET 11a may be formed from a finned active pattern extending in the Y-axis direction between shallow trench isolation (STI) elements and a gate electrode G extending in the X-axis direction. Source / drain regions S / D may be formed on opposite sides of the gate electrode G, thus separating the source from the drain in the Y-axis direction. An insulating film may be formed between the channel CH and the gate electrode G. In some embodiments, the FinFET may be formed from multiple active patterns and a gate electrode G separated from each other in the X-axis direction, and may have an extended channel.

[0083] Reference Figure 11BThe GAAFET 11b can be formed from active patterns (i.e., nanowires) separated from each other in the Z-axis direction and extending in the Y-axis direction, and a gate electrode G extending in the X-axis direction. Source / drain regions S / D can be formed on opposite sides of the gate electrode G, thus the source can be separated from the drain in the Y-axis direction. An insulating film can be formed between the channel CH and the gate electrode G. The number of nanowires included in the GAAFET 11b is not limited to... Figure 11B The quantities shown.

[0084] Reference Figure 11C The MBCFET 11c can be formed from active patterns (i.e., nanosheets) that are separated from each other in the Z-axis direction and extend in the Y-axis direction, and a gate electrode G that extends in the X-axis direction. Source / drain regions S / D can be formed on opposite sides of the gate electrode G; therefore, the source can be separated from the drain in the Y-axis direction. An insulating film can be formed between the channel CH and the gate electrode G. The number of nanosheets included in the MBCFET is not limited to... Figure 11C The quantities shown.

[0085] Reference Figure 11D The VFET 11d may include a top source / drain region T_SD and a bottom source / drain region B_SD separated from each other in the Z-axis direction, with a channel CH located between the top source / drain region T_SD and the bottom source / drain region B_SD. The VFET 11d may include a gate electrode G surrounding the periphery of the channel CH between the top source / drain region T_SD and the bottom source / drain region B_SD. An insulating film may be formed between the channel CH and the gate electrode G.

[0086] Devices included in integrated circuits according to some examples may not be limited to Figures 11A to 11D Examples of devices are shown. For example, an integrated circuit may include a ForkFET, in which the N-type transistor and the P-type transistor are brought closer together because the nanosheets for the P-type transistor and the nanosheets for the N-type transistor are separated by dielectric walls. Furthermore, the integrated circuit may include bipolar junction transistors and FETs (such as complementary field-effect transistors (CFETs), negative capacitance field-effect transistors (NCFETs), and carbon nanotube (CNT) FETs).

[0087] Figure 12 This is a flowchart illustrating a method for manufacturing an integrated circuit according to some embodiments.

[0088] Reference Figure 12The method according to this embodiment can be a method of manufacturing an integrated circuit (IC) including standard cells and decoupling capacitor cells, and may include multiple operations S10, S30, S50, S70, and S90. The cell library (or standard cell library) D12 may include information about standard cells (such as information about their functions, characteristics, layout, etc.). In some embodiments, the cell library D12 may define tap cells, fill cells, and dummy cells, as well as functional cells that generate output signals from input signals. In some embodiments, the cell library D12 may define multiple bit cells. Design rules D14 may include requirements that the layout of the integrated circuit IC should follow. For example, design rules D14 may include requirements for the spacing between patterns on the same layer, the minimum width of patterns, the wiring direction in interconnect layers, etc.

[0089] In operation S10, a logic synthesis operation can be performed to generate netlist data D13 from RTL data D11. For example, a semiconductor design tool (e.g., a logic synthesis tool) can perform logic synthesis by referencing a cell library D12 from RTL data D11 written in VHSIC Hardware Description Language (VHDL) and Hardware Description Language (HDL) (such as Verilog), and can generate netlist data D13 including a bitstream or netlist. Netlist data D13 may correspond to the placement and routing inputs described below.

[0090] In operation S30, standard cells can be arranged. For example, a semiconductor design tool (e.g., a P&R tool) can arrange the standard cells used in the netlist data D13 by referencing the cell library D12. Additionally, bit cells can be arranged. For example, a semiconductor design tool can arrange bit cells next to standard cells.

[0091] In operation S50, the pins of standard cells can be routed. For example, a semiconductor design tool can generate interconnects that electrically connect the output pins of the arranged standard cells to the input pins, and generate layout data D15 defining the arrangement of the standard cells and the generated interconnects. Interconnects may include vias in a via layer and / or patterns in an interconnect layer. Interconnect layers may include a front interconnect layer disposed on the front surface of the substrate and a rear interconnect layer disposed on the rear surface of the substrate. Layout data D15 may have a format such as GDSII and may include geometric information of the cells and interconnects. The semiconductor design tool may reference design rule D14 when routing the pins of the cells. Layout data D15 may correspond to the arrangement and output of the routing. Operation S50 alone, or operations S30 and S50 together, can be collectively referred to as a method for designing integrated circuits.

[0092] In some implementations, such as Figures 1 to 10As shown, the integrated circuit may include a first decoupling capacitor cell and a second decoupling capacitor cell. In some examples, the first decoupling capacitor cell may be connected via a top metal connection to a junction region included in the I / O pad to form a first discharge path. In some examples, the second decoupling capacitor may be connected via an internal bottom metal line to a junction region formed on the internal substrate of the second decoupling capacitor cell to form a second discharge path. Thus, the plasma charge formed in the decoupling capacitor cell can be effectively discharged, thereby increasing the stability of the device.

[0093] In operation S70, mask fabrication operations can be performed. For example, optical proximity correction (OPC) for correcting distortion phenomena (such as refraction caused by the properties of light in photolithography) can be applied to the layout data D15. Patterns on the mask can be defined to form patterns arranged in multiple layers based on the data with OPC applied, and at least one mask (or photomask) can be fabricated to form the pattern for each of the layers. In some embodiments, the layout of the integrated circuit IC can be modified to a limited extent in operation S70, and the limited modification of the integrated circuit IC in operation S70 can be referred to as design polishing as a post-processing step to optimize the structure of the integrated circuit IC.

[0094] In operation S90, operations for manufacturing an integrated circuit (IC) can be performed. For example, an IC can be manufactured by patterning multiple layers using at least one mask manufactured in operation S70. The front-end process (FEOL) may include operations such as planarizing the wafer, cleaning the wafer, forming trenches, forming wells, forming gate lines, and forming source and drain electrodes. With the aid of FEOL, individual components (such as transistors, capacitors, resistors, etc.) can be formed on the substrate. Furthermore, the back-end process (BEOL) may include operations such as siliconizing gate, source, and drain regions, adding dielectrics, planarizing, forming vias, adding metal layers, forming vias, forming passivation layers, etc. Through BEOL, individual components (such as transistors, capacitors, resistors, etc.) can be interconnected. In some embodiments, a middle-end process (MOL) may be performed between FEOL and BEOL, and contacts may be formed on individual components. The IC can then be packaged into a semiconductor package and used as a component in various applications.

[0095] Figure 13 This is a block diagram illustrating a system-on-a-chip (SoC) 210 according to some embodiments.

[0096] Reference Figure 13SoC 210 may represent an integrated circuit that integrates components of a computing system or other electronic system. For example, as an example of SoC 210, an application processor (AP) may include processors and components for other functions. SoC 210 may include a core 211, a digital signal processor (DSP) 212, a graphics processing unit (GPU) 213, built-in memory (or embedded memory) 214, a communication interface (I / F) 215, and a memory interface 216. Components of SoC 210 may communicate with each other via bus 217.

[0097] Core 211 can process commands and control the operation of components included in SoC 210. For example, core 211 can drive an operating system and execute applications on the operating system by processing a series of commands. DSP 212 can generate useful data by processing digital signals (e.g., digital signals provided from communication interface 215). GPU 213 can generate data for an image to be output on a display device based on image data provided from built-in memory 214 or memory interface 216, or can encode image data. In some embodiments, the integrated circuits described above with reference to the accompanying drawings may be included in core 211, DSP 212, GPU 213, and / or built-in memory 214.

[0098] Figure 14 This is a block diagram illustrating a computing system 220 including a stored program memory according to some embodiments.

[0099] Reference Figure 14 The method for designing integrated circuits according to some embodiments (e.g., at least a portion of the operations in the flowchart above) can be executed in a computing system (or computer) 220. The computing system 220 may include a processor 221, I / O devices 222, a network interface 223, random access memory (RAM) 224, read-only memory (ROM) 225, and storage devices 226. The processor 221, I / O devices 222, network interface 223, RAM 224, ROM 225, and storage devices 226 may be connected to a bus 227 and communicate with each other via the bus 227.

[0100] Processor 221 can access memory (i.e., RAM 224 or ROM 225) via bus 227 and execute instructions stored in RAM 224 or ROM 225. RAM 224 may store program 224_1 or at least a portion of program 224_1 for methods of designing integrated circuits according to some embodiments, and program 224_1 may cause processor 221 to execute methods including those for designing integrated circuits (e.g., Figure 12At least a portion of the operations in the method. That is, program 224_1 may include a plurality of instructions executable by processor 221, and the instructions included in program 224_1 may cause processor 221 to perform at least a portion of the operations included in the above flowchart.

[0101] According to some embodiments, storage device 226 may store program 224_1. Furthermore, storage device 226 may store database (DB) 226_1, and database 226_1 may include information necessary for designing integrated circuits (such as information about design blocks, etc.). Figure 12 (The cell library D12 and / or design rule D14). Storage device 226 may store data to be processed by processor 221 or data after processing by processor 221. For example, storage device 226 may store Figure 12 The RTL data D11, netlist data D13, and / or layout data D15.

[0102] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit, comprising: The first decoupling capacitor unit has a first discharge path that guides the discharge of the first charged particle. as well as The second decoupling capacitor unit has a second discharge path that guides the discharge of the second charged particle. The first discharge path is located in the outer region of the first decoupling capacitor cell, and The second discharge path is located within the internal region of the second decoupling capacitor unit.

2. The integrated circuit as claimed in claim 1, wherein, The first decoupling capacitor unit includes multiple metal wires. The multiple metal lines include multiple sets of metal lines stacked in continuous layers. Each of the plurality of metal wires has an elongation direction. The elongation direction alternates between a first direction and a second direction from one set of metal wires to the next set of metal wires. The plurality of metal lines include a top metal line and a plurality of lower metal lines below the top metal line. Wherein, the length of the first lower metal line extending in the first direction among the plurality of lower metal lines is different from the length of the first decoupling capacitor unit in the first direction, and The length of the second lower metal line extending in the second direction is different from the length of the first decoupling capacitor unit in the second direction.

3. The integrated circuit as described in claim 2, wherein, The length of the first lower metal wire in the first direction is less than the length of the first decoupling capacitor unit in the first direction, and The length of the second lower metal wire in the second direction is less than the length of the first decoupling capacitor unit in the second direction.

4. The integrated circuit of claim 2, further comprising: The input / output pad is configured to send signals to at least one of the first decoupling capacitor unit and the second decoupling capacitor unit, and to receive signals from at least one of the first decoupling capacitor unit and the second decoupling capacitor unit. The top metal wire extends toward the upper region of the input / output pads.

5. The integrated circuit as claimed in claim 4, wherein, The input / output pads are physically connected to the top metal wires.

6. The integrated circuit as claimed in claim 5, wherein, The input / output pads include: a first junction region formed in the substrate.

7. The integrated circuit as claimed in claim 6, wherein, The input / output pads also include vias that connect the first junction area to the top metal wire in a third-order orientation.

8. The integrated circuit as claimed in claim 2, wherein, The first decoupling capacitor unit includes multiple metal-oxide-semiconductor capacitor devices, and The plurality of metal-oxide-semiconductor capacitor devices include: a plurality of gates physically connected to the plurality of lower metal lines.

9. The integrated circuit as claimed in claim 1, wherein, The second decoupling capacitor unit includes: Base; Multiple gates; and The second knot region is formed on the substrate.

10. The integrated circuit as claimed in claim 9, wherein, The second knot region includes two or more second knot regions, and Wherein, at least one of the two or more second junction regions is physically connected to a metal line above the plurality of gates.

11. The integrated circuit of claim 10, wherein, The metal line is the bottom metal line that is closest to the plurality of gates in a third-direction orientation.

12. The integrated circuit as claimed in claim 1, wherein, The size of the first decoupling capacitor unit is equal to the size of the second decoupling capacitor unit.

13. An integrated circuit, comprising: Multiple cell arrays, The plurality of cell arrays include: The first decoupling capacitor cell array includes multiple first decoupling capacitor cells, and The second decoupling capacitor cell array includes multiple second decoupling capacitor cells. Each of the plurality of first decoupling capacitor units includes multiple top metal lines forming a first path, the first path guiding the discharge of charged particles, and Each of the plurality of second decoupling capacitor units includes a second junction region forming a second path that guides the discharge of charged particles.

14. The integrated circuit of claim 13, wherein, The integrated circuit also includes: input / output pads, physically connected to the plurality of top metal lines, and The input / output pad includes: a first junction region that forms at least a portion of the first path.

15. The integrated circuit as claimed in claim 14, wherein, Each of the plurality of first decoupling capacitor cells does not include a junction region.

16. The integrated circuit of claim 13, wherein, Each of the plurality of second decoupling capacitor units includes a plurality of second junction regions, and Wherein, at least one of the plurality of second junction regions is connected in a third-party upward direction to a metal wire included in each of the plurality of second decoupling capacitor units.

17. The integrated circuit of claim 16, wherein, The metal wire is the bottom metal wire closest to the substrate in each of the plurality of second decoupling capacitor cells.

18. An integrated circuit, comprising: Multiple cell arrays; as well as Input / output pads are configured to send signals to and receive signals from the plurality of cell arrays. The input / output pad includes a first discharge path that guides the discharge of charged particles, including plasma charged particles formed by the plurality of unit arrays.

19. The integrated circuit of claim 18, wherein, The first discharge path is connected by a top metal line among multiple metal lines included in the plurality of cell arrays.

20. The integrated circuit of claim 18, wherein, The plurality of unit arrays form a second discharge path, which guides the discharge of charged particles, including plasma charged particles formed by the plurality of unit arrays.

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