A trench gate IGBT device and a manufacturing method thereof

Abstract

This invention discloses a trench gate IGBT device and its manufacturing method. The device uses a thin second portion of a first oxide layer as an insulator between the first gate and the P-type body region, and a thicker first portion of the first oxide layer as the dielectric for the sidewalls and bottom of the first gate. This reduces the electric field concentration effect at the bottom of the trench and improves the device's avalanche resistance. At the same time, the thicker first portion of the first oxide layer reduces the capacitance between the gate and collector, optimizing the device's turn-on speed and reducing losses during the turn-on process. In addition, the bottoms of the first and second oxide layers are respectively connected to the corresponding P-floating layer regions, solving the problem of direct contact between the bottom gate oxide layer and the drift region in traditional trench gate IGBTs, which increases the Miller capacitance of the IGBT device, affects the switching losses during operation, and easily induces false turn-on.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor manufacturing, and in particular to a trench gate IGBT device and its manufacturing method. Background Technology

[0002] In power electronic systems, the Insulated Gate Bipolar Transistor (IGBT), as a core power device combining the high input impedance of MOSFETs and the low conduction loss of BJTs, is widely used in medium- and high-voltage power electronic systems such as new energy power generation, electric vehicles, rail transportation, and industrial frequency conversion. As power electronic devices develop towards higher voltage, higher current, and higher efficiency, the reliability and performance limits of IGBTs face increasingly stringent challenges. Among these, weak avalanche protection has become one of the key bottlenecks restricting their safe and stable operation.

[0003] The avalanche effect in IGBTs mainly occurs under dynamic switching conditions: in scenarios such as rapid turn-off of inductive loads, sudden load changes, or LC resonance, the collector-emitter voltage can easily transiently exceed the rated blocking voltage, triggering collisional ionization of charge carriers under the strong electric field in the drift region, thus forming an avalanche multiplication effect and generating a large number of electron-hole pairs. This process is accompanied by a sharp increase in collector current and rapid accumulation of power consumption. If the energy exceeds the device's avalanche tolerance energy threshold, it will cause the junction temperature to spike, leading to local thermal runaway, and may even induce internal parasitic thyristor latch-up, causing permanent burn-out of the device. Summary of the Invention

[0004] Purpose of the invention: The present invention aims to provide a trench gate IGBT device with high avalanche resistance, and another purpose of the present invention is to provide a method for manufacturing a trench gate IGBT device with high avalanche resistance.

[0005] Technical solution: The trench gate IGBT device of the present invention includes a plurality of cells, wherein the cells include, from bottom to top, a collector structure, an N-drift region, a P-type body region, a dielectric layer and a metal layer.

[0006] The P-type body region is composed of a first P-type body region and a second P-type body region. The upper surface of the first P-type body region is provided with an N-type emission region, and the upper surface of the N-type emission region is flush with the upper surface of the second P-type body region.

[0007] The N-type launch region, the first P-type body region, and the N-drift region are provided with a first groove, and the second P-type body region and the N-drift region are provided with a second groove. The bottom of the first groove and the second groove are located in the N-drift region.

[0008] A gate structure includes a first gate and a second gate. The first gate includes a first filling layer and a first oxide layer located in a first trench. The first filling layer is disposed on the inner wall of the first trench, and the first oxide layer is disposed between the first filling layer and the inner wall of the first trench. The first oxide layer is composed of a first part and a second part. The first part is located in the first trench near the bottom wall of the first trench, and the second part is located in the first trench away from the bottom wall of the first trench. The thickness of the first part in a first direction is a first thickness, and the thickness of the second part in the first direction is a second thickness. The first thickness is greater than the second thickness. The first direction is a direction perpendicular to the sidewall of the first trench. A dielectric layer is provided between the top of the first oxide layer and the metal layer.

[0009] The second gate includes a second oxide layer and a second filling layer located in a second trench. The second filling layer is disposed on the inner wall of the second trench, and the second oxide layer is disposed between the second filling layer and the inner wall of the second trench. The thickness of the second oxide layer in a first direction is equal to the first thickness, and a dielectric layer is provided between the top of the second filling layer and the metal layer.

[0010] The bottom of the first oxide layer and the second oxide layer are respectively connected to the P-floating layer region.

[0011] Furthermore, the first part is located in the drift region; the second part is located in the P-type body region and is in contact with the N-type emission region on the side away from the second trench.

[0012] Furthermore, the top of the second oxide layer is connected to the metal layer.

[0013] Furthermore, the first part is provided with a groove for inserting the first filling layer, the first part is connected to the second part, and the opening of the groove is set in a direction away from the bottom wall of the first groove.

[0014] Furthermore, the cell can be any one of a square cell, a strip cell, or a hexagonal cell.

[0015] The method for manufacturing the trench gate IGBT device of the present invention includes:

[0016] An N-drift region is formed on the collector structure;

[0017] A P-type body region is formed on the upper surface of the N-drift region; the P-type body region consists of a first P-type body region and a second P-type body region;

[0018] An N-type emission region is formed on the upper surface of the first P-type body region, and the upper surface of the N-type emission region is flush with the upper surface of the second P-type body region.

[0019] A first groove is formed downward from the top of the N-type launch region, and a second groove is formed downward from the top of the second P-type body region. The bottoms of the first and second grooves are located in the N-drift region.

[0020] A corresponding P-floating layer region is formed below the bottom of the first trench and the second trench respectively by ion implantation process;

[0021] A first oxide layer is formed in the first trench. The first oxide layer consists of a first part and a second part. The first part is located in the first trench near the bottom wall of the first trench, and the second part is located in the first trench away from the bottom wall of the first trench. The thickness of the first part in a first direction is a first thickness, and the thickness of the second part in the first direction is a second thickness. The first thickness is greater than the second thickness. The first direction is perpendicular to the sidewall of the first trench. The bottom of the first oxide layer is connected to the P-floating layer region.

[0022] A second oxide layer is formed in the second trench, the thickness of the second oxide layer in the first direction is equal to the first thickness, and the bottom of the second oxide layer is connected to the P-floating layer region;

[0023] The cavities of the first oxide layer and the second oxide layer, which are far from the second trench, are respectively filled with fillers to form a first filling layer and a second filling layer;

[0024] A dielectric layer and a metal layer are sequentially formed on the upper surface of the N-type emitter region, the top of the first oxide layer, the top of the second oxide layer, and the upper surface of the second P-type body region using a front-side process.

[0025] Furthermore, the top of the second filler layer is connected to the metal layer.

[0026] Beneficial Effects: Compared with the prior art, the significant advantages of this invention are: 1. This invention uses a thin second part of the first oxide layer as the insulator between the first gate and the P-type body region, and a thicker first part of the first oxide layer as the dielectric for the sidewall and bottom of the first gate. This reduces the electric field concentration effect at the bottom of the trench, improves the device's avalanche resistance, and the thicker first part of the first oxide layer reduces the capacitance between the gate and collector, thus optimizing the device's turn-on speed and reducing losses during the turn-on process; 2. The bottom of the first oxide layer and the second oxide layer of this invention are respectively connected to the corresponding P-floating layer regions, solving the problem of direct contact between the bottom gate oxide layer and the drift region in traditional trench gate IGBTs, which increases the Miller capacitance of the IGBT device, affects the switching losses during operation, and easily induces false turn-on; 3. A dielectric layer is provided between the top of the second fill layer and the metal layer to form a floating structure, which can adjust the size of the gate-emitter capacitance and optimize the switching characteristics of the device; 4. This invention can optimize the overall avalanche resistance of the device, improve the turn-on speed, and reduce the turn-on loss. Attached Figure Description

[0027] Figure 1 A schematic diagram of the cross-sectional structure of a trench gate IGBT device provided in an embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram of the cross-sectional structure of the trench gate IGBT device provided in an embodiment of the present invention;

[0029] Figure 3 This is a flowchart of the method of the present invention;

[0030] Figure 4 This is a schematic diagram of the cross-sectional structure of the trench gate IGBT device provided in an embodiment of the present invention;

[0031] Figure 5 This is a schematic diagram of the cross-sectional structure of the trench gate IGBT device provided in an embodiment of the present invention;

[0032] Figure 6 This is a schematic diagram of the cross-sectional structure of the trench gate IGBT device provided in an embodiment of the present invention;

[0033] Figure 7 This is a schematic diagram of the cross-sectional structure of a trench gate IGBT device provided in an embodiment of the present invention;

[0034] Figure 8 This is a schematic diagram of the cross-sectional structure of a trench gate IGBT device provided in an embodiment of the present invention;

[0035] Figure 9 This is a schematic diagram of the cross-sectional structure of a trench gate IGBT device provided in an embodiment of the present invention. Detailed Implementation

[0036] The invention will now be further described with reference to the accompanying drawings.

[0037] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0038] In the description of the embodiments of this application, it should be noted that the terms "upper," "lower," "vertical," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0039] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0040] Example 1

[0041] like Figure 1 As shown, the trench gate IGBT device of the present invention includes a plurality of cells, which, from bottom to top, include a collector structure, an N-drift region 4, a P-type body region 7, a dielectric layer 9, and a metal layer 10. The P-type body region 7 is composed of a first P-type body region and a second P-type body region. An N-type emitter region 8 is provided on the upper surface of the first P-type body region, and the upper surface of the N-type emitter region 8 is flush with the upper surface of the second P-type body region.

[0042] The N-type launch region 8, the first P-type body region, and the N-drift region 4 are provided with a first groove, and the second P-type body region and the N-drift region 4 are provided with a second groove. The bottom of the first groove and the second groove are located in the N-drift region 4.

[0043] The gate structure adopts a trench gate structure, including a first gate and a second gate. The first gate includes a first filling layer 61 and a first oxide layer 62 located in a first trench. The first filling layer is disposed on the inner wall of the first trench, and the first oxide layer is disposed between the first filling layer and the inner wall of the first trench. The first oxide layer 62 is composed of a first part and a second part. The first part is located in the first trench near the bottom wall of the first trench, and the second part is located in the first trench away from the bottom wall of the first trench. The thickness of the first part in a first direction is a first thickness, and the thickness of the second part in the first direction is a second thickness. The first thickness is greater than the second thickness. The first direction is a direction perpendicular to the sidewall of the first trench. A dielectric layer 9 is provided between the top of the first oxide layer 62 and the metal 10. The second gate includes a second oxide layer 112 and a second filler layer 111 located within a second trench. The second filler layer 111 is disposed on the inner wall of the second trench, and the second oxide layer 112 is disposed between the second filler layer and the inner wall of the second trench. The thickness of the second oxide layer 112 in a first direction is equal to the first thickness. A dielectric layer 9 is provided between the top of the second filler layer 111 and the metal layer 10, forming a floating structure that can adjust the size of the gate-emitter capacitance of the device and optimize the switching characteristics of the device. The bottoms of the first oxide layer 62 and the second oxide layer 112 are respectively connected to a P-floating layer region 5.

[0044] Furthermore, the first part is located in the drift region; the second part is located in the P-type body region and is in contact with the N-type emission region on the side away from the second trench.

[0045] Furthermore, the top of the second oxide layer is connected to the metal layer.

[0046] Furthermore, the first part is provided with a groove for inserting the first filling layer, the first part is connected to the second part, and the opening of the groove is set in a direction away from the bottom wall of the first groove.

[0047] Furthermore, the cell can be one of the following: square cell, strip cell, or hexagonal cell.

[0048] Example 2

[0049] like Figure 2 As shown, the difference between this embodiment and Embodiment 1 is that the second filler layer, which was originally not in contact with the metal layer, is now connected to the metal layer. This device only improves the resistance to high avalanche but cannot adjust the size of the device's gate-emitter capacitance.

[0050] Example 3

[0051] like Figure 3 As shown, the manufacturing method of the trench gate IGBT device of the present invention includes:

[0052] (1) such as Figure 4As shown, a first trench and a second trench are formed vertically downwards from the top of the silicon substrate. P-floating layer regions are formed below the bottom of the first and second trenches respectively using an ion implantation process; in one embodiment, this can be achieved by implanting boron. A P-floating layer region is formed simultaneously at the bottom of the first trench and at the bottom of the second trench.

[0053] (2) For example Figure 5 As shown, an oxide layer of a first thickness is formed inside the first trench by depositing oxides. Simultaneously, a second oxide layer of the same first thickness is formed on the sidewall of the second trench.

[0054] (3) such as Figure 6 As shown, in one embodiment of this application, an etching process is used to etch the portion of the oxide layer of the first thickness away from the bottom wall of the first trench to a second thickness. That is, the first oxide layer consists of a first part and a second part. The first part is located within the first trench near the bottom wall of the first trench, and the second part is located within the first trench away from the bottom wall of the first trench. The thickness of the first part in a first direction is the first thickness, and the thickness of the second part in the first direction is the second thickness. The first thickness is greater than the second thickness, and the first direction is perpendicular to the sidewall of the first trench.

[0055] (4) such as Figure 7 As shown, in one embodiment of this application, a first filling layer is formed in the cavity of the first oxide layer by a deposition process. The step of filling the cavity of the first oxide layer to form the first filling layer simultaneously forms a second filling layer in the cavity of the second oxide layer. The materials filling the cavities of the first oxide layer and the second oxide layer are the same.

[0056] (5) such as Figure 8 As shown, in one embodiment of this application, a P-type body region, an N-type emitter region, and an N-drift region are formed on the upper surface of a silicon substrate by ion implantation. The P-type body region is located on the upper surface of the N-drift region and is composed of a first P-type body region and a second P-type body region. An N-type emitter region is provided on the upper surface of the first P-type body region, and the upper surface of the N-type emitter region is flush with the upper surface of the second P-type body region.

[0057] Step (5) also includes forming a dielectric layer 9, which may be a silicon oxide layer, such as a doped or undoped silicon oxide material layer formed using a thermal chemical vapor deposition (CVD) process or a high-density plasma (HDP) process. Specifically, it may be undoped silicon glass (USG), silicon phosphosilicate glass (PSG), or borosilicate phosphosilicate glass (BPSG). Alternatively, the dielectric layer may also be a boron-doped or phosphorus-doped spin-on-glass (SOG) or a phosphorus-doped tetraethoxysilane (PTEOS).

[0058] Furthermore, a portion of the dielectric layer is etched and etching continues downward to the P-type body region, forming a contact with the N-type emitter region. After contact is formed, conductive material is filled into the contact hole to form a metal layer 10. In one embodiment, the metal layer can be formed by filling with aluminum. During the etching of the portion of the dielectric layer, a portion of the dielectric layer at the top of the second trench is also included to ensure the connection between the top of the second trench and the metal layer.

[0059] (6) For example Figure 9 As shown, in one embodiment of this application, after the IGBT is reversed, an N-type buffer layer and a P-type collector layer are formed by ion implantation. In this embodiment, phosphorus ions can be used for the N-type buffer layer, and boron ions can be used for the P-type collector layer. Further, collector metal is formed by deposition.

[0060] In one embodiment of this application, the first oxide layer is first formed inside the first trench by depositing oxide to form an oxide layer with a thickness less than the second thickness, and then a first portion of the first thickness is formed by thermally growing an oxide layer.

[0061] In one embodiment of this application, a second portion of the second thickness is formed by thermally growing an oxide layer.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A trench gate IGBT device, characterized in that, It includes several cells, which from bottom to top include a collector structure, an N-drift region (4), a P-type body region (7), a dielectric layer (9), and a metal layer (10). The P-type body region (7) is composed of a first P-type body region and a second P-type body region. The upper surface of the first P-type body region is provided with an N-type emission region (8), and the upper surface of the N-type emission region (8) is flush with the upper surface of the second P-type body region. The N-type launch region (8), the first P-type body region and the N-drift region (4) are provided with a first groove, and the second P-type body region and the N-drift region (4) are provided with a second groove. The bottom of the first groove and the second groove are located in the N-drift region (4). The gate structure includes a first gate and a second gate. The first gate includes a first filling layer (61) and a first oxide layer (62) located in a first trench. The first filling layer (61) is disposed on the inner wall of the first trench, and the first oxide layer (62) is disposed between the first filling layer (61) and the inner wall of the first trench. The first oxide layer (62) is composed of a first part and a second part. The first part is located in the first trench near the bottom wall of the first trench, and the second part is located in the first trench away from the bottom wall of the first trench. The thickness of the first part in the first direction is a first thickness, and the thickness of the second part in the first direction is a second thickness. The first thickness is greater than the second thickness. The first direction is a direction perpendicular to the side wall of the first trench. A dielectric layer (9) is provided between the top of the first oxide layer (62) and the metal layer (10). The second gate includes a second oxide layer (112) and a second filling layer (111) located in the second trench. The second filling layer (111) is disposed on the inner wall of the second trench, and the second oxide layer (112) is disposed between the second filling layer (111) and the inner wall of the second trench. The thickness of the second oxide layer (112) in the first direction is equal to the first thickness. A dielectric layer (9) is provided between the top of the second filling layer (111) and the metal layer (10). The bottom of the first oxide layer (62) and the second oxide layer (112) are respectively connected to the P-floating layer region (5).

2. The trench gate IGBT device according to claim 1, characterized in that, The first part is located in the drift region (4); the second part is located in the P-type body region (7) and is in contact with the N-type emission region (8) on the side away from the second trench.

3. The trench gate IGBT device according to claim 1, characterized in that, The top of the second oxide layer (112) is connected to the metal layer (10).

4. The trench gate IGBT device according to claim 1, characterized in that, The first part is provided with a groove for inserting the first filling layer (61). The first part is connected to the second part, and the opening of the groove is set in a direction away from the bottom wall of the first groove.

5. The trench gate IGBT device according to claim 1, characterized in that, The cell can be any one of square cell, strip cell, or hexagonal cell.

6. A method for manufacturing a trench gate IGBT device according to any one of claims 1-5, characterized in that, include: An N-drift region is formed on the collector structure; A P-type body region is formed on the upper surface of the N-drift region; The P-type body region consists of a first P-type body region and a second P-type body region; An N-type emission region is formed on the upper surface of the first P-type body region, and the upper surface of the N-type emission region is flush with the upper surface of the second P-type body region. A first groove is formed downward from the top of the N-type launch region, and a second groove is formed downward from the top of the second P-type body region. The bottoms of the first and second grooves are located in the N-drift region. A corresponding P-floating layer region is formed below the bottom of the first trench and the second trench respectively by ion implantation process; A first oxide layer is formed in the first trench. The first oxide layer consists of a first part and a second part. The first part is located in the first trench near the bottom wall of the first trench, and the second part is located in the first trench away from the bottom wall of the first trench. The thickness of the first part in a first direction is a first thickness, and the thickness of the second part in the first direction is a second thickness. The first thickness is greater than the second thickness. The first direction is perpendicular to the sidewall of the first trench. The bottom of the first oxide layer is connected to the P-floating layer region. A second oxide layer is formed in the second trench, the thickness of the second oxide layer in the first direction is equal to the first thickness, and the bottom of the second oxide layer is connected to the P-floating layer region; The cavities of the first oxide layer and the second oxide layer, which are far from the second trench, are respectively filled with fillers to form a first filling layer and a second filling layer; A dielectric layer and a metal layer are sequentially formed on the upper surface of the N-type emitter region, the top of the first oxide layer, the top of the second oxide layer, and the upper surface of the second P-type body region using a front-side process.

7. The method for manufacturing the trench gate IGBT device according to claim 6, characterized in that, The top of the second filler layer is connected to the metal layer.

Images