Photoelectric conversion element, photoelectric conversion device, and apparatus

Abstract

This invention relates to a photoelectric conversion element, a photoelectric conversion device, and an apparatus. The photoelectric conversion element, disposed in a semiconductor layer having a first surface and a second surface opposite to the first surface, includes: a first semiconductor region of a first conductivity type, arranged to extend across a first depth relative to the first surface; a second semiconductor region of a second conductivity type, arranged to surround the first semiconductor region in a planar view and having a peak of impurity concentration at a second depth between the first surface and the first depth; and a third semiconductor region of a second conductivity type, arranged closer to the second surface than the first semiconductor region to the second surface, and forming an avalanche photodiode with the first semiconductor region. The boundary surface of the second semiconductor region on the second surface side is located closer to the first surface than the first depth to the first surface.

Description

Technical Field

[0001] This disclosure relates to photoelectric conversion elements, photoelectric conversion devices, and equipment. Background Technology

[0002] Single-photon avalanche diodes (SPADs) are known as detectors capable of detecting weak light at the single-photon level. SPADs utilize the avalanche multiplication phenomenon, generated by a strong electric field induced in a pn junction of a semiconductor, to multiply the signal charge excited by photons by several to millions of times. By converting the current generated by the avalanche multiplication phenomenon into pulse signals and counting the number of pulse signals, the number of incident photons can be directly measured. Japanese Patent Application Laid-Open No. 2020-057651 describes a photoelectric detection device and system using SPADs.

[0003] Japanese Patent Application Publication No. 2020-057651 discloses a configuration in which, from the viewpoint of reducing noise while suppressing the increase in operating voltage, a semiconductor region with a low impurity concentration is arranged between the cathode and anode to increase the electric field strength between the cathode and anode. However, in the configuration described in Japanese Patent Application Publication No. 2020-057651, although the increase in operating voltage can be suppressed by increasing the electric field strength between the cathode and anode, noise may be generated due to carriers generated at the carrier generation energy level in the photoelectric conversion element. Summary of the Invention

[0004] This disclosure provides a photoelectric conversion element and a photoelectric conversion device capable of reducing noise caused by carriers generated from carrier generation energy levels in a photoelectric conversion element.

[0005] According to one disclosure of this specification, a photoelectric conversion element is provided, disposed in a semiconductor layer having a first surface and a second surface opposite to the first surface. The photoelectric conversion element includes: a first semiconductor region of a first conductivity type, arranged to extend over a first depth relative to the first surface; a second semiconductor region of a second conductivity type, arranged to surround the first semiconductor region in a planar view and having a peak of impurity concentration at a second depth between the first surface and the first depth; and a third semiconductor region of the second conductivity type, arranged closer to the second surface than the first semiconductor region and forming an avalanche photodiode with the first semiconductor region, wherein the boundary surface of the second semiconductor region on the second surface side is located closer to the first surface than the first depth.

[0006] The features of this disclosure will become apparent from the following description of embodiments with reference to the accompanying drawings. The following description of the embodiments is given by way of example. Attached Figure Description

[0007] Figure 1 and Figure 2 This is a block diagram illustrating a schematic configuration of a photoelectric conversion device according to the first embodiment.

[0008] Figure 3 This is a block diagram illustrating an example of the pixel configuration of the photoelectric conversion device according to the first embodiment.

[0009] Figure 4 (A) Figure 4 (B) Figure 4 (C) Figure 5 (A) Figure 5 (B) Figure 5 (C) and Figure 5 (D) is a diagram illustrating the basic operation of the photoelectric conversion unit in the photoelectric conversion device according to the first embodiment.

[0010] Figure 6 This is a perspective view illustrating an example configuration of the photoelectric conversion device according to the first embodiment.

[0011] Figure 7 This is a schematic cross-sectional view illustrating the structure of the photoelectric conversion device according to the first embodiment.

[0012] Figure 8 This is a plan view illustrating the structure of the photoelectric conversion element of the photoelectric conversion device according to the first embodiment.

[0013] Figure 9 This is a schematic cross-sectional view illustrating the structure of the photoelectric conversion element of the photoelectric conversion device according to the first embodiment.

[0014] Figure 10 This is a graph illustrating the depth distribution of impurities in the photoelectric conversion element constituting the photoelectric conversion device according to the first embodiment.

[0015] Figure 11 This is a schematic cross-sectional view illustrating the structure of the photoelectric conversion element of a photoelectric conversion device according to a reference example.

[0016] Figure 12 This is a schematic cross-sectional view illustrating the structure of the photoelectric conversion element of the photoelectric conversion device according to the second embodiment.

[0017] Figure 13 This is a graph illustrating the depth distribution of impurities in the photoelectric conversion element constituting the photoelectric conversion device according to the second embodiment.

[0018] Figure 14 This is a schematic cross-sectional view illustrating the structure of the photoelectric conversion element in a modified photoelectric conversion device according to the second embodiment.

[0019] Figure 15 This is a block diagram illustrating a schematic configuration of the photoelectric detection system according to the third embodiment.

[0020] Figure 16 This is a block diagram illustrating a schematic configuration of a distance image sensor according to the fourth embodiment.

[0021] Figure 17 This is a schematic diagram illustrating an example configuration of an endoscopic surgical system according to the fifth embodiment.

[0022] Figure 18A , Figure 18B and Figure 18C This is a schematic diagram illustrating an example configuration of a movable body according to the sixth embodiment.

[0023] Figure 19 This is a block diagram illustrating a schematic configuration of the photoelectric detection system according to the sixth embodiment.

[0024] Figure 20 This is a flowchart illustrating the operation of the photoelectric detection system according to the sixth embodiment.

[0025] Figure 21A and Figure 21B This is a schematic diagram illustrating an exemplary configuration of the photoelectric detection system according to the seventh embodiment.

[0026] Figure 22 This is a block diagram illustrating a schematic configuration of the device according to the eighth embodiment. Detailed Implementation

[0027] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the technology of the claims. Although multiple features are described in the embodiments, not all of these multiple features are necessary for the present disclosure, and the multiple features can be combined arbitrarily. In the following description, terms used to indicate a particular direction or position (e.g., "up," "down," "right," "left," and other terms including these terms) are used as needed. The use of these terms is to facilitate understanding of the embodiments with reference to the accompanying drawings, and the technical scope of the present disclosure is not limited by the meaning of these terms. In addition, the size and positional relationships of the components illustrated in the drawings may be exaggerated for clarity of description.

[0028] In the various embodiments described below, photoelectric conversion devices for imaging purposes will be primarily described as examples of semiconductor devices. However, the embodiments are not limited to photoelectric conversion devices for imaging purposes and can be applied to other semiconductor devices. For example, other examples of semiconductor devices include ranging devices (devices for distance measurement, etc., using focus detection or time-of-flight (TOF)) and photometers (devices for measuring the amount of incident light), etc. First Embodiment

[0029] Reference Figure 1 A schematic configuration of the photoelectric conversion device according to the first embodiment is described. Figure 1 This is a block diagram illustrating a schematic configuration of the photoelectric conversion device according to this embodiment.

[0030] like Figure 1 As illustrated, the photoelectric conversion device 100 according to this embodiment includes a pixel region 10, a vertical scanning circuit unit 40, a readout circuit unit 50, a horizontal scanning circuit unit 60, an output circuit unit 70, and a control pulse generation unit 80.

[0031] Pixel region 10 is provided with a plurality of pixels 12 arranged in an array to form a plurality of rows and a plurality of columns. As described later, each pixel 12 may include a photoelectric conversion unit and a signal processing unit, the photoelectric conversion unit including a photoelectric conversion element and the signal processing unit processing the signal output from the photoelectric conversion unit. The number of pixels 12 constituting pixel region 10 is not particularly limited. For example, as in a typical digital camera, pixel region 10 may include a plurality of pixels 12 arranged in an array of thousands of rows × thousands of columns. Alternatively, pixel region 10 may include a plurality of pixels 12 arranged in a row or a column. Alternatively, pixel region 10 may include a single pixel 12.

[0032] In each row of the pixel array in pixel region 10, control lines 14 are arranged in a first direction ( Figure 1 The control lines 14 extend in the horizontal direction. Each control line 14 is connected to a pixel 12 arranged in the corresponding row in the first direction, and forms a signal line shared by these pixels 12. The first direction in which the control lines 14 extend can be referred to as the row direction or the horizontal direction. Each control line in the control lines 14 may include multiple signal lines for supplying multiple types of control signals to the pixels 12.

[0033] In each column of the pixel array of pixel region 10, the output line 16 is arranged in a second direction intersecting the first direction. Figure 1 The output lines 16 extend in the vertical direction. Each output line 16 is connected to a pixel 12 arranged in a corresponding column in the second direction, and forms a signal line shared by these pixels 12. The second direction in which the output lines 16 extend can be referred to as the column direction or the vertical direction. Each output line 16 may include multiple signal lines. For example, each output line 16 may include multiple signal lines for transmitting multi-bit digital signals output from the pixel 12 bit by bit.

[0034] The control lines 14 for each row are connected to the vertical scanning circuit unit 40. The vertical scanning circuit unit 40 is a control circuit that generates control signals for driving pixels 12 in response to control signals from the control pulse generation unit 80, and supplies the generated control signals to pixels 12 via the control lines 14. Logic circuits such as shift registers or address decoders can be used as the vertical scanning circuit unit 40. The vertical scanning circuit unit 40 sequentially scans the pixels 12 in the pixel region 10 row by row to output the pixel signals of the pixels 12 to the readout circuit unit 50 via the output lines 16.

[0035] The output lines 16 of each column are connected to the readout circuit unit 50. The readout circuit unit 50 includes a plurality of holding units (not shown) arranged corresponding to each column of the pixel array of the pixel region 10, and has the function of holding the pixel signals of the pixels 12 of each column output from the pixel region 10 in rows via the output lines 16 in the holding units of the respective columns.

[0036] The horizontal scanning circuit unit 60 is a control circuit that functions as follows: in response to a control signal from the control pulse generation unit 80, it generates control signals for reading pixel signals from the holding cells of each column of the readout circuit unit 50, and supplies the generated control signals to the readout circuit unit 50. Logic circuits such as shift registers or address decoders can be used as the horizontal scanning circuit unit 60. The horizontal scanning circuit unit 60 sequentially scans the holding cells of each column of the readout circuit unit 50 to sequentially output the pixel signals held in the holding cells to the output circuit unit 70.

[0037] Output circuit unit 70 is a circuit unit for outputting the pixel signal from readout circuit unit 50 to the outside of photoelectric conversion device 100, and includes external interface circuitry. There are no particular limitations on the external interface circuitry included in output circuit unit 70. For example, a serializer / deserializer (SerDes) transmission circuit can be used as the external interface circuitry. Examples of SerDes transmission circuits include Low Voltage Differential Signaling (LVDS) circuitry and Scalable Low Voltage Signaling (SLVS) circuitry. Note that output circuit unit 70 may also include a signal processing circuit disposed in front of the external interface circuitry, which performs predetermined digital signal processing on the pixel signal output from readout circuit unit 50.

[0038] The control pulse generation unit 80 is a control circuit used to generate control signals and supply the generated control signals to each functional block. These control signals are used to control the operation and timing of the vertical scanning circuit unit 40, the readout circuit unit 50, and the horizontal scanning circuit unit 60. At least a portion of the control signals used to control the operation and timing of the vertical scanning circuit unit 40, the readout circuit unit 50, and the horizontal scanning circuit unit 60 can be supplied from outside the photoelectric conversion device 100.

[0039] The connection mode of each functional block of the photoelectric conversion device 100 is not limited to... Figure 1 Configuration examples, and can be, for example, as follows Figure 2 The configuration is shown in the example.

[0040] exist Figure 2 In the configuration example, output lines 16 extending in the first direction are arranged in each row of the pixel array of the pixel region 10. Each output line 16 is connected to a pixel 12 arranged in the first direction in the corresponding row, and forms a signal line shared by these pixels 12. Control lines 18 extending in the second direction are arranged in each column of the pixel array of the pixel region 10. Each control line 18 is connected to a pixel 12 arranged in the second direction in the corresponding column, and forms a signal line shared by these pixels 12.

[0041] The control lines 18 of each column are connected to the horizontal scanning circuit unit 60. The horizontal scanning circuit unit 60 generates control signals for reading pixel signals from the pixel 12 in response to a control signal output from the control pulse generation unit 80, and supplies the generated control signals to the pixel 12 via the control lines 18. Specifically, the horizontal scanning circuit unit 60 sequentially scans a plurality of pixels 12 in the pixel region 10 column by column to output the pixel signals of the pixels 12 belonging to each row of the selected column to the output line 16.

[0042] The output lines 16 of each row are connected to the readout circuit unit 50. The readout circuit unit 50 includes a plurality of holding units (not shown) arranged corresponding to each row of the pixel array of the pixel region 10, and has the function of holding the pixel signals of the pixels 12 of each row output from the pixel region 10 in column units via the output lines 16 in the holding units of the corresponding rows.

[0043] In response to the control signal output from the control pulse generation unit 80, the readout circuit unit 50 sequentially outputs the pixel signals held in the holding units of each row to the output circuit unit 70.

[0044] Figure 2 Other configurations in the configuration examples can be compared with... Figure 1 The configuration is the same as in the configuration example.

[0045] Figure 3 This is a block diagram illustrating a configuration example for pixel 12. (Example...) Figure 3 As illustrated, each pixel 12 includes a photoelectric conversion unit 20 and a signal processing unit 30. The photoelectric conversion unit 20 includes a photoelectric conversion element 22 and outputs a signal corresponding to the incident light. The signal processing unit 30 is a signal processing circuit that processes the signal output from the photoelectric conversion unit 20. The signal processing unit 30 may, for example, include: a functional block 30A, which includes a quenching element 32 and a waveform shaping circuit 34; and a functional block 30B, which includes a processing circuit 36 ​​and a selection circuit 38. Figure 3 In the illustrated pixel configuration, the control lines 14 of each row may include signal lines 14A and 14B, wherein a control signal pRES is supplied from the vertical scan circuit unit 40 to the signal line 14A, and a control signal pSEL is supplied from the vertical scan circuit unit 40 to the signal line 14B.

[0046] The photoelectric conversion element 22 may be an avalanche photodiode (hereinafter referred to as "APD"). The anode of the APD constituting the photoelectric conversion element 22 is connected to a node supplied with a voltage VL. The cathode of the APD constituting the photoelectric conversion element 22 is connected to one terminal of the quenching element 32 and the input node of the waveform shaping circuit 34. The connection node of the photoelectric conversion element 22, the quenching element 32, and the waveform shaping circuit 34 is the output node of the photoelectric conversion unit 20 and also the input node of the signal processing unit 30. The other terminal of the quenching element 32 is connected to a node supplied with a voltage VH higher than the voltage VL. The voltages VL and VH are configured such that a reverse bias voltage sufficient to cause the APD to perform avalanche multiplication operation is applied. In one example, a negative high voltage is applied as voltage VL, and a positive voltage equivalent to the supply voltage is applied as voltage VH. For example, voltage VL may be approximately -20V to -30V, and voltage VH may be approximately 2V to 3V. In the following description, for simplicity, it is assumed that voltage VL is -Vbd and voltage VH is Vex. Here, voltage Vbd is the breakdown voltage of the APD, and voltage Vex is the overbias voltage. That is, the voltage obtained by applying the overbias voltage Vex to the breakdown voltage Vbd is applied between the cathode and anode of the APD.

[0047] The photoelectric conversion element 22 can be configured by an APD as described above. When a reverse bias voltage sufficient for avalanche multiplication operation is supplied to the APD, charge carriers generated by the light incident on the APD cause avalanche multiplication and generate an avalanche current. Operating modes with a reverse bias voltage supplied to the APD include Geiger mode and linear mode. Geiger mode is an operating mode in which the voltage applied between the anode and cathode is set to a reverse bias voltage greater than the breakdown voltage of the APD. Linear mode is an operating mode in which the voltage applied between the anode and cathode is set to a reverse bias voltage close to or lower than the breakdown voltage of the APD. An APD operating in Geiger mode is called a single-photon avalanche diode (SPAD). The APD constituting the photoelectric conversion element 22 can operate in linear mode or Geiger mode, but a SPAD with a larger potential difference and a significantly improved signal-to-noise ratio compared to an APD in linear mode is preferred.

[0048] Despite Figure 3 In the circuit configuration, the anode of the APD is set to a fixed potential and the signal is extracted from the cathode side. However, the cathode of the APD can be set to a fixed potential and the signal can be extracted from the anode side. In the former case, the signal charge is electrons. In the latter case, the signal charge is holes. Furthermore, in this embodiment, the case where one node of the APD is set to a fixed potential will be described, but the potentials of both nodes can vary. In the following description, the configuration where electrons are used as signal charges will be described. When holes are used as signal charges, the conductivity type of the semiconductor regions constituting each part of the photoelectric conversion element 22 can be opposite to the conductivity type of the configuration described below.

[0049] The quenching element 32 has the function of converting the change in avalanche current generated in the photoelectric conversion element 22 into a voltage signal. Furthermore, the quenching element 32 functions as a load circuit (quenching circuit) during signal multiplication via avalanche multiplication, and has the function of suppressing avalanche multiplication by reducing the voltage applied to the photoelectric conversion element 22. The operation of the quenching element 32 in suppressing avalanche multiplication is called a quenching operation. The quenching element 32 has the function of resetting the voltage supplied to the photoelectric conversion element 22 to voltage VH by allowing a current corresponding to the voltage drop caused by the quenching operation to flow. The operation of resetting the voltage supplied from the quenching element 32 to voltage VH is called a recharge operation. The quenching element 32 can be configured as a resistor or a MOS transistor, etc.

[0050] The waveform shaping circuit 34 includes an input node and an output node, to which the output signal of the photoelectric conversion unit 20 is supplied. The waveform shaping circuit 34 has the function of converting the analog signal supplied from the photoelectric conversion unit 20 into a pulse signal. The waveform shaping circuit 34 can be configured with logic circuits including NOT circuits (inverter circuits), NOR circuits, and NAND circuits. The output node of the waveform shaping circuit 34 is connected to the processing circuit 36.

[0051] The processing circuit 36 ​​includes an input node to which the output signal of the waveform shaping circuit 34 is supplied, a control node connected to the control line 14, and an output node. The processing circuit 36 ​​has the function of performing predetermined signal processing on the output signal of the waveform shaping circuit 34 and maintaining the processed signal or processing result. Although not particularly limited, the processing circuit 36 ​​may include, for example, a counter circuit and a memory. When the processing circuit 36 ​​includes a counter circuit, it counts the pulses superimposed on the signal output from the waveform shaping circuit 34 and maintains the count value as a result. The signal supplied to the processing circuit 36 ​​from the vertical scan circuit unit 40 via the control line 14 may include an enable signal for controlling the pulse counting period (exposure period) and a reset signal for resetting the count value maintained by the processing circuit 36, etc. As an example, Figure 3 Example of a reset signal (control signal pRES) supplied via signal line 14A. The output node of processing circuit 36 ​​is connected to selection circuit 38.

[0052] The selection circuit 38 has the function of switching the electrical connection state (connected or not connected) between the processing circuit 36 ​​and the output line 16. The selection circuit 38 operates according to a selection signal supplied from the vertical scan circuit unit 40 via the control line 14 (or in...). Figure 2 In the configuration example, a selection signal supplied from the horizontal scan circuit unit 60 via control line 18 switches the connection state between the processing circuit 36 ​​and the output line 16. As an example, Figure 3 An example is a selection signal (control signal pSEL) supplied via signal line 14B. Processing circuitry 36 may include buffer circuitry for the output signal.

[0053] Typically, pixel 12 is a unit structure that outputs pixel signals used to form an image. However, in cases where the goal is distance measurement, for example using a Time-of-Flight (TOF) method, pixel 12 does not necessarily need to be a unit structure that outputs pixel signals used to form an image. That is, pixel 12 can be a unit structure that outputs signals used to measure the time and amount of light arrival.

[0054] It is not necessary to set up a signal processing unit 30 for each pixel 12, but a signal processing unit 30 can be set up for multiple pixels 12. In this case, a single signal processing unit 30 can be used to sequentially process the signals of multiple pixels 12.

[0055] Next, we will refer to Figure 4 (A) to Figure 5 (D) describes the basic operation of the photoelectric conversion unit 20 in the photoelectric conversion device according to this embodiment. Figure 4 (A) to Figure 5 (D) is a diagram illustrating the basic operation of the photoelectric conversion element 22, the quenching element 32 and the waveform shaping circuit 34 in the photoelectric conversion device according to this embodiment. Figure 4 (A) to Figure 4 Example (C) illustrates the operation when the quenching element 32 is formed by a passive element, and Figure 5 (A) to Figure 5 Example (D) illustrates the operation when the quenching element 32 is formed by an active element. Here, for the sake of simplicity, it is assumed that the waveform shaping circuit 34 is configured as an inverter circuit.

[0056] First, the operation will be described when the quenching element 32 is formed by a passive element. Examples of the quenching element 32 being formed by a passive element include the case where the quenching element 32 is formed by a resistor and the case where the quenching element 32 is formed by a MOS transistor connected by a diode. Figure 4 (A) is a circuit diagram of photoelectric conversion element 22, quenching element 32 and waveform shaping circuit 34. Figure 4 Example (B) shows the waveform of the signal at the input node (node ​​A) of the waveform shaping circuit 34. Figure 4 Example (C) shows the waveform of the signal at the output node (node ​​B) of waveform shaping circuit 34.

[0057] At time t0, a potential difference corresponding to (VH-VL) (that is, a reverse bias voltage of (Vbd+Vex)) is applied to the photoelectric conversion element 22. Although a reverse bias voltage sufficient to cause avalanche multiplication is applied between the anode and cathode of the APD constituting the photoelectric conversion element 22, there are no primary carriers required for avalanche multiplication when photons are not incident on the photoelectric conversion element 22. Therefore, avalanche multiplication does not occur in the photoelectric conversion element 22, and no current flows through the photoelectric conversion element 22.

[0058] At a subsequent time t1, it is assumed that a photon is incident on photoelectric conversion element 22. When the photon is incident on photoelectric conversion element 22, electron-hole pairs are generated through photoelectric conversion. These primary charge carriers cause avalanche multiplication, and an avalanche multiplication current flows through photoelectric conversion element 22. When the avalanche multiplication current flows through quenching element 32, a voltage drop occurs due to quenching element 32, and the voltage at node A begins to decrease. When the voltage drop at node A becomes large and reaches approximately Vex, avalanche multiplication stops at time t3, and the voltage level at node A no longer decreases. The potential at which avalanche multiplication stops is approximately 0V, that is, the voltage applied to photoelectric conversion element 22 is approximately Vbd.

[0059] When the avalanche multiplication in the photoelectric conversion element 22 stops, the current compensating for the voltage drop flows from node VH to node A via the quenching element 32, and the voltage at node A gradually increases. Thereafter, at time t5, node A stabilizes back to its original voltage level.

[0060] The waveform shaping circuit 34 binarizes the signal input from node A according to a predetermined judgment threshold and outputs the signal from node B. Specifically, the waveform shaping circuit 34 outputs a low-level signal from node B when the voltage level of node A exceeds the judgment threshold, and outputs a high-level signal from node B when the voltage level of node A is equal to or less than the judgment threshold. For example, as... Figure 4 As illustrated in (B), it is assumed that during the time interval from time t2 to time t4, the voltage of node A is equal to or below the judgment threshold. In this case, as... Figure 4 As illustrated in (C), the signal level at node B becomes low during the time intervals from time t0 to time t2 and from time t4 to time t5, and becomes high during the time interval from time t2 to time t4.

[0061] Therefore, the analog signal input from node A is shaped into a digital signal by the waveform shaping circuit 34. The pulse signal output from the waveform shaping circuit 34 in response to photons incident on the photoelectric conversion element 22 is a photon detection pulse signal.

[0062] Next, the operation when the quenching element 32 is formed by an active element will be described. In the case where the quenching element 32 is formed by an active element, for example, the case where the quenching element 32 is formed by a MOS transistor operated by an external control signal can be illustrated. Figure 5 (A) is a circuit diagram of photoelectric conversion element 22, quenching element 32 and waveform shaping circuit 34. Figure 5 Example (B) shows the waveform of the signal at the input node (node ​​C) of the quenching element 32. Figure 5 Example (C) shows the waveform of the signal at the input node (node ​​A) of the waveform shaping circuit 34. Figure 5Example (D) shows the waveform of the signal at the output node (node ​​B) of waveform shaping circuit 34.

[0063] exist Figure 5 In circuit (A), the quenching element 32 is formed by a p-channel MOS transistor. The source of the p-channel MOS transistor is connected to the node of voltage VH, and the drain of the p-channel MOS transistor is connected to the cathode of the photoelectric conversion element 22 and the input node of the waveform shaping circuit 34. The connection node between the drain of the p-channel MOS transistor, the cathode of the photoelectric conversion element 22, and the input node of the waveform shaping circuit 34 is node A. For example... Figure 5 As illustrated in (B), a periodic pulse signal (hereinafter referred to as the reset pulse signal) is input to the gate (node ​​C) of the p-channel MOS transistor. The reset pulse signal is a falling pulse that transitions from a high level to a low level. The p-channel MOS transistor turns off when node C is high to disconnect node A from the voltage VH, and turns on when node C is low to reset node A to the voltage VH.

[0064] When a reset pulse signal is input to node C at time t1, the p-channel MOS transistor turns on, and node A is reset to voltage VH. When node C returns to a high level, the p-channel MOS transistor turns off, and node A enters a floating state at voltage VH.

[0065] At time t2, it is assumed that a photon is incident on photoelectric conversion element 22. When the photon is incident on photoelectric conversion element 22, electron-hole pairs are generated through photoelectric conversion. These charge carriers act as seeds, causing avalanche multiplication, and an avalanche multiplication current flows through photoelectric conversion element 22. When this avalanche multiplication current flows through quenching element 32, a voltage drop occurs due to quenching element 32, and the voltage at node A begins to decrease. When the voltage drop at node A becomes large and reaches approximately Vex, avalanche multiplication stops at time t4, and the voltage level at node A no longer decreases. The potential at which avalanche multiplication stops is approximately 0V, that is, the voltage applied to photoelectric conversion element 22 is approximately Vbd. Node A enters a floating state while remaining at the decreasing potential.

[0066] When the reset pulse signal is input to node C again at time t5, the p-channel MOS transistor turns on, and node A is reset to voltage VH again.

[0067] The waveform shaping circuit 34 binarizes the signal input from node A according to a predetermined judgment threshold and outputs the signal from node B. Specifically, the waveform shaping circuit 34 outputs a low-level signal from node B when the voltage level of node A exceeds the judgment threshold, and outputs a high-level signal from node B when the voltage level of node A is equal to or less than the judgment threshold. For example, as... Figure 5 As illustrated in (C), it is assumed that during the time interval from time t3 to time t5, the voltage of node A is equal to or below the judgment threshold. In this case, as... Figure 5 As illustrated in (D), the signal level at node B becomes low during the time interval from time t0 to time t3 and after time t5, and becomes high during the time interval from time t3 to time t5.

[0068] Therefore, the analog signal input from node A is shaped into a digital signal by the waveform shaping circuit 34. The pulse signal output from the waveform shaping circuit 34 in response to photons incident on the photoelectric conversion element 22 is a photon detection pulse signal.

[0069] exist Figure 5 (A) to Figure 5 In operation (D), if no photon is incident between time t1 and time t5, node A remains at voltage VH, and node B remains at a low level. Furthermore, if a photon is incident again during the period from the time of photon incident at time t2 until time t5 (i.e., while the potential of node A is reduced), the photoelectric conversion element 22 cannot cause further avalanche multiplication. Therefore, the waveform shaping circuit 34 can detect a maximum of one photon incident during the period from time t1 to time t5.

[0070] As mentioned above, in Figure 5 (A) to Figure 5 In the operation of (D), it is possible to distinguish whether the number of photons incident during one cycle of the reset pulse signal is zero or one or more. On the other hand, when two or more photons are incident during one cycle of the reset pulse signal, these photons cannot be distinguished from each other, and there is a possibility of signal detection loss.

[0071] When photons appear continuously, Figure 4 (A) to Figure 4 In operation (C), avalanche multiplication in photoelectric conversion element 22 does not stop, and the avalanche current continues to flow, meaning a so-called pile-up state occurs. In this pile-up state, no photon detection pulse signal is generated, and current simply flows wastefully, which is a major problem in SPAD operation.

[0072] On the other hand, Figure 5 (A) to Figure 5 In the operation of (D), when two or more photons are incident during one cycle of the reset pulse signal, these photons cannot be distinguished from each other, but there are the following advantages: Figure 4 (A) to Figure 4The accumulation that may occur during operation (C) will not happen. Although in Figure 5 (A) to Figure 5 While signal detection loss can certainly occur during the operation of (D), SPADs were originally designed for photon detection in situations with small photon incidence, where few photons are incident multiple times during a single reset pulse cycle, and signal detection loss is negligible. Therefore, when SPADs are specifically used as image sensors, they are typically applied... Figure 5 (A) to Figure 5 The operation of (D).

[0073] The photoelectric conversion device 100 according to this embodiment can be formed on a single substrate, or configured as a stacked photoelectric conversion device comprising multiple substrates. In the latter case, for example... Figure 6 As illustrated, the photoelectric conversion device can be configured as a stacked photoelectric conversion device, wherein the sensor substrate 110 (first substrate) and the circuit substrate 180 (second substrate) are stacked and electrically connected to each other. At least the photoelectric conversion unit 20 of the constituent elements of the pixel 12 can be arranged on the sensor substrate 110. In addition, the signal processing unit 30 of the constituent elements of the pixel 12 can be arranged on the circuit substrate 180. The photoelectric conversion unit 20 and the signal processing unit 30 are electrically connected to each other via connection wiring provided for each pixel 12. The circuit substrate 180 may also include a vertical scanning circuit unit 40, a readout circuit unit 50, a horizontal scanning circuit unit 60, an output circuit unit 70, and a control pulse generation unit 80.

[0074] The photoelectric conversion unit 20 and signal processing unit 30 of each pixel 12 can be arranged on the sensor substrate 110 and circuit substrate 180 in a manner that overlaps with each other in a plan view. The vertical scanning circuit unit 40, readout circuit unit 50, horizontal scanning circuit unit 60, output circuit unit 70, and control pulse generation unit 80 can be arranged around the pixel region 10 composed of multiple pixels 12. Here, the term "plan view" refers to a view viewed from a direction orthogonal to the surface of the sensor substrate 110.

[0075] By configuring the stacked photoelectric conversion device 100, the integration of components can be increased and higher functionality can be achieved. In particular, by arranging the photoelectric conversion unit 20 and the signal processing unit 30 on different substrates, the photoelectric conversion element 22 can be arranged at a high density without sacrificing the light-receiving area of ​​the photoelectric conversion element 22, and the photon detection efficiency can be improved.

[0076] The number of substrates constituting the photoelectric conversion device 100 is not limited to two, and three or more substrates can be stacked to constitute the photoelectric conversion device 100. For example, when the photoelectric conversion device 100 is constructed by stacking three substrates, the photoelectric conversion unit 20 in the constituent elements of the pixel 12 can be arranged on the sensor substrate. In addition, the functional block 30A in the constituent elements of the pixel 12 can be arranged on the first circuit substrate, and the functional block 30B in the constituent elements of the pixel 12 can be arranged on the second circuit substrate. By dividing the substrates to be arranged according to the characteristics of the elements constituting each functional block, appropriate manufacturing processes can be applied to each element, and the performance of the photoelectric conversion device can be improved.

[0077] exist Figure 6 In this context, it is assumed that the diced chip serves as the sensor substrate 110 and the circuit substrate 180, but the sensor substrate 110 and the circuit substrate 180 are not limited to chips. For example, the sensor substrate 110 and the circuit substrate 180 can each be a wafer. Alternatively, the sensor substrate 110 and the circuit substrate 180 can be stacked in wafer form and then diced, or they can be stacked and bonded after forming the chip.

[0078] Next, we will refer to Figure 7 The specific component structure of the photoelectric conversion device 100 according to this embodiment is described. Figure 7 This is a schematic cross-sectional view illustrating the structure of the photoelectric conversion device according to this embodiment.

[0079] For example Figure 7 As illustrated, the photoelectric conversion device 100 according to this embodiment can be configured as a stacked photoelectric conversion device, wherein a sensor substrate 110 and a circuit substrate 180 are stacked. The sensor substrate 110 includes a semiconductor layer 120 having a first surface 122 and a second surface 124 opposite to the first surface 122, and an interconnect structure layer 150 disposed on the first surface 122 side of the semiconductor layer 120. An optical structure layer 190 may be disposed on the second surface 124 side of the semiconductor layer 120. The circuit substrate 180 is stacked on the interconnect structure layer 150 side of the sensor substrate 110. Figure 7 The bonding surface 170 is the bonding portion between the sensor substrate 110 and the circuit substrate 180. In the photoelectric conversion device according to this embodiment, the second surface 124 side of the semiconductor layer 120 on which the optical structure layer 190 is provided serves as a light-receiving surface on which the light to be detected is incident. That is, the photoelectric conversion device according to this embodiment is a so-called back-illuminated photoelectric conversion device.

[0080] For example, semiconductor layer 120 is formed by thinning a single-crystal silicon substrate and contains a predetermined concentration of n-type or p-type impurities. In this embodiment, as an example, it is assumed that semiconductor layer 120 is obtained by thinning an n-type silicon substrate having a low impurity concentration. Photoelectric conversion elements 22, each including an n-type semiconductor region, a p-type semiconductor region, and a semiconductor region, are disposed in semiconductor layer 120. The specific structure of photoelectric conversion element 22 will be described later. This embodiment is based on... Figure 4 (A) to Figure 5 The method for detecting changes in cathode potential is illustrated in (D). However, the method for detecting changes in anode potential can be used.

[0081] The interconnect structure layer 150 includes an insulating layer 152 and an interconnect layer 154 disposed in the insulating layer 152. The interconnect layer 154 includes an anode electrode 156 (second electrode) connected to the p-type semiconductor region 136, a cathode electrode 158 (first electrode) connected to the n-type semiconductor region 126, and a pad electrode 160 formed by the interconnect layer furthest from the semiconductor layer 120.

[0082] The circuit board 180 is stacked on the interconnect structure layer 150 side of the sensor board 110. Figure 7 The bonding surface 170 is the bonding portion between the sensor substrate 110 and the circuit substrate 180. The circuit substrate 180 includes a semiconductor layer on which elements such as transistors are disposed, and an interconnect structure layer disposed on the semiconductor layer. For the sake of simplicity, Figure 7 Only a portion of the interconnect layer 184, which is connected to the pad electrode 182, and the pad electrode 182 formed by the uppermost interconnect layer are illustrated in the semiconductor layer and interconnect structure layer constituting the circuit substrate 180. The sensor substrate 110 and the circuit substrate 180 can be physically and electrically connected to each other, for example, by metal-metal bonding between the metal members constituting the pad electrode 160 and the metal members constituting the pad electrode 182. The circuit substrate 180 may include multiple substrates.

[0083] The optical structure layer 190 may include a pinned film 192, a planarization layer 194, and a microlens layer including a plurality of microlenses 196. The optical structure layer 190 may also include a filter layer (not shown). Various optical filters, such as color filters, infrared cutoff filters, and monochromatic filters, may be applied to the filter layer. Known materials may be applied to the pinned film 192.

[0084] Next, we will refer to Figure 8 and Figure 9 The specific component structure of the photoelectric conversion element 22 in the photoelectric conversion device 100 according to this embodiment is described. Figure 8 This is a plan view illustrating the structure of the photoelectric conversion element in the photoelectric conversion device according to this embodiment. Figure 9This is a schematic cross-sectional view illustrating the structure of the photoelectric conversion element in the photoelectric conversion device according to this embodiment. Figure 8 This corresponds to a plan view of the semiconductor layer 120 as seen from the side view of the first surface 122. Figure 9 It is along Figure 8 The cross-sectional view intercepted by the line IX-IX'.

[0085] like Figure 8 and Figure 9 As illustrated, semiconductor layer 120 includes n-type semiconductor region 126, p-type semiconductor regions 128, 130, 132, 134, and 136, and semiconductor regions 138 and 140. P-type semiconductor region 130 is disposed on the second surface 124 side of semiconductor layer 120 in cross-sectional view. P-type semiconductor region 130 is configured to cover the entire area where photoelectric conversion elements 22 are arranged, and overlaps with n-type semiconductor regions 126, p-type semiconductor regions 128, 132, 134, and 136, and semiconductor regions 138 and 140 in plan view. When a back-illuminated photoelectric conversion device is configured, p-type semiconductor region 134 is preferably arranged to contact the second surface 124. This configuration prevents the generation of dark current on the second surface 124. P-type semiconductor region 132 is disposed at the boundary between adjacent photoelectric conversion elements 22. That is, p-type semiconductor region 132 is disposed around the respective areas where photoelectric conversion elements 22 are arranged in plan view. A p-type semiconductor region 132 is provided from the first surface 122 of the semiconductor layer 120 up to the depth where the p-type semiconductor region 130 is disposed. Although in Figure 8 and Figure 9 One photoelectric conversion element 22 is arranged in the region surrounded by the p-type semiconductor region 132, but two or more photoelectric conversion elements 22 may be arranged in each region surrounded by the p-type semiconductor region 132.

[0086] In this specification, the term "plan view" refers to a view taken from the normal direction of the light incident surface (second surface 124) or the opposite surface (first surface 122) of the semiconductor layer 120. Conversely, "cross-sectional view" refers to a view taken from the normal direction of a cut surface parallel to the normal direction of the first surface 122 or the second surface 124 of the semiconductor layer 120.

[0087] n-type semiconductor region 126, p-type semiconductor regions 128, 134 and 136, and semiconductor regions 138 and 140 are disposed inside the region surrounded by p-type semiconductor regions 130 and 132. n-type semiconductor region 126 is disposed on the first surface 122 side of semiconductor layer 120, separated from p-type semiconductor region 132. n-type semiconductor region 126 is disposed in the region extending from the first surface 122 to a depth D3. Depth here refers to the distance from the first surface 122 towards the second surface 124. p-type semiconductor region 128 is disposed in the region extending from a depth D4 relative to depth D3 on the second surface 124 side to a depth D5 relative to depth D4 on the second surface 124 side. p-type semiconductor region 128 contacts p-type semiconductor region 132 in the periphery of the plan view. A p-type semiconductor region 136 is arranged in a plan view to surround an n-type semiconductor region 126 from a depth D1 between the first surface 122 and a depth D3 to a depth D2, wherein the depth D2 is deeper than the depth D1 and equal to or shallower than the depth D3. The p-type semiconductor region 136 contacts the n-type semiconductor region 126. Figure 8 In the plan view, p-type semiconductor region 136 is separated from p-type semiconductor region 132 in the peripheral portion, but can contact p-type semiconductor region 132. P-type semiconductor region 134 is disposed on the first surface 122 side of semiconductor layer 120 in a manner that contacts p-type semiconductor region 132 and is separated from n-type semiconductor region 126. For example... Figure 8 As illustrated, p-type semiconductor region 134 can be in contact with p-type semiconductor region 136. Conversely, p-type semiconductor region 136 can be separated from p-type semiconductor regions 132 and 134. The portion of the region extending from the first surface 122 to depth D4, excluding n-type semiconductor regions 126 and p-type semiconductor regions 132, 134, and 136, is semiconductor region 138. The region between p-type semiconductor regions 128 and 130 is semiconductor region 140. The conductivity type of semiconductor regions 138 and 140 is not particularly limited, and they can be either n-type or p-type.

[0088] The n-type semiconductor region 126 forms the cathode of the APD and contacts the cathode electrode 158, and is formed of an n-type semiconductor containing a high concentration of n-type impurities. The p-type semiconductor region 134 is the portion that contacts the anode electrode 156 of the APD, and is formed of a p-type semiconductor containing a high concentration of p-type impurities. The p-type semiconductor region 128 is the region that serves as the anode of the APD, and is formed of a p-type semiconductor containing p-type impurities. The p-type semiconductor region 128 is disposed at a depth closer to the second surface 124 than the depth from the cathode (n-type semiconductor region 126) to the second surface 124. The p-type semiconductor region 128 is formed to cover substantially the entire region where the photoelectric conversion element 22 is arranged. The semiconductor region 140 is the photoelectric conversion region and is formed of a semiconductor containing a low concentration of n-type or p-type impurities. The semiconductor region 138 is formed of a semiconductor containing a low concentration of n-type or p-type impurities, and at least the vicinity of the n-type semiconductor region 126 is depleted during operation.

[0089] In the photoelectric conversion element 22 according to this embodiment, the depletion layer formed in the pn junction between the n-type semiconductor region 126 and the p-type semiconductor region 128 serves as an avalanche multiplication region. The p-type semiconductor region 132 serves not only as an isolation portion of the element but also as a path for supplying an anode potential to the p-type semiconductor region 128 constituting the anode of the APD. That is, the anode potential supplied from the anode electrode 156 is supplied to the p-type semiconductor regions 128 and 130 via the p-type semiconductor regions 134 and 132. As a result, the potentials of the p-type semiconductor regions 132, 128, and 130 become anode potentials.

[0090] By applying a predetermined reverse bias voltage between the cathode electrode 158 and the anode electrode 156, a high electric field is applied to the pn junction between the n-type semiconductor region 126 and the p-type semiconductor region 128, and the APD can operate. During the operation of the APD, depletion occurs at least in the portion of the p-type semiconductor region 128 that overlaps with the n-type semiconductor region 126 in the planar view, penetrating the p-type semiconductor region 128 vertically. As a result, the signal charge generated by the incident photons on the semiconductor region 140 flows into the n-type semiconductor region 126 through the depletion region of the p-type semiconductor region 128 formed directly below the cathode, and in the process causes avalanche multiplication.

[0091] Here, it is known that: Since the first facet 122 of the semiconductor layer 120 is the terminal portion of the atomic arrangement constituting the semiconductor, many semiconductor atoms have dangling bonds and many carrier generation energy levels exist. Therefore, electron-hole pairs are generated at a high rate near the first facet 122 around the cathode, which is depleted during APD operation. When some of these pairs reach the strong electric field region between the cathode and anode, they cause avalanche multiplication, which leads to an increase in the dark count rate (DCR). Note that the DCR is the number of counts per unit time caused by dark carriers generated in the SPAD. The DCR is a major factor of dark noise in the SPAD and is desirable to reduce as much as possible.

[0092] From this perspective, in the photoelectric conversion element 22 according to this embodiment, a p-type semiconductor region 136 is provided around the n-type semiconductor region 126 in the plan view. The p-type semiconductor region 136 has a peak of p-type impurity concentration at a depth between the first surface 122 and the depth D3. The reason why the photoelectric conversion element 22 according to this embodiment has such a p-type semiconductor region 136 will be described below.

[0093] In this specification, the term "impurity concentration" means the effective impurity concentration, that is, the net impurity concentration obtained by subtracting the amount offset by impurities of the opposite conductivity type. In other words, the region where the concentration of p-type impurities is higher than the concentration of n-type impurities is a p-type semiconductor region having the impurity concentration obtained by subtracting the concentration of n-type impurities from the concentration of p-type impurities. The region where the concentration of n-type impurities is higher than the concentration of p-type impurities is an n-type semiconductor region having the impurity concentration obtained by subtracting the concentration of p-type impurities from the concentration of n-type impurities.

[0094] Figure 10 This is a graph illustrating the distribution of impurities along the depth direction along a vertical line passing through the center of the n-type semiconductor region 126 in the plan view. The horizontal axis represents the depth in the direction from the first surface 122 toward the second surface 124, and the vertical axis represents the impurity concentration (logarithmic axis). Figure 10 Examples include the concentration distribution of n-type impurity 126N constituting n-type semiconductor region 126, the concentration distribution of p-type impurity 128P constituting p-type semiconductor region 128, and the concentration distribution of p-type impurity 136P constituting p-type semiconductor region 136.

[0095] Figure 10 The depth D3 is the depth of the bottom surface of the n-type semiconductor region 126 (cathode), that is, the depth of the n-type semiconductor region 126 on the side of the second surface 124. In the operating state of the APD, the concentration of n-type impurities in the n-type semiconductor region 126 is approximately 1 × 10⁻⁶. 17 cm -3Or even smaller areas are depleted, so the actual cathode is an n-type semiconductor region 126 where the concentration of n-type impurities is approximately 1 × 10⁻⁶. 17 cm -3 Or a larger portion. Therefore, in this specification, the concentration of n-type impurities on the p-type semiconductor region 128 side is 1 × 10⁻⁶. 17 cm -3 The depth is defined as the depth D3 of the bottom surface of the n-type semiconductor region 126. The region on the side of the second surface 124, which is deeper than the depth D3, is a high electric field region that causes avalanche multiplication.

[0096] The p-type impurity 136P constituting the p-type semiconductor region 136 can be disposed not only around the n-type semiconductor region 126 in a planar view, but also in the portion overlapping with the n-type semiconductor region 126. Therefore, when viewing the distribution of the impurity along the depth direction of a vertical line passing through the center of the n-type semiconductor region 126, as... Figure 10 As illustrated, the p-type impurity 136P constituting the p-type semiconductor region 136 can exist between the first surface 122 and the depth D3. However, since the impurity concentration of the p-type impurity 136P is sufficiently less than the impurity concentration of the n-type impurity 126N, the net conductivity type in the overlapping portion of the n-type semiconductor region 126 and the p-type semiconductor region 136 is n-type. The p-type semiconductor region 136 has no particular effect there. Note that providing the p-type semiconductor region 136 in the overlapping portion with the n-type semiconductor region 126 has the advantage of preventing characteristic changes due to misalignment with the n-type semiconductor region 126.

[0097] On the other hand, when focusing on the region that does not overlap with the n-type semiconductor region 126 in the planar diagram, for example, at point C (see... Figure 8 and Figure 9 On the vertical line of the semiconductor region 136, the impurity concentration of the p-type impurity constituting the p-type semiconductor region 136 is higher than that of the impurity constituting the semiconductor region 138. Therefore, the conductivity type of the portion corresponding to the p-type impurity 136P becomes p-type, and the function of the p-type semiconductor region 136 becomes apparent.

[0098] Figure 10The illustrated depth D6 is the depth at which the concentration of p-type impurities constituting the p-type semiconductor region 136 becomes the peak. Depth D6 is located closer to the second surface 124 than the distance from the first surface 122 to the second surface 124. On the perpendicular line passing through point C, the p-type impurity concentration at the first surface 122 and depth D3 is sufficiently lower than the p-type impurity concentration at depth D6. That is, the p-type semiconductor region 136 needs to have a steep concentration gradient of p-type impurities relative to the depth direction. In this sense, in the region that does not overlap with the n-type semiconductor region 126 in the plan view, it is more preferable that the first surface 122 and its vicinity and depth D3 and its vicinity have n-type conductivity. Note that the case where the conductivity around depth D3 is n-type includes the case where the conductivity is n-type at a depth deeper than but closer to depth D3, and the case where the conductivity is n-type at a depth closer to depth D3 from a location deeper than depth D6.

[0099] Here, in the structure described above, we consider the generation of carriers from the carrier generation level of the first surface 122. As described above, during SPAD operation, the region surrounding the n-type semiconductor region 126 is depleted regardless of its conductivity type. Then, carriers are generated at a high rate from the depleted interface state of the first surface 122. When the direction parallel to the first surface 122 and the second surface 124 is defined as the lateral direction, the lateral component of the electric field around the n-type semiconductor region 126 in the planar view is large. Therefore, electrons generated on the first surface 122 drift toward the n-type semiconductor region 126, which serves as the cathode, and holes generated on the first surface 122 drift toward the p-type semiconductor region 128, which serves as the anode. When these carriers reach the high electric field region between the n-type semiconductor region 126 and the p-type semiconductor region 128, these carriers cause avalanche multiplication and are counted as DCR.

[0100] At this time, since the p-type semiconductor region 136 acts as a potential barrier for electrons, the region around the first surface 122 becomes a stable region with the lowest potential relative to electrons generated near the first surface 122. On the other hand, the p-type semiconductor region 136 becomes a stable region with the lowest potential relative to holes generated near the first surface 122. Therefore, both electrons and holes generated near the first surface 122 are prevented from diffusing in the depth direction by the p-type semiconductor region 136 and are not easily able to reach high electric field regions.

[0101] In other words, around the n-type semiconductor region 126 in the planar view, the first surface 122 and its vicinity serve as electron emission paths, and the p-type semiconductor region 136 serves as hole emission paths. It is more efficient for the conductivity type around the n-type semiconductor region 126 and its vicinity of the first surface 122 to form electron emission paths. However, even when the conductivity type around the n-type semiconductor region 126 in the planar view is p-type, emission paths can still be formed conditionally. Based on the inventors' considerations and simulations, by setting the p-type impurity concentration of the first surface 122 and its vicinity and the depth D3 and its vicinity to be equal to or less than half the peak impurity concentration of the p-type semiconductor region 136, electron emission paths that are less efficient than those of the n-type first surface and its vicinity can be formed. In other words, in at least one of the first surface 122 and its vicinity and the depth D3 and its vicinity, the p-type impurity concentration can be set to be equal to or less than half the peak impurity concentration of the p-type semiconductor region 136, or an n-type semiconductor region can be used. When the n-type semiconductor region is configured, the maximum impurity concentration in the n-type semiconductor region is set to be lower than the maximum impurity concentration in the n-type semiconductor region 126.

[0102] Figure 11 This is a schematic cross-sectional view illustrating the structure of a photoelectric conversion element according to the reference example. In the photoelectric conversion element 22 according to the reference example, a p-type semiconductor region 136 with a uniform low impurity concentration is provided around the n-type semiconductor region 126 and over a region at a depth D4 relative to the first surface 122 of the semiconductor layer. In this structure, when the p-type semiconductor region 136 is depleted, the potential of the p-type semiconductor region 136 is affected by the cathode potential of the n-type semiconductor region 126, becoming higher on the first surface 122 and lower in the depth direction, thus creating a potential gradient that drives holes in the deeper direction. Electrons can also diffuse in the deeper direction at locations away from the n-type semiconductor region 126. As a result, in this structure, no carrier exhaust path is formed, and the DCR caused by carriers generated on the first surface 122 of the semiconductor layer cannot be reduced.

[0103] The effect of this embodiment becomes more significant when the first surface 122 and its vicinity, and the depth D3 and its vicinity, around the n-type semiconductor region 126 in the plan view have an n-type conductivity structure. Therefore, n-type impurities can be actively introduced into the depths of the first surface 122 and its vicinity, and the depths of the depth D3 and its vicinity to form an n-type semiconductor region. The n-type semiconductor region can be set in the same region as the p-type semiconductor region 136 in the plan view, or it can be set in the entire region where the photoelectric conversion element 22 is arranged.

[0104] Despite Figure 8 and Figure 9In the configuration example, p-type semiconductor regions 136 and 134 are directly connected, but p-type semiconductor region 136 does not necessarily have to be directly connected to p-type semiconductor region 134. For example, even if an n-type semiconductor region with a low impurity concentration exists between p-type semiconductor regions 134 and 136, p-type semiconductor region 136 can still function as a hole evacuation path to p-type semiconductor region 134, provided that the n-type semiconductor region is depleted during operation. P-type semiconductor region 136 can be directly connected to p-type semiconductor region 134 or p-type semiconductor region 132. Additionally, in Figure 8 and Figure 9 In the configuration example, two p-type semiconductor regions 134 are arranged, but this embodiment is not limited to this, and one p-type semiconductor region 134 or three or more p-type semiconductor regions 134 can be arranged.

[0105] As described above, according to this embodiment, a p-type semiconductor region with a peak of impurity concentration is provided around the cathode at a position shallower than the bottom surface of the cathode, thereby reducing noise caused by carriers generated from the carrier generation level in the photoelectric conversion element, particularly at the first semiconductor surface 122. Second Embodiment

[0106] Reference Figure 12 A photoelectric conversion device according to a second embodiment is described. Figure 12 This is a schematic cross-sectional view illustrating the structure of the photoelectric conversion element in the photoelectric conversion device according to this embodiment. Components identical to those in the photoelectric conversion device according to the first embodiment are indicated by the same reference numerals, and their descriptions will be omitted or simplified.

[0107] Except for the different structure of the photoelectric conversion element 22, the photoelectric conversion device according to this embodiment is the same as the photoelectric conversion device according to the first embodiment. In this embodiment, the differences between the photoelectric conversion element of this embodiment and the photoelectric conversion element of the first embodiment will be mainly described, and the description of the parts common to the photoelectric conversion element of the first embodiment will be appropriately omitted.

[0108] The difference between the photoelectric conversion element 22 in this embodiment and the photoelectric conversion element in the first embodiment lies in the structure of the n-type semiconductor region 126. That is, as... Figure 12 As illustrated, the n-type semiconductor region 126 of the photoelectric conversion element 22 in this embodiment has a narrow portion 142 in the depth direction. The narrow portion 142 of the n-type semiconductor region 126 is located at the same depth as the p-type semiconductor region 136 is disposed, and more preferably, it is located near the depth D6 where the concentration of p-type impurities constituting the p-type semiconductor region 136 becomes the peak.

[0109] Figure 13 This is a graph illustrating the distribution of impurities along a vertical line passing through the center of the n-type semiconductor region 126 in the depth direction. The horizontal axis represents the depth in the direction from the first surface 122 toward the second surface 124, and the vertical axis represents the impurity concentration (logarithmic axis). Figure 13 Examples include the concentration distributions of n-type impurities 126-1N and 126-2N constituting n-type semiconductor region 126, the concentration distribution of p-type impurity 128P constituting p-type semiconductor region 128, and the concentration distribution of p-type impurity 136P constituting p-type semiconductor region 136.

[0110] In this embodiment, the n-type semiconductor region 126 in the photoelectric conversion element 22 can be formed, for example, by repeatedly implanting n-type impurities with ions under different projection ranges. Figure 13 In the diagram, n-type impurity 126-1N indicates the distribution of n-type impurity ions implanted when the projected range becomes shallower than the depth D6, and n-type impurity 126-2N indicates the distribution of n-type impurity ions implanted when the projected range becomes deeper than the depth D6. Here, the n-type semiconductor regions formed by ion implantation are referred to as n-type semiconductor regions 126-1 and 126-2, respectively. The projected range of the implanted ions can be arbitrarily changed by appropriately setting the acceleration energy according to the ion type.

[0111] The n-type semiconductor region 126-1 has a peak of n-type impurity concentration closer to the first surface 122 than the depth D6 to the first surface 122. The n-type semiconductor region 126-2 has a peak of n-type impurity concentration on the second surface 124 side, which is deeper than the bottom surface of the second surface 124 side of the n-type semiconductor region 126-1. The n-type semiconductor regions 126-1 and 126-2 are configured such that at least a portion of the tail of the n-type semiconductor region 126-1 on the second surface 124 side overlaps with at least a portion of the tail of the n-type semiconductor region 126-2 on the first surface 122 side. The n-type semiconductor regions 126-1 and 126-2 are electrically connected to each other at their overlapping portion and have substantially the same potential. That is, in the photoelectric conversion element 22 of this embodiment, the n-type semiconductor regions 126-1 and 126-2 are integrally formed into a cathode. The connection between the n-type semiconductor region 126-1 and the n-type semiconductor region 126-2 is located at the depth where the p-type semiconductor region 136 is arranged.

[0112] Impurities doped by ion implantation are distributed not only in the depth direction but also in the horizontal direction. The smaller the area of ​​the region to be doped and the deeper the formation location, the greater the curvature of the central portion of the convex shape in the cross-sectional shape of the semiconductor region to be formed. This is because, due to the distribution of impurities constituting the semiconductor region, the impurity concentration becomes lower as the distance relative to the central portion increases, and the impurity distribution tends to expand as the formation location becomes deeper. As a result, the width of n-type semiconductor regions 126-1 and 126-2 in the planar view near the depth D6 where the tails of n-type semiconductor regions 126-1 and 126-2 overlap is smaller than the maximum width of n-type semiconductor regions 126-1 and 126-2 in the planar view. This portion corresponds to the narrow portion 142 of n-type semiconductor region 126.

[0113] n-type semiconductor regions 126-1 and 126-2 can have the same shape in a planar view, but they do not necessarily need to have the same shape and can have different sizes in the planar view. However, when n-type semiconductor regions 126-1 and 126-2 have substantially the same shape in a planar view, they can be formed by the same mask process, which is advantageous in terms of simplifying the manufacturing process.

[0114] The p-type semiconductor region 136 can be disposed at a depth substantially the same as the overlap depth of the n-type semiconductor regions 126-1 and 126-2. The peak impurity concentration of the p-type semiconductor region 136 is preferably lower than the concentration of n-type impurities at the overlap depth of the n-type semiconductor regions 126-1 and 126-2. This is because if the concentration of p-type impurities constituting the p-type semiconductor region 136 is higher than the concentration of n-type impurities, there is a possibility that electrical conduction between the n-type semiconductor regions 126-1 and 126-2 cannot be maintained.

[0115] Similarly, in this embodiment, the n-type impurity concentration on the p-type semiconductor region 128 side of the cathode region formed by the n-type semiconductor region 126 is 1×10⁻⁶. 17 cm -3 The depth D3 is defined as the bottom surface of the cathode. Based on 1×10 17 cm -3 The reason for defining the bottom surface of the cathode based on the n-type impurity concentration is the same as in the first embodiment. The region on the side of the second surface 124, which is deeper than depth D3, is a high-field region that causes avalanche multiplication. Since the p-type semiconductor region 136 is located at a depth substantially the same as the depth at which the n-type semiconductor regions 126-1 and 126-2 overlap, the depth D3 of the bottom surface of the cathode is located closer to the second surface 124 than the depth D6, where the concentration of the p-type impurity 136P is at its peak.

[0116] Generally, in charge-collecting SPADs, the cathode size is small relative to the pixel size, and when a high voltage is applied between the anode and cathode during operation, the electric field lines are concentrated on the cathode, and the electric field strength increases near the cathode. On the other hand, electrons generated at the first surface 122 drift towards the cathode from the first surface 122 and its vicinity, and are accelerated by the electric field near the cathode. At this time, some of the electrons accelerated by the electric field near the cathode retain kinetic energy even when they enter the cathode end near the neutral region, potentially causing impact ionization. Holes from the carrier pairs generated by impact ionization diffuse to the neutral region near the cathode end.

[0117] In the structure of the photoelectric conversion element according to the first embodiment or the photoelectric conversion element according to the reference example, holes generated in the neutral region inside the cathode by the above-described mechanism diffuse with a certain probability to the bottom of the cathode. The bottom of the cathode is the location with the highest electric field strength in the photoelectric conversion element, and the probability of avalanche multiplication is the highest. Therefore, holes reaching the bottom of the cathode can be detected as DCR in this way.

[0118] Similarly, in the photoelectric conversion element 22 of this embodiment, holes can be generated by impact ionization at the cathode in contact with the first surface 122 (that is, at the end of the n-type semiconductor region 126). However, as Figure 12 As illustrated, the cathode of the photoelectric conversion element 22 in this embodiment has a narrow portion 142 at the depth where the n-type semiconductor regions 126-1 and 126-2 overlap. As described above, the narrow portion 142 is formed because the n-type semiconductor region 126-2 has a convex shape and the peak depth of the impurity concentration is at a position deeper than the bottom surface of the n-type semiconductor region 126-1.

[0119] In the planar view, the peripheries of the n-type semiconductor regions 126-1 and 126-2 are depleted, generating an electric field in the lateral direction. However, in the narrow portion 142 of the cathode, the depleted region has a shape that intrudes into the cathode. Holes generated in the neutral region near the end of the n-type semiconductor region 126 tend to diffuse in a deeper direction (towards the second surface 124), but at the narrow portion 142, they leave and reach the outside of the n-type semiconductor region 126, and are discharged when they pass through the p-type semiconductor region 136, which serves as a hole discharge path. Therefore, holes hardly reach the bottom of the cathode (i.e., the depth D3 of the bottom of the n-type semiconductor region 126), and hole counts as DCR can be prevented. To further clarify the narrow structure of the cathode, in a region substantially the same as the region of the n-type semiconductor region 126 in the planar view, p-type impurities can be further introduced to a depth substantially the same as the depth of the narrow portion 142.

[0120] The periphery of the n-type semiconductor region 126 in the plan view, the first surface 122 and its vicinity and the depth D3 and its vicinity can be an n-type semiconductor region or a p-type semiconductor region having a p-type impurity concentration equal to or less than half of the peak impurity concentration of the p-type semiconductor region 136.

[0121] Figure 14 This is a schematic cross-sectional view illustrating the structure of a photoelectric conversion element according to a modified example of this embodiment. Besides Figure 12 In addition to the components of the illustrated photoelectric conversion element, Figure 14 The illustrated photoelectric conversion element also includes n-type semiconductor regions 144 and 146. In the plan view, n-type semiconductor region 144 is disposed at a depth in and around a first surface 122 surrounding n-type semiconductor region 126. In the plan view, n-type semiconductor region 146 is disposed at a location in the plan view surrounding n-type semiconductor region 126 at a depth greater than the peak depth of p-type semiconductor region 136. In other words, n-type semiconductor region 146 is arranged in the plan view in the region overlapping with p-type semiconductor region 136 to have a peak of impurity concentration between p-type semiconductor region 136 and depth D3.

[0122] exist Figure 14 In the illustrated photoelectric conversion element, the n-type semiconductor region 144 functions as an electron ejection path, and the p-type semiconductor region 136 functions as a potential barrier for electrons. Although the p-type semiconductor region 136 functions as a hole ejection path, the n-type semiconductor region 146 acts as a potential barrier for holes, effectively preventing holes in the p-type semiconductor region 136 from diffusing to deeper layers. Therefore, the DCR reduction effect can be further enhanced. The maximum impurity concentration in the n-type semiconductor regions 144 and 146 is set to be lower than the maximum impurity concentration in the n-type semiconductor region 126.

[0123] As described above, according to this embodiment, a p-type semiconductor region with a peak of impurity concentration at a position shallower than the bottom surface of the cathode is provided around the cathode, thereby reducing noise caused by carriers generated from the carrier generation energy level in the photoelectric conversion element. Furthermore, by providing a narrow portion in the depth direction of the cathode, carriers generated from the carrier generation energy level can be discharged more effectively, and noise can be further reduced. Third Embodiment

[0124] Reference Figure 15 A photoelectric detection system according to a third embodiment is described. Figure 15 This is a block diagram illustrating a schematic configuration of the photoelectric detection system according to this embodiment. In this embodiment, a photoelectric detection sensor using the photoelectric conversion device 100 according to the first or second embodiment will be described.

[0125] The photoelectric conversion device 100 described in the first or second embodiment can be applied to various photoelectric detection systems. Examples of applicable photoelectric detection systems include imaging systems such as digital still cameras, digital video cameras, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Camera modules, including optical systems such as lenses and imaging devices, are also included in photoelectric detection systems. Figure 15 Here is an example of a block diagram of a digital still camera, which is one of these.

[0126] Figure 15 The illustrated photoelectric detection system 200 includes a photoelectric conversion device 201, a lens 202 that forms an optical image of a subject on the photoelectric conversion device 201, an aperture 204 for varying the amount of light passing through the lens 202, and a baffle 206 for protecting the lens 202. The lens 202 and the aperture 204 form an optical system that concentrates light onto the photoelectric conversion device 201. The photoelectric conversion device 201 is the photoelectric conversion device 100 described in the first or second embodiment, and converts the optical image formed by the lens 202 into image data.

[0127] The photoelectric detection system 200 also includes a signal processing unit 208 for processing the output signal from the photoelectric conversion device 201. The signal processing unit 208 generates image data based on the digital signal output from the photoelectric conversion device 201. Furthermore, the signal processing unit 208 performs various corrections and compressions as needed and outputs the processed image data. The photoelectric conversion device 201 may include an AD conversion unit for generating the digital signal to be processed by the signal processing unit 208. The AD conversion unit may be formed on a semiconductor layer (semiconductor substrate) on which the photoelectric conversion element of the photoelectric conversion device 201 is formed, or it may be formed on a different semiconductor layer than the semiconductor layer on which the photoelectric conversion element of the photoelectric conversion device 201 is formed. The signal processing unit 208 may be formed on the same semiconductor layer as the photoelectric conversion device 201.

[0128] The photoelectric detection system 200 also includes a buffer memory unit 210 for temporarily storing image data and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. Furthermore, the photoelectric detection system 200 includes a storage medium 214, such as a semiconductor memory, for storing or retrieving image data, and a storage medium control interface unit (storage medium control I / F unit) 216 for storing or retrieving data from the storage medium 214. The storage medium 214 may be built into the photoelectric detection system 200 or may be removable. Communication between the storage medium control I / F unit 216 and the storage medium 214, as well as communication from the external I / F unit 212, can be wireless.

[0129] The photoelectric detection system 200 also includes a general-purpose control / operation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the photoelectric conversion device 201 and the signal processing unit 208. Here, timing signals can be input from external sources, and the photoelectric detection system 200 may include at least the photoelectric conversion device 201 and the signal processing unit 208 for processing the output signals from the photoelectric conversion device 201. The timing generation unit 220 may be mounted on the photoelectric conversion device 201. Furthermore, the general-purpose control / operation unit 218 and the timing generation unit 220 may be configured to perform part or all of the control functions of the photoelectric conversion device 201.

[0130] The photoelectric conversion device 201 outputs a camera signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the camera signal output from the photoelectric conversion device 201 and outputs image data. The signal processing unit 208 uses the camera signal to generate an image. The signal processing unit 208 can be configured to perform distance measurement calculations on the signal output from the photoelectric conversion device 201.

[0131] As described above, according to this embodiment, by using a photoelectric conversion device according to the first embodiment or the second embodiment to configure the photoelectric detection system, a photoelectric detection system capable of acquiring higher quality images can be realized. Fourth embodiment

[0132] Reference Figure 16 A distance image sensor according to a fourth embodiment is described. Figure 16 This is a block diagram illustrating a schematic configuration of a distance image sensor according to this embodiment. In this embodiment, the distance image sensor will be described as an example of a photoelectric detection system applying the photoelectric conversion device 100 according to the first or second embodiment.

[0133] like Figure 16As illustrated, the distance image sensor 300 according to this embodiment may include an optical system 302, a photoelectric conversion device 304, an image processing circuit 306, a monitor 308, and a memory 310. The distance image sensor 300 receives light (modulated light or pulsed light) emitted from the light source device 320 toward the subject 330 and reflected on the surface of the subject 330, and acquires a distance image corresponding to the distance to the subject 330.

[0134] The optical system 302 includes one or more lenses and has the function of forming an image of the image light (incident light) from the subject 330 on the light-receiving surface (sensor unit) of the photoelectric conversion device 304.

[0135] The photoelectric conversion device 304 is the photoelectric conversion device 100 described in the first embodiment or the second embodiment, and has the function of generating a distance signal for indicating the distance to the subject 330 based on the image light from the subject 330 and supplying the generated distance signal to the image processing circuit 306.

[0136] The image processing circuit 306 has the function of performing image processing for constructing a distance image based on the distance signal supplied from the photoelectric conversion device 304.

[0137] Monitor 308 has the function of displaying distance images (image data) obtained through image processing in image processing circuit 306. Memory 310 has the function of storing (recording) distance images (image data) obtained through image processing in image processing circuit 306.

[0138] As described above, according to this embodiment, by using a photoelectric conversion device according to the first embodiment or the second embodiment to configure the distance image sensor, a distance image sensor that can acquire a distance image including more accurate distance information can be realized in combination with the improvement of the characteristics of pixel 12. Fifth embodiment

[0139] Reference Figure 17 A description of an endoscopic surgical system according to a fifth embodiment. Figure 17 This is a schematic diagram illustrating an example configuration of an endoscopic surgical system according to this embodiment. In this embodiment, the endoscopic surgical system will be described as an example of applying a photoelectric detection system of the photoelectric conversion device 100 according to the first or second embodiment.

[0140] Figure 17 This example illustrates the state of an operator (surgeon) 460 performing surgery on a patient 472 on a bed 470 using an endoscopic surgical system 400.

[0141] like Figure 17As illustrated, the endoscopic surgery system 400 according to this embodiment may include an endoscope 410, surgical instruments 420, and a trolley 430 equipped with various devices for endoscopic surgery. A camera control unit (CCU) 432, a light source device 434, an input device 436, a processing tool control device 438, and a display device 440 may be mounted on the trolley 430.

[0142] Endoscope 410 includes a tube 412 inserted into the body cavity of patient 472 at a predetermined length from its tip, and a camera 414 connected to the base of the tube 412. Although Figure 17 An example is an endoscope 410 configured as a so-called rigid endoscope with a rigid endoscope tube 412, but the endoscope 410 can also be configured as a so-called flexible endoscope with a flexible endoscope tube. The endoscope 410 is held in a movable state by an arm 416.

[0143] The endoscope tube 412 has an opening at its front end, into which the objective lens is fitted. A light source device 434 is connected to the endoscope 410, and the light generated by the light source device 434 is guided to the front end of the endoscope tube 412 via a light guide extending inside the tube and then illuminated through the objective lens toward the object of observation within the patient's body cavity 472. Note that the endoscope 410 can be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0144] An optical system and a photoelectric conversion device (not shown) are provided inside the camera 414, and the reflected light (observation light) from the observed object is focused onto the photoelectric conversion device by the optical system. The photoelectric conversion device performs photoelectric conversion on the observation light and generates an electrical signal corresponding to the observation light (i.e., an image signal corresponding to the observed image). The photoelectric conversion device 100 described in the first embodiment or the second embodiment can be used as the photoelectric conversion device. The image signal is transmitted as RAW data to the CCU 432.

[0145] The CCU 432 can be configured with a central processing unit (CPU) or a graphics processing unit (GPU), and controls the operation of the endoscope 410 and the display device 440 as a whole. Furthermore, the CCU 432 receives image signals from the camera 414 and performs various types of image processing on the image signals, such as image processing (de-mosaicing), for displaying images based on those image signals.

[0146] The display device 440 displays an image based on the image signal processed by the CCU 432 under the control of the CCU 432.

[0147] The light source device 434 may be configured with a light source such as a light-emitting diode (LED) and supply illumination light to the endoscope 410 when photographing the surgical site, etc.

[0148] Input device 436 is an input interface for endoscopic surgery system 400. Users can input various information and commands into endoscopic surgery system 400 via input device 436.

[0149] The processing tool control device 438 controls the drive of the energy processing tool 450 used for tissue ablation, incision or blood vessel sealing, etc.

[0150] When imaging the surgical site, the light source device 434 supplying illumination light to the endoscope 410 can be configured, for example, a white light source composed of LEDs, a laser light source, or a combination thereof. When the white light source is configured as a combination of RGB laser light sources, the white balance of the captured image can be adjusted within the light source device 434 because the output intensity and timing of each color (each wavelength) can be controlled with high precision. Furthermore, in this case, images corresponding to each RGB can be captured in a time-division manner by using lasers from each RGB laser light source to illuminate the object under observation in a time-division manner and controlling the driving of the imaging element of the camera 414 in synchronization with the illumination timing. According to this method, a color image can be obtained without a color filter in the image sensor.

[0151] Furthermore, the drive of the light source device 434 can be controlled to change the intensity of the light to be output at predetermined times. By controlling the drive of the image sensor of the camera 414 in time-division multiplexing in sync with the timing of the changes in light intensity, and by synthesizing the image in a time-division multiplexing manner, an image with high dynamic range can be generated without so-called shadow loss and highlight clipping.

[0152] The light source device 434 can be configured to supply light of a predetermined wavelength corresponding to special light observation. In special light observation, for example, the wavelength dependence of light absorption in body tissue is utilized. Specifically, compared to the illumination light used in normal observation (i.e., white light), a predetermined tissue, such as blood vessels in the mucosal surface, is imaged with high contrast by irradiating a narrow band of light. Alternatively, in special light observation, fluorescence observation can be performed to obtain an image by irradiating fluorescence generated by excitation light. In fluorescence observation, body tissue is irradiated with excitation light to observe fluorescence from that body tissue, or a reagent such as indocyanine green (ICG) is locally injected into body tissue, and the body tissue is irradiated with excitation light corresponding to the fluorescence wavelength of that reagent to obtain a fluorescence image. The light source device 434 can be configured to supply narrow band light and / or excitation light corresponding to this special light observation.

[0153] As described above, according to this embodiment, by using a photoelectric conversion device according to the first embodiment or the second embodiment to configure the endoscopic surgery system, an endoscopic surgery system capable of acquiring higher quality images can be realized. Sixth Embodiment

[0154] Reference Figures 18A to 20 The photoelectric detection system and movable body according to the sixth embodiment are described. Figures 18A to 18C This is a schematic diagram illustrating an example configuration of a movable body according to this embodiment. Figure 19 This is a block diagram illustrating a schematic configuration of the photoelectric detection system according to this embodiment. Figure 20 This is a flowchart illustrating the operation of the photoelectric detection system according to this embodiment. In this embodiment, an application example of a vehicle-mounted camera will be described as applying the photoelectric detection system of the photoelectric conversion device 100 according to the first or second embodiment.

[0155] Figures 18A to 18C This is a schematic diagram illustrating an example configuration of a movable body (vehicle system) according to this embodiment. Figures 18A to 18C An example of a vehicle 500 (automobile) configuration is shown, which incorporates a photoelectric detection system using a photoelectric conversion device according to the first or second embodiment. Figure 18A This is a front view of vehicle 500. Figure 18B It is a two-dimensional schematic diagram of vehicle 500, and Figure 18C This is a schematic diagram of the rear of vehicle 500. Vehicle 500 includes a pair of photoelectric conversion devices 502 on its front side. Here, the photoelectric conversion device 502 is the photoelectric conversion device 100 described in the first or second embodiment. Vehicle 500 includes an integrated circuit 503, an alarm device 512, and a main control unit 513.

[0156] Figure 19 This is a block diagram illustrating an example configuration of a photoelectric detection system 501 installed on a vehicle 500. The photoelectric detection system 501 includes a photoelectric conversion device 502, an image preprocessing unit 515, an integrated circuit 503, and an optical system 514. The photoelectric conversion device 502 is the photoelectric conversion device 100 described in the first or second embodiment. The optical system 514 forms an optical image of a subject on the photoelectric conversion device 502. The photoelectric conversion device 502 converts the optical image of the subject formed by the optical system 514 into an electrical signal. The image preprocessing unit 515 performs predetermined signal processing on the signal output from the photoelectric conversion device 502. The function of the image preprocessing unit 515 can be incorporated into the photoelectric conversion device 502. At least two sets of optical systems 514, photoelectric conversion devices 502, and image preprocessing units 515 are provided in the photoelectric detection system 501, and the outputs from each set of image preprocessing units 515 are input to the integrated circuit 503.

[0157] Integrated circuit 503 is an integrated circuit used in camera system applications and includes an image processing unit 504, an optical ranging unit 506, a parallax calculation unit 507, an object recognition unit 508, and an anomaly detection unit 509. The image processing unit 504 processes the image signal output from the image preprocessing unit 515. For example, the image processing unit 504 performs image processing such as image processing and defect correction on the output signal of the image preprocessing unit 515. The image processing unit 504 includes a memory 505 for temporarily storing the image signal. The memory 505 may, for example, store the positions of known defective pixels in the photoelectric conversion device 502.

[0158] The optical ranging unit 506 focuses and measures the distance to the subject. The parallax calculation unit 507 calculates distance measurement information (distance information) based on multiple image data (parallax images) acquired by multiple photoelectric conversion devices 502. Each photoelectric conversion device 502 may be configured to acquire various information such as distance information. The object recognition unit 508 recognizes subjects such as vehicles, roads, signs, or people. When an anomaly is detected in the photoelectric conversion device 502, the anomaly detection unit 509 notifies the main control unit 513 of the anomaly.

[0159] The integrated circuit 503 can be implemented through specially designed hardware, through software modules, or through a combination of these. Furthermore, it can be implemented using field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs), or through a combination of these.

[0160] The main control unit 513 integrates the operation of the photoelectric detection system 501, vehicle sensor 510, and control unit 520. The vehicle 500 may not include the main control unit 513. In this case, the photoelectric conversion device 502, vehicle sensor 510, and control unit 520 transmit and receive control signals via a communication network. For example, the Controller Area Network (CAN) standard can be used for the transmission and reception of control signals.

[0161] Integrated circuit 503 has the function of receiving control signals from main control unit 513 or transmitting control signals or setting values ​​to photoelectric conversion device 502 through its own control unit.

[0162] The photoelectric detection system 501 is connected to the vehicle sensor 510 and can detect the vehicle's driving status (such as vehicle speed, yaw rate, and steering angle), the external environment, and the status of other vehicles and obstacles. The vehicle sensor 510 is also a distance information acquisition unit for acquiring distance information of the subject. Furthermore, the photoelectric detection system 501 is connected to a driver support control unit 511 for performing various driver support functions such as automatic steering, automatic driving, and collision avoidance. Specifically, regarding the collision detection function, the driver support control unit 511 estimates a collision with other vehicles or obstacles and determines whether a collision with other vehicles or obstacles exists based on the detection results of the photoelectric detection system 501 and the vehicle sensor 510. Therefore, avoidance control is performed when a collision is estimated, and safety devices are activated upon collision.

[0163] The photoelectric detection system 501 is also connected to an alarm device 512 for issuing warnings to the driver based on the judgment result of the collision judgment unit. For example, when the collision judgment unit determines that a collision is highly likely, the main control unit 513 performs vehicle control to avoid a collision and reduce damage by applying the brakes, returning the accelerator to its original position, or suppressing engine output. The alarm device 512 alerts the user by emitting warnings such as sounds, displaying warning information on a screen such as a car navigation system or dashboard, or vibrating the seat belt or steering wheel.

[0164] In this embodiment, the photoelectric detection system 501 captures images of the vehicle's surrounding environment (e.g., in front or behind). Figure 18B An example of the arrangement of the photoelectric detection system 501 in the case where the photoelectric detection system 501 captures an image of the front of the vehicle.

[0165] As described above, the photoelectric conversion device 502 is arranged in front of the vehicle 500. Specifically, preferably, the center line relative to the forward / reverse direction or external shape (e.g., vehicle width) of the vehicle 500 is considered as the axis of symmetry, and the two photoelectric conversion devices 502 are arranged symmetrically with respect to this axis of symmetry to obtain distance information between the vehicle 500 and the subject to be photographed and to determine the possibility of a collision. Furthermore, the photoelectric conversion device 502 is preferably arranged so as not to interfere with the driver's field of vision when the driver visually identifies the situation outside the vehicle 500 from the driver's seat. The alarm device 512 is preferably arranged to be easily accessible to the driver.

[0166] Next, we will refer to Figure 20 This describes the fault detection operation of the photoelectric conversion device 502 in the photoelectric detection system 501. The fault detection operation of the photoelectric conversion device 502 can be based on... Figure 20 The illustrated steps S110 to S180 are performed.

[0167] Step S110 is the step of setting up the photoelectric conversion device 502 when it is started. That is, the settings for the operation of the photoelectric conversion device 502 are transmitted from outside the photoelectric detection system 501 (e.g., the main control unit 513) or inside the photoelectric detection system 501, and the camera operation and fault detection operation of the photoelectric conversion device 502 are started.

[0168] Next, in step S120, a pixel signal is acquired from the valid pixel. In step S130, an output value from the fault detection pixel set for fault detection is acquired. The fault detection pixel may include a photoelectric conversion element in the same manner as the valid pixel. A predetermined voltage is written into the photoelectric conversion element of the fault detection pixel. The fault detection pixel outputs a signal corresponding to the voltage written into the photoelectric conversion element. Note that steps S120 and S130 can be reversed.

[0169] Next, in step S140, the expected output value of the fault detection pixel and the actual output value from the fault detection pixel are classified. As a result of the classification in step S140, if the expected output value matches the actual output value, the process proceeds to step S150, determining that the camera operation is proceeding normally, and the process proceeds to step S160. In step S160, the pixel signal of the scan line is transmitted to memory 505 and temporarily stored. Afterwards, the process returns to step S120 to continue the fault detection operation. On the other hand, as a result of the classification in step S140, if the expected output value does not match the actual output value, the process proceeds to step S170. In step S170, it is determined that an abnormality exists in the camera operation, and an alarm is notified to the main control unit 513 or the alarm device 512. The alarm device 512 causes the display unit to display that an abnormality has been detected. Afterwards, in step S180, the photoelectric conversion device 502 is stopped, and the operation of the photoelectric detection system 501 ends.

[0170] Furthermore, while this embodiment describes an example for each line of a loop flowchart, fault detection operations can be performed on individual multi-line loop flowcharts or on individual frames. The alarm from step S170 can be notified to the outside of the vehicle via a wireless network.

[0171] Furthermore, while this embodiment describes control to prevent the vehicle from colliding with other vehicles, it is also applicable to control of the vehicle following other vehicles and performing autonomous driving, as well as control of the vehicle performing autonomous driving without veering out of its lane. Moreover, the photoelectric detection system 501 is not limited to vehicles such as the vehicle itself, but can be applied to other mobile bodies (mobile devices) such as ships, aircraft, or industrial robots. Furthermore, this disclosure is not limited to mobile bodies, but can be widely applied to devices using object recognition, such as intelligent transportation systems (ITS). Seventh Embodiment

[0172] Reference Figure 21A and Figure 21B A photoelectric detection system according to the seventh embodiment is described. Figure 21A and Figure 21B This is a schematic diagram illustrating a configuration example of the photoelectric detection system according to this embodiment. In this embodiment, an application example of glasses (smart glasses) will be described as applying a photoelectric detection system using the photoelectric conversion device 100 according to the first or second embodiment.

[0173] Figure 21A An example of glasses 600 (smart glasses) according to an application example is shown. Glasses 600 includes lenses 601, photoelectric conversion device 602, and control device 603.

[0174] The photoelectric conversion device 602 is the same as the photoelectric conversion device 100 described in the first or second embodiment, and is disposed on the lens 601. One photoelectric conversion device 602 may be disposed, or multiple photoelectric conversion devices may be disposed. When multiple photoelectric conversion devices 602 are used, a combination of multiple types of photoelectric conversion devices 602 may be used. The arrangement position of the photoelectric conversion device 602 is not limited to... Figure 21A A display device (not shown) including a light-emitting device such as an organic light-emitting diode (OLED) or an LED can be disposed on the back side of the lens 601.

[0175] The control device 603 functions as a power source supplying power to the photoelectric conversion device 602 and the display device. The control device 603 has the function of controlling the operation of the photoelectric conversion device 602 and the display device. The lens 601 may be equipped with an optical system for concentrating light onto the photoelectric conversion device 602.

[0176] Figure 21B An example of another application is shown: glasses 610 (smart glasses). Glasses 610 includes lenses 611 and a control device 612. A photoelectric conversion device (not shown) corresponding to photoelectric conversion device 602 and a display device may be mounted on the control device 612.

[0177] The lens 611 is equipped with a photoelectric conversion device in the control device 612 and an optical system for projecting light from the display device, and projects an image onto it. The control device 612 functions as a power source for supplying power to the photoelectric conversion device and the display device, and has the function of controlling the operation of the photoelectric conversion device and the display device.

[0178] The control device 612 may include a gaze detection unit for detecting the wearer's gaze. In this case, an infrared light emitting unit may be provided in the control device 612, and the infrared light emitted from the infrared light emitting unit can be used to detect the gaze. Specifically, the infrared light emitting unit emits infrared light toward the eyes of the user viewing the displayed image. An image of the eye is obtained by detecting the reflected light from the eye using a camera unit with a light-receiving element. By providing a light reduction unit in the planar view for reducing the light from the infrared light emitting unit to the display unit, image quality degradation can be reduced.

[0179] A user's gaze toward a displayed image can be detected from an image of the eye obtained by capturing infrared light. Any known technique can be applied to gaze detection using an image of the eye. As an example, a gaze detection method based on the Purkinje image caused by the reflection of incident light on the cornea can be used. More specifically, gaze detection processing based on the pupil-corneal reflection method can be performed. Using the pupil-corneal reflection method, the user's gaze can be detected by calculating a gaze vector representing the orientation (rotation angle) of the eye, based on the pupil image and the Purkinje image included in the image of the eye.

[0180] The display device according to this embodiment may include a photoelectric conversion device with a light-receiving element, and may be configured to control the display image based on the user's gaze information from the photoelectric conversion device. Specifically, the display device determines a first viewing area and a second viewing area other than the first viewing area based on the gaze information. The first and second viewing areas may be determined by a control device of the display device, or by an external control device. When the external control device makes a determination, the determination result may be transmitted to the display device via communication. In the display area of ​​the display device, the display resolution of the first viewing area may be controlled to be higher than the display resolution of the second viewing area. That is, the resolution of the second viewing area may be lower than the resolution of the first viewing area.

[0181] The display area may include a first display area and a second display area different from the first display area, and a high-priority area can be determined from the first and second display areas based on gaze information. The first and second display areas can be determined by the control device of the display device, or by an external control device. When the external control device makes a determination, the determination result can be transmitted to the display device via communication. The resolution of the high-priority area can be controlled to be higher than the resolution of other areas. That is, the resolution of areas with relatively low priority can be reduced.

[0182] Note that artificial intelligence (AI) can be used to determine the primary viewing area or areas with high priority. AI can be a model configured to use images of the eye and the actual direction of the eye viewing the image as teacher data to estimate the angle of the gaze and the distance to a target object in front of the gaze from the image of the eye. The AI ​​program can be included in a display device, a photoelectric conversion device, or an external device. When the external device has a program, information can be transmitted to the display device via communication.

[0183] In the case of display control based on visual recognition detection, this disclosure can be preferably applied to smart glasses that also include a photoelectric conversion device for capturing external images. The smart glasses can display the captured external information in real time. Eighth embodiment

[0184] Reference Figure 22 Describe the device according to the eighth embodiment. Figure 22 This is a block diagram illustrating a schematic configuration of the device according to this embodiment.

[0185] Figure 22 This is a schematic diagram illustrating a device EQP including a photoelectric conversion device APR. The photoelectric conversion device APR has the functionality of a photoelectric conversion device 100 according to a first or second embodiment. All or part of the photoelectric conversion device APR is a semiconductor device IC. The photoelectric conversion device APR of this example can be used as, for example, an image sensor, an autofocus (AF) sensor, a light metering sensor, or a distance measurement sensor. The semiconductor device IC includes a pixel region PX, wherein pixel circuits PXC, each including a photoelectric conversion unit, are arranged in a matrix. The semiconductor device IC may include a peripheral region PR surrounding the pixel region PX. Circuitry other than the pixel circuitry may be arranged in the peripheral region PR.

[0186] The photoelectric conversion device APR can have a structure in which a first semiconductor chip having multiple photoelectric conversion units is stacked and a second semiconductor chip having peripheral circuits is stacked (a chip stack structure). Each peripheral circuit in the second semiconductor chip can be a column circuit corresponding to a pixel column of the first semiconductor chip. The peripheral circuits in the second semiconductor chip can also be matrix circuits corresponding to pixels or pixel blocks in the first semiconductor chip. The connection between the first and second semiconductor chips can be achieved using through-silicon vias (TSVs), inter-chip wiring via direct bonding through a conductor such as copper, connections via microbumps between chips, or connections via wire bonding, etc.

[0187] In addition to a semiconductor device IC, an APR (Agent Photovoltaic Power Regulator) may also include a package PKG (Package Box Governing Body) that houses the semiconductor device IC. The package PKG may include a substrate on which the semiconductor device IC is fixed, a cover such as glass facing the semiconductor device IC, and connecting members such as bonding wires or bumps for connecting terminals provided on the substrate to terminals provided on the semiconductor device IC.

[0188] The device EQP may also include at least one of an optical device OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a storage device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric conversion device APR, which is a photoelectric conversion device, and is, for example, a lens, shutter, or mirror. The control device CTRL controls the photoelectric conversion device APR and is, for example, a semiconductor device such as an ASIC. The processing device PRCS processes the signal output from the photoelectric conversion device APR and constitutes an analog front-end (AFE) or a digital front-end (DFE). The processing unit PRCS is a semiconductor device such as a CPU or an ASIC. The display device DSPL may be an EL display device or a liquid crystal display device that displays information (images) obtained by the photoelectric conversion device APR. The storage device MMRY may be a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion device APR. The storage device MMRY may be a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive. The mechanical device MCHN may include a movable part or a propulsion part such as a motor or engine. In the device EQP, the signal output from the photoelectric conversion device APR is displayed on the display device DSPL or transmitted to the outside via a communication device (not shown) included in the device EQP. Therefore, preferably, the device EQP also includes a storage device MMRY and a processing device PRCS, separate from the storage circuit unit and the arithmetic circuit unit included in the photoelectric conversion device APR.

[0189] Figure 22The illustrated device EQP can be an electronic device such as an information terminal with shooting capabilities (e.g., a smartphone or wearable device) or a camera (e.g., an interchangeable lens camera, a compact camera, a camcorder, and a surveillance camera). The mechanical device MCHN in the camera can drive components of the optical device OPT for zooming, focusing, and shutter operation. The device EQP can be a transportation device (mobile body) such as a vehicle, ship, or aircraft. The device EQP can be a medical device such as an endoscope or a CT scanner.

[0190] The mechanical device MCHN in the transport device can be used as a mobile device. The equipment EQP as a transport device is suitable for transporting the photoelectric conversion device APR, or suitable for assisted and / or automated operation (manipulation) utilizing camera functions. The processing device PRCS for assisted and / or automated operation (manipulation) can perform processing for operating the mechanical device MCHN as a mobile device based on information obtained from the photoelectric conversion device APR.

[0191] The photoelectric conversion device APR according to this embodiment can provide high value to its designers, manufacturers, distributors, purchasers, and / or users. Therefore, when the photoelectric conversion device APR is installed on the device EQP, the value of the device EQP can also increase. Therefore, when manufacturing and selling the device EQP, it is advantageous to install the photoelectric conversion device APR of this embodiment on the device EQP to increase the value of the device EQP. Modified embodiments

[0192] This disclosure is not limited to the above embodiments, and various modifications can be made.

[0193] For example, examples of adding a portion of the configuration of any embodiment to another embodiment or replacing a portion of the configuration of any embodiment with a portion of the configuration of another embodiment are also embodiments of this disclosure.

[0194] Furthermore, the circuit configuration of pixel 12 is not limited to the embodiments described above. For example, a switch, such as a transistor, can be provided between the photoelectric conversion element 22 and the quenching element 32, or between the photoelectric conversion element 22 and the signal processing unit 30, to control the electrical connection state between them. Additionally, a switch, such as a transistor, can be provided between a node supplied with voltage VH and the quenching element 32, and / or between a node supplied with voltage VL and the photoelectric conversion element 22, to control the electrical connection state between them. Multiple photoelectric conversion elements 22 can be provided for one pixel 12.

[0195] Furthermore, in the circuit configuration of pixel 12 in the above embodiment, signal charge (electrons) is extracted from the cathode side using the anode side of the APD as a fixed potential, but signal charge (holes) can be extracted from the anode side using the cathode side of the APD as a fixed potential. In this case, the conductivity type of the semiconductor regions described in the above embodiment can be reversed.

[0196] Furthermore, while the above embodiments have described an application example of a so-called back-illuminated photoelectric conversion device, the above embodiments can also be applied to a so-called front-illuminated photoelectric conversion device. The front-illuminated photoelectric conversion device is configured to perform photoelectric conversion on light incident from the first surface 122 side of the semiconductor layer 120 in the semiconductor region 140, but the structure of the photoelectric conversion element 22 can be the same as that in the above embodiments.

[0197] Furthermore, in the above embodiments, a counter circuit has been described as being used as the processing circuit 36; however, a time-to-digital converter (TDC) and a memory can be used instead of the counter circuit. In this case, the generation timing of the pulse signal output from the waveform shaping circuit 34 is converted into a digital signal by the TDC. When measuring the timing of the pulse signal, a control pulse pREF (reference signal) is supplied to the TDC from the vertical scan circuit unit 40 via control line 14. The TDC acquires the input timing of the signal output from each pixel 12 as a digital signal based on the relative time of the control pulse pREF.

[0198] According to this disclosure, noise caused by carriers generated from carrier generation levels in a photoelectric conversion element can be reduced.

[0199] While this disclosure has been described with reference to embodiments, it should be understood that this disclosure is not limited to the disclosed embodiments. The scope of the appended claims should be given the broadest interpretation to cover all such modifications and equivalent structures and functions.

Claims

1. A photoelectric conversion element disposed in a semiconductor layer having a first surface and a second surface opposite to the first surface, the photoelectric conversion element comprising: A first semiconductor region of a first conductivity type is arranged to extend to a first depth relative to the first surface; A second semiconductor region of a second conductivity type is arranged to surround the first semiconductor region in a plan view and has a peak of impurity concentration at a second depth between the first surface and the first depth; as well as The third semiconductor region of the second conductivity type is arranged closer to the second surface than the first semiconductor region, and together with the first semiconductor region, forms an avalanche photodiode. Wherein, the boundary surface of the second semiconductor region on the second surface side is located closer to the first surface than the first depth to the first surface.

2. The photoelectric conversion element according to claim 1, wherein, The boundary surface of the second semiconductor region on the first surface side is located on a deeper side than the first surface.

3. The photoelectric conversion element according to claim 1, wherein, The width of the first semiconductor region at the depth where the second semiconductor region is located is less than the maximum width of the first semiconductor region in the plan view.

4. The photoelectric conversion element according to claim 1, wherein, The first semiconductor region includes: The fourth semiconductor region of the first conductivity type is arranged to contact the first surface and has a peak of impurity concentration on the first surface side compared to the second depth. The fifth semiconductor region of the first conductivity type has a peak of impurity concentration at a depth between the second depth and the first depth, and is in contact with the fourth semiconductor region at a depth where the second semiconductor region is disposed.

5. The photoelectric conversion element according to any one of claims 1 to 4, wherein, In the region overlapping with the second semiconductor region in the plan view, the impurity concentration of the second semiconductor region on the first face side compared to the second depth is equal to or less than half of the impurity concentration of the second semiconductor region at the second depth.

6. The photoelectric conversion element according to any one of claims 1 to 4, further comprising: The sixth semiconductor region of the first conductivity type is arranged in the region overlapping with the second semiconductor region in the plan view at a depth closer to the first surface than the second semiconductor region to the first surface.

7. The photoelectric conversion element according to claim 6, wherein, The maximum impurity concentration in the sixth semiconductor region is lower than the maximum impurity concentration in the first semiconductor region.

8. The photoelectric conversion element according to any one of claims 1 to 4, wherein, In the plan view, the impurity concentration of the second semiconductor region at the first depth in the region overlapping with the second semiconductor region is equal to or less than half of the impurity concentration of the second semiconductor region at the second depth.

9. The photoelectric conversion element according to any one of claims 1 to 4, further comprising: The seventh semiconductor region of the first conductivity type is arranged in a region that overlaps with the second semiconductor region in the plan view, and has a peak of impurity concentration at a depth between the second semiconductor region and the first depth.

10. The photoelectric conversion element according to claim 9, wherein, The maximum impurity concentration in the seventh semiconductor region is lower than the maximum impurity concentration in the first semiconductor region.

11. The photoelectric conversion element according to any one of claims 1 to 4, wherein, The impurity concentration in the second semiconductor region at the second depth is lower than the impurity concentration in the first semiconductor region at the second depth.

12. The photoelectric conversion element according to claim 11, wherein, The second conductivity type impurity constituting the second semiconductor region is doped in the region that overlaps with the first semiconductor region in the plan view.

13. The photoelectric conversion element according to any one of claims 1 to 4, further comprising: The eighth semiconductor region is arranged to be closer to the second surface than the third semiconductor region. The avalanche photodiode is configured to multiply the signal charge generated in the eighth semiconductor region.

14. The photoelectric conversion element according to any one of claims 1 to 4, wherein, The periphery of the first semiconductor region is depleted during the operation of the avalanche photodiode.

15. The photoelectric conversion element according to any one of claims 1 to 4, further comprising: The ninth semiconductor region of the second conductivity type is arranged to surround the region in the plan view where the first semiconductor region, the second semiconductor region and the third semiconductor region are arranged, and is connected to the third semiconductor region at the periphery of the third semiconductor region in the plan view; as well as The tenth semiconductor region of the second conductivity type is configured to contact the second surface, thereby overlapping the first semiconductor region, the second semiconductor region and the third semiconductor region in a plan view, and connected to the ninth semiconductor region.

16. The photoelectric conversion element according to claim 15, further comprising: A first electrode is connected to the first semiconductor region; as well as The second electrode is connected to the ninth semiconductor region.

17. The photoelectric conversion element according to claim 1, wherein, The second semiconductor region is formed by ion implantation.

18. A photoelectric conversion device, comprising: Multiple pixels, arranged to form multiple rows and multiple columns, Each of the plurality of pixels includes: a photoelectric conversion element according to any one of claims 1 to 17; and a signal processing circuit configured to process a signal output from the photoelectric conversion element.

19. The photoelectric conversion device according to claim 18, further comprising: The first substrate includes a semiconductor layer on which photoelectric conversion elements of each of the plurality of pixels are disposed; as well as The second substrate is provided with signal processing circuits for each of the plurality of pixels.

20. An apparatus including a photoelectric conversion device, in, The photoelectric conversion device is the photoelectric conversion device according to claim 18 or 19. The device also includes at least one of the following: Optical devices corresponding to the aforementioned photoelectric conversion device. A control device configured to control the photoelectric conversion device. A processing device configured to process the signal output from the photoelectric conversion device. A mechanical device, which is controlled based on the information obtained from the photoelectric conversion device. A display device configured to display information obtained by the photoelectric conversion device, and A storage device configured to store information obtained by the photoelectric conversion device.

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