Patterned substrate and method of making same, epitaxial wafer and LED chip

Abstract

This application provides a patterned substrate and its fabrication method, an epitaxial wafer, and an LED chip. The patterned substrate includes patterned areas and unpatterned areas. The patterned areas include multiple microstructures, and unpatterned areas are spaced apart from adjacent patterned areas, with each unpatterned area having a certain width. The unpatterned areas act as a separator between the patterned areas, allowing for a relatively clear distinction between them. The patterned substrate does not have any abnormal splicing patterns caused by closely adjacent exposed areas. In applications where a semiconductor epitaxial layer is fabricated on the patterned substrate, and then the epitaxial layer is etched to fabricate LED pixels, the unpatterned areas can be avoided. This ensures that all LED pixels in the LED chip are fabricated within the patterned areas, resulting in essentially uniform luminous performance among the LED pixels. This improves the uneven luminous performance of the LED chip and enhances wavelength uniformity.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a patterned substrate and its fabrication method, an epitaxial wafer, and an LED chip. Background Technology

[0002] Patterned sapphire substrate (PSS) is a key material used in the fabrication of high-brightness light-emitting diodes (LEDs). Compared to traditional planar sapphire substrates, PSS has a microstructured pattern on its surface. PSS plays a crucial role in improving the performance of LED devices. It can reduce gallium nitride (GaN) epitaxial defects, improve external and internal quantum efficiency, and the microstructure of PSS can disrupt the total internal reflection angle, thereby improving external quantum efficiency and light extraction capability. However, LED chips currently fabricated on PSS suffer from uneven light emission. Summary of the Invention

[0003] To address the problems existing in the prior art, embodiments of this application provide a patterned substrate and its fabrication method, an epitaxial wafer, and an LED chip, improving the structure of the patterned substrate to enhance the luminous uniformity of the fabricated LED chip.

[0004] Firstly, embodiments of this application provide a patterned substrate, which includes patterned areas and unpatterned areas, with unpatterned areas spaced apart from adjacent patterned areas. Each patterned area includes multiple microstructures, each with a diameter of d1. The width of the unpatterned area between two adjacent patterned areas is d2, where d2 ≥ 2 * d1. In the patterned substrate provided by this application, unpatterned areas are spaced apart from adjacent patterned areas, and these unpatterned areas have a certain width, allowing for a relatively clear distinction between the patterned and unpatterned areas. The unpatterned areas act as a separating structure between the patterned areas, eliminating abnormal splicing patterns caused by closely adjacent exposed areas on the patterned substrate. In applications where a semiconductor epitaxial layer is fabricated on the patterned substrate, and then the epitaxial layer is etched to fabricate LED pixels, the unpatterned areas can be avoided. This ensures that all LED pixels in the LED chip are fabricated within the patterned areas, resulting in essentially uniform luminous performance among the LED pixels. This improves the uneven luminous performance of the LED chip and enhances wavelength uniformity.

[0005] In some implementations, d2 ≤ 5*d1. In this application, an epitaxial layer is fabricated on a patterned substrate, then etched and diced to obtain multiple LED chips. In this application, the width of the unpatterned region is set within a certain range to meet the requirement of forming dicing channels at the unpatterned region location, ensuring the LED chip dicing yield. Furthermore, the width of the unpatterned region is not set too large, ensuring full utilization of the entire patterned substrate area and avoiding wasted space and increased manufacturing costs.

[0006] In some implementations, the unpatterned area has multiple alignment marks. These alignment marks can serve as zero-point alignment points for subsequent semiconductor processes on the patterned substrate, enabling LED pixels to be fabricated within the patterned area and preventing the LED chip from crossing the unpatterned area. This ensures that the luminous performance of each LED pixel in the LED chip is essentially uniform, improving the defect of uneven light emission in LED chips.

[0007] In some embodiments, the unpatterned area includes a first area and a second area extending in different directions, the first and second areas intersecting to define multiple patterned areas; at least some alignment marks are located at the intersection of the first and second areas. This location provides relatively large space, allowing for more flexible design of the alignment marks' shapes. Furthermore, the apex of the patterned area is located at the intersection of the first and second areas; placing the alignment marks at this location allows for relatively simple and accurate positioning of the patterned area.

[0008] In some embodiments, the patterned substrate includes a first surface having a plurality of microstructures; the height of the first surface in the unpatterned region is the same as the height of the microstructures.

[0009] In some embodiments, the patterned substrate includes a first surface having a plurality of microstructures and grooves between adjacent microstructures; the height of the first surface in the unpatterned region is level with the bottom of the groove.

[0010] Based on the same inventive concept, embodiments of this application also provide a method for fabricating a patterned substrate, the method comprising:

[0011] Photoresist is coated on a substrate, and multiple exposure areas on the substrate are exposed using a step-step exposure process, with a certain distance between adjacent exposure areas. After etching and development, multiple microstructures are formed in the exposure areas, which are patterned areas, and unpatterned areas are formed between the patterned areas. The diameter of the microstructure is d1, and the width of the unpatterned area between two adjacent patterned areas is d2, where d2 ≥ 2 * d1. In this embodiment, a certain distance is set between adjacent exposure areas, and the step size is adjusted in the step-step exposure process so that the step size is greater than the width of the exposure area in the step direction to meet the exposure process requirements. This produces a patterned substrate including patterned and unpatterned areas, which avoids splicing defects between adjacent exposure areas. In application, this avoids affecting the brightness uniformity of the LED chip array formed on the patterned substrate and can improve wavelength uniformity.

[0012] Furthermore, the fabrication method also includes: using an etching process to create multiple alignment marks in the unpatterned area. The fabrication method provided by this embodiment can form alignment marks on a patterned substrate. In application, these alignment marks can serve as zero-point alignment points for subsequent semiconductor processes on the patterned substrate, enabling LED pixels to be fabricated in the patterned area and preventing LED chips from crossing the unpatterned area.

[0013] Based on the same inventive concept, embodiments of this application also provide an epitaxial wafer, including the patterned substrate provided in any embodiment of this application.

[0014] Based on the same inventive concept, this application also provides an LED chip, which includes a patterned substrate and an epitaxial layer located on one side of the patterned substrate. The patterned substrate includes a patterned region and a plateau region. The patterned region includes multiple microstructures, and the patterned region and the epitaxial layer are opposite to each other. The portion of the patterned substrate from which the epitaxial layer extends is the plateau region. The LED chip provided by this application can have good brightness uniformity. In applications, the plateau region of the LED chip can be easily used to fabricate encapsulation dams. When individual LED chips need to be assembled for use in an application scenario, the encapsulation dams can also prevent optical crosstalk between adjacent LED chips.

[0015] In some implementations, the diameter of the microstructure is d1, and the width of the platform region is d3, where d3 < 5 * d1.

[0016] In some embodiments, the patterned substrate includes a first surface having a plurality of microstructures; the height of the first surface within the platform region is level with the height of the microstructures.

[0017] In some embodiments, the patterned substrate includes a first surface having a plurality of microstructures and grooves between adjacent microstructures; the height of the first surface within the platform region is level with the bottom of the groove. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A flowchart of the PSS manufacturing process in related technologies;

[0020] Figure 2 A schematic diagram of fabricating a micro-LED array chip on a PSS;

[0021] Figure 3 A schematic diagram of a patterned substrate provided in an embodiment of this application;

[0022] Figure 4 for Figure 3 A schematic diagram of a cross-section at the position of the tangent AA′;

[0023] Figure 5 for Figure 3 Another cross-sectional view at the location of the tangent AA′;

[0024] Figure 6 This is a schematic diagram of another patterned substrate provided in an embodiment of this application;

[0025] Figure 7 for Figure 6 Enlarged view of a specific location in the middle;

[0026] Figure 8 This is a schematic diagram of another patterned substrate provided in an embodiment of this application;

[0027] Figure 9 A flowchart illustrating a method for fabricating a patterned substrate, as provided in an embodiment of this application;

[0028] Figure 10 A flowchart illustrating another method for fabricating a patterned substrate provided in an embodiment of this application;

[0029] Figure 11 A schematic diagram of an epitaxial wafer provided in an embodiment of this application;

[0030] Figure 12 A schematic diagram of an LED chip manufacturing process;

[0031] Figure 13 A schematic diagram of an LED chip provided in an embodiment of this application;

[0032] Figure 14This is a schematic diagram of another LED chip provided in an embodiment of this application;

[0033] Figure 15 This is a schematic diagram of an LED package according to an embodiment of this application;

[0034] Figure 16 This is a schematic diagram of an LED package according to an embodiment of this application. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0037] Figure 1 This is a flowchart of the PSS manufacturing process in related technologies. Figure 2 This is a schematic diagram of fabricating a micro-LED array chip on a PSS.

[0038] PSS is a substrate with a surface microstructure formed by patterning and etching a sapphire substrate. For example... Figure 1 As shown, firstly, photoresist 01 is coated on substrate 00. The photoresist 01 is then exposed and developed to obtain a developed pattern. Next, substrate 00 is etched to obtain a pattern of microstructures 02. After removing the photoresist 01, a patterned substrate 000 with multiple microstructures 02 is obtained. In the exposure process, multiple closely adjacent exposure areas need to be defined on substrate 00, and then a step-by-step process is used to expose each exposure area individually. Figure 1 The illustration shows the etching of substrate 00 using ICP etching. Because the exposed areas are closely adjacent, the photoresist 01 at the boundary between two adjacent exposed areas undergoes a slight volume change during exposure. This results in a splicing defect at the seam between the two exposed areas, causing a slight deviation in the pattern obtained in subsequent etching processes. In other words, the final PSS exhibits a certain difference in pattern between the exposed areas and at the seam between the two exposed areas.

[0039] Figure 2The exposed areas 03 on the patterned substrate 000 are illustrated by intersecting dashed lines. This simplified representation shows that multiple micro-LED chips 04 are fabricated on the patterned substrate 000. Each micro-LED chip 04 includes multiple LED pixels arranged in an array, with each LED pixel serving as a light-emitting unit. When fabricating micro-LED chips 04 on the patterned substrate 000, the splicing positions of adjacent exposed areas 03 cannot be easily identified during the process. Therefore, it is impossible to fabricate chips based on the positions of the exposed areas 03, resulting in micro-LED chips 04 crossing splicing areas. When micro-LED chips 04 cross splicing areas, due to pattern defects at the seams, the LED light-emitting units fabricated above the splicing area differ from the LED pixels fabricated at other locations. The LED pixels fabricated above the splicing area exhibit color purity deviations when lit, leading to abnormally emitting LED pixels in the micro-LED chips 04 that cross the splicing areas, resulting in uneven light emission across the entire chip.

[0040] To address the problems existing in related technologies, this application provides a patterned substrate and its fabrication method, an epitaxial wafer, and an LED chip. During fabrication, the exposure areas on the substrate are designed not to be adjacent. In the exposure process, the step size of the stepping process is adjusted to maintain a certain distance between adjacent exposure areas, thereby obtaining a patterned substrate including patterned and unpatterned areas. The unpatterned areas lack microstructures, making it easy to distinguish between the patterned and unpatterned areas. A semiconductor epitaxial layer is fabricated on the patterned substrate to form an epitaxial wafer. When etching the epitaxial wafer to form the LED chip, the unpatterned areas are avoided, ensuring that the luminous performance of each LED pixel in the LED chip is essentially uniform, thus improving the defect of uneven light emission in LED chips. The LED chip provided in this application can be applied to pixelated micro-LED automotive lights, pixelated micro-LED displays, pixelated micro-LED lighting devices, etc.

[0041] Figure 3 This is a schematic diagram of a patterned substrate provided in an embodiment of this application. Figure 4 for Figure 3 A schematic diagram of a cross-section at the location of the midtangent AA′. (Combined with...) Figure 3 and Figure 4 The patterned substrate 10 includes patterned regions 11 and unpatterned regions 12, with unpatterned regions 12 spaced apart from adjacent patterned regions 11. The intersecting unpatterned regions 12 define multiple patterned regions 11. Each patterned region 11 includes multiple microstructures 111, with a diameter of d1 for each microstructure 111. The width of the unpatterned region 12 between two adjacent patterned regions 11 is d2, where d2 ≥ 2 * d1. Figure 4In the schematic diagram, patterned areas 11 are arranged in an array, and unpatterned areas 12 extending horizontally and vertically intersect to define multiple patterned areas 11. The multiple patterned areas 11 in the array are arranged along a first direction x and a second direction y, with the first direction x and the second direction y intersecting. The width of the unpatterned area 12 between two adjacent patterned areas 11 is understood as follows: for two adjacent patterned areas 11 in the first direction x, the width d2 of the unpatterned area 12 between them is the width of the unpatterned area 12 in the first direction x; for two adjacent patterned areas 11 in the second direction y, the width d2 of the unpatterned area 12 between them is the width of the unpatterned area 12 in the second direction y. This application does not limit the shape of the microstructure 111; the microstructure 111 can be a pointed cone, a dot, a circle, a column, a polygonal prism, etc. Figure 4 As shown, the pattern area 11 also includes grooves 112 located between microstructures 111, and multiple microstructures 111 are arranged periodically within the pattern area 11.

[0042] The patterned substrate 10 provided in this embodiment includes patterned areas 11 and unpatterned areas 12. Adjacent patterned areas 11 are separated by unpatterned areas 12, and the unpatterned areas 12 are provided with a certain width, allowing for a relatively clear distinction between the patterned areas 11 and the unpatterned areas 12. The unpatterned areas 12 act as a separating structure between the patterned areas 11, eliminating abnormal splicing areas caused by closely adjacent exposed areas on the patterned substrate 10. In applications where a semiconductor epitaxial layer is fabricated on the patterned substrate 10, and then the epitaxial layer is etched to fabricate LED pixels, the unpatterned areas 12 can be avoided. This ensures that all LED pixels in the LED chip are fabricated in the patterned areas 11, resulting in essentially uniform luminous performance among the LED pixels. This improves the uneven luminous performance of the LED chip and enhances wavelength uniformity.

[0043] In some embodiments, 2*d1≤d2≤5*d1. In this application, an epitaxial layer is fabricated on a patterned substrate 10, then etched and diced to obtain multiple LED chips. In this application, the width of the unpatterned region 12 is set within a certain range to meet the requirement of forming dicing channels at the location of the unpatterned region 12, ensuring the LED chip dicing yield. Furthermore, the width of the unpatterned region 12 is not set too large, ensuring full utilization of the entire patterned substrate 10 area and avoiding wasted space and increased manufacturing costs.

[0044] like Figure 4 As shown, the patterned substrate 10 includes a first surface M1, which has multiple microstructures 111. That is, the first surface M1 is the side of the patterned substrate 10 with the microstructures 111. Within the unpatterned region 12, the height of the first surface M1 is substantially the same as the height of the microstructures 111, or their heights are approximately identical or differ only slightly. Figure 4 In this embodiment, the substrate structure in the unpatterned region 12 is not etched, the boundary between the unpatterned region 12 and the patterned region 11 is defined by the edge of the groove 112 in the patterned region 11, and the width d2 of the unpatterned region 12 is calculated by the distance between the edges of the two grooves 112 on its left and right sides.

[0045] In other implementations, Figure 5 for Figure 3 Another cross-sectional diagram at the location of the tangent AA′. (See diagram below.) Figure 5 As shown, the patterned substrate 10 includes a first surface M1, which has a plurality of microstructures 111. Grooves 112 are formed between adjacent microstructures 111; the height of the first surface M1 within the unpatterned region 12 is flush with the bottom of the groove 112. Figure 5 In this embodiment, the substrate structure in the unpatterned region 12 is thinned after etching. The boundary between the unpatterned region 12 and the patterned region 11 is defined by the edge of the microstructure 111 in the patterned region 11. The width d2 of the unpatterned region 12 is calculated by the distance between the edges of the two microstructures 111 on its left and right sides.

[0046] Figure 4 and Figure 5 The height of the unpatterned area 12 differs in the embodiments, and the photoresist used in their fabrication is different.

[0047] In some implementations... Figure 6 This is another schematic diagram of a patterned substrate provided in an embodiment of this application, such as... Figure 6 As shown, the unpatterned region 12 has multiple alignment marks 120. These alignment marks 120 can serve as zero-point alignment points for subsequent semiconductor processes on the patterned substrate 10, enabling LED pixels to be fabricated in the patterned region 11 and preventing the LED chip from crossing the unpatterned region 12. This ensures that the luminous performance of each LED pixel in the LED chip is essentially uniform, improving the uneven luminous performance defect of the LED chip.

[0048] Figure 7 for Figure 6 Enlarged view of a local area, combined with Figure 6 and Figure 7The unpatterned area 12 includes a first area 12-1 and a second area 12-2 extending in different directions. The first area 12-1 extends along a first direction x, and the second area 12-2 extends along a second direction y. The first direction x and the second direction y intersect, and the intersection of the first area 12-1 and the second area 12-2 defines multiple patterned areas 11. At least some of the alignment marks 120 are located at the intersection of the first area 12-1 and the second area 12-2. This location has relatively large space, allowing for more flexible design of the shape of the alignment marks 120. Furthermore, the apex of the patterned area 11 is located at the intersection of the first area 12-1 and the second area 12-2. Setting the alignment marks 120 at this location allows for relatively simple and accurate positioning of the patterned area 11.

[0049] Figure 7 The shape of the alignment mark 120 is illustrated in the form of a cross. This application does not limit the shape of the alignment mark 120, which can be a cross, an L, or other shapes.

[0050] In this application, the alignment mark 120 can be obtained by etching the unpatterned region 12. For example, during fabrication, multiple microstructures 11 are obtained through a first patterning process, and then the alignment mark 120 is obtained through a second patterning process.

[0051] Figure 8 This is another schematic diagram of a patterned substrate provided in an embodiment of this application, such as... Figure 8 As shown, the partial alignment mark 120 is located at the intersection of the first region 12-1 and the second region 12-2, and the partial alignment mark 120 is located between two adjacent pattern regions 11.

[0052] This application also provides a method for fabricating a patterned substrate, which can be used to fabricate the patterned substrate provided in this application. Figure 9 A flowchart illustrating a method for fabricating a patterned substrate, as provided in this application embodiment, is shown below. Figure 9 As shown, the manufacturing method includes:

[0053] Step S101: Coat photoresist on the substrate and expose multiple exposure areas on the substrate using a step-by-step exposure process, with a certain distance between adjacent exposure areas.

[0054] Step S102: After etching and development, multiple microstructures are formed in the exposed area. The exposed area is a patterned area, and a patternless area is formed between the patterned areas. The diameter of the microstructure in the patterned area is d1. The width of the patternless area between two adjacent patterned areas is d2, and d2≥2*d1.

[0055] In related technologies, patterned substrates are fabricated using multiple adjacent exposure regions. In a step-out process, the step size in the step direction is approximately equal to the width of the exposure region in that direction. In this embodiment, adjacent exposure regions are spaced a certain distance apart. The step size in the step-out process is adjusted so that it is greater than the width of the exposure region in the step direction to meet the exposure process requirements. This results in a patterned substrate including patterned region 11 and unpatterned region 12, avoiding splicing defects between adjacent exposure regions. In application, this avoids affecting the brightness uniformity of the LED chip array formed on the patterned substrate and improves wavelength uniformity.

[0056] In this application, either a positive or negative photoresist can be used. When using a positive photoresist, the exposed areas of the positive photoresist are soluble in the developer, while the unexposed areas form a mask, preventing the substrate beneath the mask from being etched. Using a positive photoresist allows for the fabrication of the aforementioned... Figure 4 The patterned substrate provided in this embodiment. When fabricated using negative photoresist, the exposed areas of the negative photoresist are insoluble in the developer to form a mask, while the unexposed areas are etched. The above-mentioned patterned substrate can be fabricated using negative photoresist. Figure 5 The patterned substrate provided in the embodiments.

[0057] This application also provides another method for fabricating a patterned substrate. Figure 10 A flowchart illustrating another method for fabricating a patterned substrate provided in this application embodiment is shown below. Figure 10 As shown, the manufacturing method includes:

[0058] Step S101: Coat photoresist on the substrate and expose multiple exposure areas on the substrate using a step-by-step exposure process, with a certain distance between adjacent exposure areas.

[0059] Step S102: After etching and development, multiple microstructures are formed in the exposed area. The exposed area is the patterned area, and unpatterned areas are formed between the patterned areas.

[0060] Step S103: Use an etching process to create multiple alignment marks in the patternless area.

[0061] use Figure 10 The manufacturing method provided in the embodiments can produce as follows: Figure 6 The embodiments include a patterned substrate with alignment marks.

[0062] Based on the same inventive concept, this application also provides an epitaxial wafer. Figure 11 A schematic diagram of an epitaxial wafer provided for an embodiment of this application, such as... Figure 11As shown, the epitaxial wafer includes a patterned substrate 10 provided in any embodiment of this application, and an epitaxial layer 20 is disposed on one side of the patterned substrate 10. The substrate 10 includes patterned regions 11 and unpatterned regions 12, with unpatterned regions 12 spaced apart from adjacent patterned regions 11. The patterned regions 11 include multiple microstructures 111. The epitaxial layer 20 is grown on the patterned substrate 10 using processes such as metal-organic chemical deposition. The epitaxial layer 20 includes stacked buffer layers, light-emitting layers, and conductive layers.

[0063] Based on the same inventive concept, this application also provides an LED chip, which is obtained by dividing an epitaxial wafer to obtain an LED chip with multiple LED pixels. Figure 12 A schematic diagram of an LED chip fabrication, such as... Figure 12 As shown, firstly, an epitaxial wafer 100 is provided, which includes a patterned substrate 10 provided in this embodiment of the application and an epitaxial layer 20 located on one side of the patterned substrate 10; then, dicing channels 30 are divided on the epitaxial wafer 100; LED chips 4 are obtained by dicing along the dicing channels 30. Figure 12 The diagram illustrates that the cut path 30 is located in the unpatterned area of ​​the patterned substrate 10. Figure 12 For simplification purposes only, each LED chip 4 actually includes multiple micro-LED pixels arranged in an array. Figure 12 The diagram illustrates etching away the epitaxial layer 20 at the dicing position 30, leaving only the substrate structure at the dicing position 30. In other embodiments, the epitaxial layer 20 at the dicing position 30 may be retained before dicing.

[0064] The patterned substrate 10 provided in this application embodiment includes a patterned area and a non-patterned area. An epitaxial layer 20 is formed on the patterned substrate 10 to form an epitaxial wafer 100. In some products, the epitaxial wafer 100 includes an unetched epitaxial layer 20 fabricated across its entire surface. In some products, the epitaxial layer 20 fabricated on the epitaxial wafer 100 is etched to form multiple LED pixels. When etching the epitaxial layer 20 to form LED pixels, the non-patterned area can be avoided, that is, all LED pixels are fabricated on the patterned area. Further, the epitaxial wafer is cut to form multiple LED chips. The dicing lines can be set in the non-patterned area, so one patterned area corresponds to one LED chip. In addition, depending on the application scenario of the LED chip, the size requirements of the LED chip are different. When a relatively small LED chip is required, the dicing lines can also be set in the patterned area, so one patterned area corresponds to at least two LED chips.

[0065] Figure 13 A schematic diagram of an LED chip provided for an embodiment of this application, such as... Figure 13As shown, the LED chip 4 includes a patterned substrate 10 and an epitaxial layer 20 located on one side of the patterned substrate 10. The patterned substrate 10 includes a patterned region 11 and a plateau region 13. The patterned region 11 includes multiple microstructures 111. The patterned region 11 and the epitaxial layer 20 are opposite each other. The portion of the patterned substrate 10 extending from the epitaxial layer 20 is the plateau region 13, which surrounds the patterned region 11. That is, the area of ​​the patterned substrate 10 is larger than the area of ​​the epitaxial layer 20. The edge of the patterned substrate 10 forms the plateau region 13 surrounding the epitaxial layer 20. The LED chip provided in this embodiment can have good brightness uniformity, and the optical yield of the color coordinates can reach close to 100% (or grayscale deviation <+ / -5). In addition, the plateau region 13 of the LED chip 4 can be easily used to make encapsulation dams. When individual LED chips need to be assembled for use in the application scenario, the encapsulation dams can also prevent optical crosstalk between adjacent LED chips.

[0066] Figure 13 The simplified diagram shows the buffer layer 21, N-type semiconductor layer 22, P-type semiconductor layer 23, N-electrode 24, P-electrode 25, and quantum well layer 26 between the N-type semiconductor layer 22 and the P-type semiconductor layer 23 in the epitaxial layer 20. Figure 13 The illustration shows that the LED pixel has a horizontal structure. This application does not limit the LED structure in the LED chip, and it can be any one of the following: upright structure, flip structure, and vertical structure.

[0067] like Figure 13 As shown, because the patterned region 11 of the patterned substrate 10 has multiple microstructures 111, the interface between the patterned substrate 10 and the buffer layer 21 is uneven. The light-emitting surface of the LED chip 4 can be one side of the buffer layer 21, thus the light-emitting surface has a microstructure. Optionally, the light-emitting surface can also be the side where the P electrode 25 is located. The edge of the patterned substrate 10 is a plateau region 13, where the plateau region 13 is cut in a similar manner. Figure 3 The structure left by the unpatterned region 12 of the patterned substrate in the embodiment.

[0068] like Figure 13 As shown, the diameter of the microstructure 111 is d1, and the width of the platform region 13 is d3, where d3 < 5 * d1. The LED chip provided in this embodiment is based on... Figure 12 The method provided involves cutting scribe lines within the unpatterned area of ​​the patterned substrate 10 on the epitaxial wafer during the dicing process. In the LED chip, the portion extending from the patterned substrate 10 to the epitaxial layer 20 is defined as the plateau region 13. The plateau region 13 is obtained by cutting the unpatterned area. Therefore, generally, the width of the plateau region 13 in the diced LED chip 4 is less than [a certain value]. Figure 3 The width of the patternless area 12 in the embodiment.

[0069] In some embodiments, 2*d1 <d3<5*d1。

[0070] In some embodiments, such as Figure 13 As shown, the patterned substrate 10 includes a first surface M1, which has multiple microstructures 111; the height of the first surface M1 within the platform region 13 is level with the height of the microstructures 111. Figure 4 The patterned substrate provided in the embodiment is used to fabricate an epitaxial wafer, which is then etched and cut to obtain... Figure 13 The LED chip provided in the example.

[0071] In other implementations, Figure 14 This is a schematic diagram of another LED chip provided as an embodiment of this application. Figure 14 As shown, the patterned substrate 10 includes a first surface M1, which has multiple microstructures 111, with grooves 112 between adjacent microstructures 111; the height of the first surface M1 within the platform region 13 is flush with the bottom of the grooves 112. Figure 5 The patterned substrate provided in the embodiment is used to fabricate an epitaxial wafer, which is then etched and cut to obtain... Figure 14 The LED chip provided in the example.

[0072] The LED chip provided in this application embodiment can be assembled with a packaging substrate. Figure 15 This is a schematic diagram of an LED package according to an embodiment of this application, such as... Figure 15 As shown, the LED package includes a packaging substrate 50 and an LED chip 40 provided in any embodiment of this application. The LED chip 40 and the packaging substrate 50 are disposed opposite to each other and bonded together. The LED chip 40 includes a patterned substrate 10 and an epitaxial layer 20. The packaging substrate 50 can be a CMOS substrate, which includes a driving circuit.

[0073] Figure 16 This is a schematic diagram of an LED package according to an embodiment of this application, such as... Figure 16 As shown, the LED package includes a packaging substrate 50 and an LED chip 40. The LED chip 40 is obtained by bonding the LED chip and the packaging substrate 50 and then removing the patterned substrate, as provided in any embodiment of this application. That is, the epitaxial layer 20 of the LED chip is retained, and the surface of the epitaxial layer 20 facing away from the packaging substrate 50 has an uneven structure.

[0074] The LED package provided in this application embodiment can be applied in the field of pixelated LED chips, such as pixelated car lights, augmented reality (AR), virtual reality (VR), mixed reality (MR), micro-projection and other devices.

Claims

1. A patterned substrate, characterized in that, The patterned substrate includes patterned regions and unpatterned regions, with unpatterned regions spaced apart from adjacent patterned regions; each patterned region includes multiple microstructures, the diameter of which is d1, and the width of the unpatterned region between two adjacent patterned regions is d2, where d2 ≥ 2 * d1.

2. The patterned substrate according to claim 1, characterized in that, d2≤5*d1.

3. The patterned substrate according to claim 1, characterized in that, The patternless area has multiple alignment marks.

4. The patterned substrate according to claim 3, characterized in that, The patternless area includes a first area and a second area with different extending directions, and the first area and the second area intersect to define a plurality of patterned areas; at least a portion of the alignment marks are located at the intersection of the first area and the second area.

5. The patterned substrate according to claim 1, characterized in that, The patterned substrate includes a first surface having a plurality of the microstructures; The height of the first surface within the patternless region is the same as the height of the microstructure.

6. The patterned substrate according to claim 1, characterized in that, The patterned substrate includes a first surface having a plurality of said microstructures, with grooves between adjacent said microstructures; The height of the first surface within the patternless area is level with the bottom of the groove.

7. A method for fabricating a patterned substrate, characterized in that, The manufacturing method includes: Photoresist is coated on a substrate, and multiple exposure areas on the substrate are exposed using a step-by-step exposure process, with a certain distance between adjacent exposure areas. After etching and development, multiple microstructures are formed in the exposed area, which is a patterned area, and unpatterned areas are formed between the patterned areas; the diameter of the microstructure is d1, and the width of the unpatterned area between two adjacent patterned areas is d2, where d2 ≥ 2 * d1.

8. The manufacturing method according to claim 7, characterized in that, The manufacturing method further includes: using an etching process to create multiple alignment marks in the patternless area.

9. An epitaxial wafer, characterized in that, Includes the patterned substrate as described in any one of claims 1 to 6.

10. An LED chip, characterized in that, The LED chip includes a patterned substrate and an epitaxial layer located on one side of the patterned substrate; the patterned substrate includes a patterned region and a plateau region, the patterned region includes multiple microstructures, the patterned region and the epitaxial layer are opposite to each other, and the portion of the patterned substrate extending out of the epitaxial layer is the plateau region.

11. The LED chip according to claim 10, characterized in that, The diameter of the microstructure is d1, and the width of the platform region is d3, where d3 < 5 * d1.

12. The LED chip according to claim 10, characterized in that, The patterned substrate includes a first surface having a plurality of the microstructures; The height of the first surface within the platform area is the same as the height of the microstructure.

13. The LED chip according to claim 10, characterized in that, The patterned substrate includes a first surface having a plurality of said microstructures, with grooves between adjacent said microstructures; The height of the first surface within the platform area is level with the bottom of the groove.

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