EPITACTIC FILM GROWTH ON A PATTERNED SUBSTRATE
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- INTEL CORP
- Filing Date
- 2013-06-29
- Publication Date
- 2026-07-02
AI Technical Summary
Growing III-V and Group IV materials on Si substrates is challenging due to lattice mismatch, leading to crystal defects such as screw dislocations, stacking faults, and twins, which propagate into the device layer, affecting device performance and increasing production costs.
The use of trenches with tapered sidewalls and defect barriers, annealing, and superlattices to trap and eliminate defects within the trench, reducing the aspect ratio requirement and minimizing defect propagation.
Reduces the need for high aspect ratios in trenches, traps defects within thin buffer layers, and lowers production costs by minimizing material usage and processing time, resulting in defect-free device layers.
Abstract
Description
BACKGROUND
[0001] A variety of electronic and optoelectronic devices can be enabled, for example, by developing high-quality III-V semiconductors on elemental silicon (Si) substrates or group IV semiconductors on Si substrates. Surface layers capable of achieving the performance benefits of III-V or Group IV materials can power a variety of high-performance electronic devices such as CMOS and Quantum Well (QW) transistors made of ultra-high mobility materials as under other indium antimonide (InSb), indium arsenide (InAs), germanium (Ge), and silicon germanium (SiGe). Optical devices, such as lasers, detectors, and photovoltaics, can also be fabricated from various other direct bandgap materials, such as gallium arsenide (GaAs) and indium gallium arsenide (InGaAs), among others. These devices can be further improved by monolithically integrating with conventional Si devices, since using a Si substrate has the added benefit of cost reduction.
[0002] However, growing III-V and Group IV materials on Si substrates can present many challenges. Crystal defects are caused by lattice mismatch, polar-to-nonpolar mismatch, and thermal mismatch between the III-V semiconductor epitaxial (EPI) layer and the Si semiconductor substrate or the Group IV semiconductor EPI layer and the Si semiconductor substrate . When the lattice mismatch between the EPI layer and the substrate exceeds a few percent, the compressive stress induced by the mismatch becomes too large and the defects are created by relaxing the EPI film. Once the film thickness is greater than the critical thickness (i.e. the film is fully in compressive stress below this thickness and partially relaxed above this thickness), the compressive stress is relieved by creating misfit dislocations at the interface between the film and the substrate and in the EPI film relaxed. The EPI crystal defects can appear in the form of screw dislocations, stacking faults, and twins. Many defects, particularly screw dislocations and twins, tend to propagate into the "device layer" in which the semiconductor device is fabricated. In general, the severity of defect generation correlates with the magnitude of the lattice mismatch between the III-V semiconductor and the Si substrate or the group IV semiconductor and the Si substrate. BRIEF DESCRIPTION OF THE DRAWINGS
[0003] Features and advantages of embodiments of the present invention are apparent from the appended claims, the following detailed description of one or more example embodiments, and the corresponding figures, in which:
[0004] figure 1(a)-(b) show a trench with tapered sidewalls in one embodiment.
[0005] figure 2(a)-(b) show a trench with an EPI layer and a defect barrier in one embodiment.
[0006] figure 3(a)-(b) show a trench including an annealed EPI layer in one embodiment.
[0007] figure 4(a)-(b) show a trench with a superlattice and an EPI layer in one embodiment.
[0008] figure 5 includes a process in one embodiment.
[0009] figure 6 includes a process in one embodiment.
[0010] figure 7 includes a process in one embodiment.
[0011] figure 8 includes a process in one embodiment. DETAILED DESCRIPTION
[0012] Numerous specific details are set forth in the following description, however, embodiments of the invention may be practiced without these specific details. Well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring an understanding of this description. "One embodiment," "various embodiments," and the like indicate embodiment(s) so described that may include particular features, structures, or characteristics, although not each embodiment necessarily embodies the particular features, structures or features included. Some embodiments may include some, all, or none of the features described for other embodiments. "First," "second," "third," and the like describe a common object and indicate different examples of similar referenced objects. Such adjectives do not imply that objects so described need be in any given order, whether temporal, spatial, ranked, or otherwise. "Connected" may indicate that elements are in direct physical or electrical contact with one another, and "coupled" may indicate that elements cooperate or interact with one another, but may or may not be in direct physical or electrical contact with one another. Although like or like numbers are used to designate like or like parts in different figures, it does not mean that all figures containing like or like numbers represent a single or same embodiment.
[0013] One embodiment includes depositing a material on a substrate, wherein the material has a different lattice constant than that of the substrate (eg, III-V or Group IV semiconductor EPI material on a Si substrate). One embodiment includes an EPI layer formed within a trench whose walls converge as the trench extends upward. One embodiment includes an EPI layer formed using multiple growth temperatures within a trench. A defect barrier formed in the EPI layer as the temperature changes contains defects within the trench and under the defect barrier. The EPI layer over the defect barrier and within the trench is relatively defect free. One embodiment includes an EPI layer annealed within a trench to introduce defect erasure. One embodiment includes an EPI superlattice formed within a trench and covered with a relatively defect-free EPI layer (still contained within the trench). Other embodiments are described here.
[0014] A conventional technique for EPI formation involves aspect ratio capture (ART). ART is based on screw dislocations propagating upwards at a certain angle. In ART, a trench is fabricated with a large enough aspect ratio such that the defects end at the sidewall of the trench and each layer above the endpoints is defect-free. More specifically, ART involves trapping defects along the sidewall of a shallow trench isolation (STI) portion by increasing the height (H) of the trench beyond the width (W) of the trench such that the H / W ratio is at least 1, 5 is. This ratio gives the lower limit for ART to block defects within a buffer layer.
[0015] the figure 1(a)-(b) show a trench with tapered sidewalls in an embodiment of the invention. figure 5 includes a process in an embodiment of the invention. First the figure 1(a) and figure 5 discussed and then the figure 1(b) discussed.
[0016] In one embodiment is a trench 107 , having a bottom and a rim, between the insulating parts 101 , 102 (Block 505 ) of the device 100 contain. The side walls of the ditch 107 may be shaped to narrow as they move away from the substrate 103remove (further below also described block 510 ). Such isolation portions may include STI portions, although other embodiments are not so limited. The Shares 101 , 102 are included on the substrate 103 , which has a first lattice constant. The substrate 103 may contain Si, such as a Si and / or SiGe substrate. One embodiment includes a shared SiGe buffer on a Si substrate, other embodiments are not so limited. The ditch 107 extends down to the substrate 103 . The ditch 107 has a lower width 110 near the bottom of the trench and has an upper width greater than the lower width, and the upper width is narrower than the lower width. The top width can be measured along a horizontal axis 120 run out at the narrowest point of the ditch 107 located. The top width is the difference between the widths 110 and the deviations 113 , 114 definitely. The deviation 113 is the distance between the sidewall of the trench 107 and the axis 121 and the deviation 114 is the distance between the sidewall of the trench 107 and the axis 122 .
[0017] The lower EPI layer 104 has a second lattice constant which is opposite to the first lattice constant which is assigned to the substrate 103 (or a top layer of the substrate 103 , if an intermediate layer, such as a buffer layer, between the lower portions of the substrate 103 and the EPI layer 104 is included) is mismatched. The EPI layer 104 will be in the ditch 107 near the bottom of the ditch and below the top width of the ditch, located at the narrowest point of the ditch 107 located (block 515 ), educated.
[0018] A top EPI layer is in the trench 107 above the lower EPI layer 104 contain. For example, one of the EPI layers 106 represent such an upper EPI layer. Furthermore, one of the EPI layers 105 represent such an upper EPI layer. Any of the EPI layers 105 , 106 may be included in a device layer, which may partially form a device such as a channel of a transistor (block 520 ). Any of the EPI layers 105 , 106 can be one of the lattice constants of the substrate 103 and / or the EPI layer 104 have different lattice constants. For example, the EPI layer 105 have a lattice constant such that a difference between the substrate lattice constant and the lattice constant of the EPI layer 105 greater than a difference between the substrate lattice constant and the lattice constant of the EPI layer 104 is. In one embodiment, the substrate includes 103 Si (e.g. Si and / or SiGe), the EPI layer 104 includes a III-V or Group IV material, the EPI layer 105 includes a III-V or Group IV material and the EPI layer 106 includes a III-V or Group IV material. III-V and Group IV materials include Ge, SiGe, GaAs, AlGaAs, InGaAs, InAs, and InSb, among others. Any or any of the components 103 , 104 , 105 , 106 can be different materials, such as materials containing different compositions such as Si x ge 1-x and Si y ge 1-y , where x is not equal to y. In other embodiments, the materials can be entirely different materials, such as InP, SiGe, and / or GaAs.
[0019] In one embodiment, the lower EPI layer includes 104 more defects than the upper EPI layers 105 and or 106 . In one embodiment, the lower EPI layer includes 104 more defects than the proportion of EPI layers 104 above the axis 120 . For example, the defect ends 130 within the EPI layer 104 . In one embodiment, the well includes moat 107 one (in figure1(a) not shown) length less than the total height of the trench resulting from the height 111 (which extends from the bottom of the ditch to the narrowest part of the ditch) and the height 112 (which extends from the narrowest point of the ditch to the top of the ditch). In one embodiment, the combination of heights 111 , 112 greater than 100 nm and the width 110 is smaller than the combination of heights 111 , 112 .
[0020] In one embodiment, the EPI layer 104 an n-MOS material (e.g. InP, SiGe, GaAs) used as a buffer layer in the trench 107 using different methods (e.g. molecular beam epitaxy, metal organic chemical vapor deposition (MOCVD) and / or metal organic vapor phase epitaxy (MOVPE)).
[0021] In one embodiment, the width and the length of the well are 107 much lower than the height of the ditch. This helps to identify defects (for example the defect 130 ) along the sidewalls of the STI 101 , 102 trapping and preventing defects from reaching the edge of the trench 107 to reach.
[0022] In one embodiment, the sidewalls of the trench are as in figure 1(a) (i.e., a hyperbola). The curvature allows for defect capture at a height (combined height from the heights 111 , 112 ), which is less than the product of 1.5 and the width 110 is. Subsequently, the device layers (e.g. the layers 105 , 106 ) over the buffer layer (e.g. the layer 104 ) is grown and device processing (not shown) is performed. Such an embodiment can reduce the need for a high aspect ratio for the trench, allowing defects to be trapped within the thin buffer layers, reducing the costs associated with the process by reducing required materials (for higher layers of EPI and the like) and the Process tool time can be reduced.
[0023] In one embodiment, the trench 107 combined heights 111 , 112 (extending from the top of the trench to the bottom of the trench) smaller than the product of 1.5 times the bottom width 110 are. In one embodiment, the trench includes 107 a lower portion having sidewalls that narrow as the sidewalls move away from the substrate; the sidewalls stop narrowing at the top width (at the axle 120 located); and the combined heights 111 , 112 are no greater than the product of 1.5 and the top width at the axis 120 . In one embodiment, the top width is at the axis 120 by a first difference (deviation 113 + deviation 114 ) narrower than the lower width 110 and the combination of the heights 111 , 112 is no greater than the product of 1.5 and the width 110 minus one half of the difference (e.g. deviation 113 or deviation 114 ).
[0024] In one embodiment, both deviations are 113 , 114 3 to 195 nm, the combination of heights 111 , 112 is 5 nm to several microns and the width 110 is 5 to 200 nm. This compares to a conventional ART system where a trench width of 10 nm would require a height of at least 15 nm (the height is equal to the product of 1.5 and the width, based on the tangent with an angle of 55 degrees between the trench bottom and a defect). One embodiment includes a height equal to the product of 1.5 and (the width 110 – the deviation 113 , which is equal to 10 nm – 3 nm). Consequently, the height is 10.5 nm (instead of 15 nm, which would be the case in a classic ART system using a 10 nm width).
[0025] the figure 1(b) includes an embodiment in which the trench 107 a lower part (bounded by the bottom of the trench, the side walls and the width at the axis 120) that is shaped like a trapezoid. In one embodiment, the height 111 equal to the product of 1.5 and the deviation 113 , for a height equal to 20-750 nm in various embodiments. In various embodiments, is the sum of the widths 110 , 113 , 114 equal to 15 to 500 nm. The width 113 and the width 114 can each be 5 nm or more. The height 112 can be 0 nm up to several microns. One embodiment includes an altitude 111 equal to the product of 1.5 and (the width 110 – the deviation 113 , which is equal to 10 nm – 3 nm). Consequently, the amount is 111 10.5 nm (instead of 15 nm which would be the case in a classic ART system using a 10 nm width).
[0026] Both the figure 1(a) as well as the figure 1(b) include the trench 107 with a lower half that includes a side wall that is at an angle 123 merges into the bottom of the ditch. The angle 123 can be than 70 degrees. In other embodiments, the angle 123 60, 55, 50, 45, 40 degrees and the like. Although 1.5 as a ratio for determining heights (e.g. combining the heights 111 , 112 for figure 1(a) and the height 111 for figure 1(b)), other ratios are also contemplated in various embodiments, as dictated by the size of the angle 123 and the curvature of the trench sidewalls can be dictated. In one embodiment, the trench has a height ranging from the edge of the trench to the bottom of the trench and the height is less than 1.3 times the width 110 . In one embodiment, the trench has a height ranging from the trench edge to the trench bottom and the height is less than 1.4 times the width 110 . In one embodiment, the trench has a height ranging from the trench edge to the trench bottom and the height is less than 1.1 times the width 110 (see the example where the height is 10.5 nm and the width is 10 nm).
[0027] Regarding the design of the side walls of the trench 107 can the ditch 107 for example in the embodiment of figure 1(a) using a photoresist layer and a hard mask. The photoresist layer is patterned and then a hard mask is etched using the photoresist as the mask. The choice of etch chemistry and the size of the etch depth dictate the curved profile of the sidewalls in the trench. In figure 1(b), a hard mask is etched using patterned photoresist, which is used to create a fin covering the top of the trench 107 gives the straight profile. Regarding the lower part of the ditch 107 becomes part of the substrate 103 under the hard mask selectively wet etched in (111) direction to achieve the tapered profile. STI is filled around the patterned hard mask and underlying fin. This is followed by the selective removal of the hard mask and fin with respect to the STI, leaving the trench 107 results. This can be followed by EPI layer growth.
[0028] the figure 2(a)-(b) show a device 200 with a trench including an EPI layer with a defect barrier in an embodiment of the invention. figure 6 includes a process in an embodiment of the invention. First the figure 2(a) and figure 6 discussed and then the figure 2(b) discussed.
[0029] In the figure 2(a) is the ditch 207 in the STI shares 201 , 202 and on the substrate 203 included (block 605 ). The substrate 203 may include Si, such as a Si and / or SiGe substrate, but other embodiments are not so limited. One embodiment includes a shared SiGe buffer on a Si substrate, other embodiments are not so limited. The ditch 207 includes a rim and a bottom and extends down to the substrate 203 . The lower EPI layer 204, located in the ditch near the bottom of the ditch (block 610 ), has a lattice constant that is opposite to a lattice constant that of the substrate 203 (or a top layer of the substrate 203 , if an intermediate layer, such as a buffer layer, between the lower portions of the substrate 203 and the EPI layer 204 is included) is mismatched.
[0030] The top EPI layer 205 becomes above and in direct contact with the lower EPI layer 204 formed, with the lower and the upper EPI layer 204 , 205 are monolithic to each other (block 615 ). Furthermore, the lower and the upper EPI layer 204 , 205 at the barrier 220 directly connected to each other, what defects (for example, the defect 230 ) in the lower EPI layer 204 blocked. In one embodiment, the EPI layer 205 a lattice constant generally the same as that of the EPI layer 204 on.
[0031] The embodiment of figure 2(a) solves defects due to temperature changes during EPI growth in the trench 207 on. The slowly growing temperature film 204 is grown up first. Subsequently, the growth is paused and the growth temperature is increased. The growth pause changes the surface condition such that an interface 220 is formed, the defects in the underlying layer 204 prevents it from going up in the layer 205 to progress. Subsequent growth is completed at higher temperatures to form the layer 205 to build. In one embodiment, the lower temperature is 400°C and the higher temperature is 550°C, whereas other embodiments are not so limited and lower temperatures of, for example, 300, 325, 350, 375, 400, 450°C and higher temperatures of 450, 475, 500, 525, 575, 600°C.
[0032] Consequently, the lower EPI layer includes 204 in one embodiment more defects than the top EPI layer 205 . The defect 230 in the lower EPI layer 204 grows upwards and then becomes at the barrier 220 deflected and grows downward (see defect fraction 231 ) to the substrate 203 (Block 620 ). In one embodiment, the barrier extends 220 from one of the trench sidewalls to another of the sidewalls.
[0033] In one embodiment, the height 211 equal to the product of 1.5 and the width 210 ; however, other embodiments are not so limited.
[0034] figure 2(b) includes an image showing the moat 207 with the defect barrier 220 between the layers 204 and 205 illustrated. The layer 204 has significantly more defects within the layer than the layer 205 , which shows fewer defects, if any, that are close to the barrier 220 and are concentrated away from the edge of the ditch.
[0035] the figure 3(a)-(b) show a device 300 with a trench including an annealed EPI layer in an embodiment of the invention. figure 7 includes a process in an embodiment of the invention.
[0036] In the figure 3(a) is the ditch 307 between the STI shares 301 , 302 and above the substrate 303 (Block 705 ). An EPI layer 304 is inside the moat 307 (Block 710 ) educated. Due to a lattice mismatch between the EPI layer 304 and the substrate 303 progress defects (for example, the defect 330 ) within the layer 304 ahead (block 715 ). However, annealing of the layer results 304 the embodiment of figure 3(b) (Block 720 ). In one embodiment, the height 311 equal to the product of 1.5 and the width 310 ; however, other embodiments are not so limited.
[0037] figure 3(b) includes an embodiment with a trench 307, which has an edge and a bottom, between the insulating layers 301 , 302 and on the substrate 303 . The EPI layer 304 is in the ditch 304 close to the bottom of the trench and shows no defects. The absence of defects may be caused by tempering (Block 720 ). In one embodiment, the EPI layer comprises 304 a Group IV and / or a III-V material and the substrate 303 includes silicon (e.g. Si or SiGe). In one embodiment include the EPI layer 304 and the substrate 303 equal lattice constants (e.g. due to annealing) and the EPI layer 304 contacts the substrate 303 direct.
[0038] In another embodiment (not shown), the EPI layer couples 304 to the substrate via an intermediate layer with a lattice constant equal to the lattice constant (due to annealing) of the EPI layer 303 and the EPI layer directly contacts the intermediate layer.
[0039] Thus, in one embodiment, after growing an EPI layer in the trench, the device is annealed at a high temperature (e.g., rapid thermal, spike, flash, and / or laser anneal). The large thermal energy content melts the EPI film. Immediately after melting, the wafer is cooled to room temperature. The cooling cycle induces recrystallization of the molten film, which then matches the lattice constant of the underlying layer (e.g., the substrate or the interface between the bottom portion of the substrate and the EPI layer). However, in another embodiment, the EPI layer is not melted. Instead, in the embodiment at temperatures below the melting point of the layer 304 annealed while still causing recrystallization. In one embodiment, recrystallization occurs at a temperature above the product of 0.6 and the melting point of the EPI layer 304 on; however, other embodiments are not so limited and may include, for example, multipliers of 0.5, 0.7, 0.8, and the like.
[0040] the figure 4(a)-(b) show a device 400 with a trench including a superlattice and an EPI layer in an embodiment of the invention. figure 8 includes a process in an embodiment of the invention.
[0041] In the figure 4(a) is the ditch 407 between the STI shares 401 , 402 and above the substrate 403 . Due to a lattice mismatch between the EPI layer 406 and the substrate 403 progress defects (for example, the defect 430 ) within the layer 406 Ahead.
[0042] However, the figure 4(b) an embodiment with a trench 407 , which is between the layers of insulation 401 , 402 included (block 805 ) and on the substrate 403 is formed. The substrate 403 may include Si, such as a Si and / or SiGe substrate, but other embodiments are not so limited. One embodiment includes a shared SiGe buffer on a Si substrate, other embodiments are not so limited. The ditch also includes 407 near the bottom of the ditch (block 810 ) and the axis 420 a superlattice. A superlattice is a periodic structure of layers of two (or more) materials (which may vary only in concentration among elements, or may contain completely different elements). The superlattice, including the EPI layer(s) 404 or the EPI layer(s) 405 is above and in direct contact with one of the EPI layers 404 educated. The EPI layer 406 is in the ditch 407 over the superlattice (block 815 ). The superlattice can contain 2, 3, 4, 5, 6, 7 or more layers. In various embodiments, the superlattice includes alternating layers of, for example, Si and SiGe, InGaAs and InP, and combinations of Si, SiGe, InGaAs, and InP.
[0043] In one embodiment, the superlattice includes a Ge seed layer that contacts an intermediate layer that directly contacts a Si substrate. The Ge seed layer is followed by Si on top 50 ge 50 , Ge, Si 50 ge 50 , Ge and then more superlattice layers or a layer like the layer 406 . The intermediate layer can be Si near the substrate 70 ge 30 and near the Ge seed layer Si 30 ge 70 include. Another embodiment is the same as above only without a Ge seed layer.
[0044] Any of the EPI layers 404 , 405 , 406 or even the EPI layer 408 can have the same lattice constant among themselves or a different lattice constant from one or more peer EPI layers. Also, any of the EPI layers 404 , 405 , 406 a lattice mismatch with the substrate 403 or any intermediate layer between a lower portion of the substrate 403 and the conscious EPI layer.
[0045] In the embodiment of figure 4(b), multilayer growth is used to form defects (e.g. the defect 430 ) at the progression into upper layers, like the layer 406 , to hinder or to slip away. From the superlattice (e.g. the layers 404 , 405 ) introduced compressive stress causes dislocations to bend and annihilate in the superlattice (block 820 ). An embodiment may also include implementation of multi-layers in buffer / substrate layer(s). Thus, in one embodiment, the superlattice contains more defects than the EPI layer 406 .
[0046] In one embodiment, the height 411 equal to the product of 1.5 and the width 410 ; however, other embodiments are not so limited. In one embodiment, the width is 410 between 5 and 200 nm. In one embodiment, the superlattice has a height between 2 and 50 nm. In one embodiment, an interface layer between the bottom substrate and the superlattice has a height of 1.3 microns.
[0047] Any of the EPI layers discussed herein may be included in a channel of a transistor, for example.
[0048] In one embodiment, a device includes: a trench, having a rim and a bottom, in an isolation layer located on a substrate having a first lattice constant; wherein (a) the trench extends downward toward the substrate; (b) the trench near the bottom of the trench has a bottom width and a top width above the bottom width; and (c) the top width is narrower than the bottom width; and a bottom epitaxial (EPI) layer having a second lattice constant mismatched to the first lattice constant in the trench near the trench bottom and below the upper trench width. An embodiment includes an upper EPI layer over the lower EPI layer in the trench. In one embodiment, the lower EPI layer contains more defects than the upper EPI layer. In one embodiment, the top EPI layer is included in a device layer and has a third lattice constant; and a difference between the first and third lattice constants is greater than a difference between the first and second lattice constants. In one embodiment, the trench has a height ranging from the trench edge to the trench bottom and the height is less than 1.5 times the bottom width. In one embodiment, the trench has a height ranging from the trench edge to the trench bottom and the height is less than 1.4 times the bottom width. In one embodiment, the trench has a height ranging from the trench edge to the trench bottom and the height is less than 1.3 times the bottom width. In one embodiment, the trench includes a lower portion with sidewalls that narrow as the sidewalls move away from the substrate; the sidewalls stop narrowing at the top width; the ditch has a height ranging from the ditch bottom to the top width; and the upper width is narrower than the lower width by a first difference and the height is no greater than a product of 1.3 and one-half the difference. In one embodiment, the trench includes a height ranging from the trench edge to the trench bottom: the trench includes a lower portion with sidewalls that narrow as the sidewalls move away from the substrate and the sidewalls stop narrowing at the upper width; and the upper width is narrower than the lower width by a first difference and the height is no greater than a product of 1.3 and one-half the difference. In one embodiment, the trench has a cross section shaped like a hyperbola. In one embodiment, the trench includes a lower portion in the shape of a trapezoid extending from the lower width to the upper width. In one embodiment, the trench includes a lower half and an upper half, and the lower half includes a sidewall that transitions to the bottom of the trench at an angle of less than 70 degrees between the sidewall and the bottom of the trench.
[0049] An embodiment includes: a trench enclosed in an isolation layer formed on a substrate having a first lattice constant, the trench having a rim and a bottom and extending down to the substrate; a bottom epitaxial (EPI) layer having a second lattice constant mismatched to the first lattice constant in the trench near the trench bottom; a top EPI layer formed over and in direct contact with the bottom EPI layer, the bottom and top EPI layers being monolithic to one another; wherein the bottom and top EPI layers connect directly to each other at a barrier that blocks defects in the bottom EPI layer. In one embodiment, the lower EPI layer contains more defects than the upper EPI layer. One embodiment involves a defect in the lower EPI layer that grows upward, then deflects at the barrier and grows downward toward the substrate. In one embodiment, the top EPI layer has a third lattice constant that is generally equal to the second lattice constant. In one embodiment, the trench includes opposing sidewalls and the barrier extends from one of the sidewalls to another of the sidewalls. In one embodiment, the bottom EPI layer is formed at a bottom EPI layer growth temperature and the top EPI layer is formed at a top EPI layer growth temperature that is higher than the bottom EPI layer growth temperature.
[0050] An embodiment includes: a trench enclosed in an isolation layer formed on a substrate having a substrate lattice constant, the trench having a rim and a bottom and extending down to the substrate; a superlattice in the trench near the bottom of the trench, the superlattice including: (a) a first epitaxial (EPI) layer having a first lattice constant mismatched to the substrate lattice constant, and (b) a second over and in close contact with the first EPI layer formed EPI layer; a third EPI layer in the trench above the superlattice. In one embodiment, the superlattice contains more defects than the third EPI layer. In one embodiment, defects in the superlattice cancel out. In one embodiment, the second EPI layer includes a second lattice constant, the third EPI layer includes a third lattice constant, and a difference between the substrate and third lattice constant is greater than a difference between the substrate and first lattice constant.
[0051] An embodiment includes: a trench having a rim and a bottom in an isolation layer located on a substrate having a first lattice constant; and an epitaxial (EPI) layer having a second lattice constant in the trench near the trench bottom; where the EPI layer contains no defects. In one embodiment, the EPI layer comprises a Group IV and / or a III-V material and the substrate comprises silicon. In one embodiment, the first lattice constant is equal to the second lattice constant and the EPI layer directly contacts the substrate. In one embodiment, the EPI layer couples to the substrate via an intermediate layer with a third lattice constant, the second lattice constant is equal to the third lattice constant, and the EPI layer directly contacts the intermediate layer.
[0052] Although the present invention has been described with reference to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
Claims
[1] Device comprising the following: a trench with a rim and a bottom, in an insulating layer located on a substrate with a first lattice constant; wherein (a) the trench extends downwards towards the substrate; (b) the trench near the trench bottom has a lower width and an upper width greater than the lower width; and (c) the upper width is narrower than the lower width; and a lower epitaxial (EPI) layer which, in the trench near the trench bottom and below the upper trench width, has a second lattice constant that is mismatched to the first lattice constant. [2] Device according to claim 1, comprising an upper EPI layer above the lower EPI layer in the trench. [3] Device according to claim 2, wherein the lower EPI layer contains more defects than the upper EPI layer. [4] Device according to claim 3, wherein the upper EPI layer is enclosed in a device layer and has a third lattice constant; and a difference between the first and the third lattice constant is greater than a difference between the first and the second lattice constant. [5] Device according to claim 3, wherein the trench has a height extending from the trench edge to the trench bottom, and the height is less than 1.3 times the lower width. [6] Device according to claim 3, wherein: the trench includes a lower portion with side walls that narrow as the side walls move away from the substrate; the side walls cease to narrow at the top width; the ditch has a height that extends from the ditch bottom to its upper width; and The upper width is narrower than the lower width by a first difference, and the height is no greater than a product of 1.3 and one and a half of the difference. [7] Device according to claim 3, wherein: the ditch has a height that extends from the edge of the ditch to the bottom of the ditch; The trench includes a lower portion with sidewalls that narrow as the sidewalls move away from the substrate, and the sidewalls cease to narrow at the upper width; and The upper width is narrower than the lower width by a first difference, and the height is no greater than a product of 1.3 and one and a half of the difference. [8] Device according to claim 3, wherein the trench has a cross-section shaped like a hyperbola. [9] Device according to claim 3, wherein the trench includes a lower portion in the form of a trapezoid extending from the lower width to the upper width. [10] Device according to claim 1, wherein the trench comprises a lower half and an upper half and the lower half comprises a side wall which merges into the bottom of the trench at an angle of less than 70 degrees between the side wall and the bottom of the trench. [11] Device comprising the following: a trench enclosed in an insulating layer formed on a substrate with a first lattice constant, wherein the trench has a rim and a bottom and extends downwards towards the substrate; a lower epitaxial (EPI) layer which, in the trench near the trench bottom, has a second lattice constant that is mismatched to the first lattice constant; an upper EPI layer formed above and in direct contact with the lower EPI layer, wherein the lower and upper EPI layers are monolithic to each other; the lower and upper EPI layers connect directly to each other at a barrier that blocks defects in the lower EPI layer. [12] Device according to claim 11, wherein the lower EPI layer contains more defects than the upper EPI layer. [13] Device according to claim 12, wherein a defect in the lower EPI layer grows upwards and is then deflected at the barrier and grows downwards towards the substrate. [14] Device according to claim 12, wherein the upper EPI layer has a third lattice constant which is generally equal to the second lattice constant. [15] Device according to claim 12, wherein the trench includes opposing side walls and the barrier extends from one of the side walls to another of the side walls. [16] Device according to claim 12, wherein the lower EPI layer is formed at a lower EPI layer growth temperature and the upper EPI layer is formed at an upper EPI layer growth temperature which is higher than the lower EPI layer growth temperature. [17] Device comprising the following: a trench enclosed in an insulating layer formed on a substrate with a substrate lattice constant, wherein the trench has a rim and a bottom and extends downwards towards the substrate; a superlattice in the trench near the trench bottom, the superlattice comprising: (a) a first epitaxial (EPI) layer having a first lattice constant mismatched to the substrate lattice constant, and (b) a second EPI layer formed above and in direct contact with the first EPI layer; and a third EPI layer in the trench above the overgrid. [18] Device according to claim 17, wherein the superlattice contains more defects than the third EPI layer. [19] Device according to claim 17, wherein defects in the superlattice are extinguished. [20] Device according to claim 17, wherein the second EPI layer includes a second lattice constant, the third EPI layer includes a third lattice constant and a difference between the substrate and the third lattice constant is greater than a difference between the substrate and the first lattice constant. [21] Device comprising the following: a trench with a border and a bottom in an insulating layer, located on a substrate with a first lattice constant; and an epitaxial (EPI) layer, which has a second lattice constant, in the trench near the trench bottom; where the EPI layer contains no defects. [22] Device according to claim 21, wherein the EPI layer comprises a group IV and / or a III-V material and the substrate includes silicon. [23] Device according to claim 22, wherein the first lattice constant is equal to the second lattice constant and the EPI layer directly contacts the substrate. [24] Device according to claim 22, wherein the EPI layer couples to the substrate via an intermediate layer with a third lattice constant, the second lattice constant being equal to the third lattice constant and the EPI layer directly contacting the intermediate layer.