An active cooling die, a method of making the same, and a method of packaging a die using the same

Abstract

This invention relates to the field of chip manufacturing technology, primarily disclosing an active cooling die, its preparation method, and its packaging method with a chip. The active cooling die includes a microchannel layer, with at least one set of microfluidic grooves formed within the microchannel layer, and a bonding region on the microchannel layer; wherein the bonding region is located within the microfluidic groove region or between the microfluidic grooves; a first interconnect unit is disposed within the bonding region and connects the upper and lower surfaces of the microchannel layer; wherein the first interconnect unit has a deformation region formed within it. This invention solves the contradiction between the high power heat dissipation requirements and the high vertical interconnect density or high performance requirements of three-dimensional integrated chips, which is difficult to address with existing chip heat dissipation technologies. It also solves the problems of high thermal resistance in the integration of microchannels and TSVs, TSV reliability, and the integration of cooling dies and active dies.

Description

Technical Field

[0001] This invention relates to the technical field of chip manufacturing, and in particular to an active cooling die, its preparation method, and its packaging method with the chip. Background Technology

[0002] Integrated chip technology is one of the main paths to improve chip computing power in the post-Moore's Law era. Through a new design paradigm of "decomposition-combination-integration," it drives the evolution of chips towards higher integration levels in three dimensions, and is a key method for my country to fabricate high-performance chips across process nodes. However, on the one hand, due to the continuous development of chip technology, the average power consumption and local hotspot heat flux density of a single chip are increasing, reaching 800W / cm² in the 7nm process. 2 Micrometer-scale localized hot spots, with an average heat flux density on the chip approaching 150 W / cm². 2 On the other hand, as chips evolve from 2D planar layouts to 3D three-dimensional layouts, the heat dissipation requirements of chips on the vertical projected area increase significantly for the same total power consumption. Furthermore, the heat dissipation path of chips far from heat dissipation devices is lengthened, and parasitic thermal resistance increases. Therefore, remote heat dissipation methods based on layer-by-layer heat transfer can no longer meet the heat dissipation requirements of high-power, highly integrated 3D integrated chips.

[0003] In recent years, microchannel near-junction cooling, which involves creating microchannels on the back substrate of a chip to directly introduce fluid heat dissipation, has attracted attention due to its ability to significantly reduce thermal resistance and effectively address the problem of heat accumulation in high-power chips. However, traditional microchannel near-junction cooling methods integrate the microchannels with the substrate of the active heat-generating chip, forcing an increase in chip thickness. On the one hand, due to the needs of integration technology, current 3D integrated chips are developing towards thinner thicknesses, with single-layer chip thicknesses reduced to below 100μm. Integrating heat dissipation fluid microchannels at this thickness will lead to a sharp increase in flow resistance, a decrease in heat dissipation efficiency, and an increase in the pump power required for heat dissipation, resulting in a significant decrease in economy and energy efficiency. If the chip substrate thickness is increased to the thickness required for setting up microchannels, such as 300μm, the area of ​​through-silicon vias (TSVs) used for 3D electrical interconnects will increase due to the requirements of their fabrication process (consistent TSV aspect ratio), leading to a significant increase in the area of ​​passive regions required for electrical interconnects, thereby squeezing the area of ​​the active layer and resulting in a decrease in chip performance for the same chip area. On the other hand, incorporating microchannel fabrication processes into active chip manufacturing processes will severely impact the yield of active chips and significantly increase costs. Therefore, traditional near-junction heat dissipation methods for substrate-integrated microchannels cannot balance the conflicting demands of high power and high integration density in three-dimensional integrated chips.

[0004] Therefore, there is an urgent need to develop a new microchannel heat dissipation method suitable for high-power, highly integrated 3D integrated chips. Furthermore, the following technical problems encountered in the integration of microchannels and TSVs must be addressed in its fabrication process: (1) Traditional near-junction microchannels use conventional hydrophilic bonding methods in their bonding and sealing processes. Due to the limitations of their process principles, a micron-thickness buried silica layer will form at the bonding interface, and voids are prone to exist at the bonding interface. Voids will affect the bonding reliability and lead to failure. The buried silica layer will hinder subsequent TSV fabrication processes such as etching, sputtering, and electroplating, resulting in the failure of the heat dissipation structure and electrical interconnect integration.

[0005] (2) The height of the microchannel must meet the requirements of heat dissipation and heat exchange efficiency, so the volume of the TSV will increase with its height. For example, when the aspect ratio of the TSV is set to 8:1 in current mature processes, if the depth of the TSV increases to 400μm, its diameter needs to reach 50μm; in contrast, the diameter of the TSV in a conventional 3D chip is 5-10μm. Since the thermal expansion coefficients of the conductive metal (e.g., copper) filled in the TSV are very different from those of silicon, large-volume TSVs will be subject to greater thermal stress in the high-temperature annealing process of TSV fabrication and in high-temperature application scenarios during service, which may eventually lead to risks such as TSV expansion, heat exchange structure rupture or chip failure. Summary of the Invention

[0006] Therefore, the technical problem to be solved by the present invention is: (1) Existing chip heat dissipation technology is difficult to resolve the contradiction between the high power heat dissipation requirements and the high vertical interconnect density (or high performance) requirements of three-dimensional integrated chips.

[0007] (2) Existing microchannel bonding and sealing technologies are difficult to achieve effective integration of TSVs with microchannels or heat dissipation structures. Furthermore, traditional microchannel and TSV integration schemes are difficult to solve the problems of electrical failure or heat exchange structure damage and microchannel failure caused by the thermal expansion stress of large-volume TSVs.

[0008] (3) When actively cooled core particles are integrated with three-dimensional integrated chips in a modular fashion, conventional eutectic bonding and thermo-pressing bonding processes that use only fluid inlet and outlet and electrical signal interface as bonding interfaces will result in excessive thermal resistance of the bonding layer and difficulty in heat dissipation of the chip; while using hybrid bonding technology for integrated bonding of fluid-electric interface will result in problems such as high process difficulty, high cost and low yield.

[0009] The above-mentioned technical problem (1) is solved by the following technical solution: An active cooling core particle, comprising a microchannel layer, wherein at least one set of microfluidic grooves are formed in the microchannel layer, and an interconnection region is formed on the microchannel layer; wherein the interconnection region is located within the microfluidic groove region or between the microfluidic grooves; a first interconnection unit is provided in the interconnection region and connects the upper and lower surfaces of the microchannel layer; wherein a deformation region is formed in the first interconnection unit.

[0010] In a preferred embodiment of the active cooling core of the present invention: several groups of microfluidic channels are interconnected, or several groups of microfluidic channels are relatively independent.

[0011] In a preferred embodiment of the active cooling core of the present invention: a first deposition hole is formed in the interconnection region, and the radial cross-sectional shape of the first deposition hole is circular.

[0012] In a preferred embodiment of the active cooling core of the present invention: an insulating layer, a barrier layer and a first seed layer are deposited sequentially from the hole wall toward the axis in the first deposition hole; the first interconnect unit is formed by electrochemical deposition of the first seed layer.

[0013] In a preferred embodiment of the active cooling core of the present invention: the first interconnecting unit is closed at both ends and hollow inside to form the deformation zone.

[0014] In a preferred embodiment of the active cooling core of the present invention: the length of the first interconnect unit is greater than the thickness of the microchannel layer, and the top and bottom protruding ends of the first pad and the second pad are respectively fixedly provided.

[0015] In a preferred embodiment of the active cooling core of the present invention: a first welding area and a second welding area are respectively provided on the upper and lower surfaces of the microchannel layer in areas other than the first and second pads; the surface of the first pad is flush with the surface of the first welding area, and the surface of the second pad is flush with the surface of the second welding area.

[0016] In a preferred embodiment of the active cooling core of the present invention: an insulating ring is provided between the first pad and the first welding area, and the insulating ring is also provided between the second pad and the second welding area; the first welding area and the second welding area have fluid inlet and outlet at corresponding positions of the microfluidic groove.

[0017] In a preferred embodiment of the active cooling core of the present invention: an insulating medium is provided between the first welding area and the second welding area and the microchannel layer.

[0018] In a preferred embodiment of the active cooling core of the present invention: the thickness of the first interconnecting unit on one side is β, the aperture of the deformation zone is α, and the ratio of β to α is in the range of 1:10 to 2:5.

[0019] In a preferred embodiment of the active cooling core of the present invention: the thickness of one side of the insulating ring is φ, the outer diameter of the first pad and the second pad is γ, and the ratio of φ to γ ​​is in the range of 1:10 to 3:10.

[0020] To solve the above-mentioned technical problems (2) and (3), the present invention also proposes the following technical solution: a method for preparing an actively cooled chip, comprising the following steps: spin-coating photoresist on the upper surface of a first silicon wafer, forming a microfluidic trench on the first silicon wafer after passing through a standard photolithography process and deep silicon etching, and removing the remaining photoresist; wherein, a bonding region is formed in the area of ​​the first silicon wafer outside the microfluidic trench; surface activation is performed on the bonding region and the upper surface of the second silicon wafer to form a first activation region and a second activation region respectively, bonding the first activation region and the second activation region, sealing and forming a microchannel layer; thinning the upper surface of the microchannel layer, etching the bonding region and forming a first deposition hole; depositing an insulating layer, a barrier layer and a first seed layer successively in the first deposition hole, performing an annealing process, and performing electrochemical deposition to form the first interconnect unit, filling the first interconnect unit with a soft adhesive, and chemically depositing... Mechanical grinding and polishing down to the insulating layer; a barrier layer and a second seed layer are deposited sequentially on the insulating layer on the upper surface of the microchannel layer; after electrochemical deposition of the second seed layer, chemical mechanical grinding and polishing are performed, and after patterning by standard photolithography, the first pad, insulating ring, and first welding area are etched to form; fluid inlets and outlets are formed on the first welding area, and the depth of the fluid inlets and outlets is etched down to the position of the insulating layer; a carrier sheet is temporarily bonded to the upper surface of the first pad using a temporary bonding method, and the lower surface of the microchannel layer is thinned to expose the metal at the lower end of the first interconnect unit; a barrier layer and a third seed layer are deposited using the same method as the first pad, and a second pad, insulating ring, second welding area, and fluid inlets and outlets in the second welding area are prepared; the carrier sheet is debonded, and the fluid inlets and outlets in the first welding area and the second welding area are etched to the position of communicating with the microfluidic channel in the microchannel layer to form an active cooling core.

[0021] In a preferred embodiment of the preparation method of the active cooling core of the present invention: the first silicon wafer and the second silicon wafer are double-polished silicon wafers with a surface roughness of less than 0.5 nm.

[0022] In a preferred embodiment of the active cooling core preparation method of the present invention: the photoresist spin-coated on the upper surface of the first silicon wafer is AZ4620, the spin-coating speed of the spin coater is 2500 r / min, the spin-coating time is 30 s, after spin-coating, it is baked at 100°C for 5 min, the designed microchannel structure pattern is exposed and developed using a photolithography machine, and then heated to 110°C for 5 min; the microchannel is etched using a deep silicon etching method, the depth range of which is 50~300 μm; after etching, the photoresist is removed and cleaned using acetone and isoacetone solutions.

[0023] In a preferred embodiment of the preparation method of the active cooling core of the present invention: the first activation region and the second activation region are prepared by the following steps: First, the etched first silicon wafer and the second silicon wafer are ultrasonically cleaned sequentially with acetone, anhydrous ethanol and deionized water for 10 minutes, and then dried with nitrogen gas for later use; Second, the cleaned first silicon wafer and the second silicon wafer are placed on a fixture inside the cavity, the cavity is sealed, and a vacuum is drawn into the cavity, with a vacuum degree of 10. -6 The process involves applying pressure to the bonding region of the first silicon wafer and the upper surface of the second silicon wafer using an Ar ion beam. The irradiation time is 180s to 420s, and the Ar ion beam energy is 0.6 to 1keV. Finally, the first and second silicon wafers are bonded together using a bonding machine with pressure applied from top to bottom. The bonding time is 250s, and the bonding pressure is 0.6 to 1.2MPa.

[0024] In a preferred embodiment of the preparation method of the actively cooled core of the present invention: the first interconnect unit is prepared by electrochemical deposition, wherein the first interconnect unit is made of metal, and the metal is at least one of Cu and Au; wherein, electrochemical deposition is performed on the first deposition hole using an electrochemical workstation, the electrochemical deposition solution is copper methanesulfonate, the current density is 0.3~0.6ASD, the electrochemical deposition time is 15~30min, and the temperature is 25℃; after the electrochemical deposition is completed, the first interconnect unit is annealed in a vacuum environment, specifically by heating the silicon wafer from room temperature to 400℃ in a vacuum furnace at a heating rate of 5℃ / min, and holding it at 400℃ for 30~90min before natural cooling.

[0025] In a preferred embodiment of the preparation method of the active cooling core of the present invention: the deformation zone is sealed and filled with a soft adhesive using a vacuum-assisted filling process, wherein the soft adhesive is one of benzocyclobutene resin, polydimethylsiloxane and epoxy resin.

[0026] In a preferred embodiment of the active cooling core preparation method of the present invention: during the sputtering deposition of the insulating layer inside the first deposition hole, the insulating layer covers the upper surface of the microchannel layer to form the insulating medium; a second seed layer is deposited on the upper surface of the insulating medium, the second seed layer grows and completely covers the surface of the insulating medium and communicates with the first seed layer; the insulating ring is coaxially formed at the position corresponding to the first deposition hole, the insulating ring is an annular vacuum groove, the inner region of the insulating ring is the first pad, and the outer region of the insulating ring is the first soldering area.

[0027] In a preferred embodiment of the preparation method of the active cooling core of the present invention: after thinning the lower surface of the microchannel layer to expose the metal at the lower end of the first interconnect unit, an insulating layer is deposited on the lower surface of the microchannel layer by PECVD or ALD to form the insulating medium; and a perforation hole is etched at the corresponding position of the first deposition hole on the lower surface of the microchannel layer, and a third seed layer is deposited on the surface of the insulating medium. The third seed layer is electrochemically deposited on the lower surface, and the third seed layer passes through the perforation hole and communicates with the first seed layer, and completely covers the surface of the insulating medium on the lower surface; the insulating ring is coaxially formed at the corresponding position of the first deposition hole on the surface of the insulating medium below, the inner region of the insulating ring is the second pad, and the outer region of the insulating ring is the second soldering area.

[0028] In a preferred embodiment of the preparation method of the active cooling core of the present invention: before the second seed layer and the third seed layer completely cover the upper and lower surfaces of the microchannel layer, a barrier layer is sputtered on the upper and lower surfaces of the microchannel layer using magnetron sputtering; the barrier layer is made of at least one of Cr and Ti, and has a thickness of 20~30nm; the second seed layer and the third seed layer covering the upper and lower surfaces of the microchannel layer are made of at least one of Cu and Au, and have a thickness of 200~500nm.

[0029] To solve the above-mentioned technical problems, the present invention also proposes the following technical solution: a packaging method for an active cooling chip and a three-dimensional integrated chip, which includes the above-mentioned active cooling chip and its preparation method, and further includes the following steps: bonding and integrating the first pad and the second pad with the fluid pad and electrical signal interface pad of the active chip to be cooled on the upper and lower layers respectively by a high vacuum surface activation bonding method.

[0030] The beneficial effects of this invention are as follows: 1. Unlike conventional design methods that open channels on active substrates, this invention employs a modular approach of first disassembling and then reassembling. This completely decouples the heat dissipation microchannels from the active chip, reconstructing them into an active cooling chip containing only microchannels, TSVs, electrical interconnect layers, and bonding pads. Then, by designing fluid and electrical signal pad interfaces, the cooling chip is integrated into the 3D integrated chip using bonding integration. This ensures a thin active chip, high vertical interconnect density, and high active layer area utilization.

[0031] 2. By employing surface activation bonding technology, the presence of a silicon dioxide layer on the bonding surface is avoided, which would otherwise make it difficult to create holes. This solves the problem of bonding void ratio. The bonding of this invention is almost void-free, and characterization results show that silicon dioxide is not present.

[0032] 3. In order to solve the problem of thermal stress, the present invention adopts hollow interconnected metal pillars, which can effectively avoid failure caused by thermal stress during hot annealing process and high-temperature application scenarios during service, resulting in failure of electrical performance or failure caused by heat exchange structure damage.

[0033] 4. To address the issue of high bonding thermal resistance and impeded heat dissipation caused by the traditional high thickness and small bonding area of ​​the eutectic bonding layer in the modular integration of cooling and active heating cores, this invention redesigns the bonding pad layer, reducing the thickness of the bonding pad layer on one side to less than 500 nm. A hollow ring structure is formed outside the first and second pads, and a large area of ​​bonding metal is formed outside the hollow ring structure and the fluid inlet and outlet areas. High-vacuum surface activation bonding technology is used to make the hollow ring structure vacuum insulated. This ensures the electrical insulation performance of the bonding layer while greatly reducing the thermal resistance of the bonding layer. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings of the embodiments of the present invention will be briefly described below. Obviously, the drawings described below only relate to some embodiments of the present invention and are not intended to limit the present invention. Wherein: Figure 1 A schematic diagram showing the connection between the microchannel layer and the first interconnect unit of the active cooling core particle is shown; Figure 2 A cross-sectional view showing the distribution of microfluidic channels within the active cooling core is shown. Figure 3 The diagram shows the structure of the bonding region with different morphologies in the actively cooled core particles; Figure 4 A cross-sectional view of the first deposition hole of the actively cooled core particle is shown; Figure 5 A diagram showing the formation process of the first interconnecting unit of the actively cooled core is shown; Figure 6 An overall cross-sectional view of the active cooling core is shown; Figure 7 An axial cross-sectional view of the first interconnecting unit of the actively cooled core is shown; Figure 8 A radial cross-sectional view of the first interconnecting unit of the actively cooled core is shown; Figure 9 A schematic diagram showing the ratio of the pads to the insulating ring of the active cooling core is shown; Figure 10 The distribution diagrams of the first and second activation regions of the actively cooled core particles are shown. Figure 11 A diagram showing the bonding region distribution of the actively cooled core particles is presented; Figure 12 A flow chart of the microchannel layer fabrication process for the active cooling core particle is shown; Figure 13 A process flow diagram for the fabrication of the remaining structure of the actively cooled core particle is shown; Figure 14 The fluid inlet and outlet distribution diagram of the active cooling core is shown; Figure 15 A diagram showing the bonding of the actively cooled core particles is provided. Figure 16 The image shows a high-precision ultrasonic scanning result of the microfluidic channel; Figure 17 The diagram shows the bonding situation between the first and second activation regions; Figure 18 The image shows an actual etched wafer with grooved and microneedle-ribbed microchannel heat transfer enhancement structures; Figure 19 An enlarged view of the deformation zone of the actively cooled core is shown; Figure 20 A schematic diagram of the active cooling core and the three-dimensional chip integration is shown. Detailed Implementation

[0035] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0036] The terminology used in this invention is that which is currently widely used in the art in consideration of the function of the invention; however, these terms may vary according to the intent of those skilled in the art, precedent, or new technology in the art. Furthermore, specific terms may be chosen by the applicant, and in such cases, their detailed meanings will be described in the detailed description of the invention. Therefore, the terms used in this specification should not be construed as simple names, but rather based on their meanings and the overall description of the invention.

[0037] Example 1

[0038] Reference Figures 1 to 11 This is the first embodiment of the present invention, which provides an active cooling chip C. Its core function is to provide near-junction heat dissipation for active chips in a three-dimensional integrated chip, while simultaneously achieving efficient electrical interconnection with the active chips. The active cooling chip C includes a microchannel layer 100, which serves as the core carrier for heat dissipation. At least one set of microfluidic grooves A are formed within the microchannel layer 100 for the flow of cooling fluids, such as deionized water or fluorinated liquid, to remove heat. An interconnection region D is provided on the microchannel layer 100, which is used to fabricate electrical interconnection structures.

[0039] The interconnection area D is located within the microfluidic channel A area or between microfluidic channels A. Furthermore, the location of the interconnection area D has been optimized for spatial compatibility, and it can be flexibly located within the microfluidic channel A area, such as the reserved area on the side wall or bottom of the channel, or in the gap area between microfluidic channels A, which avoids occupying extra space and ensures that the subsequent interconnection structure and heat dissipation channel do not interfere with each other.

[0040] The first interconnect unit 200, namely the through silicon via (TSV), is responsible for transmitting electrical signals. The first interconnect unit 200 is located in the interconnect area D and is vertically connected to the upper and lower surfaces of the microchannel layer 100 to realize cross-layer electrical interconnection.

[0041] The first interconnect unit 200 has a deformation zone B, which is a hollow structure, used to alleviate the thermal stress caused by the difference in thermal expansion coefficients between the first interconnect unit 200 and the microchannel layer 100, and to prevent structural cracking or electrical performance failure.

[0042] Several sets of microfluidic channels A are interconnected, or several sets of microfluidic channels A are relatively independent.

[0043] A first deposition hole D1 for preparing the first interconnect unit 200 is provided in the interconnect region D. The radial cross-sectional shape of the first deposition hole D1 is circular. The circular structure can make the subsequent coating thickness more uniform and reduce stress concentration points.

[0044] The first deposition hole D1 has an insulating layer, a barrier layer and a first seed layer deposited sequentially from the hole wall toward the axis; the first interconnect unit 200 is formed by electrochemical deposition of the first seed layer.

[0045] Specifically, the insulating layer is preferably silicon dioxide or silicon nitride to achieve electrical insulation between the first interconnect unit 200 and the microchannel layer 100; the barrier layer is preferably TiN or TaN to prevent metal ions from diffusing and contaminating the silicon substrate; the first seed layer is preferably Cu or Au to provide a conductive substrate for subsequent electrochemical deposition; the first interconnect unit 200 is formed by growing the first seed layer through an electrochemical deposition process, which can ensure the density of metal filling and reduce interconnect resistance.

[0046] The initial form of the first interconnect unit 200 is a blind hole structure with one end open and the other end closed. A deformation zone B is formed inside the first interconnect unit 200 at the open end. A soft adhesive is subsequently filled in to further optimize the stress buffering effect. After fabrication, the first interconnect unit 200 is a solid structure with both ends closed and the interior filled with soft adhesive, and the deformation zone B is enclosed within the first interconnect unit 200.

[0047] The length of the first interconnect unit 200 is greater than the thickness of the microchannel layer 100. The top and bottom protruding ends of the unit are respectively fixedly provided with a first pad 201 and a second pad 202. The protruding end design can ensure that the pads form a stable connection with the surface of the microchannel layer, and at the same time facilitate docking with the active chips of the upper and lower layers.

[0048] The microchannel layer 100 has a first welding area 203 and a second welding area 204 on its upper and lower surfaces, respectively, in areas other than the first pad 201 and the second pad 202. The welding area provides a large area of ​​metal contact for the bonding of the active cooling core C and the active core, thereby reducing the bonding thermal resistance.

[0049] The surface of the first pad 201 is flush with the surface of the first soldering area 203, and the surface of the second pad 202 is flush with the surface of the second soldering area 204. The flush design can ensure uniform force during bonding and avoid bonding voids or poor contact caused by height differences.

[0050] An insulating ring 201a is provided between the first pad 201 and the first welding area 203. The insulating ring 201a is also provided between the second pad 202 and the second welding area 204. The insulating ring 201a is an annular vacuum groove to prevent short circuits between electrical signals and the bonding area.

[0051] The first welding area 203 and the second welding area 204 have fluid inlets and outlets at corresponding positions in the microfluidic tank A. The fluid inlets and outlets are precisely connected to the microfluidic tank A to ensure that the cooling fluid can smoothly enter and exit the flow channel, while avoiding mutual interference with the metal structure of the welding area.

[0052] An insulating medium E is provided between the first welding area 203, the second welding area 204 and the microchannel layer 100. The insulating medium E is preferably silicon dioxide. The insulating medium E can further enhance the electrical insulation between the welding area and the microchannel layer 100, and at the same time improve the structural stability of the welding area.

[0053] The thickness of the first interconnect unit 200 on one side is β, and the aperture of the deformation region B is α. The ratio of β to α ranges from 1:10 to 2:5. This ratio range has been optimized through mechanical and electrical simulations: it ensures that the first interconnect unit 200 has a small integrated resistance to support the electrical interconnection function, and it also ensures that the deformation region B has sufficient space to buffer thermal stress, avoiding insufficient buffering due to an excessively small ratio or structural fragility due to an excessively large ratio.

[0054] The thickness of the insulating ring 201a on one side is φ, and the outer diameter of the first pad 201 and the second pad 202 is γ. The ratio of φ to γ ​​is in the range of 1:10 to 3:10. This ratio can minimize the space occupied by the insulating ring 201a while ensuring the insulation effect, so as to reserve a larger area for the welding area and reduce the bonding thermal resistance.

[0055] Example 2

[0056] Reference Figures 1 to 19 This is the second embodiment of the present invention. This embodiment differs from the first embodiment in that it provides a method for preparing an actively cooled core particle C. This method is designed around the principles of "precise structural forming, reliable bonding and electrical interconnection integration, and stable performance," and specifically includes the following steps: Photoresist is spin-coated onto the surface of the first silicon wafer. After a standard photolithography process (including photoresist coating, pre-baking, exposure, development, and post-baking) and deep silicon etching, a microfluidic groove A with a preset pattern is formed on the first silicon wafer. After etching, a special photoresist remover solution is used to remove the remaining photoresist to ensure that there are no residual impurities on the inner wall of the microfluidic groove A, so as to avoid affecting the subsequent cooling fluid flow or bonding quality.

[0057] Among them, the first silicon wafer region outside the microfluidic trench A forms the bonding region Q. The bonding region Q is reserved for the subsequent fabrication of the first interconnect unit 200 (TSV). Its area and position need to be planned in advance according to the layout of the microfluidic trench A and the electrical interconnection requirements.

[0058] It should be noted that the area of ​​interconnect region D is smaller than the area of ​​bonding region Q. Interconnect region D is the area where the first interconnect unit 200 is located, and bonding region Q is the area where the first silicon wafer and the second silicon wafer are bonded. Therefore, the area of ​​bonding region Q is larger than that of interconnect region D.

[0059] Surface activation is performed on the bonding region Q and the upper surface of the second silicon wafer (used to seal the microfluidic groove A to form a closed flow channel) to form the first activation region H1 and the second activation region H2 respectively. The first activation region H1 and the second activation region H2 are bonded together to seal and form a microchannel layer 100, thus avoiding the silicon dioxide buried layer formed in the traditional Si-Si direct bonding process.

[0060] Specifically, the first activation region H1 and the second activation region H2 are tightly bonded together through a bonding process to achieve the sealing of the microfluidic groove A and form a complete microchannel layer 100. The sealing effect directly affects whether the cooling fluid leaks, so the bonding process parameters must be strictly controlled to avoid voids.

[0061] It should be noted that, due to the use of the above-mentioned microchannel etching and bonding methods, the presence of buried silicon dioxide layers on the bonding surface can be avoided, which is beneficial for the etching of the first deposition hole D1 and the subsequent filling of the conductive metal layer.

[0062] The upper surface of the microchannel layer 100 is thinned by a combination of mechanical grinding and chemical polishing to achieve the design thickness of the microchannel layer 100, which is preferably 150~400μm in this embodiment. The bonding region Q is etched by DRIE (deep silicon etching) process to form the first deposition hole D1. The etching process needs to control the etching rate and perpendicularity to ensure that the aspect ratio of the first deposition hole D1 meets the requirements of the subsequent coating.

[0063] An insulating layer, a barrier layer, and a first seed layer are deposited sequentially in the first deposition hole D1 using sputtering or PECVD (plasma-enhanced chemical vapor deposition) processes. The thickness of each layer needs to be precisely controlled to balance insulation, anti-diffusion, and conductivity. Electrochemical deposition is then performed based on the first seed layer to grow and form the first interconnect unit 200. After deposition, the first interconnect unit 200 is filled with a soft adhesive. During the filling process, air bubbles must be avoided to ensure stress buffering effect.

[0064] After the soft adhesive is filled and cured, the upper surface of the microchannel layer 100 is thinned and polished using a chemical mechanical polishing (CMP) process to remove excess soft adhesive outside the deformation area until the insulating medium E is exposed. Then, a barrier layer and a second seed layer are deposited sequentially on the insulating layer on the upper surface of the microchannel layer 100. After electrochemical deposition of the second seed layer, chemical mechanical polishing is performed to make the surface flatness meet the bonding requirements (typically surface roughness <0.5nm). Subsequently, after patterning by a standard photolithography process, the first pad 201, the insulating ring 201a, and the first welding area 203 are etched. The pad pattern needs to match the active chip pads to be connected later. Fluid inlets and outlets are opened on the first welding area 203. The depth of the fluid inlets and outlets is etched to the position of the insulating layer without penetrating the microchannel layer 100 to form the chip preform M.

[0065] The carrier piece is temporarily bonded to the upper surface of the first pad 201 using a temporary bonding method, providing support for the subsequent thinning of the lower surface of the microchannel layer 100 and preventing structural deformation. The lower surface of the microchannel layer 100 is thinned to a preset thickness, exposing the lower metal of the first interconnect unit 200. The exposed length must meet the requirements for the subsequent fabrication of the second pad 202. The second pad 202, the insulating ring 201a, the second welding area 204, and the fluid inlet and outlet within the second welding area 204 are fabricated using the same photolithography and etching processes as the first pad 201, ensuring the consistency of the upper and lower pads.

[0066] In the temporary bonding method, thermally release adhesive or water-soluble adhesive is preferably used as the temporary bonding medium, and the carrier sheet is preferably made of glass or silicon wafer.

[0067] The carrier sheet is debonded by heating or dissolving the temporary bonding medium, and the fluid inlet and outlet in the first welding area 203 and the second welding area 204 are further etched to the position of communicating with the microfluidic groove A in the microchannel layer 100. The aperture of the inlet and outlet needs to match the external fluid pipeline, and finally an active cooling core C that can be directly used for integration is formed.

[0068] Both the first and second silicon wafers are double-polished silicon wafers with a surface roughness of less than 0.5nm. The high flatness of the surface is the basis for ensuring that subsequent bonding is void-free and the microfluidic groove A dimension is accurate.

[0069] The photoresist spin-coated on the surface of the first silicon wafer is AZ4620. This type of photoresist has high resolution and good etching resistance, making it suitable for the fine patterning of microfluidic trench A. The spin-coating speed of the spin coater is 2500 r / min, and the spin-coating time is 30 s. These parameters allow the photoresist thickness to be uniformly controlled within the range of 2~3 μm. After spin-coating, the substrate is baked at 100℃ for 5 min to remove the solvent from the photoresist and enhance the adhesion between the photoresist and the silicon wafer. The designed microchannel structure pattern is then exposed using a photolithography machine. The exposure dose needs to be adjusted according to the photoresist thickness. After exposure, development is performed to remove the photoresist in the unexposed areas, forming the pattern of microfluidic trench A.

[0070] Furthermore, the designed microchannel structure pattern is exposed and developed using a photolithography machine, and then heated to 110°C and held for 5 minutes to further enhance the etching resistance of the photoresist.

[0071] Microchannels are etched using deep silicon etching, with a depth range of 50~300μm. The specific depth needs to be determined based on heat dissipation requirements: deeper etching is chosen when the heat flux density is high (to increase the channel volume), and shallower etching is chosen when the heat flux density is low (to reduce material consumption). After etching, acetone and isoacetone solutions are used for photoresist removal and cleaning. The two solutions can dissolve the photoresist matrix and residual small molecules respectively, ensuring thorough photoresist removal.

[0072] The first activation region H1 and the second activation region H2 are prepared using the following steps. The core of this process is to remove the surface oxide layer and impurities to form a highly active surface to achieve silica-free bonding: First, the etched first and second silicon wafers are ultrasonically cleaned sequentially for 10 minutes each with acetone, anhydrous ethanol, and deionized water, and then dried with nitrogen gas for later use. It should be noted that nitrogen gas must be used to dry the wafers after each cleaning step to avoid cross-contamination. Acetone is used to remove photoresist residue, anhydrous ethanol is used to remove acetone, and deionized water is used to remove water-soluble impurities, ultimately ensuring that there is no organic matter or particulate contamination on the surface of the silicon wafers.

[0073] Next, the cleaned first and second silicon wafers are placed on the fixtures inside the cavity. These fixtures are professional-grade and ensure the wafers are flat and securely fixed. The cavity is then sealed and evacuated to a vacuum level of 10. -6 The Pa level and high vacuum can prevent air molecules from forming voids at the bonding interface and prevent secondary oxidation of the surface.

[0074] Then, the bonding region of the first silicon wafer and the upper surface of the second silicon wafer are activated using an Ar ion beam for 180s to 420s. The Ar ion beam energy is 0.6 to 1keV. The Ar ions remove the natural oxide layer (silicon dioxide) on the surface of the silicon wafer through physical bombardment and form a fresh Si active layer on the surface, laying the foundation for subsequent covalent bonding. The beam current and irradiation time must be matched: when the beam current is high, the time should be shortened to avoid excessive bombardment that would cause surface roughness; when the beam current is low, the time should be extended to ensure that the oxide layer is completely removed.

[0075] Finally, the first and second silicon wafers are bonded together by applying pressure from above and below using a bonding machine. The bonding time is 250s and the bonding pressure is 0.6~1.2MPa. The combination of pressure and time can promote the formation of Si-Si covalent bonds, ensure the bonding strength, and at the same time avoid excessive pressure that could cause the silicon wafer to crack or the microfluidic groove A to deform.

[0076] Furthermore, the first interconnect unit 200 is prepared by electrochemical deposition. The first interconnect unit 200 is made of metal, and the metal is at least one of Cu and Au. Cu has the advantages of high conductivity (low resistivity) and low cost, and is suitable for general electrical interconnection scenarios. Au has excellent corrosion resistance and reliability, and is suitable for high-requirement scenarios (such as automotive or aerospace chips).

[0077] Electrochemical deposition was performed on the first deposition hole D1 using an electrochemical workstation. The electrochemical deposition solution was copper methanesulfonate, which has the characteristics of high stability and low toxicity. The deposited Cu grains are fine and dense. The current density was 0.3~0.6 ASD. Too low a current density would result in slow deposition speed and low efficiency, while too high a current density would easily lead to rough coating and pinholes. The electrochemical deposition time was 15~30 min, and the specific time was determined according to the depth and diameter of the first deposition hole D1 to ensure that the metal completely filled the through hole. The temperature was 25℃ to avoid changes in solution composition or damage to the silicon wafer caused by high temperature.

[0078] After electrochemical deposition, the first interconnect unit 200 is annealed in a vacuum environment. The core purpose of annealing is to eliminate the internal stress generated during the deposition process and improve the density and conductivity of the coating. The specific steps are as follows: the silicon wafer is heated from room temperature to 400°C in a vacuum furnace at a slow heating rate of 5°C / min. The slow heating can avoid the additional stress caused by sudden temperature changes. After holding at 400°C for 30 to 90 minutes, it is allowed to cool naturally. The holding time needs to be adjusted according to the coating thickness. When the coating is thick, the holding time is extended to ensure that the stress is fully released. After the holding time is completed, it is allowed to cool naturally to room temperature to avoid stress re-accumulation caused by rapid cooling.

[0079] The deformation zone B is sealed and filled with a flexible adhesive using a vacuum-assisted filling process. The flexible adhesive is one of the following: benzocyclobutene resin (BCB), polydimethylsiloxane (PDMS), and epoxy resin. BCB has excellent high-temperature resistance and insulation properties, making it suitable for high-temperature service scenarios. PDMS has good elasticity and excellent stress buffering effect, making it suitable for scenarios with frequent thermal cycling. Epoxy resin has high bonding strength and low cost, making it suitable for general scenarios.

[0080] The filling process consists of three steps: First, the adhesion promoter AP3000 is filled into the deformation zone B through a 2-minute vacuum treatment to enhance the bonding force between the soft adhesive and the metal. The vacuum environment ensures that the promoter fully penetrates to the bottom of the deformation zone B. Then, the adhesive is spin-coated at 500 rpm for 6 seconds and 3000 rpm for 40 seconds on a spin coater, and then baked at 95°C for 10 minutes to form a thin adhesion promoter layer. Baking removes the solvent in the promoter.

[0081] Then, in a vacuum chamber, the flexible adhesive is filled into the deformation zone B of the metal in the through-silicon via. The vacuum environment can prevent air bubbles from entering. The initially thick flexible adhesive layer is thinned and smoothed by spin coating at 500 rpm for 6 seconds and at 1000 rpm for 40 seconds, ensuring that the flexible adhesive fills the deformation zone B evenly.

[0082] Finally, the flexible adhesive is cured in a nitrogen atmosphere at 250℃ for 60–120 minutes. The nitrogen atmosphere prevents oxidation of the flexible adhesive. The curing time needs to be adjusted according to the type of flexible adhesive to ensure complete curing and to provide stress buffering. After filling and curing, excess flexible adhesive outside the deformation zone is removed using chemical mechanical polishing.

[0083] During the process of depositing the insulating layer in the first deposition hole D1, the insulating layer covers the upper surface of the microchannel layer 100 by controlling the sputtering angle and range, forming the insulating medium E. This design can reduce a separate process of depositing the insulating medium E, simplify the process flow, and at the same time ensure the continuity and consistency of the insulating layer.

[0084] After the soft adhesive is filled and cured, the upper surface of the microchannel layer 100 is thinned and polished using a chemical mechanical polishing (CMP) process to remove excess soft adhesive outside the deformation zone until the insulating medium E is exposed.

[0085] Specifically, the first pad 201 and the first welding area 203 are prepared by the following method: a second seed layer is further sputtered on the upper surface of the insulating medium E. The second seed layer grows and completely covers the surface of the insulating medium E and communicates with the metal in the first deposition hole D1. The metal layer formed after electrochemical deposition is thinned by chemical mechanical polishing to a final thickness of 200-500 nm and the surface roughness is ensured to be <0.5 nm. Subsequently, an insulating ring 201a is coaxially formed at the corresponding position of the first deposition hole D1 by photolithography and etching processes. The insulating ring 201a is an annular vacuum groove. The metal area inside the insulating ring 201a is defined as the first pad 201, and the metal area outside the insulating ring 201a is defined as the first welding area 203. The insulating ring 201a makes the first pad 201 insulated from the external vacuum.

[0086] After thinning the lower surface of the microchannel layer 100 to expose the metal at the lower end of the first interconnect unit 200, an insulating layer is deposited on the lower surface of the microchannel layer 100 by PECVD or ALD method to form an insulating medium E consistent with the upper surface.

[0087] Among them, PECVD has a fast deposition rate and is suitable for large-area deposition, while ALD has precise control over deposition thickness and high step coverage.

[0088] The corresponding position of the first deposition hole D1 on the lower surface of the microchannel layer 100 is etched by photolithography and etching process, and a third seed layer is deposited on the surface of the insulating medium E. The third seed layer is electrochemically deposited on the lower surface. The third seed layer passes through the leakage hole and communicates with the first seed layer, and completely covers the surface of the insulating medium E on the lower surface to ensure conductivity continuity.

[0089] An insulating ring 201a is coaxially formed at the position corresponding to the first deposition hole D1 on the surface of the insulating medium E below. The inner area of ​​the insulating ring 201a is the second pad 202, and the outer area of ​​the insulating ring 201a is the second welding area 204. The structure of the lower surface is symmetrical with that of the upper surface to ensure consistency when bonding with the active core in the future.

[0090] Before the second and third seed layers completely cover the upper and lower surfaces of the microchannel layer 100, a barrier layer is sputtered onto the upper and lower surfaces of the microchannel layer 100 using magnetron sputtering. The barrier layer is used to enhance the bonding force between the first seed layer and the insulating medium E, prevent the seed layer from falling off during subsequent processes or service, and prevent Cu atoms from diffusing into the silicon layer during high-temperature processing or high-temperature applications.

[0091] The barrier layer is made of at least one of Cr and Ti, with a thickness of 20-30 nm. Cr has strong adhesion to silicon and the insulating layer, while Ti has excellent anti-diffusion properties. If the thickness is too thin, the adhesion will be insufficient, while if it is too thick, it may affect the conductivity or increase the thermal resistance. The second and third seed layers covering the upper and lower surfaces of the microchannel layer 100 are made of at least one of Cu and Au, with a thickness of 200-500 nm. This thickness can ensure that the conductivity of the seed layer meets the requirements of electrochemical deposition, while avoiding surface flatness problems caused by excessive thickness.

[0092] The remaining structure is the same as that in Example 1.

[0093] Example 3

[0094] Reference Figures 1 to 20 This is the third embodiment of the present invention. This embodiment differs from the second embodiment in that it provides a packaging method for an active cooling chip and a three-dimensional integrated chip. This method focuses on "low-resistance bonding, high-efficiency integration, and heat dissipation-electrical interconnection synergy." Its core is to integrate the active cooling chip C and the active chip 300 through a standardized interface. It includes the aforementioned active cooling chip C and its preparation method, and further includes the following steps: The first pad 201 and the second pad 202 are bonded and integrated with the fluid pads and electrical signal interface pads of the active core 300 to be cooled on the upper and lower layers respectively by a high vacuum surface activation bonding method.

[0095] Specifically, the high vacuum environment can prevent voids from forming at the bonding interface and improve the vacuum insulation of the insulating ring 201a. The surface activation treatment can remove the oxide layer and impurities on the surface of the pads, ensuring direct metal-to-metal bonding and significantly reducing bonding resistance and thermal resistance.

[0096] Furthermore, during bonding, it is necessary to ensure that the first pad 201 is precisely aligned with the electrical signal interface pad of the active chip 300 (to achieve electrical interconnection), the first soldering area 203 is aligned with the fluid pad and mechanical support pad of the active chip 300 (to ensure unobstructed cooling fluid pathways), the second pad 202 is aligned with the electrical signal interface pad of the lower active chip 300, and the second soldering area 204 is aligned with the continued support pad of the lower active chip 300, ultimately forming a three-dimensional stacked structure of "active chip - active cooling chip - active chip" to achieve coordinated heat dissipation and electrical interconnection of multiple chips.

[0097] The remaining structure is the same as that in Example 2.

[0098] Finally, it should be noted that the methods and devices described in detail above are merely embodiments, and those skilled in the art can modify these embodiments in different ways as long as they do not depart from the scope of the present invention.

Claims

1. An active cooling core (C), characterized in that: include, A microchannel layer (100) is provided, wherein at least one set of microfluidic grooves (A) are formed in the microchannel layer (100), and an interconnection area (D) is provided on the microchannel layer (100). The interconnection area (D) is located within the microfluidic channel (A) region or between the microfluidic channels (A); The first interconnection unit (200) is disposed within the interconnection area (D) and connects the upper and lower surfaces of the microchannel layer (100); The first interconnection unit (200) has a deformation region (B).

2. The active cooling core according to claim 1, characterized in that: Several groups of microfluidic channels (A) are interconnected, or several groups of microfluidic channels (A) are relatively independent.

3. The active cooling core according to claim 2, characterized in that: A first deposition hole (D1) is provided in the interconnection area (D), and the radial cross-sectional shape of the first deposition hole (D1) is circular.

4. The active cooling core according to claim 3, characterized in that: The first deposition hole (D1) has an insulating layer, a barrier layer and a first seed layer deposited sequentially from the hole wall toward the axis; The first interconnect unit (200) is formed by electrochemical deposition of a first seed layer.

5. The active cooling core according to any one of claims 1 to 3, characterized in that: The first interconnecting unit (200) is closed at both ends and hollow inside to form the deformation zone (B).

6. The active cooling core according to any one of claims 1 to 3, characterized in that: The first interconnect unit (200) is longer than the thickness of the microchannel layer (100), and its top and bottom protruding ends are respectively fixedly provided with a first pad (201) and a second pad (202).

7. The active cooling core according to claim 6, characterized in that: The microchannel layer (100) has a first soldering area (203) and a second soldering area (204) on its upper and lower surfaces, in areas other than the first solder pad (201) and the second solder pad (202). The surface of the first pad (201) is flush with the surface of the first soldering area (203), and the surface of the second pad (202) is flush with the surface of the second soldering area (204).

8. The active cooling core according to claim 7, characterized in that: An insulating ring (201a) is provided between the first pad (201) and the first welding area (203), and the insulating ring (201a) is also provided between the second pad (202) and the second welding area (204); The first welding area (203) and the second welding area (204) have fluid inlets and outlets at corresponding positions in the microfluidic tank (A).

9. The active cooling core according to claim 8, characterized in that: An insulating medium (E) is provided between the first welding area (203) and the second welding area (204) and the microchannel layer (100).

10. The active cooling core according to any one of claims 1-3 and 7-9, characterized in that: The thickness of the first interconnect unit (200) on one side is β, the aperture of the deformation region (B) is α, and the ratio of β to α is in the range of 1:10 to 2:

5.

11. The active cooling core according to claim 8 or 9, characterized in that: The insulating ring (201a) has a thickness of φ on one side, and the outer diameter of the first pad (201) and the second pad (202) is γ. The ratio of φ to γ ​​is in the range of 1:10 to 3:

10.

12. A method for preparing an actively cooled core particle (C), characterized in that: Includes the following steps, Photoresist is spin-coated onto the upper surface of the first silicon wafer. After standard photolithography and deep silicon etching, a microfluidic trench (A) is formed on the first silicon wafer, and the remaining photoresist is removed. The first silicon wafer region outside the microfluidic groove (A) forms a bonding region (Q); Surface activation is performed on the bonding region (Q) and the upper surface of the second silicon wafer to form a first activation region (H1) and a second activation region (H2) respectively. The first activation region (H1) and the second activation region (H2) are bonded together and sealed to form a microchannel layer (100). The upper surface of the microchannel layer (100) is thinned, the bonding region (Q) is etched and a first deposition hole (D1) is formed; an insulating layer, a barrier layer and a first seed layer are deposited in the first deposition hole (D1) in sequence, an annealing process is performed, and electrochemical deposition is performed to form the first interconnect unit (200). The first interconnect unit (200) is filled with soft adhesive and chemically mechanically polished to the insulating layer. A barrier layer and a second seed layer are deposited sequentially on the insulating layer on the upper surface of the microchannel layer (100). After electrochemical deposition of the second seed layer, chemical mechanical polishing is performed, and after patterning by standard photolithography, a first pad (201), an insulating ring (201a), and a first welding area (203) are etched. A fluid inlet and outlet are opened on the first welding area (203), and the depth of the fluid inlet and outlet is etched to the position of the insulating layer. The carrier sheet is temporarily bonded to the upper surface of the first pad (201) by temporary bonding method, and the lower surface of the microchannel layer (100) is thinned to expose the metal at the lower end of the first interconnect unit (200). The barrier layer and the third seed layer are deposited in the same way as the first pad (201), and the second pad (202), the insulating ring (201a), the second welding area (204) and the fluid inlet and outlet in the second welding area (204) are prepared. Unbond the carrier sheet, etch the fluid inlet and outlet in the first welding area (203) and the second welding area (204) to the position where they communicate with the microfluidic groove (A) in the microchannel layer (100) to form an active cooling core (C).

13. The method for preparing the actively cooled core according to claim 12, characterized in that: The first and second silicon wafers are double-polished silicon wafers with a surface roughness of less than 0.5 nm.

14. The method for preparing the actively cooled core according to claim 12 or 13, characterized in that: The photoresist spin-coated on the upper surface of the first silicon wafer is AZ4620. The spin-coating speed of the spin coater is 2500 r / min, the spin-coating time is 30s, and after spin-coating, it is baked at 100℃ for 5min. The designed microchannel structure pattern is exposed and developed using a photolithography machine, and then heated to 110℃ for 5min. Microchannels are etched using deep silicon etching methods, with a depth range of 50~300μm; After etching, acetone and isoacetone solutions are used for desizing and cleaning.

15. The method for preparing the actively cooled core according to claim 14, characterized in that: The first activation region (H1) and the second activation region (H2) are prepared using the following steps: First, the etched first and second silicon wafers are ultrasonically cleaned for 10 minutes in sequence with acetone, anhydrous ethanol and deionized water, and then dried with nitrogen gas for later use. Next, the cleaned first and second silicon wafers are placed on fixtures inside the cavity, the cavity is sealed, and a vacuum of 10⁻⁶ is applied. -6 Pa level; Then, the bonding region of the first silicon wafer and the upper surface of the second silicon wafer were activated using an Ar ion beam for 180s to 420s, with an Ar ion beam energy of 0.6 to 1keV. Finally, the first and second silicon wafers are bonded together by applying pressure from above and below using a bonding machine. The bonding time is 250 seconds and the bonding pressure is 0.6~1.2 MPa.

16. The method for preparing the actively cooled core according to claim 15, characterized in that: The first interconnect unit (200) is prepared by electrochemical deposition. The first interconnect unit (200) is made of metal, and the metal is at least one of Cu and Au. Electrochemical deposition was performed on the first deposition well (D1) using an electrochemical workstation. The electrochemical deposition solution was copper methanesulfonate, the current density was 0.3~0.6 ASD, the electrochemical deposition time was 15~30 min, and the temperature was 25℃. After electrochemical deposition, the first interconnect unit (200) is annealed in a vacuum environment. The specific steps are as follows: the silicon wafer is heated from room temperature to 400°C in a vacuum furnace at a heating rate of 5°C / min, and then naturally cooled after being kept at 400°C for 30 to 90 minutes.

17. The method for preparing the actively cooled core according to any one of claims 12, 13, 15 and 16, characterized in that: The deformation zone (B) is sealed and filled with a soft adhesive using a vacuum-assisted filling process. The soft adhesive is one of benzocyclobutene resin, polydimethylsiloxane, and epoxy resin.

18. The method for preparing the actively cooled core according to claim 17, characterized in that: During the sputtering deposition of the insulating layer inside the first deposition hole (D1), the insulating layer covers the upper surface of the microchannel layer (100) to form the insulating medium (E). A second seed layer is deposited on the surface of the insulating medium (E). The second seed layer grows and completely covers the surface of the insulating medium (E) and communicates with the first seed layer. An insulating ring (201a) is coaxially formed at the position corresponding to the first deposition hole (D1). The insulating ring (201a) is an annular vacuum groove. The inner region of the insulating ring (201a) is the first pad (201), and the outer region of the insulating ring (201a) is the first soldering area (203).

19. The method for preparing the actively cooled core according to claim 18, characterized in that: After thinning the lower surface of the microchannel layer (100) to expose the metal at the lower end of the first interconnect unit (200), an insulating layer is deposited on the lower surface of the microchannel layer (100) by PECVD or ALD method to form the insulating medium (E). The perforation hole is etched at the corresponding position of the first deposition hole (D1) on the lower surface of the microchannel layer (100), and a third seed layer is deposited on the surface of the insulating medium (E). The third seed layer is electrochemically deposited on the lower surface. The third seed layer passes through the perforation hole and communicates with the first seed layer, and completely covers the surface of the insulating medium (E) on the lower surface. An insulating ring (201a) is coaxially formed at the position corresponding to the first deposition hole (D1) on the surface of the insulating medium (E) below. The inner region of the insulating ring (201a) is the second pad (202), and the outer region of the insulating ring (201a) is the second soldering area (204).

20. The method for preparing the actively cooled core according to claim 19, characterized in that: Before the second and third seed layers completely cover the upper and lower surfaces of the microchannel layer (100), a barrier layer is sputtered onto the upper and lower surfaces of the microchannel layer (100) using magnetron sputtering. The barrier layer is made of at least one of Cr and Ti, with a thickness of 20-30 nm. The second and third seed layers covering the upper and lower surfaces of the microchannel layer (100) are made of at least one of Cu and Au, with a thickness of 200-500 nm.

21. A packaging method for an actively cooled chip and a three-dimensional integrated chip, characterized in that: Including the aforementioned active cooling core (C) and its preparation method, the method further includes the following steps: The first pad (201) and the second pad (202) are bonded and integrated with the fluid pads and electrical signal interface pads of the active core particles (300) to be dissipated on the upper and lower layers respectively by the high vacuum surface activation bonding method.

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