Radio frequency transceiver and digital circuit chip level hybrid packaging system

Abstract

The application provides a radio frequency transceiver and digital circuit chip-level hybrid packaging system, which comprises a packaging substrate, a radio frequency transceiver chip and a digital circuit chip, the radio frequency transceiver chip and the digital circuit chip are connected to the top surface of the packaging substrate; the bottom surface of the packaging substrate is divided into a middle region, a ring belt region and a peripheral region from the center to the periphery, the middle region is provided with a middle pad, the peripheral region is provided with a peripheral pad, the radio frequency transceiver chip is electrically connected with one of the middle pad and the peripheral pad, and the digital circuit chip is electrically connected with the other one of the middle pad and the peripheral pad; the ring belt region is distributed with first passive elements. The radio frequency transceiver and digital circuit chip-level hybrid packaging system provided by the application can form an electrical isolation and filter buffer zone between the radio frequency signal and the digital signal through the first passive elements in the ring belt region, so as to reduce the interference and crosstalk between the two types of signals, and improve the stability and reliability of signal transmission.

Description

Technical Field

[0001] This invention belongs to the field of chip-level system packaging technology, specifically relating to a hybrid packaging system for radio frequency transceivers and digital circuits at the chip level. Background Technology

[0002] Traditional System in Package (SIP) for radio frequency (RF) mainly focuses on miniaturizing RF front-end modules. Its package contents usually do not include digital chips such as FPGA, Flash, and DDR, making it difficult to achieve complete system functions such as data acquisition and baseband processing, and it has obvious limitations in terms of functional integration.

[0003] As semiconductor technology continues to approach its physical limits, Moore's Law faces challenges, and the market demand for highly integrated, high-performance computing chips (such as CPUs, GPUs, and FPGAs) is increasing. Integrating multiple chips at the packaging level to achieve system miniaturization, multifunctionality, and high density has become an important way to continue improving integrated circuit performance.

[0004] Currently, hybrid packaging of RF transceiver chips and digital circuit chips has become a technological trend. These microsystems integrate heterogeneous integration concepts, helping to achieve smaller size, higher density, more multifunctionality, and higher performance in electronic systems beyond Moore's Law. However, existing technologies lack effective solutions for hybrid packaging of RF transceiver chips and digital circuit chips. How to effectively ensure signal integrity and suppress mutual interference between RF and digital signals while achieving high-density integration remains a pressing technical challenge. Summary of the Invention

[0005] The hybrid packaging system for radio frequency transceivers and digital circuit chips provided in this invention aims to solve the technical problem that mutual interference between radio frequency signals and digital signals is easily generated when radio frequency transceiver chips and digital circuit chips are packaged together, making it difficult to ensure signal integrity.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is: to provide a hybrid packaging system for radio frequency transceivers and digital circuits at the chip level, comprising: A packaging substrate has an internal interconnection wiring structure; a cap is connected to the top of the packaging substrate, and the cap and the packaging substrate enclose a packaging cavity; and At least one radio frequency transceiver chip and at least one digital circuit chip are respectively connected to the top surface of the packaging substrate and are both located in the packaging cavity. The radio frequency transceiver chip and the digital circuit chip are electrically connected through the interconnection trace structure. The bottom surface of the packaging substrate is divided into a middle area, a ring area and a peripheral area from the center to the outer periphery. The middle area is provided with a central pad and the peripheral area is provided with a peripheral pad. The central pad and the peripheral pad are respectively used for electrical connection with the circuit board. The radio frequency transceiver chip is electrically connected to the central pad through the interconnection trace structure, and the digital circuit chip is electrically connected to the peripheral pad through the interconnection trace structure; or, the radio frequency transceiver chip is electrically connected to the peripheral pad through the interconnection trace structure, and the digital circuit chip is electrically connected to the central pad through the interconnection trace structure. Several first passive components are distributed and connected within the annular region to form signal isolation between the intermediate region and the peripheral region.

[0007] In one possible implementation, the RF transceiver and digital circuit chip-level hybrid packaging system further includes a power chip connected to the top surface of the packaging substrate and located within the packaging cavity. The digital circuit chip includes a computing chip and at least one storage chip, wherein the computing chip and the storage chip are spaced apart and electrically connected through the interconnection trace structure. The power chip is electrically connected to the RF transceiver chip, the computing chip, and the storage chip through the interconnection wiring structure.

[0008] In some embodiments, the hybrid packaging system for radio frequency transceivers and digital circuit chips further includes a plurality of second passive components, which are surface-mounted on the top surface of the packaging substrate and located within the packaging cavity, and the plurality of second passive components are distributed on the outer periphery of the radio frequency transceiver chip.

[0009] In some embodiments, the bottom surfaces of the RF transceiver chip, the digital circuit chip, and the power chip are provided with multiple flip-chip balls, and the top surface of the packaging substrate is provided with multiple flip-chip soldering pads. The flip-chip balls and the flip-chip soldering pads are soldered and fixed in a one-to-one correspondence.

[0010] In one possible implementation, a heat sink is embedded in the top plate of the cover, the heat sink being disposed through the top plate of the cover in a vertical direction, the heat sink being used to dissipate heat from the encapsulation chamber.

[0011] In some embodiments, the top surfaces of both the RF transceiver chip and the digital circuit chip are connected to a heat conductor, which is thermally connected to the heat sink.

[0012] In some embodiments, the thermal conductor is thermal grease or thermal adhesive.

[0013] In some embodiments, the bottom surface of the heat sink is provided with a plurality of downwardly protruding bosses, and the plurality of bosses are respectively provided in correspondence with the radio frequency transceiver chip and the digital circuit chip, and the heat conductor is wrapped around the outer periphery of the bosses.

[0014] In one possible implementation, the packaging substrate is an ABF substrate, the ABF substrate has a plurality of dielectric layers arranged in the vertical direction, the interconnection trace structure includes horizontal traces and vertical traces, the horizontal traces are arranged along the plane of the dielectric layers, and the vertical traces are arranged through the dielectric layers in the vertical direction.

[0015] In one possible implementation, the central pad and the peripheral pad are electrically connected to the circuit board via solder balls, and the connection surface between the solder balls and the circuit board is lower than the bottom surface of the first passive component.

[0016] The beneficial effects of the RF transceiver and digital circuit chip-level hybrid packaging system provided by the present invention are as follows: Compared with the prior art, the RF transceiver and digital circuit chip-level hybrid packaging system of the present invention connects at least one RF transceiver chip and at least one digital circuit chip to the top surface of the same packaging substrate, so that the two types of chips are sealed in the same packaging cavity, and the two types of chips are electrically connected through the interconnection wiring structure inside the packaging substrate, thereby realizing the integrated integration of RF transceiver and digital processing functions, greatly improving the system integration and reducing the overall packaging volume. At the same time, the packaging cavity provides a basic physical protection and electromagnetic shielding environment for the internal chips.

[0017] Based on this, by dividing the bottom surface of the packaging substrate into a middle area, a ring area, and a peripheral area, and setting a central pad and a peripheral pad for external electrical connection in the middle area and the peripheral area respectively, and distributing and connecting the first passive component in the ring area, this layout structure physically separates the external connection interface into two areas, so that the radio frequency signal path and the digital signal path are spatially separated. The first passive component in the ring area can form a certain electrical isolation and filtering buffer between the two paths, thereby helping to reduce interference and crosstalk between the two types of signals and improving the stability and reliability of signal transmission. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1This is a cross-sectional view of a hybrid packaging system for radio frequency transceivers and digital circuits provided in an embodiment of the present invention. Figure 2 A cross-sectional view of the connection between the RF transceiver and digital circuit chip-level hybrid packaging system and the circuit board provided in an embodiment of the present invention (the heat sink adopts another embodiment). Figure 3 This is a top view of the packaging substrate provided in an embodiment of the present invention; Figure 4 This is a bottom view of the packaging substrate provided in an embodiment of the present invention.

[0020] The following are the labeling elements in the figure: 1. Packaging substrate; 11. Middle area; 111. Middle pad; 12. Ring area; 121. First passive component; 13. Peripheral area; 131. Peripheral pad; 14. Flip-chip solder pad; 15. Solder ball; 2. Interconnect trace structure; 3. Cap; 31. Heat sink; 311. Boss; 32. Heat conductor; 4. Packaging chamber; 5. RF transceiver chip; 51. Flip-chip ball; 6. Digital circuit chip; 61. Computing chip; 62. Memory chip; 7. Power chip; 8. Second passive component; 10. Circuit board. Detailed Implementation

[0021] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0022] It should be noted that when an element is referred to as being "set on" another element, it can be directly on the other element or indirectly on the other element. It should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.

[0023] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a number" means two or more, unless otherwise explicitly specified.

[0024] Please refer to the following: Figures 1 to 4 The present invention will now describe the hybrid packaging system for radio frequency transceivers and digital circuits at the chip level. The hybrid packaging system includes a packaging substrate 1, at least one radio frequency transceiver chip 5, and at least one digital circuit chip 6. The packaging substrate 1 has an interconnect wiring structure 2 inside. A cover 3 is connected to the top of the packaging substrate 1, and the cover 3 and the packaging substrate 1 enclose a packaging cavity 4. The radio frequency transceiver chip 5 and the digital circuit chip 6 are respectively connected to the top surface of the packaging substrate 1 and are both located within the packaging cavity 4. The radio frequency transceiver chip 5 and the digital circuit chip 6 are electrically connected through the interconnect wiring structure 2. The bottom surface of the packaging substrate 1 is divided from the center outwards into a central region 11, a ring region 12, and a peripheral region 13. The central region 11 contains… A central pad 111 is provided, and an outer pad 131 is provided in the outer region 13. The central pad 111 and the outer pad 131 are respectively used for electrical connection with the circuit board 10. The RF transceiver chip 5 is electrically connected to the central pad 111 through the interconnection trace structure 2, and the digital circuit chip 6 is electrically connected to the outer pad 131 through the interconnection trace structure 2; or, the RF transceiver chip 5 is electrically connected to the outer pad 131 through the interconnection trace structure 2, and the digital circuit chip 6 is electrically connected to the central pad 111 through the interconnection trace structure 2. A plurality of first passive components 121 are distributed and connected in the ring region 12 to form signal isolation between the central region 11 and the outer region 13.

[0025] The RF transceiver and digital circuit chip-level hybrid packaging system provided in this embodiment, compared with the prior art, connects at least one RF transceiver chip 5 and at least one digital circuit chip 6 to the top surface of the same packaging substrate 1, so that the two types of chips are sealed in the same packaging chamber 4, and the two types of chips are electrically connected through the interconnection wiring structure 2 inside the packaging substrate 1, thereby realizing the integrated integration of RF transceiver and digital processing functions, greatly improving the system integration and reducing the overall packaging volume. At the same time, the packaging chamber 4 provides a basic physical protection and electromagnetic shielding environment for the internal chips.

[0026] Based on this, by dividing the bottom surface of the packaging substrate 1 into a middle region 11, a ring region 12, and a peripheral region 13, and setting a central pad 111 and a peripheral pad 131 for external electrical connection in the middle region 11 and peripheral region 13 respectively, and distributing and connecting a first passive component 121 in the ring region 12, this layout structure physically separates the external connection interface into two regions, so that the radio frequency signal path and the digital signal path are spatially separated. The first passive component 121 in the ring region 12 can form a certain electrical isolation and filtering buffer between the two paths, thereby helping to reduce interference and crosstalk between the two types of signals and improving the stability and reliability of signal transmission.

[0027] In addition, by concentrating the first passive component 121 in the ring area 12 on the bottom surface of the packaging substrate 1, a large amount of additional space is not required on the top surface of the packaging substrate 1. This makes the layout of the RF transceiver chip 5 and the digital circuit chip 6 on the top surface more compact, further improving the integration density of the packaging system. At the same time, it facilitates the interconnection between passive components and chips, reduces the interconnection trace length, and significantly reduces signal loss.

[0028] Specifically, the packaging substrate 1 has a multilayer structure, and the multilayer metal wiring layers inside it are interconnected through through-holes formed by laser or photolithography, thereby forming a high-density interconnect wiring structure 2. This structure needs to be designed with impedance control to meet the transmission requirements of radio frequency and digital signals.

[0029] The cover 3 can be made of metal (such as copper alloy or aluminum alloy) or a ceramic cover plate with a metal coating. Through processes such as brazing or epoxy resin bonding, the four edges of the cover 3 are firmly bonded to the top edge of the packaging substrate 1, thereby forming a sealed packaging chamber 4, which realizes electromagnetic shielding, mechanical protection and dust and moisture protection for the internal chip.

[0030] Both the RF transceiver chip 5 and the digital circuit chip 6 are bare chips and can be micro-assembled onto the top surface of the packaging substrate 1 using a flip-chip bonding process, which helps to reduce the package height. Specifically, the RF transceiver chip 5 can be an RFIC integrating an LNA, PA, and Mixer for generating RF signals; the digital circuit chip 6 can be a GPU, FPGA, ASIC, or processor for generating digital signals.

[0031] The first passive component 121 can specifically be a resistor and a capacitor, which are soldered to the ring area 12 on the bottom surface of the package substrate 1 using surface mount technology (SMT). The resistor and capacitor can be integrated into the circuit configuration of the system as necessary electronic components. Secondly, their physical existence and electrical characteristics can form an isolation band, effectively increasing the spatial distance between the digital signal and the radio frequency signal loop, and absorbing high-frequency noise through filtering and decoupling.

[0032] In some embodiments, see Figure 3 The RF transceiver and digital circuit chip-level hybrid packaging system also includes a power chip 7, which is connected to the top surface of the packaging substrate 1 and located in the packaging chamber 4; the digital circuit chip 6 includes a computing chip 61 and at least one memory chip 62, which are spaced apart and electrically connected through an interconnection trace structure 2; the power chip 7 is electrically connected to the RF transceiver chip 5, the computing chip 61 and the memory chip 62 through the interconnection trace structure 2 respectively.

[0033] The power chip 7 is a bare power management unit chip integrated on the top surface of the packaging substrate 1, and can be micro-assembled using flip-chip bonding. The power input terminal of the power chip 7 is connected to the central pad 111 or the peripheral pad 131 on the bottom of the packaging substrate 1 through the interconnection trace structure 2 to receive raw power from the external circuit board 10. The multiple voltage output terminals of the power chip 7 are connected to the corresponding power pins of the RF transceiver chip 5, the computing chip 61, and the storage chip 62 through the interconnection trace structure 2, respectively, to provide independent, stable, and low-noise operating voltages for each functional chip.

[0034] The computing chip 61 can be a GPU or FPGA, and the storage chip 62 can be a bare DDR, SDRAM, or Flash memory chip. Both can be micro-assembled on a designated area on the top surface of the packaging substrate 1 using flip-chip bonding technology. The data bus, address bus, and control pins of the storage chip 62 are directly connected to the built-in storage controller interface of the computing chip 61 through the interconnection trace structure 2, forming a high-speed data access channel.

[0035] In actual manufacturing, the power distribution network and signal interconnection need to be designed collaboratively at the system level. The layout of the power chip 7 needs to be close to its main power supply target to shorten the power supply loop; the layout between the RF transceiver chip 5, the computing chip 61, and the storage chip 62 needs to meet the timing and length matching requirements of the high-speed interface. All chip interconnections are achieved through the interconnect wiring structure 2 in the packaging substrate 1. The corresponding power integrity, signal integrity, and thermal simulation verifications need to be completed during the design phase before the packaging substrate 1 and the interconnect wiring structure 2 are fabricated.

[0036] For example, Figure 3 A specific arrangement is shown, wherein there are three memory chips 62, and the three memory chips 62 are arranged in the same column on the right side of the packaging substrate 1, and the power chip 7, computing chip 61 and RF transceiver chip 5 are arranged in the same column on the left side of the packaging substrate 1.

[0037] This embodiment integrates the RF transceiver chip 5, the computing chip 61, the storage chip 62, and the power supply chip 7 to achieve a complete functional closed loop and internal power supply in system-level packaging. This minimizes the number of external components and interconnection nodes required by the system, further promoting the miniaturization, high reliability, and lightweighting of the device.

[0038] In some embodiments, see Figure 1 and Figure 3 The RF transceiver and digital circuit chip-level hybrid packaging system also includes several second passive components 8. The second passive components 8 are surface-mounted on the top surface of the packaging substrate 1 and located in the packaging chamber 4. The several second passive components 8 are distributed on the outer periphery of the RF transceiver chip 5.

[0039] The second passive component 8 is a resistor and capacitor that are soldered to the top surface of the packaging substrate 1 using surface mount technology during the packaging assembly process. These resistors and capacitors can be roughly divided into two parts: one part mainly surrounds the RF transceiver chip 5, and the other part is dispersed in the gap area between the computing chip 61 and the storage chip 62.

[0040] The second passive component 8 integrated on the periphery of the RF transceiver chip 5 shortens the transmission path of high-frequency signals, thereby optimizing the electrical performance and signal quality of the RF front end. In addition, integrating multiple second passive components 8 into the package cavity 4 saves space on the system-level circuit board 10, further promoting the compactness of the overall system.

[0041] In some embodiments, see Figure 1 and Figure 3 The bottom surfaces of the RF transceiver chip 5, digital circuit chip 6, and power chip 7 are provided with multiple flip-chip balls 51, and the top surface of the packaging substrate 1 is provided with multiple flip-chip soldering pads 14. The flip-chip balls 51 and flip-chip soldering pads 14 are soldered and fixed in a one-to-one correspondence.

[0042] It should be noted that, Figure 3 The radio frequency transceiver chip 5, computing chip 61, storage chip 62, power chip 7 and second passive component 8 indicated by the reference number all refer to the flip-chip soldering positions of the above-mentioned components, and each position is provided with a corresponding flip-chip soldering pad 14.

[0043] During the micro-assembly process, a high-precision pick-and-place machine picks up and aligns each chip, ensuring that the flip-chip ball 51 on the bottom surface of each chip is precisely aligned with the flip-chip solder pad 14 on the top surface of the packaging substrate 1. Then, soldering is performed in a controlled atmosphere reflow oven. During the reflow process, the flip-chip ball 51 melts and forms an intermetallic compound with the flip-chip solder pad 14 on the packaging substrate 1, thereby achieving a stable mechanical connection and electrical interconnection.

[0044] This embodiment clarifies that all chips on the top surface of the packaging substrate 1 are manufactured using flip-chip bonding, allowing for simultaneous mounting and bonding in a single process. This avoids the complexity and operational difficulties associated with switching process parameters, equipment, and procedures when using different technologies such as flip-chip bonding and wire bonding, significantly simplifying the assembly process and improving production line efficiency and process window consistency. Furthermore, flip-chip bonding ensures that the active surfaces of each chip are facing downwards and tightly bonded to the packaging substrate 1, drastically reducing the overall thickness of the package and meeting the requirements for thinner electronic devices.

[0045] It should be noted that in flip-chip soldering, after the flip-chip ball 51 and flip-chip soldering pad 14 are soldered and fixed, epoxy resin material, i.e. filler, needs to be injected into the gap between each chip and the packaging substrate 1. The filler wraps and seals the solder joints and micro interconnect lines, which plays a protective and isolation role. At the same time, it can buffer stress and improve local heat dissipation, ensuring the long-term stability of the product.

[0046] However, with the increase in chip size and integration, the diameter of the flip chip ball 51 in this embodiment has reached tens of micrometers, and the center-to-center spacing of the flip bonding pads 14 is only hundreds of micrometers. The extremely narrow gaps result in high flow resistance of the colloid, which easily leads to uneven filling or incomplete filling areas. After curing, voids are easily formed, which will become stress concentration points and thermal resistance points, severely weakening the protective effect of the filler.

[0047] Therefore, this embodiment has specifically designed the material properties of the filler in flip-chip bonding. Specifically, the underfiller in this embodiment has a low viscosity, a coefficient of thermal expansion that matches the system, and a suitable glass transition temperature, which can improve the delamination and void phenomenon of the underfiller and enhance the long-term reliability of the interconnect structure.

[0048] First, maintaining a low viscosity before dispensing and curing enhances the flowability and capillary action of the filler in narrow, micron-sized gaps, ensuring that the filler can fully wet and displace air between solder joints, thereby physically reducing the possibility of void formation.

[0049] Secondly, the coefficient of thermal expansion of the cured filler is designed to be as close as possible to the coefficient of thermal expansion of each chip, flip chip ball 51 and packaging substrate 1. This can significantly reduce the thermal stress generated inside or at the interface of the filler due to uneven expansion and contraction of each material during temperature cycling, thereby avoiding cracking or delamination of the filler caused by stress concentration. These cracks and delaminations are often the origin or expansion factors of voids.

[0050] Furthermore, the glass transition temperature of the filler is set in a range higher than the system's maximum operating temperature but lower than the reflow soldering temperature. At the operating temperature, the filler is in a glassy state, providing stable mechanical support; during the assembly and reflow soldering process, it can briefly enter a highly elastic state, releasing some of the process stress and reducing initial interface defects caused by stress.

[0051] In some embodiments, see Figure 1 A heat sink 31 is embedded in the top plate of the cover 3. The heat sink 31 is arranged through the top plate of the cover 3 in the vertical direction. The heat sink 31 is used to dissipate heat from the encapsulation chamber 4.

[0052] In this embodiment, the heat sink 31 is made of a material with high thermal conductivity, such as copper, copper-tungsten alloy, or diamond composite material. The top plate of the cover 3 has a through-hole mounting hole. The heat sink 31 is a flat plate component, embedded in the mounting hole through machining, brazing, or interference fit. The top surface of the heat sink 31 is flush with the top surface of the cover 3, ensuring that it does not increase the overall height of the system. To further enhance the heat dissipation capacity of the heat sink 31, heat dissipation fins, a fan, or a vapor chamber can be added to the top surface of the heat sink 31 to achieve a higher level of heat dissipation design.

[0053] The heat sink 31 is embedded in the top plate of the cover 3, ensuring the overall structural integrity and airtightness of the cover 3. Moreover, as part of the cover 3, the metal material of the heat sink 31 also contributes to the electromagnetic shielding function, significantly enhancing the active heat dissipation capability of the packaging system without sacrificing the original protective performance of the packaging.

[0054] In some embodiments, see Figure 1 The top surfaces of both the RF transceiver chip 5 and the digital circuit chip 6 are connected to a heat conductor 32, which is thermally connected to the heat sink 31.

[0055] The heat conductor 32 is made of a material with high thermal conductivity and can have a certain degree of flexibility or plasticity. When the cover 3 with the heat sink 31 embedded is welded and fixed to the packaging substrate 1, the heat conductor 32 is compressed and filled in the gap between the top surface of each chip and the lower surface of the heat sink 31, and forms a tight, low thermal resistance physical contact with the back of the chip and the surface of the metal heat sink 31. Thus, the heat conductor 32 constructs an efficient heat conduction path between the chip heat source and the heat sink 31, which significantly improves the heat dissipation efficiency.

[0056] In an embodiment where a power chip 7 is also integrated on the packaging substrate 1, a heat conductor 32 is also connected to the top surface of the power chip 7, and a heat conduction channel is established between the heat conductor 32 and the heat sink 31 to ensure the working stability of the power chip 7.

[0057] In some specific embodiments, the thermal conductor 32 is a thermal grease or thermal adhesive. The thermal grease is a paste-like substance composed of a base oil such as silicone oil and a high thermal conductivity filler (such as alumina, zinc oxide, boron nitride, or silver powder), which has advantages such as high thermal conductivity, low adhesion, and good long-term stability. The thermal adhesive is an epoxy resin or silicone resin matrix, also filled with a high thermal conductivity filler, and possesses certain adhesive and curing properties.

[0058] Both thermal grease and thermal adhesive are flexible thermal conductors 32, which can adaptively fill the different gaps between each chip and the heat sink 31, ensuring that each chip can obtain a low thermal resistance heat dissipation connection and maximizing heat dissipation efficiency. At the same time, the soft thermal grease or thermal adhesive can also absorb and buffer the small relative displacement between the chip and the heat sink 31 caused by temperature changes, preventing mechanical damage or interface peeling caused by rigid contact and ensuring package reliability.

[0059] In some embodiments, see Figure 2 The bottom surface of the heat sink 31 is provided with several downward protruding bosses 311. The bosses 311 are respectively set to correspond one-to-one with the radio frequency transceiver chip 5 and the digital circuit chip 6. The heat conductor 32 is wrapped around the outer periphery of the bosses 311.

[0060] During assembly, the heat conductor 32 (such as thermal grease or thermal adhesive) is first spread all over the top surface of the chip. When the heat sink 31 with the protrusion 311 structure is pressed down with the cover 3, each protrusion 311 precisely presses down on the corresponding heat conductor 32 on the top surface of the chip. The cross-sectional dimension of the protrusion 311 is slightly smaller than that of the top surface of the chip. Under pressure, the heat conductor 32 will extend from the contact surface between the protrusion 311 and the chip to the surrounding areas, thus fully wrapping the side walls and root of the protrusion 311, thereby forming a three-dimensional wrapping heat exchange interface.

[0061] In an embodiment where a power chip 7 is also integrated on the packaging substrate 1, the bottom surface of the heat sink 31 is provided with protrusions 311 corresponding to the upper and lower surfaces of the power chip 7, and the heat conductor 32 located on the top surface of the power chip 7 wraps around the outer periphery of the corresponding protrusions 311 to form an all-round heat dissipation interface.

[0062] The heat conductor 32, compressed by the boss 311, can more thoroughly expel interface bubbles, ensuring dense contact and further reducing thermal resistance. Simultaneously, the shape enveloping the sidewall of the boss 311 significantly increases the effective contact area between the heat conductor 32 and the metal heat sink 31, thereby improving overall thermal conductivity. Furthermore, this enveloping structure effectively secures the heat conductor 32, preventing migration, drying, or separation from the interface under long-term thermal cycling or vibration, thus increasing long-term thermal stability.

[0063] In some embodiments, the packaging substrate 1 is an ABF (Ajinomoto Build-up Film) substrate. The ABF substrate has several dielectric layers arranged in the vertical direction. The interconnection trace structure 2 includes horizontal traces and vertical traces. The horizontal traces are arranged along the plane of the dielectric layers, and the vertical traces are arranged through the dielectric layers in the vertical direction.

[0064] The ABF substrate consists of several dielectric layers stacked sequentially in the vertical direction. The main body of the dielectric layer is ABF resin, which is a photosensitive insulating film with excellent insulation, high-frequency characteristics and adhesion. The dielectric layers are firmly bonded together by a hot pressing process.

[0065] Interconnection structure 2 is a three-dimensional network constructed within the aforementioned multi-layer dielectric structure. Specifically, horizontal traces are metal lines (usually copper) fabricated in the plane of each ABF dielectric layer using patterning processes (such as exposure, development, and electroplating). Horizontal traces are responsible for transmitting signals or distributing power within the same planar layer. Vertical traces are formed by creating vias using laser drilling or photolithography, and then electroplating copper inside the vias to create vertical conductive channels. Vertical traces penetrate one or more dielectric layers in the vertical direction, responsible for achieving electrical interconnection between different dielectric layers, thus forming a three-dimensional conductive path from the chip to the bottom pads of the packaging substrate 1.

[0066] Furthermore, in multilayer cabling design, traces carrying radio frequency (RF) signals and traces carrying digital signals are planned and laid out on different, non-adjacent dielectric layers. Additionally, the layout of RF and digital signals can be further refined, such as distributing low-frequency and high-frequency RF signals on different dielectric layers or different areas within the same dielectric layer; and distributing low-speed and high-speed digital signals on different dielectric layers or different areas within the same dielectric layer.

[0067] Specifically, one or more complete dielectric layers without critical signal traces can be specifically set between the RF signal layer and the digital signal layer. These dielectric layers can serve as dedicated ground or power planes to form an effective electromagnetic shielding layer. Furthermore, by rationally planning the paths of vertical traces, long-distance parallel proximity between RF signal vias and digital signal vias in space is avoided, reducing near-field coupling in the vertical direction. These measures achieve three-dimensional signal isolation, fundamentally suppressing crosstalk between different signals.

[0068] ABF substrates possess excellent mechanical strength, thermal stability, and high adhesion to copper conductors. Their multilayer structure exhibits good thermal expansion coefficient matching with the flip-chip bonded to the top surface, helping to reduce overall package warpage and thermal stress. Furthermore, the ABF process is highly compatible with advanced packaging processes such as flip-chip bonding and microvia filling, ensuring the feasibility and yield of large-scale production and providing a reliable guarantee for the industrialization of hybrid packaging systems.

[0069] In some embodiments, see Figure 2 The central pad 111 and the outer pad 131 are electrically connected to the circuit board 10 through solder balls 15, and the connection surface between the solder balls 15 and the circuit board 10 is lower than the bottom surface of the first passive component 121.

[0070] The central pad 111 and peripheral pad 131 on the bottom surface of the packaging substrate 1 are the final electrical output or input ports of the system. After the chip is packaged, the packaging system is connected to the external circuit board 10 (PCB) through the central pad 111 and peripheral pad 131. Specifically, tin-based alloy solder balls 15 are first implanted and reflowed on the central pad 111 and peripheral pad 131, and then electrically connected and mechanically fixed to the corresponding pads on the external circuit board 10 through a secondary reflow soldering process.

[0071] After the solder ball 15 is soldered to the external circuit board 10 and forms a final connection, its connection interface with the circuit board 10 (i.e., the soldering surface between the bottom of the solder ball 15 and the PCB pad) must be lower than the bottom surface of the first passive component 121 on the bottom surface of the packaging substrate 1. This means that when the packaging system is soldered onto the circuit board 10, there will be a clear vertical gap between the first passive component 121 in the ring area 12 and the surface of the circuit board 10. That is, the bottom surface of the first passive component 121 is suspended between the bottom surface of the packaging substrate 1 and the surface of the circuit board 10 and does not contact the circuit board 10.

[0072] By limiting the connection surface between the solder ball 15 and the circuit board 10 to be lower than the bottom surface of the first passive component 121, a safe gap is ensured from a physical structure perspective after the system is mounted. This completely avoids the mechanical interference and short circuit risk between the bottom component of the packaging substrate 1 and the circuit board 10, thus ensuring the mounting success rate and long-term reliability of the packaging system.

[0073] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A hybrid packaging system for radio frequency transceivers and digital circuits at the chip level, characterized in that, include: The packaging substrate (1) has an interconnection wiring structure (2) inside; a cover (3) is connected to the top of the packaging substrate (1), and the cover (3) and the packaging substrate (1) enclose a packaging chamber (4). as well as At least one radio frequency transceiver chip (5) and at least one digital circuit chip (6) are respectively connected to the top surface of the packaging substrate (1) and are both located in the packaging chamber (4). The radio frequency transceiver chip (5) and the digital circuit chip (6) are electrically connected through the interconnection trace structure (2). The bottom surface of the packaging substrate (1) is divided into a middle region (11), a ring region (12) and a peripheral region (13) from the center to the outer periphery. The middle region (11) is provided with a central pad (111), and the peripheral region (13) is provided with a peripheral pad (131). The central pad (111) and the peripheral pad (131) are respectively used for electrical connection with the circuit board (10). The radio frequency transceiver chip (5) is electrically connected to the central pad (111) through the interconnection trace structure (2), and the digital circuit chip (6) is electrically connected to the peripheral pad (131) through the interconnection trace structure (2); or, the radio frequency transceiver chip (5) is electrically connected to the peripheral pad (131) through the interconnection trace structure (2), and the digital circuit chip (6) is electrically connected to the central pad (111) through the interconnection trace structure (2); A plurality of first passive components (121) are distributed and connected within the annular region (12) to form signal isolation between the intermediate region (11) and the peripheral region (13).

2. The hybrid packaging system for RF transceiver and digital circuit chips as described in claim 1, characterized in that, The radio frequency transceiver and digital circuit chip-level hybrid packaging system also includes a power chip (7), which is connected to the top surface of the packaging substrate (1) and located in the packaging chamber (4); The digital circuit chip (6) includes a computing chip (61) and at least one storage chip (62), the computing chip (61) and the storage chip (62) are spaced apart and electrically connected through the interconnection wiring structure (2); The power chip (7) is electrically connected to the radio frequency transceiver chip (5), the computing chip (61) and the storage chip (62) respectively through the interconnection wiring structure (2).

3. The hybrid packaging system for RF transceivers and digital circuits at the chip level as described in claim 2, characterized in that, The RF transceiver and digital circuit chip-level hybrid packaging system also includes several second passive components (8), which are surface-mounted on the top surface of the packaging substrate (1) and located in the packaging chamber (4). The several second passive components (8) are distributed on the outer periphery of the RF transceiver chip (5).

4. The hybrid packaging system for RF transceivers and digital circuits at the chip level as described in claim 2, characterized in that, The bottom surfaces of the RF transceiver chip (5), the digital circuit chip (6), and the power chip (7) are provided with multiple flip-chip ball bearings (51), and the top surface of the packaging substrate (1) is provided with multiple flip-chip solder pads (14). The flip-chip ball bearings (51) and the flip-chip solder pads (14) are soldered and fixed in a one-to-one correspondence.

5. The hybrid packaging system for RF transceivers and digital circuits at the chip level as described in claim 1, characterized in that, A heat sink (31) is embedded in the top plate of the cover (3). The heat sink (31) is arranged to penetrate the top plate of the cover (3) in the vertical direction. The heat sink (31) is used to dissipate heat from the encapsulation chamber (4).

6. The hybrid packaging system for RF transceivers and digital circuits at the chip level as described in claim 5, characterized in that, The top surfaces of the radio frequency transceiver chip (5) and the digital circuit chip (6) are both connected to a heat conductor (32), and the heat conductor (32) is thermally connected to the heat sink (31).

7. The hybrid packaging system for RF transceivers and digital circuits at the chip level as described in claim 6, characterized in that, The heat conductor (32) is a thermal grease or thermal adhesive.

8. The hybrid packaging system for RF transceivers and digital circuits at the chip level as described in claim 7, characterized in that, The bottom surface of the heat sink (31) is provided with a plurality of downward protruding bosses (311), and the plurality of bosses (311) are respectively provided in correspondence with the radio frequency transceiver chip (5) and the digital circuit chip (6), and the heat conductor (32) is wrapped around the outer periphery of the bosses (311).

9. The hybrid packaging system for radio frequency transceivers and digital circuits at the chip level as described in any one of claims 1-8, characterized in that, The packaging substrate (1) is an ABF substrate, which has a plurality of dielectric layers arranged in the vertical direction. The interconnection trace structure (2) includes horizontal traces and vertical traces. The horizontal traces are arranged along the plane of the dielectric layer, and the vertical traces are arranged through the dielectric layer in the vertical direction.

10. The hybrid packaged system for radio frequency transceivers and digital circuits at the chip level as described in any one of claims 1-8, characterized in that, The central pad (111) and the peripheral pad (131) are electrically connected to the circuit board (10) via solder balls (15), and the connection surface between the solder balls (15) and the circuit board (10) is lower than the bottom surface of the first passive component (121).

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