A semiconductor device structure

Abstract

This application discloses a semiconductor device structure, including: a semiconductor layer; a first insulating layer and a second insulating layer jointly covering a first surface of the semiconductor layer; a polysilicon layer partially covering the first insulating layer and having a gap between it and the second insulating layer; a third insulating layer including a first region, a second region, and a third region; a lower metal layer covering at least the first and second regions of the third insulating layer; an upper metal layer located above the lower metal layer; and a passivation layer covering the third insulating layer not covered by the lower metal layer and extending to cover a portion of the lower metal layer. The semiconductor device structure of this application embodiment has a maximum height of the passivation layer lower than the maximum height of the upper metal layer. This ensures that the passivation layer resists moisture penetration and corrosion while reducing the stress on the passivation layer from the packaging, thus reducing the risk of cracking in the passivation layer during temperature cycling.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to the structure of a semiconductor device. Background Technology

[0002] With the advancement and development of science and technology, semiconductor materials have also undergone generational changes. Third-generation semiconductor materials offer economic and environmental benefits such as small size, low pollution, and low operating losses, meeting the demands of modern society for high temperature, high power, high voltage, high frequency, and radiation resistance. Therefore, third-generation semiconductor materials are gradually becoming the focus of development. Currently, the mainstream third-generation semiconductor materials are silicon carbide and gallium nitride. Silicon carbide materials are mostly used in high-voltage applications such as smart grids and rail transportation.

[0003] Currently, silicon carbide power devices are mainly positioned for applications with power ranging from 1kW to 500kW and operating frequencies between 10kHz and 100MHz. They are particularly useful in applications with high energy efficiency and space requirements, where they can replace some silicon-based MOSFETs and IGBTs. The fabrication process of silicon carbide power devices involves device fabrication and packaging. At the end of the device fabrication process, a passivation layer is placed above the dielectric and metal layers to prevent external moisture intrusion and improve device stability. In the packaging process, a molding compound and a housing are filled to form the packaged device.

[0004] During the packaging process of silicon carbide power devices, the packaged devices need to undergo reliability tests such as temperature cycling tests and thermal shock tests. Due to the mismatch of the thermal expansion coefficients of the materials between the molding compound / dielectric layer / metal layer, excessive stress can cause cracks or metal deformation in the passivation layer structure. This not only affects the appearance of the device, but also reduces the device's ability to resist water vapor corrosion, thus affecting the long-term reliability of the device. Summary of the Invention

[0005] This application provides a semiconductor device structure that forms a step between the two metal layers through a double metal layer structure and the structure of each layer below the metal layer. The edge of the passivation layer falls on the metal layer below the metal layer, so that the maximum height of the passivation layer is lower than the maximum height of the upper metal layer. This ensures that the passivation layer resists moisture penetration and corrosion, while reducing the stress of the package on the passivation layer and reducing the risk of cracks in the passivation layer during temperature cycling.

[0006] According to an embodiment of the present invention, a semiconductor device structure is provided, comprising: a semiconductor layer having a first surface; a first insulating layer partially covering the first surface of the semiconductor layer; a second insulating layer partially covering the first surface of the semiconductor layer, wherein the second insulating layer is in contact with the first insulating layer and the thickness of the second insulating layer is greater than the thickness of the first insulating layer; a polysilicon layer partially covering the first insulating layer and having a gap between it and the second insulating layer; a third insulating layer including a first region, a second region, and a third region, wherein the second region covers the polysilicon layer, the first region covers the first insulating layer not covered by the polysilicon layer, and the third region covers the second insulating layer; a lower metal layer at least covering the first and second regions of the third insulating layer; an upper metal layer located above the lower metal layer; and a passivation layer covering the third insulating layer not covered by the lower metal layer and extending to cover a portion of the lower metal layer.

[0007] According to one embodiment of this application, an electronic device is provided, including the aforementioned semiconductor device structure, and further including: an organic passivation layer covering a portion of an upper metal layer of the semiconductor device structure, the passivation layer, and other areas not covered by the upper metal layer and the passivation layer; and a molding compound encapsulating the semiconductor device structure covered by the organic passivation layer. Attached Figure Description

[0008] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings:

[0009] Figure 1 A schematic diagram of an existing semiconductor device structure 100;

[0010] Figure 2 This is a schematic diagram of a semiconductor device structure 200 according to an embodiment of this application;

[0011] Figure 3 This is a schematic diagram of a semiconductor device structure 300 according to an embodiment of this application;

[0012] Figure 4 This is a schematic diagram of a semiconductor device structure 400 according to an embodiment of this application;

[0013] Figure 5 This is a schematic diagram of a semiconductor device structure 500 according to an embodiment of this application;

[0014] Figure 6 This is a schematic diagram of the structure of an electronic device 600 according to an embodiment of this application. Detailed Implementation

[0015] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0016] Throughout this specification, references to "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases "in an embodiment," "in an embodiment," "an example," or "an example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale. The same reference numerals indicate the same elements. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. The drawings are not drawn to scale and are for illustrative purposes only. For clarity, unless otherwise stated, the same elements have been designated by corresponding reference numerals in different drawings.

[0017] The terms “having,” “comprising,” “including,” “include,” etc., are open-ended, and these terms indicate the presence of the said structure, element, or feature, but do not exclude additional elements or features.

[0018] When describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that it contains other layers or regions between it and another layer or region. Furthermore, if the device is flipped, the layer or region will be located "below" or "under" another layer or region.

[0019] To describe a situation where it is located directly on another layer or another area, this article will use the expressions "directly on top of" or "on and adjacent to".

[0020] Figure 1 This is a schematic diagram of an existing semiconductor device structure 100. (Example) Figure 1As shown, the semiconductor device structure 100 includes a semiconductor layer 101, a polysilicon layer 106, an insulating layer 107, a metal layer 108, and a passivation layer 109. The semiconductor layer 101 includes a substrate layer 102, an epitaxial layer 103, an insulating layer 104, and an insulating layer 105 forming a stacked structure. The polysilicon layer 106 is partially covered on the insulating layer 104. The insulating layer 107, the metal layer 108, and the passivation layer 109 are sequentially covered on the polysilicon layer 106, the insulating layer 104, and the insulating layer 105. The passivation layer 109 covers the entire terminal structure to provide electrical insulation and device protection.

[0021] from Figure 1 As can be seen, the passivation layer 109 completely covers the metal layer 108 and the insulating layer 107. When the semiconductor device is subjected to reliability testing during the packaging process, the materials of the passivation layer 109, the metal layer 108 and the insulating layer 107 are different, and their linear expansion coefficients are mismatched. Excessive stress may cause cracks or metal deformation in the passivation layer structure.

[0022] Figure 2 This is a schematic diagram of a semiconductor device structure 200 according to an embodiment of this application. Figure 2 As shown, the semiconductor device structure 200 includes a semiconductor layer 201, an insulating layer 204, an insulating layer 205, a polysilicon layer 206, an insulating layer 207, a lower metal layer 208, an upper metal layer 210, and a passivation layer 209. The semiconductor layer 201 includes a substrate layer 202 and an epitaxial layer 203.

[0023] The substrate layer 202 and the epitaxial layer 203 include silicon-based materials, silicon carbide-based materials, or gallium nitride materials, etc. The substrate layer 202 and the epitaxial layer 203 have the same doping type, for example, both can be P-type materials or both can be N-type materials. The doping concentration of the substrate layer 202 is greater than the doping concentration of the epitaxial layer 203. In some embodiments, the epitaxial layer 203 can be a multilayer epitaxial layer, i.e., a multilayer structure including different doping concentrations. Furthermore, the portion of the epitaxial layer 203 away from the substrate layer 202 can also include device structures made of various different materials to meet the performance requirements of semiconductor device structures.

[0024] Insulating layers 204 and 205 cover the epitaxial layer 203. In some embodiments, insulating layer 204 includes a gate oxide layer, and insulating layer 205 includes a field oxide layer. The material of insulating layer 204 includes silicon dioxide (SiO2), silicon nitride (Si3N4), or hafnium oxide (HfO2), etc. The material of insulating layer 205 includes silicon dioxide (SiO2). The thickness of insulating layer 205 is greater than the thickness of insulating layer 204, and the two form a stepped structure at the junction on the surface of epitaxial layer 203.

[0025] exist Figure 2In this embodiment, the polysilicon layer 206 covers a portion of the insulating layer 204 and extends to a position at a certain distance from the insulating layer 205. That is, the edge region of the polysilicon layer 206 is located on the insulating layer 204 and is not in contact with the insulating layer 205. Further, an insulating layer 207 is also covered above the polysilicon layer 206. This insulating layer 207 covers the polysilicon layer 206, the area of ​​the insulating layer 204 not covered by the polysilicon layer 206, and the insulating layer 205. Due to the different thicknesses of the polysilicon layer 206, the insulating layer 204, and the insulating layer 205, the insulating layer 207 is formed as follows: Figure 2 The diagram shows a stepped structure with varying elevations. Figure 2 In this structure, insulating layer 207 serves as an interlayer dielectric layer, used to isolate the conductive layer, prevent electrical short circuits and interference, and also provide mechanical support. The material of insulating layer 207 can be a low dielectric constant material such as silicon dioxide (SiO2), fluorosilicone glass (FSG), or carbon-doped oxide (CDO), or a high dielectric constant material such as hafnium oxide (HfO2).

[0026] exist Figure 2 In this embodiment, the lower metal layer 208 covers the insulating layer 207, and due to the stepped structure of the insulating layer 207, the lower metal layer 208 forms a three-step structure. The upper metal layer 210 covers the lower metal layer 208 and correspondingly forms a three-step structure. The lowest step 210a of the upper metal layer 210 is directly below the lower metal layer 208, the insulating layer 207, and the insulating layer 204, and the lowest step 210a has a first height H11 to the surface of the epitaxial layer 203. The middle step 210b of the upper metal layer 210 is directly below the lower metal layer 208, the insulating layer 207, the polysilicon layer 206, and the insulating layer 204, and the middle step 210b has a second height H12 to the surface of the epitaxial layer 203. Directly below the highest step 210c of the upper metal layer 210 are the lower metal layer 208, the insulating layer 207, and the insulating layer 205, and the highest step 210c has a third height H13 to the surface of the epitaxial layer 203. The steps of the upper metal layer 210 are sequentially connected to each other through other parts of the upper metal layer 210, forming a whole. The cross-section 210d of the upper metal layer 210 extending towards the passivation layer 209 is located above the insulating layer 205. Figure 2 As shown, the thickness of insulating layer 205 is greater than the sum of the thicknesses of insulating layer 204 and polysilicon layer 206, thus causing the upper metal layer 210 to have the highest step 210c above insulating layer 205.

[0027] exist Figure 2In this embodiment, the highest step 210c of the upper metal layer 210 does not completely cover the lower metal layer 208, thus causing the lower metal layer 208 to have an extension 208a not covered by the upper metal layer 210. The passivation layer 209 covers the area of ​​the insulating layer 207 not covered by the lower metal layer 208 and extends to cover the extension 208a of the lower metal layer 208, forming a shape with the lower metal layer 208 as shown in the figure. Figure 2 The overlapping structure is shown. In Figure 2 In the embodiment, the edge 209a of the passivation layer 209 near the upper metal layer 210 is kept at a certain distance from the upper metal layer 210.

[0028] The material of the lower metal layer 208 may include alloy materials such as titanium nitride. The material of the upper metal layer 210 may include any one or a combination of at least two of aluminum, silver, copper, and gold. The upper metal layer 210 and the lower metal layer 208 have different etching rates. In one embodiment, after forming the upper metal layer 210 and the lower metal layer 208 using the same mask, the edge portion of the upper metal layer 210 is etched away by a wet etching method, thereby exposing the extension portion 208a of the lower metal layer 208. The passivation layer 209 covers a portion of the extension portion 208a of the lower metal layer 208.

[0029] exist Figure 2 In the embodiment, a multi-level structure of metal layers is formed on the surface of the epitaxial layer 203, and the surface of the epitaxial layer 203 is also referred to as the first surface 203a of the semiconductor layer.

[0030] In one embodiment, the thickness of the upper metal layer 210 is greater than or equal to 0.5 μm, and the thickness of the lower metal layer 208 is 0.1 μm to 0.3 μm. The thickness of the polycrystalline silicon layer 206 is greater than or equal to 0.1 μm. The thickness of the insulating layer 207 is greater than or equal to 0.1 μm.

[0031] exist Figure 2 In the embodiment, the height difference between the lowest step 210a and the middle step 210b of the upper metal layer 210 is equal to the thickness of the polysilicon layer 206, and the height difference between the lowest step 210a and the highest step 210c is equal to the thickness difference between the insulating layer 204 and the insulating layer 205.

[0032] exist Figure 2 In this embodiment, the thickness of the passivation layer 209 is greater than or equal to 0.05 μm. The maximum height H2 of the passivation layer 209 from the first surface 203a of the semiconductor layer is the sum of the thicknesses of the passivation layer 209, the underlying metal layer 208, the insulating layer 207, and the insulating layer 205. Figure 2In this embodiment, the highest height H2 of the passivation layer 209 from the first surface 203a of the semiconductor layer is less than the highest height of the upper metal layer 210 from the first surface 203a of the semiconductor layer, that is, less than the height H13 of the highest step 210c of the upper metal layer 210 from the first surface 203a of the semiconductor layer.

[0033] exist Figure 2 In this embodiment, the thickness of the passivation layer 209 is less than the sum of the thickness of the polysilicon layer 206 and the thickness of the insulating layer 207.

[0034] The material of the passivation layer 209 may include silicon oxide, silicon nitride, or a stack of silicon oxide and silicon nitride.

[0035] Figure 2 The embodiment utilizes a wet etching process based on a traditional semiconductor structure to change the positional relationship between the passivation layer 209 and the metal layers 210 and 208. The process is simple to implement and compatible with the field plate structure on the semiconductor terminal structure. It has a sufficient process window and is mass-producible and universal.

[0036] In this embodiment, insulating layer 204 is also referred to as the first insulating layer, insulating layer 205 is also referred to as the second insulating layer, and insulating layer 207 is also referred to as the third insulating layer.

[0037] Figure 3 This is a schematic diagram of a semiconductor device structure 300 according to an embodiment of this application. The semiconductor device structure 300 and... Figure 2 The semiconductor device structure in the embodiment is similar to 200, except that, Figure 3 In this configuration, the cross section 310d of the upper metal layer 310 extending towards the passivation layer 309 is located above the insulating layer 204. That is, the upper metal layer 310 does not extend above the insulating layer 205. Therefore, the highest step of the upper metal layer 310 is located above the polysilicon layer 206.

[0038] exist Figure 3In this embodiment, the lowest step 310a of the upper metal layer 210 is directly below the lower metal layer 208, insulating layer 207, and insulating layer 204, and the lowest step 210a has a first height H11 to the surface 203a of the epitaxial layer 203. The highest step 310b of the upper metal layer 310 is directly below the lower metal layer 208, insulating layer 207, polysilicon layer 206, and insulating layer 204, and the highest step 310b has a second height H12 to the surface 203a of the epitaxial layer 203. The steps of the upper metal layer 310 are sequentially connected to each other parts of the upper metal layer 310 to form a whole. The cross section 310d of the upper metal layer 310 extending towards the passivation layer 209 is located above the insulating layer 204. It should be understood that, due to the imprecise control characteristics of the process, the cross section 310d of the upper metal layer 310 may be located on the lower metal layer 208 above the insulating layer 204 and the insulating layer 207, or it may be located at the connection portion of the lower metal layer above the insulating layer 204 and the lower metal layer above the insulating layer 205.

[0039] exist Figure 3 In this embodiment, the lower metal layer 208 extends above the insulating layer 205. The passivation layer 309 covers the area of ​​the insulating layer 207 not covered by the lower metal layer 208, and extends to cover the extended portion 208a of the lower metal layer 208, forming a shape with the lower metal layer 208 as shown. Figure 3 The overlapping structure is shown. In Figure 3 In the embodiment, the edge 309a of the passivation layer 309 near the upper metal layer 310 maintains a certain distance from the upper metal layer 310.

[0040] exist Figure 3 In this embodiment, the maximum height H4 of the passivation layer 309 from the first surface 205a of the semiconductor layer is equal to the thickness of the metal layer 208 plus the thickness of the polysilicon layer 206 and the thickness of the passivation layer 309. Figure 3 In this embodiment, the highest height H4 of the passivation layer 309 from the first surface 205a of the semiconductor layer is less than the highest height of the metal layer 208, that is, less than the height H3 of the highest step 208b of the metal layer 208 from the first surface 205a of the semiconductor layer.

[0041] exist Figure 3 In this embodiment, the thickness of the passivation layer 309 is greater than or equal to 0.05 μm. The maximum height H2 of the passivation layer 309 from the first surface 203a of the semiconductor layer is the sum of the thicknesses of the passivation layer 209, the underlying metal layer 208, the insulating layer 207, and the insulating layer 205. Figure 3In this embodiment, the highest height H2 of the passivation layer 309 from the first surface 203a of the semiconductor layer is less than the highest height of the upper metal layer 210 from the first surface 203a of the semiconductor layer, that is, less than the height H12 of the highest step 310b of the upper metal layer 210 from the first surface 203a of the semiconductor layer.

[0042] exist Figure 3 In the embodiment, the maximum height of the metal layer 310 is less than Figure 2 The embodiment has a maximum height of metal layer 210, ample process window, and can significantly reduce the compression of metal layer 310 by encapsulant. Metal layer 310 has better shape retention in temperature cycling tests, further improving device reliability.

[0043] Figure 4 This is a schematic diagram of a semiconductor device structure 400 according to an embodiment of this application. The semiconductor device structure 400 and... Figure 3 The semiconductor device structure 300 in the embodiment is similar, except that... Figure 4 In this process, the passivation layer 409 extends upwards from the lower metal layer 208 to the upper metal layer 310 until it contacts the cross-section 310d of the upper metal layer 310. Figure 4 In one embodiment, the edge 409a of the passivation layer 409 is located on the cross section 310d of the upper metal layer 310, and is lower than the lowest step 310a. In some embodiments, the passivation layer 409 may extend to the lowest step 310a of the upper metal layer 310, that is, the edge 409a of the passivation layer 409 is located on the lowest step 310a.

[0044] exist Figure 4 In this embodiment, the passivation layer 409, the lower metal layer 208, and the upper metal layer 310 have a larger overlap area, which improves the device's ability to resist moisture penetration and corrosion.

[0045] Figure 5 This is a schematic diagram of a semiconductor device structure 500 according to an embodiment of this application. The semiconductor device structure 500 and... Figure 4 The semiconductor device structure in the embodiment is similar to that of 400, except that, in Figure 5 In the middle, the upper metal layer 310 and the lower metal layer 508 extend to the same position and then stop. The upper metal layer 310 and the lower metal layer 508 can be formed by a single photolithography process and using a dry etching process.

[0046] exist Figure 5 In this structure, the passivation layer 509 covers the insulating layer 207 and extends to be in contact with the cross-section 310d of the upper metal layer 310 and the cross-section 508a of the lower metal layer 508. Figure 5In this embodiment, the edge 509a of the passivation layer 509 terminates at the cross section 310d of the upper metal layer 310, and the passivation layer 509 is lower than the lowest step 310a of the upper metal layer 310. In some embodiments, the passivation layer 509 may extend to the lowest step 310a of the upper metal layer 310, that is, the edge 509a of the passivation layer 509 is located on the lowest step 310a of the upper metal layer 310.

[0047] exist Figure 5 In this embodiment, the passivation layer 509 is lower than the highest step 310b of the upper metal layer 310 to prevent stress from the upper metal layer 310 from being transmitted to the passivation layer 509.

[0048] To achieve a smaller linewidth of the metal layer 310, the industry often uses dry etching processes for patterning the metal layer. Figure 5 In this embodiment, the upper metal layer 310 and the lower metal layer 310b are aligned, which is compatible with dry etching processes.

[0049] It should be understood that the edge region described in the embodiments of this application represents the edge of the corresponding material layer and the portion of the region connected to the edge.

[0050] Figure 6 This is a schematic diagram of the structure of an electronic device 600 according to an embodiment of this application. The electronic device 600 includes a semiconductor device structure 200, an organic passivation layer 602, and a molding compound 601. The organic passivation layer 602 covers the passivation layer and an upper metal layer, providing mechanical and moisture protection for the semiconductor device structure 200, and leaving a portion 603 of the upper metal layer exposed for wire bonding connections on the upper metal layer 603. The molding compound 601 encapsulates the semiconductor device structure 200 covering the organic passivation layer 602. It should be understood that... Figure 6 The diagram shown is only a partial cross-sectional view; the electronic device also includes other structures, such as lead frames. The pins of the lead frame are exposed outside the molding compound 601 for connection to external devices. The semiconductor device structure 200 can be replaced by semiconductor device structures 300, 400, and 500 in other embodiments of this application.

[0051] As described above, these embodiments of the present application do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to make good use of the present application and modifications based on it. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor device structure, comprising: A semiconductor layer having a first surface of a semiconductor layer; A first insulating layer partially covers the first surface of the semiconductor layer; A second insulating layer partially covers the first surface of the semiconductor layer, and the second insulating layer is in contact with the first insulating layer, and the thickness of the second insulating layer is greater than the thickness of the first insulating layer; A polycrystalline silicon layer partially covers the first insulating layer and has a gap between it and the second insulating layer; The third insulating layer includes a first region, a second region, and a third region, wherein the second region covers the polysilicon layer, the first region covers the first insulating layer not covered by the polysilicon layer, and the third region covers the second insulating layer; The underlying metal layer at least covers the first and second regions of the third insulating layer; The upper metal layer is located above the lower metal layer; as well as A passivation layer covers a third insulating layer that is not covered by the underlying metal layer, and extends to cover a portion of the underlying metal layer.

2. The semiconductor device structure as described in claim 1, wherein: The upper metal layer has a three-step structure, including a highest step, a middle step and a lowest step, wherein the highest step is located above the third region of the third insulating layer, the middle step is located above the first region of the third insulating layer and the lowest step is located above the second region of the third insulating layer. as well as The highest step of the upper metal layer covers a portion of the lower metal layer, and the passivation layer covers a portion of the lower metal layer exposed outside the upper metal layer, while maintaining a distance from the highest step of the upper metal layer.

3. The semiconductor device structure as described in claim 1, wherein: The upper metal layer has a two-stage stepped structure, including a highest step and a lowest step, wherein the highest step is located above the first region of the third insulating layer, and the lowest step is located above the second region of the third insulating layer. as well as The passivation layer covers a portion of the lower metal layer exposed outside the upper metal layer and is spaced apart from the lowest step of the upper metal layer. The edge of the passivation layer is located above the third region of the third insulating layer.

4. The semiconductor device structure as described in claim 1, wherein: The upper metal layer has a two-stage stepped structure, including a highest step and a lowest step, wherein the highest step is located above the first region of the third insulating layer, and the lowest step is located above the second region of the third insulating layer. as well as The passivation layer covers the area of ​​the lower metal layer exposed outside the upper metal layer, and the passivation layer extends to meet the cross-section of the upper metal layer, with the edge of the passivation layer located on the cross-section of the upper metal layer.

5. The semiconductor device structure of claim 4, wherein the passivation layer further extends to the lowest step of the upper metal layer.

6. The semiconductor device structure as described in claim 1, wherein: The upper metal layer has a two-stage stepped structure, including a highest step and a lowest step, wherein the highest step is located above the first region of the third insulating layer, and the lowest step is located above the second region of the third insulating layer. The lower metal layer and the upper metal layer terminate at the same position; The passivation layer covers the third insulating layer exposed outside the lower metal layer and extends to meet the cross-section of the upper metal layer, with the edge of the passivation layer located on the cross-section of the upper metal layer.

7. The semiconductor device structure of claim 6, wherein the passivation layer further extends to the lowest step of the upper metal layer.

8. The semiconductor device structure according to any one of claims 1-7, wherein: The thickness of the upper metal layer is greater than or equal to 0.5 μm; The thickness of the underlying metal layer ranges from 0.1 μm to 0.3 μm; as well as The thickness of the passivation layer is greater than or equal to 0.05 μm.

9. The semiconductor device structure according to any one of claims 1-7, wherein, The upper metal layer and the lower metal layer have different etching rates.

10. An electronic device comprising the semiconductor device structure as described in any one of claims 1-9, further comprising: An organic passivation layer covers a portion of the upper metal layer of a semiconductor device structure, the passivation layer itself, and other areas not covered by the upper metal layer and passivation layer. as well as A molding compound that encapsulates the semiconductor device structure covered with an organic passivation layer.

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