Hybrid protocol chip bus delay adjustment method, electronic device and medium

Abstract

This invention relates to the field of chip technology, and more particularly to a hybrid protocol chip bus delay adjustment method, electronic device, and medium. The method includes step S1: constructing the nth hybrid chip bus structure B of the chip design. n Step S2: At the initiating terminal S of the m-th hybrid chip bus that requires delay adjustment in the chip design and is connected to the network, m Insert delay information T m Step S3, Analysis S m Corresponding B n and T m Based on C i n Get the corresponding Q j m Based on C i n The corresponding Q j m F i n Generate H i n The corresponding delay adjustment unit R i n Based on P m and C i n Corresponding G i n Set R i n Corresponding gated clock; Step S4, based on all C i n The corresponding R i n For S m Generate B n The corresponding delay adjustment module W n This invention enables delay adjustment of the hybrid protocol chip bus.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a hybrid protocol chip bus delay adjustment method, electronic device, and medium. Background Technology

[0002] In chip design, the logical interconnections between modules must first be established, followed by physical connections based on these logical interconnections. Due to different placement and routing methods, the distance and type of connections between different modules may vary. Especially when the distance is too long, directly establishing connections between modules according to the logical interconnection method can affect the timing performance between the two interconnected modules. Therefore, delay modules are usually inserted between the two interconnected modules to optimize their timing. These delay modules can include multiple delay units. Due to the large scale of chips, the number of delay units inserted is also very large. During delay adjustment, each delay unit transmits data, but this also includes the transmission of a large amount of invalid data, resulting in significant waste of chip power. Therefore, a gated clock can be set to reduce chip power consumption during delay adjustment. However, existing bus delay adjustment methods are all for single protocol buses, while some chip buses are hybrid protocol buses. Existing bus delay adjustment methods do not support delay adjustment for hybrid protocol chip buses. Therefore, how to implement delay adjustment for hybrid protocol chip buses has become an urgent technical problem to be solved. Summary of the Invention

[0003] The purpose of this invention is to provide a method, electronic device, and medium for adjusting the delay of a hybrid protocol chip bus, thereby realizing the delay adjustment of the hybrid protocol chip bus.

[0004] According to a first aspect of the present invention, a method for adjusting the bus delay of a hybrid protocol chip is provided, comprising: Step S1: Construct the nth hybrid chip bus structure B in the chip design. n B n ={C1 n C2 n ,....,C i n ,...,C f(n) n}, where n ranges from 1 to N, N is the total number of hybrid chip buses in the chip design, and C i n For B n The structure of the corresponding i-th channel, C i n ={E i n ,Fi n G i n H i n}, E i n C i n The corresponding bus protocol, F i n C i n The corresponding key signal identifier, G i n C i n The corresponding gated clock information, H i n C i n The corresponding signal list; Step S2: At the initiating terminal S of the m-th hybrid chip bus that requires delay adjustment in the chip design and is connected... m Insert delay information T m The value of m ranges from 1 to M, where M is the total number of initiators of the hybrid chip bus that require delay adjustment in the chip design and are connected. T m ={P m Q1 m Q2 m ,...,Q j m ,...,Q g(m) m}, P m For T m The corresponding gated clock information, Q j m For T m The corresponding delay adjustment information for the j-th type of bus protocol; Step S3, Analysis of S m Corresponding B n and T m Based on C i n Get the corresponding Q j m Based on C i n The corresponding Q j m F i n Generate H i n The corresponding delay adjustment unit R i n Based on P m and Ci n Corresponding G i n Set R i n The corresponding gated clock; Step S4, based on all C i n The corresponding R i n For S m Generate B n The corresponding delay adjustment module W n .

[0005] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in the first aspect of the present invention.

[0006] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions for performing the method described in the first aspect of the present invention.

[0007] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the hybrid protocol chip bus delay adjustment method, electronic device, and medium provided by this invention achieve considerable technological advancement and practicality, and have broad industrial application value. It has at least the following beneficial effects: This invention constructs a hybrid chip bus structure and inserts delay information at the initiating end of the hybrid chip bus that requires delay adjustment and is connected. By parsing the hybrid chip bus structure and the delay information, a delay adjustment unit corresponding to each channel in the hybrid chip bus structure is constructed, and the gate clock corresponding to each channel is finely set. Finally, a delay adjustment module corresponding to the hybrid chip bus structure is generated, realizing the delay adjustment of the hybrid protocol chip bus. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 A flowchart of a hybrid protocol chip bus delay adjustment method provided in an embodiment of the present invention. Detailed Implementation

[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0011] This invention provides a method for adjusting the bus delay of a hybrid protocol chip, such as... Figure 1 As shown, it includes: Step S1: Construct the nth hybrid chip bus structure B in the chip design. n B n ={C1 n C2 n ,....,C i n ,...,C f(n) n}, where n ranges from 1 to N, N is the total number of hybrid chip buses in the chip design, and C i n For B n The structure of the corresponding i-th channel, C i n ={E i n ,F i n G i n H i n}, E i n C i n The corresponding bus protocol, F i n C i n The corresponding key signal identifier, G i n C i n The corresponding gated clock information, H i n C i n The corresponding signal list.

[0012] It should be noted that the hybrid chip bus involves multiple bus protocols and can be divided into different channels according to different gating clock adjustment requirements. This application divides the hybrid bus structure into different channels based on bus protocols and gating clock adjustment requirements. Signals within the same channel of the hybrid chip bus correspond to the same bus protocol and have the same gating clock adjustment requirements. Different channels of the hybrid chip bus may correspond to the same or different bus protocols. The gating clock adjustment requirements for different channels of the hybrid chip bus may also be the same or different.

[0013] The signal list can include multiple signal information, each of which includes information such as signal direction, signal width, signal reset value, and signal default value.

[0014] Step S2: At the initiating terminal S of the m-th hybrid chip bus that requires delay adjustment in the chip design and is connected... m Insert delay information T m The value of m ranges from 1 to M, where M is the total number of initiators of the hybrid chip bus that require delay adjustment in the chip design and are connected. T m ={P m Q1 m Q2 m ,...,Q j m ,...,Q g(m) m}, P m For T m The corresponding gated clock information, Q j m For T m The delay adjustment information corresponding to the j-th type of bus protocol.

[0015] It should be noted that this invention only addresses delay adjustment for the initiating end of a hybrid chip bus that requires delay adjustment and is connected. Delay adjustment for other types of initiating ends can be implemented using existing delay adjustment methods, which will not be elaborated here. The delay adjustment information includes delay levels and clock domain identifiers. The delay levels are determined based on the target physical distance of the corresponding bus protocol, and the delay adjustment unit is generated based on the clock domain identifier corresponding to the delay adjustment information. The delay levels refer to the number of delay units corresponding to the bus protocol, and the clock domain identifier refers to the default clock domain identifier of the delay module unit corresponding to the bus protocol.

[0016] Step S3, Analysis of S m Corresponding B n and T m Based on C i n Get the corresponding Q j m Based on Ci n The corresponding Q j m F i n Generate H i n The corresponding delay adjustment unit R i n Based on P m and C i n Corresponding G i n Set R i n The corresponding gated clock.

[0017] It should be noted that P m This is used to control whether the initiator needs to enable gated clock control. If the initiator needs to enable gated clock control, it can be further controlled via C. i n The corresponding gated clock information finely controls the gated clock of each channel in the hybrid chip bus.

[0018] Step S4, based on all C i n The corresponding R i n For S m Generate B n The corresponding delay adjustment module W n .

[0019] As one embodiment, step S3 includes: Step S31, Obtain S m Corresponding B n As B to be processed n .

[0020] It should be noted that an S m It may correspond to one or more hybrid chip bus structures B n For each B n Simply generate the corresponding delay adjustment modules one by one.

[0021] Step S32: Obtain the B to be processed n C to be processed i n Corresponding E to be processed i n .

[0022] Step S33: Obtain the E to be processed i n In T m The corresponding Q in jm As Q to be processed j m .

[0023] Step S34, based on the Q to be processed j m In the pending C i n The corresponding H i n The corresponding signal line generation delay adjustment unit R i n ; Specifically, a delay adjustment unit can be generated based on the clock domain identifier corresponding to the delay adjustment information.

[0024] Step S35, based on the C to be processed i n Corresponding F i n Set R i n It can be either a one-way adjustment mode or a two-way adjustment mode.

[0025] In the unidirectional adjustment mode, only the delay from the sending end to the receiving end needs to be adjusted, while in the bidirectional adjustment mode, the delay from the sending end to the receiving end and from the receiving end to the sending end need to be adjusted.

[0026] Step S36, based on the C to be processed i n Corresponding G i n and S m Corresponding P m Set R i n The corresponding gated clock.

[0027] As one embodiment, the key signal identifiers include a valid identifier, a send identifier, and a free identifier. If the key signal identifier is a valid identifier, the corresponding delay adjustment mode is a one-way adjustment mode, and the delay operation is performed when the valid signal is high. If the key signal identifier is a send identifier or a free identifier, the corresponding delay adjustment mode is a two-way adjustment mode. The send identifier corresponds to the delay adjustment in the direction from the sender to the receiver, and the free identifier corresponds to the delay adjustment in the direction from the receiver to the sender.

[0028] As one embodiment, step S35 includes: Step S351, if the C to be processed i n Corresponding F i nTo ensure the validity of the identifier, set R. i n It is a one-way adjustment mode, and performs a delay operation when the valid signal is high.

[0029] Step S352, if the C to be processed i n Corresponding F i n To ensure that the valid identifier is the send identifier, set R. i n It is set to bidirectional adjustment mode, and R is set. i n This is for adjusting the delay from the sending end to the receiving end.

[0030] Step S353, if the C to be processed i n Corresponding F i n To ensure that the valid identifier is the release identifier (free), set R. i n It is set to bidirectional adjustment mode, and R is set. i n This is for adjusting the delay from the receiver to the transmitter.

[0031] As one example, G i n Set to either the first control identifier or the second control identifier. The first control identifier indicates that the corresponding channel C is enabled. i n The gated clock, the second control flag indicates that the corresponding channel C is closed. i n The gated clock, P m This can be set to either the third or fourth control flag. The third control flag enables the gated clock of the corresponding hybrid chip bus, while the fourth control flag disables it. Specifically, the first and third control flags can be set to true, and the second and fourth control flags can be set to false. (This can be achieved through G...) i n and P m The combined settings enable flexible and controllable gated clock adjustment of hybrid chip bus delay, resulting in more reasonable power saving.

[0032] As one embodiment, step S36 includes: Step S361, if S m Corresponding P m If set as the fourth control identifier, then set S. m Each corresponding R i nThe corresponding gated clock is in the off state.

[0033] Where S m Corresponding P m Set as the fourth control identifier, indicating S m The corresponding delay adjustment modules do not require setting a gated clock, so there is no need to consider the C to be processed. i n Corresponding G i n Directly put S m Each corresponding R i n The corresponding gated clock should be in the off state.

[0034] Step S362, if S m Corresponding P m Set as the third identifier and pending C i n Corresponding G i n If set as the second control identifier, then set the pending C. i n The corresponding R i n The corresponding gated clock is in the off state.

[0035] Step S363, if S m Corresponding P m Set as the third identifier and pending C i n Corresponding G i n If set as the first control identifier, then set the pending C. i n The corresponding R i n The corresponding gated clock is in the ON state.

[0036] It should be noted that, through steps S362-S363, in S... m Corresponding P m Set as the third identifier, S m When the corresponding delay adjustment module requires the gating clock to be enabled, based on each pending C... i n Corresponding G i n Control each C to be processed separately i n The corresponding R i n The corresponding gated clock.

[0037] As one embodiment, the sending end S mIt may be interconnected with only one receiver, i.e., a one-to-one interconnection. It may also be interconnected with multiple receivers simultaneously. Different types of delay adjustment modules are generated for different interconnection methods. Step S4 includes: Step S41, if S m Corresponding B n If only one receiver is connected, then proceed to step S42. If S m Corresponding B n If interconnected with multiple receivers, proceed to step S43.

[0038] Step S42, S m Corresponding B n The corresponding R i n Encapsulate and generate delay adjustment submodule U n , will X i n cascaded U n Package to generate B n The corresponding delay adjustment module W n W n Insert S m The process ends with X, connecting to the corresponding receiver. i n For R i n The corresponding delay adjustment level.

[0039] It should be noted that when the sending end S m When using a one-to-one interconnection mode, B n The corresponding R i n The code can be directly distributed in the delay adjustment submodule without additional encapsulation.

[0040] Step S43, S m Corresponding B n Each corresponding R i n Encapsulate and generate a secondary delay adjustment submodule V i n , will S m Corresponding B n All corresponding V i n Encapsulate and generate a first-level delay adjustment module L n , will S m With L n All input interfaces are interconnected, connecting each V i n In L n The corresponding output port is interconnected with the corresponding receiver.

[0041] It should be noted that when the sending end S m When using a one-to-many interconnection mode, each R needs to be... i n A two-level delay adjustment submodule is encapsulated and generated. Then, based on the specific interconnection between the transmitter and receiver, each V... i n In L n The corresponding output port is interconnected with the corresponding receiver.

[0042] In this embodiment of the invention, a hybrid chip bus structure is constructed and delay information is inserted at the initiating end of the hybrid chip bus that requires delay adjustment and is connected. By parsing the hybrid chip bus structure and the delay information, a delay adjustment unit corresponding to each channel in the hybrid chip bus structure is constructed, and the gate clock corresponding to each channel is finely set. Finally, a delay adjustment module corresponding to the hybrid chip bus structure is generated, realizing the delay adjustment of the hybrid protocol chip bus.

[0043] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. A process can be terminated when its operation is complete, but it may also have additional steps not included in the figures. A process can correspond to a method, function, procedure, subroutine, subroutine, etc.

[0044] This invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in this invention.

[0045] This invention also provides a computer-readable storage medium storing computer-executable instructions for performing the methods described in this invention.

[0046] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A method for adjusting bus delay in a hybrid protocol chip, characterized in that, include: Step S1: Construct the nth hybrid chip bus structure B in the chip design. n B n ={C1 n C2 n ,....,C i n ,...,C f(n) n }, where n ranges from 1 to N, N is the total number of hybrid chip buses in the chip design, and C i n For B n The structure of the corresponding i-th channel, C i n ={E i n ,F i n G i n H i n }, E i n C i n The corresponding bus protocol, F i n C i n The corresponding key signal identifier, G i n C i n The corresponding gated clock information, H i n C i n The corresponding signal list; Step S2: At the initiating terminal S of the m-th hybrid chip bus that requires delay adjustment in the chip design and is connected... m Insert delay information T m The value of m ranges from 1 to M, where M is the total number of initiators of the hybrid chip bus that require delay adjustment in the chip design and are connected. T m ={P m Q1 m Q2 m ,...,Q j m ,...,Q g(m) m }, P m For T m The corresponding gated clock information, Q j m For T m The corresponding delay adjustment information for the j-th type of bus protocol; Step S3, Analysis of S m Corresponding B n and T m Based on C i n Get the corresponding Q j m Based on C i n The corresponding Q j m F i n Generate H i n The corresponding delay adjustment unit R i n Based on P m and C i n Corresponding G i n Set R i n The corresponding gated clock; Step S4, based on all C i n The corresponding R i n For S m Generate B n The corresponding delay adjustment module W n .

2. The method according to claim 1, characterized in that, Step S3 includes: Step S31, Obtain S m Corresponding B n As B to be processed n ; Step S32: Obtain the B to be processed n C to be processed i n Corresponding E to be processed i n ; Step S33: Obtain the E to be processed i n In T m The corresponding Q in j m As Q to be processed j m ; Step S34, based on the Q to be processed j m In the pending C i n The corresponding H i n The corresponding signal line generation delay adjustment unit R i n ; Step S35, based on the C to be processed i n Corresponding F i n Set R i n It can be either a one-way adjustment mode or a two-way adjustment mode; Step S36, based on the C to be processed i n Corresponding G i n and S m Corresponding P m Set R i n The corresponding gated clock.

3. The method according to claim 2, characterized in that, The key signal identifiers include a valid identifier, a send identifier, and a free identifier. If the key signal identifier is a valid identifier, the corresponding delay adjustment mode is a one-way adjustment mode, and the delay operation is performed when the valid signal is high. If the key signal identifier is a send identifier or a free identifier, the corresponding delay adjustment mode is a two-way adjustment mode. The send identifier corresponds to the delay adjustment in the direction from the sender to the receiver, and the free identifier corresponds to the delay adjustment in the direction from the receiver to the sender.

4. The method according to claim 3, characterized in that, Step S35 includes: Step S351, if the C to be processed i n Corresponding F i n To ensure the validity of the identifier, set R. i n It is a one-way adjustment mode, and performs a delay operation when the valid signal is high; Step S352, if the C to be processed i n Corresponding F i n To ensure that the valid identifier is the send identifier, set R. i n It is set to bidirectional adjustment mode, and R is set. i n For delay adjustment in the direction from the sending end to the receiving end; Step S353, if the C to be processed i n Corresponding F i n To ensure that the valid identifier is the release identifier (free), set R. i n It is set to bidirectional adjustment mode, and R is set. i n This is for adjusting the delay from the receiver to the transmitter.

5. The method according to claim 2, characterized in that, G i n Set to either the first control identifier or the second control identifier. The first control identifier indicates that the corresponding channel C is enabled. i n The gated clock, the second control flag indicates that the corresponding channel C is closed. i n The gated clock, P m Set to either the third or fourth control identifier. The third control identifier indicates that the gated clock of the corresponding hybrid chip bus is enabled, and the fourth control identifier indicates that the gated clock of the corresponding hybrid chip bus is disabled.

6. The method according to claim 5, characterized in that, Step S36 includes: Step S361, if S m Corresponding P m If set as the fourth control identifier, then set S. m Each corresponding R i n The corresponding gated clock is in the off state; Step S362, if S m Corresponding P m Set as the third identifier and pending C i n Corresponding G i n If set as the second control identifier, then set the pending C. i n The corresponding R i n The corresponding gated clock is in the off state; Step S363, if S m Corresponding P m Set as the third identifier and pending C i n Corresponding G i n If set as the first control identifier, then set the pending C. i n The corresponding R i n The corresponding gated clock is in the ON state.

7. The method according to claim 1, characterized in that, The delay adjustment information includes a delay level and a clock domain identifier. The delay level is determined based on the target physical distance of the corresponding bus protocol, and the delay adjustment unit generates the delay adjustment information based on the clock domain identifier corresponding to the delay adjustment information.

8. The method according to claim 7, characterized in that, Step S4 includes: Step S41, if S m Corresponding B n If only one receiver is connected, then proceed to step S42. If S m Corresponding B n If interconnected with multiple receivers, proceed to step S43; Step S42, S m Corresponding B n The corresponding R i n Encapsulate and generate delay adjustment submodule U n , will X i n cascaded U n Package to generate B n The corresponding delay adjustment module W n W n Insert S m The process ends with X, connecting to the corresponding receiver. i n For R i n The corresponding delay adjustment level; Step S43, S m Corresponding B n Each corresponding R i n Encapsulate and generate a secondary delay adjustment submodule V i n , will S m Corresponding B n All corresponding V i n Encapsulate and generate a first-level delay adjustment module L n , will S m With L n All input interfaces are interconnected, connecting each V i n In L n The corresponding output port is interconnected with the corresponding receiver.

9. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; The memory stores instructions that are executed by the at least one processor, the instructions being configured to perform the method of any one of claims 1-8.

10. A computer-readable storage medium, characterized in that, The device stores computer-executable instructions for performing the method of any one of claims 1-8.

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