A method for manufacturing a high aspect ratio x-ray grating and an x-ray grating

Abstract

This invention discloses a method for fabricating a high aspect ratio X-ray grating and the X-ray grating itself, relating to the fields of micro / nano fabrication and X-ray optical device manufacturing technology. The method includes: using a highly doped, low-resistivity single-crystal silicon wafer as a substrate, cleaning it, and then depositing a silicon dioxide hard mask on its surface; transferring the grating pattern to the silicon dioxide hard mask, and etching it using an improved low-temperature Bosch process to create vertical deep trenches; removing the natural oxide layer on the back side, followed by depositing a metal layer and thermal annealing to construct a conductive back electrode; performing multi-stage cleaning; placing the substrate in a bismuth ion-assisted gold sulfite plating solution for electroplating, ensuring that the gold layer fills the vertical deep trenches from the bottom upwards without voids; removing the silicon dioxide hard mask, cleaning, and drying to obtain the X-ray grating. This invention alleviates the technical problems of uneven performance, poor reliability, high production costs, and low production efficiency and yield of X-ray gratings fabricated by existing technologies.

Description

Technical Field

[0001] This invention relates to the field of micro-nano fabrication and X-ray optical device manufacturing technology, and in particular to a method for fabricating a high aspect ratio X-ray grating and the X-ray grating itself. Background Technology

[0002] X-ray phase-contrast imaging, particularly methods based on grating interferometry, can significantly improve the imaging contrast of low atomic number materials such as soft tissues, demonstrating great potential in the fields of biomedicine, materials science, and safety inspection. One of the core components of this technology is the absorption grating (such as G0 and G2 gratings), which requires the fabrication of periodically arranged micro-trenches with a high aspect ratio (typically greater than 50:1) on a silicon substrate and filling them with high atomic number metals such as gold and tungsten to achieve effective absorption of hard X-rays.

[0003] Currently, fabricating such high aspect ratio microstructures with metal filling faces significant challenges. Mainstream solutions include LIGA (lithography, electroforming, and injection molding) technology combined with silicon-based micromachining and electroplating filling techniques. While LIGA technology can fabricate thick metal structures, it relies on synchrotron radiation sources, resulting in high costs and difficulty in reducing pattern periods to below 2 micrometers. In contrast, silicon-based micromachining technology, utilizing the mature deep reactive ion etching (DRIE) process, can fabricate high aspect ratio trench arrays with steep sidewalls and periods below 1 micrometer on larger silicon wafers at a lower cost, thus becoming a more promising technological approach.

[0004] However, achieving void-free, fully dense, high-quality metal filling in silicon trenches, especially for narrow trenches with aspect ratios exceeding 50, is a key bottleneck for industrialization.

[0005] A search of Chinese patent publication number CN116741430A, entitled "X-ray Grating and its Fabrication Method," discloses a method for filling a grating structure with metal nanoparticles via electrophoretic deposition. This method first covers the sidewalls and top surface of an etched silicon grating structure with an insulating layer, making only the bottom of the trench conductive. Then, the entire structure is placed in a suspension of metal nanoparticles, and an electric field is applied to cause the particles to migrate towards the bottom of the trench and deposit until it is completely filled. Furthermore, Chinese patent publication number CN201910150687.X employs a method of pre-preparing a conductive seed layer on the inner wall of the trench before electroplating.

[0006] While these methods aim to solve the filling problem, they generate a series of new technical challenges in practical applications. Electrophoretic deposition requires precise preparation of an insulating layer to selectively expose the bottom and the formulation of a stable nanoparticle suspension containing dispersants and surfactants, resulting in a cumbersome process and complex material systems. For trenches with extremely high aspect ratios, traditional methods such as physical vapor deposition (PVD) struggle to form a continuous and uniform seed layer on the inner wall. If atomic layer deposition (ALD) technology is used, it faces bottlenecks such as slow deposition rates and extremely high precursor costs, severely restricting large-area, low-cost production.

[0007] Electrophoretic deposition relies on the accumulation of nanoparticles. Pores may exist between the particles, and in trenches with high aspect ratios, the transport and accumulation of particles under the action of an electric field may be uneven, which can easily form voids or poorly filled areas in the upper part of the trench, affecting the final uniformity of X-ray absorption.

[0008] The filling rate and final morphology of electrophoretic deposition are extremely sensitive to parameters such as electric field strength, suspension concentration, and particle size distribution. The process window is narrow and reproducibility is poor. For seed layer electroplating, if the seed layer quality is poor, a "capping" effect is easily formed at the trench opening in the early stage of electroplating, which hinders the transport of electroplating solution and ions to the depth of the trench, thereby creating irreparable voids in the lower part of the trench.

[0009] In summary, existing technologies suffer from problems such as uneven performance, poor reliability, high production costs, low production efficiency, and low yield due to complex processes, expensive materials, inherent filling quality defects, and stringent process control requirements. This severely hinders the mass production of high-performance, large-area hard X-ray gratings and their widespread application in practical imaging systems. Summary of the Invention

[0010] To address the aforementioned technical problems in the existing technology, this invention provides a method for fabricating a high aspect ratio X-ray grating and an X-ray grating. The technical solution is as follows:

[0011] On one hand, a method for fabricating a high aspect ratio X-ray grating is provided. The method includes: using a highly doped, low-resistivity single-crystal silicon wafer as a substrate, cleaning it, and depositing a silicon dioxide hard mask with a thickness of micrometers on the surface; transferring the grating pattern to the silicon dioxide hard mask based on photolithography and reactive ion etching processes; performing deep silicon etching on the substrate using an improved low-temperature Bosch process to create a high aspect ratio vertical deep trench; removing the native oxide layer on the back side of the substrate, then depositing a metal layer and performing thermal annealing to construct a low-ohmic contact conductive back electrode; removing the native oxide layer at the bottom of the vertical deep trench, electrochemically depositing a nanoscale gold nucleation layer on the inner wall of the vertical deep trench using a cyanide plating solution, and performing multi-stage cleaning; placing the substrate in a bismuth ion-assisted gold sulfite plating solution for electroplating, so that the gold layer fills from the bottom of the vertical deep trench upwards; removing the silicon dioxide hard mask, cleaning and drying to obtain the X-ray grating.

[0012] Optionally, the matrix includes N-type antimony doping. <100> Crystal-oriented monocrystalline silicon wafers.

[0013] Optionally, the grating pattern is transferred to the silicon dioxide hard mask based on photolithography and reactive ion etching processes. A modified low-temperature Bosch process is used to perform deep silicon etching on the substrate to create a high aspect ratio vertical deep trench. This includes: spin-coating photoresist onto the silicon dioxide hard mask; aligning and exposing the grating pattern mask with a photomask and developing it with a developer; exposing the grating pattern silicon dioxide hard mask through reactive ion etching with a fluorine-based gas; removing the photoresist from the silicon dioxide hard mask and then cleaning and drying it; performing deep silicon etching on the substrate using the modified low-temperature Bosch process to create a high aspect ratio vertical deep trench; removing the sidewall polymer of the vertical deep trench using oxygen plasma ashing; removing the oxide layer at the bottom of the vertical deep trench using dilute hydrofluoric acid or a buffered oxide etching solution; and then drying the material.

[0014] Optionally, the substrate is deep etched using an improved low-temperature Bosch process to create a high aspect ratio vertical deep trench, including: periodically switching between fluorine-based etching gas and fluorocarbon passivation gas, and using ion bombardment to preferentially remove the passivation layer of the vertical deep trench to form a highly anisotropic vertical deep trench.

[0015] Optionally, the aspect ratio of the vertical deep trench exceeds 50:1; the deposited metal layer is a gold layer of 100-200 nm; the cyanide plating solution is a weakly acidic gold-cobalt electroplating solution with a pH value controlled at 3.8-4.2; the electrochemical deposition is constant current electroplating with a current density of 1.0-1.5 mA / cm²; and the thickness of the nanoscale gold nucleation layer is 20-50 nm.

[0016] Optionally, a multi-stage cleaning process may be performed, including sequential overflow rinsing, acidic solution neutralization, megasonic cleaning, and final settling rinsing.

[0017] Optionally, the substrate is electroplated in a bismuth ion-assisted gold sulfite plating solution, comprising: placing the substrate in the bismuth ion-assisted gold sulfite plating solution, and using immersion spin plating and segmented potential control to induce a gold layer to fill from the bottom of the vertical deep trench upwards; wherein, the immersion spin plating comprises: placing a platinum anode at the bottom of the electrolytic cell, fixing the substrate to the end of the rotating electrode device and horizontally suspending it directly above the anode, and, driven by a motor, completely immersing the substrate in the plating solution and rotating it horizontally; the segmented potential control comprises: a first stage: when the substrate is at a potential of 280-320... In the first stage, a potential of -0.78V to -0.75V is applied while rotating at a speed of rpm for 2-4 hours to suppress deposition at the trench opening and upper sidewall. In the second stage, the potential is shifted positively to -0.73V to -0.72V and maintained for 20-30 hours to induce gold to grow upward from the bottom of the vertical deep trench until the growth front touches the strong fluid shear zone generated by high-speed rotation and automatically terminates.

[0018] Optionally, the bismuth ion-assisted gold sulfite electroplating solution comprises: 160 mmol / L sodium gold sulfite, 0.64 mol / L sodium sulfite, and bismuth ions at a concentration of 40-50 μmol / L.

[0019] Optionally, removing the silicon dioxide hard mask includes: removing the silicon dioxide hard mask using a buffered oxide etching solution in a light-protected and low-oxygen environment.

[0020] On the other hand, an X-ray grating prepared by the method for preparing a high aspect ratio X-ray grating according to an embodiment of the present invention is also provided.

[0021] This invention provides a method for fabricating a high aspect ratio X-ray grating and an X-ray grating. By utilizing the bulk conductivity of the silicon substrate, the shadowing effect of physical vapor deposition inside deep holes is overcome. Seamless metal filling from the bottom up can be achieved in micro-trenches with an aspect ratio exceeding 50:1, significantly improving the metal density and X-ray blocking efficiency of the grating lines. Utilizing the perfect lattice continuity and homogeneous conductivity of a single low-resistivity monocrystalline silicon material, an extremely high-quality isopotential cathode surface is provided for electrochemical deposition, ensuring a uniform distribution of current density across the entire wafer surface. This achieves a highly consistent growth rate of the metal grating lines, alleviating the technical problems of uneven performance, poor reliability, high production cost, and low production efficiency and yield of X-ray gratings fabricated by existing technologies. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a flowchart of a high aspect ratio X-ray grating fabrication method provided in an embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram of a low-resistivity single-crystal silicon wafer provided in an embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of the structure after depositing a micron-sized silicon dioxide hard mask according to an embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram of the structure after spin-coating photoresist according to an embodiment of the present invention;

[0027] Figure 5 This is a schematic diagram of the structure of silicon dioxide after photolithography, development and RIE etching provided in an embodiment of the present invention;

[0028] Figure 6 This is a schematic diagram of the structure after high aspect ratio silicon trenches are etched using an improved Bosch process, according to an embodiment of the present invention.

[0029] Figure 7 This is a schematic diagram of the structure of a wafer after a metal layer is deposited on the back side and annealed, according to an embodiment of the present invention.

[0030] Figure 8 This is a schematic diagram of the structure after a nanoscale gold nucleation layer is deposited in a tank using a cyanide plating solution, according to an embodiment of the present invention.

[0031] Figure 9 This is a schematic diagram of the structure of a gold layer after being filled with a bismuth ion-assisted gold sulfite electroplating solution, provided by an embodiment of the present invention.

[0032] Figure 10 This is a schematic diagram of an X-ray grating structure obtained after removing a silicon dioxide mask, provided in an embodiment of the present invention.

[0033] Figure 11 This is a scanning electron microscope cross-sectional view of an X-ray grating prepared by the high aspect ratio X-ray grating preparation method provided in this embodiment of the invention. Detailed Implementation

[0034] The technical solution of the present invention will now be described with reference to the accompanying drawings.

[0035] In embodiments of the present invention, words such as "exemplarily," "for example," etc., are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" in the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present the concept in a concrete manner. Furthermore, in embodiments of the present invention, the meaning expressed by "and / or" can be both, or either one.

[0036] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0037] Figure 1 This is a flowchart illustrating a method for fabricating a high aspect ratio X-ray grating according to an embodiment of the present invention. Figure 1 As shown, the method specifically includes the following steps:

[0038] In step S102, a silicon dioxide hard mask with a micron-thickness is deposited on the surface of a highly doped, low-resistivity single-crystal silicon wafer as the substrate after cleaning.

[0039] Step S104: Based on photolithography and reactive ion etching processes, the grating pattern is transferred to a silicon dioxide hard mask, and the substrate is etched with a modified low-temperature Bosch process to create a high aspect ratio vertical deep trench.

[0040] Step S106: Remove the natural oxide layer on the back side of the substrate, then deposit a metal layer and perform thermal annealing to construct a conductive back electrode with low ohmic contact.

[0041] Step S108: Remove the native oxide layer at the bottom of the vertical deep trench, electrochemically deposit a nanoscale gold nucleation layer on the inner wall of the vertical deep trench using cyanide plating solution, and perform multi-stage cleaning.

[0042] Step S110: The substrate is placed in a bismuth ion-assisted gold sulfite plating solution for electroplating, so that the gold layer fills from the bottom of the vertical deep trench upwards.

[0043] Step S112: Remove the silicon dioxide hard mask, wash and dry to obtain an X-ray grating.

[0044] This invention first grows a silicon dioxide layer on a low-resistivity silicon substrate, utilizing its corrosion resistance and high hardness to serve as both a robust mask for deep silicon etching and a self-stopping layer for subsequent polishing. Then, a high aspect ratio vertical trench is fabricated using deep reactive ion etching (DRIE). Next, a cyanide electroplating process is used to replace the traditional vacuum deposition process, avoiding the discontinuous seed layer coverage caused by the shadowing effect within the high aspect ratio structure. This directly constructs a conductive gold layer inside the silicon trench, solving the problem that sulfite electrolyte cannot grow directly on the silicon surface. Subsequently, the selective inhibition effect of bismuth ion additives, combined with dynamic potential control, achieves a filling mode where the gold layer grows from the bottom of the trench upwards, overcoming the void defect caused by premature closure of the trench opening in traditional electroplating processes. Finally, chemical mechanical polishing is used to remove the overflowing metal protruding above the trench surface. The silicon dioxide layer is used to automatically detect and remove the polishing endpoint, completing the fabrication of a void-free, low-cost hard X-ray grating.

[0045] Preferably, the matrix comprises N-type antimony (Sb) doping. <100> Crystal-oriented monocrystalline silicon wafers with resistivity below 0.01 Ω·cm. Figure 2 This is a schematic diagram of the structure of a low-resistivity single-crystal silicon wafer according to an embodiment of the present invention. Figure 2 As shown, preferably, the substrate is a double-sided polished wafer with a diameter of 100mm.

[0046] Specifically, step S102 further includes the following steps: selecting a highly doped, low-resistivity single-crystal silicon wafer as the substrate, and depositing a micron-thick silicon dioxide hard mask using a PECVD process after standard cleaning.

[0047] Preferably, the standard cleaning process employs a standard RCA cleaning procedure, followed by rinsing with deionized water and drying with nitrogen. The RCA cleaning process includes: removing organic contaminants using an SC-1 solution (NH4OH:H2O2:H2O = 1:1:5) at 75°C; subsequently removing metal ions using an SC-2 solution (HCl:H2O2:H2O = 1:1:6) at 75°C; and finally rinsing with deionized water and drying with nitrogen.

[0048] Preferably, a silicon dioxide layer is deposited on the wafer using a plasma-enhanced chemical vapor deposition (PECVD) process.

[0049] Preferably, the thickness of the silicon dioxide layer hard mask is 1.5 μm ± 0.1 μm. Figure 3 This is a schematic diagram of the structure after depositing a micron-sized silicon dioxide hard mask according to an embodiment of the present invention.

[0050] This invention sets the thickness of the silicon dioxide hard mask at the micrometer level, enabling it to effectively withstand long-term high-energy ion bombardment during subsequent deep silicon etching. By utilizing the high etching selectivity of silicon dioxide to silicon, it effectively compensates for the mask edge loss caused by physical sputtering during deep etching, preventing the premature exposure of the underlying silicon edges, thereby ensuring the integrity and steepness of the top contour of the high aspect ratio grating.

[0051] Specifically, step S104 further includes the following steps:

[0052] Step S1041: Photoresist is spin-coated onto a silicon dioxide hard mask. After alignment with a grating pattern mask and development with a developer, the silicon dioxide hard mask with the grating pattern is exposed by reactive ion etching using a fluorine-based gas. The structure of the substrate after spin-coating the photoresist is as follows: Figure 4 As shown, the schematic diagram of the structure after photolithography, development, and RIE etching of silicon dioxide is as follows: Figure 5 As shown.

[0053] Step S1042: After removing the photoresist from the silicon dioxide hard mask, clean and dry it to ensure the surface is clean.

[0054] In step S1043, the substrate is etched with deep silicon using an improved low-temperature Bosch process to create a vertical deep trench with a high aspect ratio.

[0055] Among them, the improved low-temperature Bosch process involves periodically switching between fluorine-based etching gas and fluorocarbon-based passivation gas, and using ion bombardment to preferentially remove the passivation layer of vertical deep trenches, thereby forming highly anisotropic vertical deep trenches.

[0056] Specifically, the process gas introduced into the reaction chamber is alternately switched periodically to achieve alternating circulation. Fluorine-based etching gas is alternately introduced to perform isotropic chemical etching on the silicon substrate, and fluorocarbon passivation gas is introduced to deposit a polymer protective layer on the trench surface. During this process, the vertical ion bombardment generated in the etching stage preferentially removes the passivation layer at the bottom of the trench while retaining the passivation layer on the sidewalls, thereby inhibiting lateral drilling and guiding the etching reaction to penetrate vertically, ultimately forming a highly anisotropic vertical deep trench.

[0057] Preferably, the substrate temperature in the improved low-temperature Bosch process is strictly controlled between -10°C and 10°C, preferably 0°C; the cavity pressure is controlled between 15-30 mTorr; and the inductively coupled plasma (ICP) power is controlled between 600-1000W.

[0058] Preferably, the depth of the formed vertical deep trench is 70-110 μm, the width of the grating trench is 1-3 μm, and the aspect ratio exceeds 50:1. A schematic diagram of the structure after forming the high aspect ratio silicon trench using the improved Bosch process is shown below. Figure 6 As shown. This invention effectively suppresses chemical corrosion of the sidewalls through a low-temperature etching process, achieving a vertical sidewall profile close to 90°, providing a good geometric basis for subsequent high-quality filling.

[0059] In step S1044, after removing the sidewall polymer of the vertical deep trench using oxygen plasma ashing, the oxide layer at the bottom of the vertical deep trench is removed using dilute hydrofluoric acid or buffered oxide etching solution, and then dried to expose the fresh silicon surface.

[0060] Specifically, step S106 includes three steps:

[0061] The first step is back-side pretreatment, which involves briefly immersing and cleaning the back of the wafer with dilute hydrofluoric acid or buffered oxide etching solution to thoroughly remove the natural oxide layer on the silicon surface of the substrate. Nitrogen drying is then performed immediately to prevent secondary oxidation.

[0062] The second step is metal deposition, in which the processed wafer is placed in a vacuum coating apparatus, and a gold layer is deposited on the back of the wafer using electron beam evaporation or magnetron sputtering. Preferably, the deposited metal layer is a 100-200 nm thick gold layer.

[0063] The third step is alloying annealing. In this step, the wafer after metal deposition is placed in a rapid thermal annealing furnace and heated to 300℃-400℃ under a nitrogen or argon protective atmosphere (this temperature range covers the gold-silicon eutectic point) and held for 10-30 minutes. This promotes interdiffusion of gold and silicon atoms at the interface, utilizing the gold-silicon eutectic reaction to construct a low-ohmic contact conductive back electrode. A schematic diagram of the structure after metal deposition and annealing on the back of the wafer is shown below. Figure 7 As shown.

[0064] This invention ensures excellent adhesion between the metal layer and the silicon substrate and forms a low-resistance ohmic contact through back-side gold deposition and annealing, thereby guaranteeing a uniform distribution of current density across the entire wafer during subsequent electroplating.

[0065] Specifically, step S108 includes the following steps:

[0066] Step S1081: Using a vapor-phase hydrofluoric acid etching process, under controlled temperature and pressure conditions, the native oxide layer at the bottom of the vertical deep trench is precisely removed while the top silicon dioxide hard mask is retained, so that a clean and conductive silicon surface is exposed inside the vertical deep trench.

[0067] Preferably, the temperature of the wafer is controlled between 25°C and 35°C. This temperature range is used to control the adsorption rate of gaseous HF on the silicon surface and prevent uncontrollable corrosion caused by HF liquefaction and condensation due to excessively low temperature.

[0068] Preferably, the back pressure of the reaction chamber is controlled within the range of 50 Torr-200 Torr. This low-pressure environment helps to increase the mean free path of gas molecules and enhance their diffusion ability in the high aspect ratio trench.

[0069] Preferably, by adjusting the flow rate ratio of carrier gas to reactant gas, the volume concentration of HF in the cavity is precisely maintained within the range of 3%-10%. This concentration range is sufficient to quickly remove the extremely thin native oxide layer at the bottom of the trench, while the etching amount on the micron-thick silicon dioxide mask is extremely small, only tens of nanometers, thus perfectly preserving its insulating barrier function.

[0070] Step S1082 involves rapidly electrochemically depositing an ultrathin, continuous, and firmly adhered nanoscale gold nucleation layer on the inner wall of a vertical deep trench using a cyanide plating solution. A schematic diagram of the structure after depositing the nanoscale gold nucleation layer in the trench using the cyanide plating solution is shown below. Figure 8 As shown.

[0071] Preferably, the cyanide plating solution is a weakly acidic gold-cobalt electroplating solution, more preferably an Autronex-GVC acidic gold-cobalt electroplating solution, with the pH value controlled at 3.8-4.2. The weakly acidic environment is used to maintain the hydrogen passivation state of the silicon surface and prevent surface re-oxidation.

[0072] Preferably, the electrochemical deposition is constant current electroplating with a current density of 1.0-1.5 mA / cm². 2 The electroplating time is 15-30 seconds; the thickness of the nanoscale gold nucleation layer is 20-50 nm.

[0073] This invention utilizes the advantages of cyanide systems, such as overcoming the hydrophobicity of silicon surfaces and achieving tight adhesion, to rapidly construct an extremely thin and dense initial conductive layer. This layer does not aim to fill the trenches but serves only as a conductive base for subsequent sulfite processes.

[0074] Step S1083 involves multi-stage deep cleaning and residue removal.

[0075] Specifically, a multi-stage cleaning process is performed, including sequential overflow rinsing, acid solution neutralization, megasonic cleaning, and final settling rinsing. Specifically, overflow rinsing involves rinsing with flowing deionized water for 10-15 minutes to remove surface and shallow plating solution; acid solution neutralization involves immersing in 5% dilute sulfuric acid for 1 minute to eliminate residual cyanide ions; megasonic cleaning involves treatment in a 1MHz megasonic water bath for 10 minutes to remove deep-seated residues; and the final settling rinsing involves standing in ultrapure water for 5 minutes as a buffer before proceeding to the next process. This step is used to remove cyanide residues to prevent contamination of the subsequent sulfite plating solution and potential plating failure.

[0076] The rigorous multi-stage cleaning process is crucial in this invention. Because the cyanide system used in the preceding step is incompatible with the subsequent sulfite system, any residual cyanide ions introduced into the sulfite plating solution could cause rapid deterioration and render the solution unusable, leading to subsequent plating failures. This step, while protecting the fragile nano-gold layer and micron-scale grating lines from collapse, completely prevents residual chemicals from the previous process from contaminating the next.

[0077] Specifically, step S110 includes the following steps: placing the substrate in a bismuth ion-assisted gold sulfite electroplating solution, and using immersion spin plating and segmented potential control to induce the gold layer to fill from the bottom of the vertical deep trench upwards. A schematic diagram of the structure after filling the gold layer using the bismuth ion-assisted gold sulfite electroplating solution is shown below. Figure 9 As shown.

[0078] Preferably, the bismuth ion-assisted gold sulfite electroplating solution comprises: sodium gold sulfite (Na3Au(SO3)2) at a concentration of 160 mmol / L, sodium sulfite (Na2SO3) at a concentration of 0.64 mol / L, and the key additive bismuth ions (Bi... 3+ The concentration is 40-50 μmol / L; the pH of the electrolyte is adjusted to 9.0-9.5.

[0079] Immersion spin plating includes:

[0080] Platinum anode is placed at the bottom of the electrolytic cell, and the substrate is fixed at the end of the rotating electrode device and suspended horizontally above the anode. Driven by a motor, the substrate is completely immersed in the electroplating solution and rotates horizontally.

[0081] Segmented potential control includes:

[0082] First stage: While the substrate is rotating at 280-320 rpm, a potential of -0.78V to -0.75V is applied for 2-4 hours to inhibit deposition at the trench opening and upper sidewall.

[0083] In the second stage, the potential is shifted positively to -0.73V to -0.72V and maintained for 20-30 hours to induce gold to grow upward from the bottom of the vertical deep trench until the growth front touches the strong fluid shear zone generated by high-speed rotation and automatically terminates.

[0084] This invention achieves a strong inhibition layer at the top of the trench while maintaining growth activity at the bottom through the synergistic effect of high rotation speed and bismuth ions. Furthermore, by combining two-stage potential control, it ensures that the gold layer can achieve void-free filling in a bottom-up manner while effectively balancing the establishment and filling efficiency of the passivation layer.

[0085] Specifically, step S112 further includes: removing the silicon dioxide hard mask using a buffer oxide etching solution in a light-proof and low-oxygen environment to obtain an X-ray grating with gold lines slightly lower than the silicon sidewalls.

[0086] Preferably, the mask removal process uses a buffered oxide etchant (BOE) with a formulation of HF:NH4F = 1:6, and the process temperature is kept constant at 25°C. The entire process must be carried out in a strictly light-proof and low-oxygen environment. A schematic diagram of the X-ray grating structure obtained after removing the silicon dioxide mask is shown below. Figure 10 As shown.

[0087] This invention minimizes the electrochemical current of the galvanic cell at the gold-silicon contact interface through the aforementioned dual inhibition mechanism, thereby ensuring that the etching solution selectively removes only the insulating silicon dioxide mask and completely avoids the risk of metal-assisted chemical corrosion of the silicon skeleton around the gold lines.

[0088] Figure 11 This is a scanning electron microscope (SEM) cross-sectional image of an X-ray grating prepared by the high aspect ratio X-ray grating preparation method provided in an embodiment of the present invention. Figure 11 As shown, there are no voids filled.

[0089] This invention also provides an X-ray grating fabricated according to the above-described high aspect ratio X-ray grating fabrication method, wherein there are no voids between the metal filler and the silicon sidewall of the X-ray grating, and the top height of the metal filler is lower than the opening plane of the trench.

[0090] As described above, the high aspect ratio X-ray grating fabrication method and X-ray grating provided by the embodiments of the present invention adopt a unique processing procedure of "back-side conduction + internal chemical nucleation". This procedure omits the PVD seed layer preparation step on the inner wall of the high aspect ratio trench, requiring only conventional PVD preparation of the back planar conductive layer. The inside of the trench is rapidly chemically nucleated using cyanide electroplating solution, eliminating the dependence on expensive atomic layer deposition (ALD) and complex deep-hole PVD processes, and significantly reducing manufacturing difficulty and equipment costs. At the same time, the present invention adopts a bismuth ion-assisted bottom-up growth mode, with the metal advancing unidirectionally from the bottom, completely solving the problem of filling voids and gaps caused by poor seed layer coverage in traditional processes. This achieves seamless and dense growth of the metal in the deep trench, thereby significantly improving the imaging quality of the X-ray grating.

[0091] This invention utilizes a fluid shear passivation mechanism to achieve "self-termination" of gold layer growth at the trench opening, eliminating the need for chemical mechanical polishing (CMP) and secondary polishing of surface-overflowing metal. This avoids mechanical stress damage to the high aspect ratio brittle silicon framework, ensuring the structural integrity of the device. This process simplifies the process, saves processing time, and significantly improves the product yield, enabling the stable fabrication of high-performance X-ray gratings to meet the stringent requirements of precision optical imaging.

[0092] Example 1 (Lower Limit Parameter Example)

[0093] This embodiment demonstrates the fabrication of a hard X-ray grating using relatively low process parameters. Substrate preparation and patterning: An N-type (100) single-crystal silicon wafer with a resistivity of 0.008 Ω·cm and a diameter of 100 mm is provided. After RCA standard cleaning, a silicon dioxide layer with a thickness of 1.0 μm is deposited on its front side using a PECVD process. A grating pattern with a period of 3.0 μm and a duty cycle of 0.5 is transferred to this silicon dioxide hard mask layer by ultraviolet lithography and reactive ion etching (RIE).

[0094] Deep silicon etching: Using an Oxford Instruments PlasmaLab 100 system, a modified Bosch process (etch / passivation time ratio of 3s / 3s) was performed at a substrate temperature of 0°C, a chamber pressure of 15 mTorr, and an ICP power of 600 W to etch a trench array with a depth of 70 μm. The trench width was approximately 1.5 μm, the aspect ratio was approximately 47:1, and the sidewall perpendicularity was approximately 86°. After etching, the sidewall polymer was removed by O2 plasma ashing.

[0095] Back electrode fabrication: After the natural oxide layer on the back side of the wafer is removed by immersion in dilute HF, it is immediately placed in an electron beam evaporation stage to deposit a 100 nm thick gold layer. Subsequently, it is annealed at 300°C for 10 minutes in a nitrogen atmosphere to form an ohmic contact.

[0096] Precise HF processing in the gas phase: The wafer is placed in a sealed chamber and treated for 40 seconds with a 3% (v / v) HF / nitrogen mixture at 25°C and a back pressure of 50 Torr. This process completely removes the native oxide layer at the bottom of the trench, while the loss of the front silicon dioxide mask, as measured by an ellipsometry, is less than 50 nm.

[0097] Seed layer deposition in the cyanide system: Electroplating was performed for 15 seconds using Autronex-GVC commercial plating solution (pH=4.0) at a constant current density of 1.0 mA / cm². A continuous gold layer with a thickness of approximately 20 nm was formed on the inner wall and bottom of the trench.

[0098] Multi-stage cleaning: The process was performed sequentially as follows: a) Overflow rinsing with deionized water for 10 minutes; b) Immersion in 5% dilute sulfuric acid for 1 minute; c) Water rinsing with 1MHz megasonic wave for 10 minutes; d) Rinsing with ultrapure water for 5 minutes. Ion chromatography analysis showed that cyanide residue was below 1 ppb after cleaning.

[0099] Bismuth-assisted bottom-up plating: The second electroplating solution was prepared, containing 160 mmol / L Na3Au(SO3)2, 0.64 mol / L Na2SO3, and 40 μmol / L Bi. 3+ The pH was adjusted to 9.0 using NaOH. A rotating disk electrode apparatus was used to horizontally immerse the wafer, with a large-area platinum sheet as the anode. Initially, a potential of -0.78 V (vs. SSE) was applied at 300 rpm for 2 hours. Subsequently, the potential was shifted positive to -0.73 V, and electroplating continued for 20 hours. SEM cross-sections showed that gold completely filled the trench from the bottom upwards, and growth automatically stopped approximately 2 μm from the trench opening, with no voids formed.

[0100] Mask Removal and Completion: The sample was immersed in a 6:1 BOE solution at 25°C in the dark for 3 minutes to completely remove the silica hard mask. After cleaning and drying, a hard X-ray grating with a gold filling height of approximately 68 μm and a flat top was obtained.

[0101] Example 2 (Upper Limit Parameter Example)

[0102] This embodiment demonstrates the fabrication of a hard X-ray grating using advanced process parameters. Substrate preparation and patterning: An N-type (100) monocrystalline silicon wafer with a resistivity of 0.005 Ω·cm is provided. A silicon dioxide hard mask layer with a thickness of 2.0 μm is deposited on its front side, and a grating pattern with a period of 2.4 μm is transferred.

[0103] Deep silicon etching: Bosch etching was performed at a substrate temperature of 10℃, a chamber pressure of 30 mTorr, and an ICP power of 800 W (etching / passivation time ratio of 4s / 2s) to form trenches with a depth of 110 μm and a width of approximately 1.2 μm, an aspect ratio of approximately 92:1, and a sidewall perpendicularity greater than 88°.

[0104] Back electrode fabrication: A 200 nm thick gold layer was deposited on the back side of the wafer and annealed at 400 °C in an argon atmosphere for 30 minutes.

[0105] Precise HF gas-phase processing: At 35°C and 200 Torr, a 10% (v / v) HF / nitrogen mixture was introduced for 20 seconds. This completely removed the bottom oxide layer, resulting in a mask loss of approximately 80 nm on the front side.

[0106] Seed layer deposition in cyanide system: at a constant current density of 1.5 mA / cm²2 Electroplating for 30 seconds forms an initial gold layer with a thickness of approximately 50 nm.

[0107] Multi-stage cleaning: Perform rigorous cleaning according to the procedure in Example 1.

[0108] Bismuth-assisted bottom-up filling: Bi in the second electroplating solution 3+ The concentration was 50 μmol / L, and the pH was adjusted to 9.5. A potential of -0.75 V was applied for 4 hours in the first stage at 320 rpm, and a potential of -0.72 V was applied for 30 hours in the second stage. The filling process was stable, ultimately yielding a void-free structure with a filling height of approximately 108 μm and exhibiting clear self-termination characteristics.

[0109] Mask Removal and Completion: Use BOE to remove the mask and obtain the final raster.

[0110] Example 3 (Intermediate Parameter Example)

[0111] This embodiment demonstrates the fabrication of a hard X-ray grating using centered process parameters. Substrate preparation and patterning: An N-type (100) monocrystalline silicon wafer with a resistivity of 0.01 Ω·cm is provided. A silicon dioxide hard mask layer with a thickness of 1.5 μm is deposited on its front side, and a grating pattern with a period of 5.25 μm is transferred.

[0112] Deep silicon etching: Bosch etching was performed at 0°C, 25 mTorr, and 700 W ICP power to form trenches with a depth of 100 μm and a width of approximately 2.63 μm, with an aspect ratio of approximately 38:1.

[0113] Back electrode fabrication: A 150 nm thick gold layer was deposited on the back side of the wafer and annealed at 350 °C in a nitrogen atmosphere for 20 minutes.

[0114] Precise HF processing in the gas phase: At 30°C and 100 Torr, a 6% (v / v) HF / nitrogen mixed gas was introduced and processed for 30 seconds. The front mask loss was approximately 65 nm.

[0115] Seed layer deposition in cyanide system: at a constant current density of 1.2 mA / cm² 2 Electroplating for 22 seconds forms an initial gold layer with a thickness of approximately 35 nm.

[0116] Multi-stage cleaning: Perform rigorous cleaning according to the procedure in Example 1.

[0117] Bismuth-assisted bottom-up filling: Bi in the second electroplating solution 3+The concentration was 45 μmol / L, and the pH was adjusted to 9.2. A potential of -0.77 V was applied for 3 hours in the first stage at 300 rpm, and a potential of -0.725 V was applied for 25 hours in the second stage. The filling effect was uniform, with good consistency in filling height throughout the wafer, averaging approximately 98 μm, and no voids or gaps were observed.

[0118] Mask Removal and Completion: The mask is removed using BOE to obtain a high-quality raster.

[0119] Table 1 is a comparison table of product quality parameters corresponding to three specific embodiments provided by the present invention. As shown in Table 1, the technical effects achieved by this solution are described below in conjunction with the three specific embodiments. These examples show that the present technical solution can stably achieve the expected goals within the parameter spectrum defined in the claims, and exhibits superior process adaptability and product performance.

[0120] Comparison Table of Product Quality Parameters for Examples

[0121]

[0122] The three embodiments fully implemented the core process chain of "cyanide system deposition of an ultrathin seed layer—multi-stage cleaning—sulfite system bottom-up filling." Final cross-sectional SEM images all showed completely dense metal filling without any voids or gaps. This result directly confirms that the designed multi-stage cleaning process can completely prevent cross-contamination between the cyanide and sulfite systems, ensuring the purity of process switching; the nanoscale gold layer formed by wet electrochemistry is sufficient as an efficient and uniform electrochemical nucleation site, successfully replacing the traditionally relied-upon and costly high aspect ratio PVD or ALD seed layer technology.

[0123] In all embodiments, through the synergistic effect of "segmented potential application" and "high-speed rotation-induced fluid shear field," gold deposition was precisely initiated from the bottom of the trench and continued to grow upwards, eventually stopping automatically in the strong shear zone near the opening. This demonstrates the high reliability of the built-in termination mechanism of "fluid shear passivation," thereby directly obtaining a smooth-surfaced filled structure without the need for chemical mechanical polishing (CMP), fundamentally avoiding the potential mechanical damage to the microstructure caused by CMP.

[0124] The examples cover the lower, median, and upper limits of key process parameters, and all successfully fabricated qualified devices, fully demonstrating the rationality and operability of the claimed parameter range. Gas-phase HF treatment, with concentrations of 3%-10% and corresponding processing times, exhibits excellent selectivity, achieving complete removal of the natural oxide layer at the bottom of the trench, while precisely controlling the hard mask loss to within 5% of the micron-level thickness. The bottom-up filling process, facing a wide range of aspect ratios from 38:1 to 92:1, utilizes adapted Bi... 3+ Concentration, potential, and time parameters all resulted in defect-free filling. Example 2, in particular, was successful even at an extreme aspect ratio approaching 100:1, strongly demonstrating the superior ability and innovative level of this invention in handling extremely high aspect ratio structures.

[0125] While achieving the common goal of high quality, each embodiment also exhibits characteristics based on parameter selection:

[0126] Example 1 (lower limit parameter) has a short process cycle and outstanding cost-effectiveness, providing a reliable solution for cost-sensitive applications.

[0127] Example 2 (upper limit parameter) targets the technical limit and achieves a top-notch horizontal fill with an aspect ratio of approximately 92:1, meeting the stringent requirements of cutting-edge high-resolution imaging systems.

[0128] Example 3 (intermediate parameters) achieves an excellent balance between performance, efficiency and cost, demonstrating its potential to be best suited for mass production.

[0129] In summary, the solution provided by this invention has demonstrated its core advantages through system verification in three embodiments: it replaces the expensive vacuum seed layer technology with a simplified wet process combination, overcomes the reliability problem of high aspect ratio metal filling, simplifies the post-processing process with the built-in "self-termination" mechanism, and is compatible with standard silicon-based micromachining processes, thus possessing significant industrialization prospects.

[0130] As described above, the embodiments of the present invention provide a method for fabricating a high aspect ratio X-ray grating and an X-ray grating, which have the following technical advantages compared with the prior art:

[0131] 1. Innovative process principle of direct electrochemical nucleation without seed layer and bottom-up superfilling catalysis:

[0132] This invention proposes a novel approach to seed layer preparation that abandons traditional physical vapor deposition (PVD) or atomic layer deposition (ALD). First, within a conductive silicon trench where the bottom oxide layer has been removed, a short-term constant-current electroplating process using a cyanide plating solution is performed to directly form an ultrathin (20-50 nm), continuous nanoscale gold layer on the silicon surface as a "chemical seed." Subsequently, the process is switched to a solution containing bismuth ions (Bi...3+ The gold sulfite plating solution with additives triggers the gold deposition reaction from the bottom of the trench and upwards through the preferential adsorption and catalytic effect of bismuth ions in the bottom region of the trench, achieving "bottom-up" superfilling.

[0133] This combination fundamentally solves the core bottleneck of discontinuous seed layer coverage and high equipment costs on the inner wall of high aspect ratio trenches. The nanoscale "chemical seeds" are prepared quickly and have good coverage; the selective catalysis of bismuth ions ensures that the filling process starts from the deepest part, effectively avoiding voids formed by premature closure of the opening, and ultimately achieving a pore-free and completely dense metal filling.

[0134] 2. Precise and selective removal of oxide layer at the bottom of high aspect ratio trenches by gas-phase hydrofluoric acid:

[0135] This invention proposes a low-pressure, room-temperature gas-phase hydrofluoric acid (HF) treatment process. By precisely controlling the pressure (50-200 Torr), temperature (25-35℃), and HF gas concentration (3%-10%) of the reaction chamber, and utilizing the good diffusion of gas molecules within the micro-nano trenches, the ultrathin natural oxide layer at the bottom of the trench is etched away only, while the etching loss on the micron-scale silicon dioxide hard mask at the top and sidewalls of the trench is reduced to negligible (<5%).

[0136] This method creatively solves the challenge of performing regionally differentiated treatments within the same structure (where the bottom needs to be conductive and the top needs to be insulating). It exposes a clean and active conductive silicon surface for subsequent seedless electrochemical nucleation, which is a prerequisite for forming good "chemical seeds." At the same time, the well-preserved top silicon dioxide mask continues to serve as a protective layer and endpoint indicator layer for subsequent processes, ensuring the feasibility of the process.

[0137] 3. Bottom-up filling and self-termination process control based on the synergy of segmented potential and rotating shear flow field:

[0138] This invention proposes a dynamic potential and hydrodynamic control strategy. During the filling stage, the wafer is completely immersed and rotated horizontally at high speed (280-320 rpm), with two stages of potential applied: the first stage (-0.78 V ~ -0.75 V) utilizes strong fluid shear force to strip away the bismuth catalyst in the trench opening and upper region, passivating it; the second stage shifts the potential positively (-0.73 V ~ -0.72 V), maintaining catalytic activity at the bottom of the trench where the fluid is relatively still, driving gold growth upwards. When the growth front advances to the strong shear region near the opening, the catalytic effect is automatically inhibited, achieving growth "self-termination".

[0139] This control method achieves spatial selectivity (bottom-only growth) and time controllability (automatic stop) in the filling region. It ensures high uniformity and consistency of filling and avoids excessive metal buildup at the top of the trench, thereby eliminating the chemical mechanical polishing (CMP) step required in traditional processes. This eliminates the mechanical damage that CMP may cause to brittle silicon structures with high aspect ratios, simplifies the process, and improves yield.

[0140] 4. A complete manufacturing solution integrating dual-system electroplating and systematic processes:

[0141] This invention proposes a systematic integrated manufacturing method from substrate processing to final shaping. The overall approach can be summarized as follows: Based on a low-resistivity silicon wafer and a silicon dioxide hard mask, trenches are formed through deep etching; an ohmic contact on the back side is constructed as the global current conduction path; selective activation of the bottom is achieved using vapor-phase HF; void-free filling is achieved through a seamless connection of a dual electroplating system of "cyanide fast plating nucleation" and "sulfite-bismuth catalytic superfilling"; finally, the hard mask is removed by wet etching. The entire scheme incorporates rigorous multi-stage cleaning steps to ensure the purity of the dual electroplating system switching. This method provides a novel hard X-ray grating manufacturing path that is independent of expensive ALD / PVD seed layer equipment, has a wide process window, and high scalability. It systematically solves the technical challenges of the entire process from conductivity establishment, selective nucleation, perfect filling to structure release, ultimately enabling the stable, efficient, and low-cost fabrication of large-area, high-performance hard X-ray gratings with void-free, high-density metal lines, meeting the dual requirements of device performance and manufacturing cost in practical applications.

[0142] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a high aspect ratio X-ray grating, characterized in that, The method includes: Using a highly doped, low-resistivity single-crystal silicon wafer as the substrate, a silicon dioxide hard mask with a thickness of micrometers is deposited on the surface after cleaning. The grating pattern is transferred to the silicon dioxide hard mask based on photolithography and reactive ion etching processes, and the substrate is deep etched using an improved low-temperature Bosch process to create a high aspect ratio vertical deep trench. The natural oxide layer on the back side of the substrate is removed, followed by deposition of a metal layer and thermal annealing to construct a conductive back electrode with low ohmic contact. Remove the native oxide layer at the bottom of the vertical deep trench, electrochemically deposit a nanoscale gold nucleation layer on the inner wall of the vertical deep trench using a cyanide plating solution, and perform multi-stage cleaning. The substrate is placed in a bismuth ion-assisted gold sulfite plating solution for electroplating, so that the gold layer fills from the bottom of the vertical deep trench upwards. After removing the silicon dioxide hard mask, the X-ray grating is obtained by washing and drying.

2. The method according to claim 1, characterized in that, The matrix includes N-type antimony doping. <100> Crystal-oriented monocrystalline silicon wafers.

3. The method according to claim 1, characterized in that, The grating pattern is transferred to the silicon dioxide hard mask using photolithography and reactive ion etching processes. A modified low-temperature Bosch process is then used to perform deep silicon etching on the substrate to create a high aspect ratio vertical deep trench, including: Photoresist is spin-coated onto the silicon dioxide hard mask. After being aligned with a grating pattern mask for exposure and development with a developer, the silicon dioxide hard mask with the grating pattern is exposed by reactive ion etching using fluorine-based gas. After removing the photoresist from the silicon dioxide hard mask, the mask is cleaned and dried. The substrate was etched with a modified low-temperature Bosch process to create a vertical deep trench with a high aspect ratio. After removing the sidewall polymer of the vertical deep trench using oxygen plasma ashing, the oxide layer at the bottom of the vertical deep trench is removed using dilute hydrofluoric acid or buffered oxide etching solution, and then dried.

4. The method according to claim 3, characterized in that, The substrate is etched using an improved low-temperature Bosch process to create high aspect ratio vertical deep trenches, including: By periodically switching between fluorine-based etching gas and fluorocarbon-based passivation gas, the passivation layer of the vertical deep trench is preferentially removed by ion bombardment, forming a highly anisotropic vertical deep trench.

5. The method according to claim 1, characterized in that, The aspect ratio of the vertical deep trench exceeds 50:1; The deposited metal layer is a gold layer with a thickness of 100-200 nm. The cyanide plating solution is a weakly acidic gold-cobalt electroplating solution with a pH value controlled between 3.8 and 4.2; the electrochemical deposition is constant current electroplating with a current density of 1.0-1.5 mA / cm², and the thickness of the nanoscale gold nucleation layer is 20-50 nm.

6. The method according to claim 1, characterized in that, The process involves multiple stages of cleaning, including overflow rinsing, acid solution neutralization, megasonic cleaning, and final settling rinsing.

7. The method according to claim 1, characterized in that, Placing the substrate in a bismuth ion-assisted gold sulfite plating solution for electroplating includes: placing the substrate in a bismuth ion-assisted gold sulfite plating solution, and using immersion spin plating and segmented potential control to induce the gold layer to fill from the bottom of the vertical deep trench upwards. The immersion spin electroplating includes: Platinum anode is placed at the bottom of the electrolytic cell, and the substrate is fixed at the end of the rotating electrode device and suspended horizontally above the anode. Driven by a motor, the substrate is completely immersed in the electroplating solution and rotates horizontally. The segmented potential control includes: First stage: While the substrate is rotating at a speed of 280-320 rpm, a potential of -0.78V to -0.75V is applied for 2-4 hours to suppress deposition at the trench opening and upper sidewall. In the second stage, the potential is shifted positively to -0.73V to -0.72V and maintained for 20-30 hours to induce gold to grow upward from the bottom of the vertical deep trench until the growth front touches the strong fluid shear zone generated by high-speed rotation and automatically terminates.

8. The method according to claim 1 or 7, characterized in that, The bismuth ion-assisted gold sulfite electroplating solution comprises: 160 mmol / L sodium gold sulfite, 0.64 mol / L sodium sulfite, and bismuth ions at a concentration of 40-50 μmol / L.

9. The method according to claim 1, characterized in that, Removing the silicon dioxide hard mask includes: removing the silicon dioxide hard mask using a buffered oxide etching solution in a light-protected and low-oxygen environment.

10. An X-ray grating prepared by the method for preparing a high aspect ratio X-ray grating according to any one of claims 1-9.

Images