A circuit for preventing simultaneous conduction of upper and lower tubes of a dcdc

Abstract

The application discloses a circuit for preventing upper and lower pipes of a dcdc from conducting simultaneously, and relates to the technical field of synchronous Buck circuits, which comprises a control and regulation unit, wherein the control and regulation unit outputs a driving signal to a power switch unit; the driving signal of the control and regulation unit comprises a high-side driving signal (Hdrv), a low-side driving signal (Ldrv), a substrate selection control module, a substrate selection module and a VDD2 generation module; the control and regulation unit outputs a PG signal to the substrate selection control module; the output end of the substrate selection module is electrically connected with the input end of the substrate selection module; the output end of the VDD2 generation module is electrically connected with the input end of the substrate selection module; and the output end of the substrate selection module is electrically connected with the substrate (Psub) of the power switch tube (PM1). The substrate potential of the power switch tube (PM1) is dynamically switched through the substrate selection module, the upper and lower pipes are prevented from conducting simultaneously from the physical layer, the power device is effectively protected, and the circuit stability is improved.

Description

Technical Field

[0001] This invention relates to the field of synchronous Buck circuit technology, and in particular to a circuit that prevents the upper and lower transistors of a DC-DC converter from conducting simultaneously. Background Technology

[0002] A DC-DC converter is a direct current voltage conversion device widely used in battery-powered equipment, consumer electronics, industrial control, new energy and power management. Its core function is to boost, buck or regulate the input DC voltage and output a stable DC voltage that adapts to different load requirements, so as to realize the efficient transmission and rational distribution of electrical energy, ensure the stable and reliable operation of various electronic devices under different power supply conditions, and improve the power energy utilization rate. It is an indispensable core power management device in modern electronic systems.

[0003] Synchronous DC-DC converters (such as synchronous Buck circuits) are commonly used step-down DC-DC converters. Their power stage consists of an upper PMOS transistor and a lower NMOS transistor. Under ideal conditions, the two transistors alternately conduct to achieve step-down conversion of electrical energy. However, since MOSFETs and other devices are not ideal switches, there is a delay in turn-on and turn-off. If the control timing is not appropriate, the upper and lower transistors may conduct simultaneously (or partially conduct). In this case, the power supply forms a low-impedance path directly to ground through the two conducting MOSFETs, generating a huge "shoot-through current" that may burn out the power transistors instantly.

[0004] To solve the straight-through problem, existing technologies mainly employ two solutions: One approach is fixed dead-time control, which inserts a fixed delay between the drive signals of the upper and lower transistors to prevent both transistors from conducting simultaneously. However, this approach has significant drawbacks: the dead-time setting requires a trade-off. If the dead time is too long, the inductor current will continue through the MOSFET body diode when the lower transistor is off and the upper transistor is not conducting, significantly increasing conduction losses and reducing circuit conversion efficiency. If the dead time is too short, the shoot-through risk cannot be completely avoided, resulting in insufficient reliability. Furthermore, the fixed dead time needs to be set according to the worst-case scenario, which is usually conservative and further sacrifices efficiency. At the same time, traditional dead-time control cannot solve the problem of false turn-on caused by parasitic parameters. That is, the upper transistor has gate-drain parasitic capacitance. When the voltage at the switching node SW changes rapidly with the alternating conduction of the two transistors, the voltage spike is easily coupled to the gate of the upper transistor through the parasitic capacitance, causing the upper transistor, which should be off, to conduct briefly, still creating a shoot-through risk.

[0005] The second is the adaptive gate drive scheme, which dynamically adjusts the dead time by detecting the power transistor's off state in real time (such as detecting the gate voltage) to adapt to the actual switching characteristics of the MOSFET. However, this scheme has a complex circuit structure and requires additional configuration of delay circuits, detection circuits, comparison circuits, etc., which leads to increased chip area, increased power consumption, increased manufacturing cost, and greater integration difficulty, making it difficult to adapt to miniaturized, low-power, and low-cost application scenarios.

[0006] Therefore, existing anti-snap-through technologies suffer from problems such as the inability to completely eliminate the risk of snap-through, difficulty in balancing efficiency and security, complex circuitry, high cost, and high power consumption, which severely restrict the reliability, practicality, and application scope of synchronous DC-DC converters. Summary of the Invention

[0007] The purpose of this section is to outline some aspects of embodiments of the present invention and to briefly describe some preferred embodiments. Simplifications or omissions may be made in this section, as well as in the abstract and title of this application, to avoid obscuring the purpose of these documents; however, such simplifications or omissions should not be construed as limiting the scope of the invention.

[0008] In view of the problems existing in the above and / or existing circuits for preventing the simultaneous conduction of the upper and lower MOSFETs of a DC-DC converter, the present invention is proposed.

[0009] Therefore, the problem to be solved by this invention is how to solve the technical problems of easy shoot-through of the upper and lower transistors in existing synchronous DC-DC converters, parasitic capacitance coupling leading to mis-shoot-through of the upper transistor, the contradiction between efficiency and safety in traditional dead-time control, and the complexity and high cost of adaptive schemes.

[0010] To solve the above technical problems, the present invention provides the following technical solution: a circuit for preventing the simultaneous conduction of the upper and lower transistors of a DC-DC converter, comprising a control and adjustment unit, wherein the control and adjustment unit outputs a drive signal to a power switching unit; the output terminal of the power switching unit is electrically connected to a power output unit, the power output unit having a feedback loop, and the feedback loop providing a feedback signal to the control and adjustment unit; the drive signal of the control and adjustment unit includes a high-side drive (Hdrv) and a low-side drive (Ldrv), the power switching unit including a power switch transistor PM1 and a power switch transistor NM1, wherein the high-side drive (Hdrv) is connected to the power switching unit; the output terminal of the power switching unit is electrically connected to a power output unit, the power output unit having a feedback loop, and the feedback loop providing a feedback signal to the control and adjustment unit; the drive signal of the control and adjustment unit includes a high-side drive (Hdrv) and a low-side drive (Ldrv), the power switching unit including a power switch transistor PM1 and a power switch transistor NM1, the high-side drive (Hdrv) is connected to the power switching unit; the output terminal of the power switching unit is electrically connected to a power output unit, the power output unit having a feedback loop, and the power output unit having a feedback signal providing a feedback signal to the control and adjustment unit; the drive signal of the control and adjustment unit includes a high-side drive (Hdrv) and a low-side drive (Ldrv), the power switching unit including ... The low-side drive Hdrv is connected to the gate of the power switch PM1, and the low-side drive Ldrv is connected to the gate of the power switch NM1. The power switch unit also includes a substrate selection control module, a substrate selection module, and a VDD2 generation module. The control and adjustment unit outputs a PG signal to the substrate selection control module. The output terminal of the substrate selection module is electrically connected to the input terminal of the substrate selection module. The output terminal of the VDD2 generation module is electrically connected to the input terminal of the substrate selection module. The output terminal of the substrate selection module is electrically connected to the substrate Psub of the power switch PM1.

[0011] Preferably, the substrate selection module includes MOS transistors PM2a and PM2b. The source of MOS transistor PM2a is connected to voltage Vin, and the drain of MOS transistor PM2a is connected to the substrate Psub of power switch transistor PM1. The source of MOS transistor PM2b is electrically connected to the output terminal of VDD2 generation module, and the drain of MOS transistor PM2b is connected to the substrate Psub of power switch transistor PM1.

[0012] Preferably, when the PG signal is zero, the MOS transistor PM2a is turned on and the MOS transistor PM2b is turned off, the substrate Psub is at voltage Vin, and the power switch PM1 is turned on. When the PG signal is 1, the MOS transistor PM2a is turned off and the MOS transistor PM2b is turned on. The substrate Psub generates the output voltage VDD2 of the VDD2 generation module, and the power switch PM1 is turned off.

[0013] Preferably, the substrate selection control module outputs control signal PG2 and control signal PG3, the gate of the MOS transistor PM2a receives control signal PG2, and the gate of the MOS transistor PM2b receives control signal PG3.

[0014] Preferably, the control signal PG2 and the control signal PG3 are complementary signals, where a low control signal PG2 corresponds to a high control signal PG3, or vice versa.

[0015] Preferably, the substrate selection control module includes inverters INV1, INV2, and INV3, and resistor R1. Inverter INV1 and inverter INV2 are connected in series, and inverter INV3 is connected in series with resistor R1. The input terminals of inverters INV1 and INV3 receive the PG signal, the output terminal of inverter INV2 outputs the PG3 signal, and the end of resistor R1 outputs the PG2 signal.

[0016] Preferably, the VDD2 generation module includes diode D1, diode D2, and capacitor C1. One end of diode D1 is connected to voltage Vin, and the other end of diode D1 is connected to intermediate node SW2. One end of diode D2 is connected to intermediate node SW2, and the other end of diode D2 outputs voltage VDD2, which powers the source of MOSFET PM2b. One end of capacitor C1 is connected to intermediate node SW2, and the other end of capacitor C1 is connected to switching node SW.

[0017] The output voltage VDD2 is higher than the voltage Vin during the repeated switching of the switching node SW, thanks to the unidirectional conduction of diodes D1 and D2 and the energy storage of capacitor C1.

[0018] Preferably, the control and adjustment unit includes a reference voltage module, an error amplifier EA, a comparator COMP, and a logic control module. The non-inverting input of the error amplifier EA receives the reference voltage Vref from the reference voltage module, and the inverting input of the error amplifier EA receives the feedback voltage Vfb provided by the feedback loop. The output of the error amplifier EA is electrically connected to the inverting input of the comparator COMP. The non-inverting input of the comparator COMP receives the ramp signal. The output of the comparator COMP is electrically connected to the input of the logic control module. The output of the logic control module is connected to the high-side drive Hdrv and the low-side drive Ldrv respectively, and simultaneously outputs a status signal PG to the substrate selection control module.

[0019] Preferably, the source of the power switch PM1 is connected to voltage Vin, the drain of the power switch PM1 is connected to the switching node SW, the drain of the power switch NM1 is connected to the switching node SW, and the source of the power switch NM1 is grounded.

[0020] Preferably, the power output unit includes a feedback loop, a load current source Iload, and two sets of LC filter networks. Each LC filter network includes an inductor L0 and a capacitor C0, with each set of inductors L0 and capacitor C0 connected in parallel. The input terminal of the LC filter network is connected to the switch node SW, the output of the LC filter network is Vout, and the capacitor C0 is grounded. The feedback loop includes resistors R1 and R2 connected in series. The upper end of resistor R1 is connected to Vout, and the lower end of resistor R2 is grounded. Resistors R1 and R2 are the feedback nodes of the feedback loop, providing feedback voltage Vfb. The feedback voltage Vfb is connected to the inverting terminal of error amplifier EA. The load current source Iload is connected to Vout.

[0021] The beneficial effects of this invention are: 1. The substrate potential of the power switch PM1 is dynamically switched by the substrate selection module. When the power switch PM1 is turned off, the substrate is raised to a voltage higher than VDD2 of Vin. By utilizing the MOS transistor body effect, the turn-on threshold is greatly increased. Even if the voltage jump of the switching node SW generates a spike through the parasitic capacitance coupled to the gate, the power switch PM1 cannot be turned on. This physically prevents the upper and lower transistors from being turned on at the same time, effectively protecting the power device and improving circuit stability.

[0022] 2. No dead time or timing detection circuit is required. Shoot protection is achieved directly through substrate potential control, avoiding the body diode freewheeling loss caused by the dead time and eliminating the shoot-through risk caused by timing loopholes. This significantly improves DC-DC conversion efficiency while ensuring safety.

[0023] 3. The anti-shoo-through circuit of this solution consists only of MOSFET PM2a, MOSFET PM2b, diode D1, diode D2 and capacitor C1. It reuses the SW node transition of the DC-DC converter to generate VDD2, without the need for additional detection, comparison or delay circuits. The number of components is small and the wiring is simple, which effectively reduces the chip area, reduces static power consumption and manufacturing cost. It is especially suitable for low power consumption and miniaturized applications such as battery power supply and consumer electronics. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 The overall system block diagram of the circuit to prevent the upper and lower transistors of the DC-DC converter from conducting simultaneously.

[0026] Figure 2 System block diagram of substrate selection control module, substrate selection module and VDD2 generation module to prevent the DCDC upper and lower transistors from conducting simultaneously.

[0027] Figure 3 The circuit diagram shows the parasitic capacitance of the power switch PM1 in a circuit designed to prevent the simultaneous conduction of the upper and lower transistors of a DC-DC converter.

[0028] Figure 4 The ideal operating waveform diagram of the power switch PM1 in a circuit that prevents the upper and lower transistors of the DC-DC converter from conducting simultaneously.

[0029] Figure 5 The actual operating waveform of the power switch PM1 in a circuit designed to prevent the upper and lower transistors of a DC-DC converter from conducting simultaneously.

[0030] Figure 6 A circuit diagram for selecting a substrate to prevent the upper and lower transistors of a DC-DC converter from conducting simultaneously.

[0031] Figure 7 The circuit diagram for selecting the substrate of the control module to prevent the upper and lower transistors of the DC-DC converter from conducting simultaneously.

[0032] Figure 8 The circuit diagram for generating VDD2 to prevent the DC-DC upper and lower transistors from conducting simultaneously.

[0033] Figure 9 The waveform diagram of the VDD2 generation module is shown to prevent the DC-DC upper and lower transistors from conducting simultaneously.

[0034] Figure 10 The overall operating waveform diagram of the circuit to prevent the upper and lower transistors of the DC-DC converter from conducting simultaneously. Detailed Implementation

[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0037] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0038] Example 1, referring to Figures 1-5 This is the first embodiment of the present invention. This embodiment provides a circuit to prevent the upper and lower transistors of a DC-DC converter from conducting simultaneously. The circuit includes a control and regulation unit, which outputs a drive signal to a power switching unit. The control and regulation unit is responsible for generating a precise drive timing signal based on the output state and outputting the drive signal stably to the power switching unit. After receiving the drive signal, the power switching unit performs the turn-on and turn-off actions of the switching transistor to realize the step-down conversion of electrical energy.

[0039] Specifically, the control and regulation unit includes a reference voltage module, an error amplifier EA, a comparator COMP, and a logic control module. The non-inverting input of the error amplifier EA receives the reference voltage Vref from the reference voltage module, and the inverting input of the error amplifier EA receives the feedback voltage Vfb provided by the feedback loop. The output of the error amplifier EA is electrically connected to the inverting input of the comparator COMP. The non-inverting input of the comparator COMP receives the ramp signal. The output of the comparator COMP is electrically connected to the input of the logic control module. The output of the logic control module is connected to the high-side drive Hdrv and the low-side drive Ldrv respectively, and simultaneously outputs a status signal PG to the substrate selection control module.

[0040] The working principle is as follows: The reference voltage module outputs a high-precision, low-drift fixed reference voltage Vref, which provides a voltage reference for the entire control system. The error amplifier EA amplifies the difference between the feedback voltage Vfb transmitted from the feedback loop and the reference voltage Vref, captures the deviation between the output voltage and the target voltage, and outputs an error signal proportional to the deviation. The comparator COMP compares the error signal output by the error amplifier with the ramp signal. When the ramp signal voltage exceeds the error signal voltage, the output flips, generating a PWM modulation signal with a duty cycle dynamically adjusted according to the output voltage deviation. The logic control module receives the PWM modulation signal and the system clock signal, converts the modulation signal into a complementary driving timing signal that adapts to the high-side drive Hdrv and the low-side drive Ldrv, and outputs the PG status signal according to the working state of the high-side drive. The output PG signal can reflect the on / off state of the upper transistor PM1 in real time, providing a status basis for the substrate selection control module.

[0041] The output terminal of the power switching unit is electrically connected to the power output unit. The power output unit has a feedback loop, which provides a feedback signal to the control and regulation unit. The drive signals of the control and regulation unit include high-side drive Hdrv and low-side drive Ldrv. The power switching unit includes power switch PM1 and power switch NM1. The high-side drive Hdrv is connected to the gate of power switch PM1, and the low-side drive Ldrv is connected to the gate of power switch NM1.

[0042] The high-side drive signal Hdrv output by the control and regulation unit directly acts on the gate of the power switch PM1 to control the turn-on and turn-off of PM1, while the low-side drive signal Ldrv directly acts on the gate of the power switch NM1 to control the turn-on and turn-off of NM1. The timing of the two drive signals is complementary, ensuring that the switching transistors work alternately.

[0043] The electrical connection between the power switching unit and the power output unit enables the conversion of high-frequency switching power into smooth DC power, while the feedback loop allows the control and regulation unit to monitor the output voltage status in real time and dynamically adjust the duty cycle of the drive signal, ensuring the stability of the DC-DC converter's step-down power supply.

[0044] In addition, the source of power switch PM1 is connected to voltage Vin, the drain of power switch PM1 is connected to switch node SW, the drain of power switch NM1 is connected to switch node SW, and the source of power switch NM1 is grounded. The power output unit includes a feedback loop, a load current source Iload, and two sets of LC filter networks. The LC filter network includes an inductor L0 and a capacitor C0, and each set of inductor L0 and capacitor C0 is set in parallel. The input of the LC filter network is connected to switch node SW, the output of the LC filter network is Vout, and capacitor C0 is grounded.

[0045] The working principle is as follows: The source of power switch PM1 is connected to the input voltage Vin, which provides power input to the circuit. The drain is connected to the switching node SW, which is responsible for transmitting the input power to the switching node. The drain of power switch NM1 is connected to the switching node SW, and the source is grounded. When PM1 is turned off, it provides a freewheeling path for the inductor current and avoids damage to the device by inductor voltage spikes.

[0046] The two sets of LC filter networks are set in parallel. The inductor L0 is connected in series between the switching node SW and the output terminal Vout to store and release energy. The capacitor C0 is connected in parallel at the output terminal and grounded to filter out high-frequency voltage ripple and convert the high-frequency pulse voltage output by the switching node SW into a smooth and stable DC output voltage Vout. At the same time, the periodic high and low level transitions of the switching node SW provide the necessary clock source signal for the subsequent VDD2 generation module.

[0047] Furthermore, the feedback loop includes resistors R1 and R2, which are connected in series. The upper end of resistor R1 is connected to Vout, and the lower end of resistor R2 is grounded. Resistors R1 and R2 are the feedback nodes of the feedback loop, providing feedback voltage Vfb. Feedback voltage Vfb is connected to the inverting terminal of error amplifier EA, and load current source Iload is connected to Vout.

[0048] Resistors R1 and R2 are connected in series to form a voltage divider branch. The upper end of resistor R1 is connected to the output voltage Vout, and the lower end of resistor R2 is grounded. The intermediate node between the two serves as a feedback node, which divides the output voltage Vout according to a fixed ratio to generate a feedback voltage Vfb. The feedback voltage Vfb is transmitted to the inverting terminal of the error amplifier EA and compared with the reference voltage Vref. This allows the control and regulation unit to sense the fluctuation of the output voltage in real time and dynamically adjust the drive signal. The load current source Iload is connected in parallel to the output terminal Vout to simulate the load current consumption in the actual circuit, making the circuit operation state close to the real application scenario.

[0049] The power switch unit also includes a substrate selection control module, a substrate selection module, and a VDD2 generation module. The control and adjustment unit outputs a PG signal to the substrate selection control module. The output terminal of the substrate selection module is electrically connected to the input terminal of the substrate selection module. The output terminal of the VDD2 generation module is electrically connected to the input terminal of the substrate selection module. The output terminal of the substrate selection module is electrically connected to the substrate Psub of the power switch transistor PM1.

[0050] The power switch unit is equipped with a substrate selection control module, a substrate selection module and a VDD2 generation module, which constitute the circuit for the anti-shoo-through function of this invention. By dynamically adjusting the substrate potential of the upper transistor PM1, the risk of shoot-through when the upper and lower transistors conduct simultaneously is eliminated from the perspective of device physical characteristics.

[0051] The PG signal output by the control and regulation unit reflects the on / off state of the upper transistor PM1 in real time and is transmitted to the substrate selection control module as a trigger signal for substrate potential switching. After receiving the PG signal, the substrate selection control module generates a complementary control signal and transmits it to the substrate selection module to realize substrate potential switching control. In addition, the VDD2 generation module uses the periodic switching of the switching node SW to generate a stable VDD2 voltage that is higher than the input voltage Vin, providing a high voltage power supply for the substrate selection module. The substrate selection module receives the control signal and the VDD2 voltage and transmits the output potential signal to the substrate Psub of the power switching transistor PM1 to dynamically switch the substrate potential of PM1 to Vin or VDD2.

[0052] By utilizing the MOS transistor body effect through dynamic substrate bias control, the conduction threshold of PM1 is increased when PM1 is turned off, thereby suppressing the false turn-on of PM1 caused by parasitic capacitance coupling from the root, significantly reducing circuit complexity, chip area and power consumption, while significantly improving the reliability of shoot-through protection and preventing the power transistor from burning out due to shoot-through current.

[0053] It should be noted that, as Figure 3 As shown, in the parasitic capacitance circuit of power switch PM1, power switch PM1 is actually a non-ideal device with parasitic parameters such as gate-drain parasitic capacitance Cgd. During the operation of the circuit, the voltage of the switching node SW will jump rapidly with the alternating conduction of PM1 and NM1. This voltage jump will be coupled to the gate of PM1 through the gate-drain parasitic capacitance Cgd, causing abnormal peak fluctuations in the gate voltage.

[0054] like Figure 4 As shown, this is the ideal operating waveform of power switch PM1. However, the ideal operating waveform does not consider the effect of parasitic capacitance. The gate voltage of PM1 changes smoothly only with the drive signal, without abnormal fluctuations, and will not experience false turn-on. Figure 5 The figure shows the actual operating waveform of the power switch PM1. In the actual operating waveform, the gate voltage spike caused by parasitic capacitance coupling can easily cause PM1, which should be turned off, to be turned on briefly, forming a shoot-through state with NM1, generating a huge shoot-through current that burns out the switch. Therefore, it is necessary to provide a substrate selection control module, a substrate selection module, and a VDD2 generation module to solve the shoot-through risk under actual operating conditions from the perspective of device parasitic characteristics.

[0055] Example 2, refer to Figure 6 and Figure 7As shown, this is the second embodiment of the present invention. This embodiment is based on the previous embodiment. This embodiment clearly defines the specific circuit structure of the substrate selection module. The substrate selection module includes MOS transistor PM2a and MOS transistor PM2b. The source of MOS transistor PM2a is connected to voltage Vin. The drain of MOS transistor PM2a is connected to the substrate Psub of power switch transistor PM1. The source of MOS transistor PM2b is electrically connected to the output terminal of VDD2 generation module. The drain of MOS transistor PM2b is connected to the substrate Psub of power switch transistor PM1.

[0056] MOSFET PM2a acts as a low-voltage-side switching switch, with its source directly connected to the input voltage Vin, providing a low-voltage power supply path for the PM1 substrate. Its drain is directly connected to the substrate Psub of the power switch PM1, responsible for transmitting the Vin voltage to the substrate. MOSFET PM2b acts as a high-voltage-side switching switch, with its source electrically connected to the output terminal of the VDD2 generation module, receiving a stable VDD2 high voltage that is higher than Vin. Its drain is also connected to the substrate Psub of the power switch PM1, responsible for transmitting the high voltage VDD2 to the substrate. By utilizing the switching characteristics of PMOS transistors, two independent and mutually exclusive substrate power supply branches are built. Their function is to provide potential switching for the substrate Psub of the power switch PM1, allowing the substrate Psub to flexibly connect to Vin or VDD2 according to the working requirements. Moreover, the circuit structure is simple and the number of components is small.

[0057] When the PG signal is zero (low level), the corresponding power switch PM1 needs to be turned on normally. MOSFET PM2a is turned on and MOSFET PM2b is turned off. The substrate Psub of the power switch PM1 is clamped to the Vin voltage, that is, the substrate Psub is the voltage Vin. The power switch PM1 is turned on. The substrate Psub of the power switch PM1 is equal to the source potential. The MOSFET body effect is the weakest. The turn-on threshold is maintained at the normal level, ensuring that PM1 can be turned on stably in a low-loss state without affecting the normal buck conversion efficiency of the DC-DC converter.

[0058] When the PG signal is 1 (high level), the corresponding power switch PM1 needs to be reliably turned off. At this time, MOSFET PM2a is turned off and MOSFET PM2b is turned on. The substrate Psub of the power switch PM1 is clamped to a voltage higher than VDD2 of Vin. That is, the substrate Psub is VDD2, which generates the output voltage VDD2 of the module. The power switch PM1 is turned off. Since the substrate potential of the power switch PM1 is higher than the source potential, the body effect is significantly enhanced, and the absolute value of the turn-on threshold is greatly increased. Even if the voltage jump of the switching node SW is coupled to the gate of PM1 through the parasitic capacitance to generate a voltage spike, it is impossible to reach the new turn-on threshold. PM1 always remains in the off state, thereby avoiding the formation of a shoot-through current when it is turned on at the same time as the power switch NM1, and completely eliminating the risk of power transistor burnout.

[0059] The substrate selection control module outputs control signals PG2 and PG3. The gate of MOSFET PM2a receives control signal PG2, and the gate of MOSFET PM2b receives control signal PG3. The substrate selection control module integrates logic circuitry that can decompose a single PG status signal into gate drive signals adapted to the two MOSFETs.

[0060] Specifically, the substrate selection control module includes inverters INV1, INV2, and INV3, and resistor R1. Inverter INV1 and inverter INV2 are connected in series, and inverter INV3 is connected in series with resistor R1. The input terminals of inverters INV1 and INV3 receive the PG signal, the output terminal of inverter INV2 outputs the PG3 signal, and the output terminal of resistor R1 outputs the PG2 signal. Thus, the single-ended PG state signal is converted into a pair of complementary drive signals with dead-time control. Resistor R1 mainly ensures that the timing of the changes in the edges of the PG2 and PG3 signals remains consistent.

[0061] The gate of MOSFET PM2a receives the PG2 signal, and its on / off state is entirely determined by the PG2 signal level. The gate of MOSFET PM2b receives the PG3 signal, and its on / off state is entirely determined by the PG3 signal level. Thus, the conduction state of MOSFETs PM2a and PM2b can be controlled by the gate voltage, thereby establishing a direct correlation between the control signal and the substrate switching action. This ensures that the substrate potential switching command can be transmitted to the actuator quickly and accurately, reducing signal delay and ensuring that the substrate potential switching is synchronized with the working state of the power switch PM1, avoiding shoot-through failure due to signal transmission lag.

[0062] It should be noted that control signals PG2 and PG3 are complementary signals. When control signal PG2 is low, control signal PG3 is high, or vice versa. That is, the two signal levels are opposite at any given time. When PG2 is low, PG3 must be high; when PG2 is high, PG3 must be low. This matches the mutual exclusion requirement of MOSFETs PM2a and PM2b in the substrate selection module. By utilizing the interlocking characteristics of the logic circuit, it avoids the two control signals being low or high at the same time, thereby preventing the abnormal condition of MOSFETs PM2a and PM2b being turned on or off at the same time.

[0063] If both transistors are turned on simultaneously, it will cause a direct short circuit between the voltage Vin and the voltage VDD2, damaging the device. If both transistors are turned off simultaneously, the PM1 substrate will be left floating, and the potential will be unstable, making it impossible to effectively control the turn-on threshold. The complementary signal can ensure that the substrate potential is always stable at either the voltage Vin or the voltage VDD2, further improving the stability and reliability of the anti-snap-through circuit.

[0064] Example 3, referring to Figures 8-10 This is the third embodiment of the present invention, based on the previous two embodiments. This embodiment clarifies the specific circuit structure of the VDD2 generation module, providing a stable high-voltage source higher than the input voltage Vin for the MOS transistor PM2b in the substrate selection module. The VDD2 generation module includes diode D1, diode D2, and capacitor C1. Diode D1 serves as a low-voltage-side unidirectional isolation device, with one end connected to the voltage Vin and the other end connected to the intermediate node SW2, allowing current to flow only from Vin to SW2 and preventing reverse charge flow. Diode D2 serves as a high-voltage-side unidirectional isolation device. For the output device, one end of diode D2 is connected to the intermediate node SW2, and the other end of diode D2 outputs voltage VDD2. Charge is only allowed to flow from SW2 to VDD2, and it supplies power to the source of MOSFET PM2b. Capacitor C1 is used as an energy storage and voltage boosting element. One end of capacitor C1 is connected to the intermediate node SW2, and the other end of capacitor C1 is connected to the switching node SW. By using the periodic high and low level transitions of the switching node SW, charge storage and transfer are realized. The switching timing of the switching node SW of the converter itself is reused, which not only meets the requirements of the boost function, but also reduces the chip area and power consumption.

[0065] Specifically, the output voltage VDD2 is higher than the voltage Vin during the repeated switching of the switching node SW, through the unidirectional conduction of diodes D1 and D2 and the energy storage of capacitor C1. When the switching node SW is low, that is, when the power switch PM1 is off and the power switch NM1 is on, diode D1 conducts in the forward direction, and the input voltage Vin charges capacitor C1 through D1, so that the voltage of the intermediate node SW2 is clamped to the level of Vin minus the conduction voltage drop of D1, and capacitor C1 stores the corresponding charge. When the switching node SW transitions to a high level, i.e., power switch PM1 is turned on and power switch NM1 is turned off, the SW voltage rises to Vin. The voltage across capacitor C1 remains constant because the charge cannot change abruptly, causing the voltage at the intermediate node SW2 to be instantaneously boosted to the sum of Vin and the voltage across the capacitor. At this time, diode D1 reverse-biasedly blocks the low-voltage side, while diode D2 forward-biased, transferring the high-voltage charge of SW2 to the VDD2 output terminal through D2. With the periodic high-low transition of the SW node, capacitor C1 repeatedly charges and discharges, continuously pumping charge into the VDD2 terminal, eventually stabilizing the output voltage to a VDD2 voltage higher than Vin. This boosting process requires no additional power supply, perfectly adapts to the DC-DC converter's operating timing, and provides a stable high voltage to the source of MOSFET PM2b, ensuring that when power switch PM1 is turned off, the substrate potential is boosted to VDD2, enhancing the body effect, increasing the turn-on threshold of power switch PM1, suppressing false turn-on caused by parasitic capacitive coupling from the root, and ensuring the implementation of the shoot-through protection function.

[0066] like Figure 8 As shown in the waveform diagram of the VDD2 generation module, the timing relationship between the switching node SW, the intermediate node SW2, and the output voltage VDD2 can be seen. The switching node SW exhibits a periodic high and low level square wave, corresponding to the alternating conduction states of PM1 and NM1. The voltage of the intermediate node SW2 changes synchronously with the switching of SW. During the low-level phase, it is clamped to near Vin voltage by D1, and during the high-level phase, it is boosted to a peak voltage higher than Vin by the capacitor. Under the unidirectional isolation effect of diode D2, the output voltage VDD2 is always maintained at a stable level higher than Vin, without significant drop or fluctuation. This directly verifies the boost effect of the VDD2 generation module of this invention, clearly demonstrating the timing linkage between SW switching, capacitor energy storage, charge transfer, and high voltage output, proving that the boost circuit works stably and the output voltage is reliable.

[0067] like Figure 9 The diagram shown is a waveform diagram of the operation of the present invention. The waveform diagram intuitively presents the timing relationship between the PG status signal, control signal PG2 and control signal PG3 output by the substrate selection control module, and the substrate potential Psub of the power switch PM1. It demonstrates the dynamic working process of the anti-shoo-through control of the present invention, verifies the synchronous switching logic of the substrate potential and the working state of the upper tube, and provides intuitive evidence for the effectiveness of the technical solution.

[0068] During the low-level phase of the PG signal, which corresponds to the conduction cycle of the power switch PM1, the complementary control signals output by the substrate selection control module are as follows: control signal PG2 is low and control signal PG3 is high. The gate of MOSFET PM2a turns on after receiving the low-level PG2 signal, and the gate of MOSFET PM2b turns off after receiving the high-level PG3 signal. The substrate Psub is connected to the input voltage Vin through the conducting PM2a, and the substrate potential is maintained at the same level as Vin. At this time, the substrate and source potentials of PM1 are equal, the MOSFET body effect is the weakest, and the conduction threshold remains at a normal level. This ensures that PM1 can conduct stably in a low-loss state without affecting the normal buck conversion efficiency of the DC-DC converter, and also avoids the negative impact of substrate boost on conduction performance, ensuring that the basic operating performance of the circuit is not affected by the anti-shoot-through control.

[0069] During the high-level phase of the PG signal, corresponding to the turn-off cycle of the power switch PM1, the complementary control signal output by the substrate selection control module flips, with control signal PG2 being high and control signal PG3 being low. The gate of MOSFET PM2a is turned off after receiving the high-level PG2 signal, while the gate of MOSFET PM2b is turned on after receiving the low-level PG3 signal. The substrate Psub is connected to VDD2 through the turned-on PM2b to generate the high voltage VDD2 output by the module. The substrate potential is stably raised to a level higher than Vin. At this time, the substrate potential of the power switch PM1 is higher than the source potential, and the MOSFET body effect is significantly enhanced. The absolute value of the turn-on threshold increases significantly. Even if the voltage jump at the switching node SW is coupled to the gate of the power switch PM1 through the gate-drain parasitic capacitance to generate a voltage spike, it is impossible to reach the new turn-on threshold. The power switch PM1 always remains in the off state, fundamentally avoiding the simultaneous turn-on with the lower transistor NM1 to form a shoot-through current, and completely eliminating the risk of the power transistor burning out due to the shoot-through current.

[0070] Furthermore, in the waveform diagram, control signals PG2 and PG3 are always complementary signals, and their levels are always opposite, perfectly matching the mutual exclusion requirements of MOSFET PM2a and MOSFET PM2b. This effectively prevents the abnormal condition of both transistors being turned on or off simultaneously, avoiding the problem of Vin and VDD2 being directly short-circuited or PM1 substrate being left floating. It ensures that the substrate potential is always stable in either Vin or VDD2, further improving the stability and reliability of the anti-snap-through circuit.

[0071] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A circuit for preventing the upper and lower transistors of a DC-DC converter from conducting simultaneously, comprising a control and adjustment unit, wherein the control and adjustment unit outputs a drive signal to a power switching unit; The power output unit is electrically connected to the output terminal of the power switch unit. The power output unit is provided with a feedback loop, and the feedback loop provides a feedback signal to the control and adjustment unit. Its features are: The drive signals of the control and adjustment unit include high-side drive Hdrv and low-side drive Ldrv. The power switching unit includes power switch PM1 and power switch NM1. The high-side drive Hdrv is connected to the gate of power switch PM1, and the low-side drive Ldrv is connected to the gate of power switch NM1. The power switching unit further includes a substrate selection control module, a substrate selection module, and a VDD2 generation module. The control and adjustment unit outputs a PG signal to the substrate selection control module. The output terminal of the substrate selection module is electrically connected to the input terminal of the substrate selection module. The output terminal of the VDD2 generation module is electrically connected to the input terminal of the substrate selection module. The output terminal of the substrate selection module is electrically connected to the substrate Psub of the power switching transistor PM1.

2. The circuit for preventing the simultaneous conduction of the upper and lower transistors of a DC-DC converter as described in claim 1, characterized in that: The substrate selection module includes MOSFET PM2a and MOSFET PM2b. The source of MOSFET PM2a is connected to voltage Vin, and the drain of MOSFET PM2a is connected to the substrate Psub of power switch MOSFET PM1. The source of MOSFET PM2b is electrically connected to the output terminal of VDD2 generation module, and the drain of MOSFET PM2b is connected to the substrate Psub of power switch MOSFET PM1.

3. The circuit for preventing the simultaneous conduction of the upper and lower transistors of a DC-DC converter as described in claim 2, characterized in that: When the PG signal is zero, the MOS transistor PM2a is turned on and the MOS transistor PM2b is turned off, the substrate Psub is at voltage Vin, and the power switch PM1 is turned on. When the PG signal is 1, the MOS transistor PM2a is turned off and the MOS transistor PM2b is turned on. The substrate Psub generates the output voltage VDD2 of the VDD2 generation module, and the power switch PM1 is turned off.

4. The circuit for preventing the simultaneous conduction of the upper and lower transistors of a DC-DC converter as described in claim 2, characterized in that: The substrate selection control module outputs control signals PG2 and PG3. The gate of the MOS transistor PM2a receives control signal PG2, and the gate of the MOS transistor PM2b receives control signal PG3.

5. The circuit for preventing the simultaneous conduction of the upper and lower transistors of a DC-DC converter as described in claim 4, characterized in that: The control signals PG2 and PG3 are complementary signals. When the control signal PG2 is low, the control signal PG3 is high, or when the control signal PG2 is high, the control signal PG3 is low.

6. The circuit for preventing the simultaneous conduction of the upper and lower transistors of a DC-DC converter as described in claim 5, characterized in that: The substrate selection control module includes inverters INV1, INV2, and INV3, and resistor R1. Inverter INV1 and inverter INV2 are connected in series, and inverter INV3 is connected in series with resistor R1. The input terminals of inverters INV1 and INV3 receive the PG signal, the output terminal of inverter INV2 outputs the PG3 signal, and the end of resistor R1 outputs the PG2 signal.

7. The circuit for preventing the simultaneous conduction of the upper and lower transistors of a DC-DC converter as described in claim 6, characterized in that: The VDD2 generation module includes diode D1, diode D2, and capacitor C1. One end of diode D1 is connected to voltage Vin, and the other end of diode D1 is connected to intermediate node SW2. One end of diode D2 is connected to intermediate node SW2, and the other end of diode D2 outputs voltage VDD2, which powers the source of MOSFET PM2b. One end of capacitor C1 is connected to intermediate node SW2, and the other end of capacitor C1 is connected to switching node SW. The output voltage VDD2 is higher than the voltage Vin during the repeated switching of the switching node SW, thanks to the unidirectional conduction of diodes D1 and D2 and the energy storage of capacitor C1.

8. The circuit for preventing the simultaneous conduction of the upper and lower transistors of a DC-DC converter as described in claim 7, characterized in that: The control and adjustment unit includes a reference voltage module, an error amplifier EA, a comparator COMP, and a logic control module. The non-inverting input of the error amplifier EA receives the reference voltage Vref from the reference voltage module. The inverting terminal of the error amplifier EA receives the feedback voltage Vfb provided by the feedback loop. The output terminal of the error amplifier EA is electrically connected to the inverting terminal of the comparator COMP. The non-inverting terminal of the comparator COMP receives the ramp signal. The output terminal of the comparator COMP is electrically connected to the input terminal of the logic control module. The output terminal of the logic control module is connected to the high-side drive Hdrv and the low-side drive Ldrv respectively, and simultaneously outputs the status signal PG to the substrate selection control module.

9. The circuit for preventing the simultaneous conduction of the upper and lower transistors of a DC-DC converter as described in claim 8, characterized in that: The source of the power switch PM1 is connected to voltage Vin, the drain of the power switch PM1 is connected to the switching node SW, the drain of the power switch NM1 is connected to the switching node SW, and the source of the power switch NM1 is grounded.

10. The circuit for preventing the simultaneous conduction of the upper and lower transistors of a DC-DC converter as described in claim 9, characterized in that: The power output unit includes a feedback loop, a load current source Iload, and two sets of LC filter networks. Each LC filter network includes an inductor L0 and a capacitor C0. The inductor L0 and capacitor C0 in each set are connected in parallel. The input terminal of the LC filter network is connected to the switch node SW. The output of the LC filter network is Vout. The capacitor C0 is grounded. The feedback loop includes resistors R1 and R2 connected in series. The upper end of resistor R1 is connected to Vout, and the lower end of resistor R2 is grounded. Resistors R1 and R2 are the feedback nodes of the feedback loop, providing feedback voltage Vfb. The feedback voltage Vfb is connected to the inverting terminal of error amplifier EA. The load current source Iload is connected to Vout.

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