Capacitor array applied to sar-assisted ramp adc, analog-to-digital converter and conversion method

Abstract

The application provides a capacitor array applied to a SAR auxiliary ramp ADC, an analog-to-digital converter and a conversion method, and belongs to the technical field of integrated circuits. The capacitor array comprises a first output end, a second output end, a first bridge capacitor, a second bridge capacitor, a first SAR capacitor subarray, a second SAR capacitor subarray, a low-bit SAR capacitor, a first to third ramp capacitor subarray and a fixed level capacitor subarray. Each capacitor is connected to a switch network through a specific connection relationship, and the capacitance ratio between each SAR capacitor and the capacitance ratio between the low-bit SAR capacitor and the bridge capacitor and the unit capacitor are configured to form a non-binary weight relationship. The application also provides a conversion method based on the capacitor array. By adopting a segmented capacitor structure and a non-binary weight design, the application can significantly reduce the capacitor array area, reduce the switch power consumption and comparator load, speed up the establishment time, and improve the linearity of the CDAC, thereby improving the overall performance of the ADC in speed, area and power consumption.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a capacitor array, analog-to-digital converter, and conversion method for use in SAR-assisted ramp ADC. Background Technology

[0002] With the rapid development of communication systems and IoT technologies, the demand for low-power, high-resolution analog-to-digital converters is increasing. Successive approximation analog-to-digital converters (SAR ADCs) are highly attractive in wireless communication systems such as Wi-Fi and LTE due to their ease of implementation at high speed and low power consumption, as well as their high tolerance to process technology.

[0003] However, as resolution increases, the performance of high-speed SAR ADCs becomes increasingly limited by the comparators. This is mainly reflected in the signal-to-noise ratio (SNR), which is typically limited to below 60 dB due to comparator noise. Moreover, the trade-off between comparator noise and power consumption is not linear; achieving an SNR higher than 60 dB often requires significantly more power consumption.

[0004] To address this issue, existing technologies have proposed a SAR-assisted digital slope ADC architecture, which combines the advantages of low-power SAR ADCs and low-noise digital slope ADCs, maintaining high power efficiency while overcoming comparator noise problems. However, in existing research, including many high-level academic conferences and journal papers, the capacitor arrays used in such ADCs are mostly traditional binary-like weighted structures. This structure has the following drawbacks and shortcomings: 1) The capacitor array area is too large, leading to increased chip cost; 2) Due to the large total capacitance value, the settling time of the capacitor array is too long, limiting the ADC conversion speed; 3) The switching power consumption is too high, which is not conducive to low-power design; 4) The layout of the most significant bit (MSB) capacitor is difficult, easily introducing parasitic parameter mismatches, affecting the linearity of the ADC. Summary of the Invention

[0005] The main objective of this application is to propose a capacitor array, analog-to-digital converter, and conversion method for SAR-assisted ramp ADCs, in order to solve the problems of excessive area, power consumption, and cost of current ADC capacitor arrays.

[0006] To achieve the above objectives, one aspect of this application proposes a capacitor array for use in a SAR-assisted ramp ADC, comprising: First output terminal (VP) and second output terminal (VN); The top plate of the first bridging capacitor (Cbri1) is connected to the first output terminal (VP); The second bridging capacitor (Cbri2) has its base plate connected to the second output terminal (VN); The first SAR capacitor subarray includes multiple first SAR capacitors (Csar2 to Csar7). The first terminal of each first SAR capacitor is connected to a reference voltage or ground via a switch, and the second terminal of each capacitor is connected to the first output terminal (VP). The second SAR capacitor subarray includes multiple second SAR capacitors (Csar9 to Csar14). The first terminal of each second SAR capacitor is connected to a reference voltage or ground via a switch, and the second terminal of each capacitor is connected to the second output terminal (VN). The low-side SAR capacitor (Csar1) has its first terminal connected to the reference voltage or ground via a switch, and its second terminal connected to the base plate of the first bridging capacitor (Cbri1). The first ramp capacitor subarray includes multiple first unit capacitors (Cdig1 to Cdig31). The first terminal of each first unit capacitor is connected to a reference voltage or ground via a switch, and its second terminal is connected to the base plate of the first bridge capacitor (Cbri1). The second ramp capacitor subarray includes multiple second unit capacitors (Cdig35 to Cdig50), the first terminal of each second unit capacitor is connected to a reference voltage or ground via a switch, and the second terminal of each unit capacitor is connected to the top plate of the second bridge capacitor (Cbri2). The third ramp capacitor subarray includes multiple third unit capacitors (Cdig51 to Cdig68), each of which has a first terminal connected to a reference voltage and a second terminal connected to the top plate of the second bridge capacitor (Cbri2). A fixed-level capacitor subarray includes at least one fixed-level capacitor (Cdig32 to Cdig34), the first terminal of each fixed-level capacitor is connected to a reference voltage, and the second terminal of each fixed-level capacitor is connected to the base plate of the first bridging capacitor (Cbri1). And a switching network connecting a portion of the capacitors in the first SAR capacitor subarray and the second SAR capacitor subarray with the second bridging capacitor; The capacitance values ​​of the first SAR capacitors (Csar2 to Csar7), the capacitance values ​​of the second SAR capacitors (Csar9 to Csar14), and the capacitance ratios between the low-order SAR capacitor (Csar1) and the first bridging capacitor (Cbri1) and the first unit capacitors (Cdig1 to Cdig31) are configured to form a non-binary weighted relationship.

[0007] In some embodiments, the capacitance ratio of the first SAR capacitors (Csar2 to Csar7) is 1:2:4:8:16:32, and the capacitance ratio of the second SAR capacitors (Csar9 to Csar14) is symmetrically set with respect to the capacitance ratio of the first SAR capacitors (Csar2 to Csar7).

[0008] In some embodiments, the capacitance values ​​of the first unit capacitor (Cdig1 to Cdig31), the second unit capacitor (Cdig35 to Cdig50), and the third unit capacitor (Cdig51 to Cdig68) are all equal and are defined as the unit capacitance value C; the capacitance value of the low-order SAR capacitor (Csar1) is 8C; and the capacitance values ​​of the first bridging capacitor (Cbri1) and the second bridging capacitor (Cbri2) are both 6C.

[0009] In some embodiments, the switching network includes: A switch is connected to the first end of a specific capacitor (Csar8) in the second SAR capacitor subarray, and the second end of the specific capacitor (Csar8) is connected to the top plate of the second bridging capacitor (Cbri2).

[0010] In some embodiments, a fixed reference voltage capacitor subarray connected to the top plate of the second bridging capacitor (Cbri2) is further included, the subarray being composed of the third ramp capacitor subarray.

[0011] In some embodiments, the capacitors connected to the base plate side of the first bridging capacitor (Cbri1) include the low-level SAR capacitor (Csar1), the first ramp capacitor subarray, and the fixed-level capacitor subarray, which together constitute a low-level weighted subnetwork.

[0012] In some embodiments, the switching of the first unit capacitors (Cdig1 to Cdig31) in the first ramp capacitor subarray is controlled by the ramp ADC logic after the SAR ADC conversion is completed, and is used to realize successive comparison of the residual voltage.

[0013] In some embodiments, the entirety of the second unit capacitor (Cdig35 to Cdig50) is used to introduce a voltage offset during the ramp ADC conversion phase to adjust the comparison range of the residual voltage.

[0014] In some embodiments, the non-binary weighting relationship is used to introduce redundancy during the SAR ADC conversion stage to relax comparator noise and setup accuracy requirements.

[0015] To achieve the above objectives, another aspect of the embodiments of this application proposes an analog-to-digital converter comprising the capacitor array described above.

[0016] To achieve the above objectives, another aspect of this application proposes a conversion method applied to the capacitor array described above, comprising the following steps: During the SAR ADC conversion stage, based on the output of the comparator, the SAR logic circuit controls the switch connecting the first SAR capacitor subarray, the second SAR capacitor subarray, and the low-position SAR capacitor to successively approximate the input signal at the first output terminal (VP) and the second output terminal (VN) to generate a residual voltage. During the ramp ADC conversion stage, based on the output of the continuity comparator, the ramp logic circuit controls the switching of the first unit capacitors (Cdig1 to Cdig31) connected in the first ramp capacitor subarray, causing the voltage of the first output terminal (VP) to decrease step by step until the output of the continuity comparator flips. The final digital output code is calculated based on the number of switches turned on during the flip and the offset introduced by the fixed-level capacitor subarray.

[0017] Compared with the prior art, this application has the following beneficial effects: (1) By adopting a segmented capacitor structure and combining it with a non-binary weight design, the total area of ​​the CDAC capacitor array can be significantly reduced, thereby reducing the chip cost.

[0018] (2) The capacitors of each part are reduced proportionally, which effectively shortens the settling time of CDAC and helps to improve the conversion speed of ADC.

[0019] (3) The reduction in total capacitance reduces the power consumption of the switch drive and the power consumption of the capacitor charging and discharging. At the same time, the load capacitance of the comparator is also reduced, which reduces the power consumption of the comparator itself.

[0020] (4) Placing the lowest bit capacitor of the SAR ADC section and the capacitor of the ramp ADC section on the same side of the bridging capacitor helps to improve the matching characteristics and linearity of the CDAC and improve the overall performance of the ADC. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a capacitor array with a special base provided in the embodiments of this application.

[0022] Figure 2 This is a structural diagram of the analog-to-digital converter provided in the embodiments of this application. Detailed Implementation

[0023] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0024] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0025] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0026] Furthermore, in the description of this invention, unless otherwise stated, "multiple" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0027] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0028] The development of communication systems and the Internet of Things (IoT) has led to a significant increase in demand for low-power, high-resolution analog-to-digital converters (ADCs). Successive approximation ADCs (SAR ADCs) are particularly attractive in wireless communication systems such as Wi-Fi and LTE due to their ease of implementation at high speeds and low power consumption, as well as their high process tolerance. However, as resolution increases, the comparator in high-speed SAR ADCs becomes an increasingly limiting factor in ADC performance. This is primarily reflected in the signal-to-noise ratio (SNR), which is typically limited to below 60dB due to comparator noise. Furthermore, the trade-off between comparator noise and power consumption is not always 1:1; generally, achieving an SNR greater than 60dB requires significantly higher power consumption.

[0029] SAR-assisted digital slope ADCs combine low-power SAR ADCs and low-noise digital slope ADCs, overcoming comparator noise issues while maintaining high power efficiency. However, existing papers, including many high-level academic conferences and journals, mostly employ a binary-like structure for the capacitor array of this ADC. This leads to problems such as excessively large capacitor array area, long settling time, excessively high switching power consumption, and difficulties in layout of the most significant bit (MSB) capacitor.

[0030] In view of this, this application provides a capacitor array (CDAC) for SAR-assisted digital ramp ADC to solve the problems of excessive area, power consumption and cost of current ADC capacitor arrays.

[0031] like Figure 1 As shown, this embodiment provides a capacitor array for use in a SAR-assisted ramp ADC, including a first output terminal VP and a second output terminal VN, a first bridging capacitor Cbri1, a second bridging capacitor Cbri2, and multiple capacitor subarrays.

[0032] (1) The structure and connection relationship of the capacitor array In this embodiment, all unit capacitors are designed with the same unit capacitance value C. The specific connection relationships and capacitance values ​​are as follows: 1.1) Positive half (related to the VP end): The top plate of the first bridging capacitor Cbri1 is directly connected to the first output terminal VP.

[0033] The first SAR capacitor subarray consists of six capacitors, Csar2 to Csar7. Their capacitance values ​​are 2C, 4C, 8C, 16C, 32C, and 64C, respectively. The base plates of these capacitors are connected to the reference voltage Vref or ground (GND) via independent switches, and their top plates are directly connected to the first output terminal VP.

[0034] The low-side SAR capacitor Csar1 has a capacitance of 8C. Its base plate is connected to Vref or GND via a switch, and its top plate is connected to the base plate of the first bridging capacitor Cbri1.

[0035] The first ramp capacitor subarray comprises 31 capacitors, Cdig1 to Cdig31, all with a capacitance value of C. Their base plates are connected to Vref or GND via independent switches, and their top plates are all connected to the base plate of the first bridging capacitor Cbri1.

[0036] The fixed-level capacitor subarray consists of three capacitors, Cdig32 to Cdig34, each with a capacitance of C. Their base plates are fixedly connected to Vref, and their top plates are all connected to the base plate of the first bridging capacitor, Cbri1.

[0037] 1.2) Negative half (related to the VN terminal): The base plate of the second bridging capacitor Cbri2 is directly connected to the second output terminal VN.

[0038] The second SAR capacitor subarray consists of six capacitors, Csar9 to Csar14. Their capacitance values ​​are 64C, 32C, 16C, 8C, 4C, and 2C, respectively (symmetrical to the positive half). The base plates of these capacitors are connected to Vref or GND via independent switches, and their top plates are directly connected to the second output terminal VN.

[0039] The specific capacitor Csar8 has a capacitance of 8C. Its base plate is connected to Vref or GND via a switch, and its top plate is connected to the top plate of the second bridging capacitor Cbri2.

[0040] The second ramp capacitor subarray comprises 16 capacitors, Cdig35 to Cdig50, all with a capacitance value of C. Their base plates are connected to Vref or GND via independent switches, and their top plates are all connected to the top plate of the second bridging capacitor Cbri2.

[0041] The third ramp capacitor subarray comprises 18 capacitors, Cdig51 to Cdig68, all with a capacitance value of C. Their base plates are fixedly connected to Vref, and their top plates are all connected to the top plate of the second bridging capacitor Cbri2.

[0042] Each of the above switches is set independently and connected to the ADC's digital logic circuit (SAR logic and ramp logic), and is controlled by the signals generated by the logic circuit.

[0043] (2) Work process and principles Combination Figure 2 The diagram shows the structure of the analog-to-digital converter. The workflow of this capacitor array is divided into two main stages: the SAR ADC conversion stage and the ramp ADC conversion stage.

[0044] 2.1) SAR ADC Conversion Stage a) Sampling Stage: The bottom switches of all capacitors are turned to the input signal VIN to sample the input signal.

[0045] b) Hold and Conversion Stage: After sampling, all switches are turned to the Vref potential. At this time, the voltage difference between the VP and VN terminals reflects the magnitude of the input signal. The dynamic comparator (Strong-Arm Comparator) starts to compare the voltages of VP and VN.

[0046] c) Successive Approximation Process: Taking the first comparison as an example, if VP > VN, the output result of the comparator is 1. After the SAR logic circuit receives this result, it controls the switch of the largest capacitor (i.e., Csar7, 64C) on the VP side to be turned from the Vref potential to GND. This operation causes the voltage at the VP terminal to drop by a large step, generating a new voltage difference.

[0047] Subsequently, the second comparison is carried out. If VP is still greater than VN at this time, it controls the switch of the second largest capacitor (i.e., Csar13, 32C) on the VN side to be turned from Vref to GND, causing the VN voltage to drop and narrowing the voltage difference; conversely, if VP < VN, it controls the switch of the second largest capacitor (Csar6, 32C) on the VP side to be turned from Vref to GND.

[0048] d) Repeat the above process, successively controlling capacitors such as Csar6 / Csar12, Csar5 / Csar11... until the successive comparison of all SAR partial capacitors (including the low-bit SAR capacitor Csar1 and the specific capacitor Csar8) is completed.

[0049] e) Redundancy Design: In this embodiment, the non-binary weights of the capacitor array (such as the ratio of 4:1:2:4:8:16:32 instead of the standard binary 1:2:4:8:16:32:64) introduce redundancy during the conversion process. This allows the comparator to tolerate a certain amount of noise and error during judgment, and subsequent bits can correct it, thus relaxing the requirements for the noise and settling accuracy of the comparator, which is one of the key advantages of this application.

[0050] 2.2) Ramp ADC Conversion Stage[[ID= {24]] After the SAR ADC conversion is completed, there will be a small residual voltage difference between VP and VN. At this time, the high-precision characteristics of the ramp ADC need to be used to refine and quantify this residual difference.

[0051] a) Voltage Shift: After the last comparison by the SAR ADC, the SAR logic outputs a WN signal, which moves the capacitor connected to the WN signal (corresponding to the capacitor on the VN side in this embodiment) from Vref to GND, causing the VN terminal voltage to be pulled down. This operation shifts the common-mode range of the residual voltage to a range suitable for single-ended comparison by the ramp ADC, such as 0, +Vmax / 32, so that the residual signal can switch down to 0 in 1LSB steps.

[0052] b) Successive Descent Comparison: Subsequently, the ramp ADC logic begins operation. It sequentially controls the switches of the unit capacitors Cdig31, Cdig30... up to Cdig1 connected in the first ramp capacitor subarray, switching the base plates of these capacitors from Vref to GND one by one. Each time a capacitor is switched, the voltage at the first output terminal VP decreases by one LSB step (in this embodiment, one LSB step corresponds to the voltage change generated by the unit capacitor C).

[0053] c) Comparison and Counting: The continuous comparator continuously compares the voltages VP and VN. When the voltage VP drops from above VN to below VN, the comparator output flips.

[0054] d) Digital Code Calculation: Record the total number of unit capacitors turned on during the process from the start of the ramp ADC conversion to the comparator flip. Then, based on this number and the voltage offset (e.g., 16 LSB) introduced by the fixed-level capacitor subarray (Cdig35 to Cdig50), the final, complete digital output code is calculated by digital logic circuitry. The final output code equals the coarse conversion result from the SAR stage plus the fine conversion result from the ramp stage, minus the offset.

[0055] (3) Analysis of key beneficial effects 3.1) Area optimization: The dual-bridge capacitor segmented structure is adopted, which isolates most of the capacitors (especially the large number of ramp capacitors) from the output terminal through the bridge capacitor, avoiding the direct use of a large capacitor array and significantly reducing the chip area.

[0056] 3.2) Power Consumption Optimization: The reduction in total capacitance directly reduces the power consumption required for switching. At the same time, the load capacitances of the outputs VP and VN (mainly the Csar2-7, Csar9-14 and bridge capacitors connected to them) are also significantly reduced, which allows the comparator to achieve the same speed and noise performance with lower power consumption.

[0057] 3.3) Linearity optimization: The low-position SAR capacitor Csar1 and the ramp capacitor Cdig1-31 are placed together on the bottom plate side of the first bridging capacitor Cbri1. This layout improves the matching characteristics of the capacitor network on both sides of the bridging capacitor and effectively improves the linearity (INL / DNL) of the entire CDAC.

[0058] 3.4) Speed ​​optimization: A smaller capacitance value means a smaller RC time constant, so the CDAC settling time is shorter, which is conducive to achieving a higher conversion speed.

[0059] (4) Specific application examples The solutions of this application embodiment will be described in detail and explained below with reference to specific application examples: In this embodiment, all Cdig values ​​are the same. The capacitor array uses Cdig capacitance as the unit capacitance value C. Csar is divided into two groups: one group from Csar1 to Csar7, and the other group from Csar8 to Csar14, with capacitance values ​​set to 8C, 2C, 4C, 8C, 16C, 32C, and 64C respectively. Cbri1 and Cbri2 are set to 6C and 6C respectively. The two ends (bottom plate and top plate) of the SAR ADC section Csar2 to Csar7 are connected to the switch and the output VP respectively; the two ends of Csar1, Cdig1 to Cdig31 are connected to the switch and the Cbri1 bottom plate respectively; the two ends of Cdig32 to Cdig34 are connected to the ADC reference voltage (Vref) and the Cbri1 bottom plate respectively; the Cbri1 top plate is connected to the output VP. Similarly, the connection method of the SAR ADC part of the other half of the capacitor array is similar, but the connection method of the bri2 top plate and bottom plate of the bri 1 is exactly the opposite of that of bri1. The capacitors of the ramp ADC part are connected in parallel from Cdig35 to Cdig50 and then connected at both ends to the switch and the top plate of Cbri2. Then, the two ends of Cdig51 to Cdig68 are connected to the ADC reference voltage (Vref) and the top plate of Cbri2 respectively to complete the connection.

[0060] The capacitor array in the SAR ADC section operates as follows: A strong-arm comparator outputs the comparison result, which is received by the SAR logic circuit and used to control the switching of the SAR section of the capacitor array. An example of this comparison is as follows: At the start of the comparison, all switches are set to the Vref potential. If the voltage at VP is greater than the voltage at VN, the comparator outputs a value of 1. At this point, the largest capacitor on the VP side, Csar7, is switched from the Vref potential to 0, creating a new voltage at VP, which is then compared with VN. If VP is greater than VN, the second largest capacitor on the VN side, Csar13, is switched from the Vref potential to 0; conversely, the second largest capacitor on the VP side, Csar6, is switched from the Vref potential to 0, and so on. This part of the operation mainly relies on the SAR logic to control the charging and discharging of the SAR section capacitors, creating a new voltage difference at the comparator front end, thus completing the successive comparison process of the SAR ADC.

[0061] After the SAR ADC comparison, the CDAC array will have residual voltage. At this time, this residual signal needs to be compared more precisely. Due to the high precision of the ramp ADC, it is used as the ADC part of the back end of the SAR ADC.

[0062] The capacitor array in the ramp ADC section is used as follows: After the last comparison of the SAR ADC, its logic section outputs a WN signal, which moves the capacitor connected to WN from the Vref potential to 0, causing the VN voltage to drop slightly. The residual voltage is shifted to [0, +Vmax / 32] so that the residual signal can switch down to 0 in 1LSB steps. To obtain the correct output code, the offset of the redundant range, i.e., 16 LSBs, needs to be subtracted from the original code. During the actual comparison, the ramp ADC logic continuously moves the switches of the same capacitors in the VP terminal, i.e., from Cdig31 to Cdig1, from the Vref potential to 0, so that VP decreases one LSB at a time until the comparison result of the continuity comparator passes 0. The number of switches at this time is recorded, and the correct digital output code is obtained by calculating the delay (usually provided by the continuity comparator) and the offset (16 LSBs).

[0063] This embodiment is applicable to various ADC architectures, including SAR ADCs and ramp ADCs. The above embodiment is merely an example to clearly illustrate the present invention and is not intended to limit the implementation of the invention. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all possible implementations. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

[0064] (5) Examples of conversion methods Based on the capacitor array described above, this embodiment also provides a conversion method, including the following steps: S1. During the SAR ADC conversion stage, based on the output of the comparator, the SAR logic circuit controls the switch connecting the first SAR capacitor subarray, the second SAR capacitor subarray, and the low-position SAR capacitor to successively approximate the input signal at the first output terminal (VP) and the second output terminal (VN) to generate a residual voltage. S2. In the ramp ADC conversion stage, based on the output of the continuity comparator, the ramp logic circuit controls the switches of the first unit capacitors (Cdig1 to Cdig31) connected in the first ramp capacitor subarray, so that the voltage of the first output terminal (VP) decreases step by step until the output of the continuity comparator flips. The final digital output code is calculated based on the number of switches turned on during the flip and the offset introduced by the fixed-level capacitor subarray.

[0065] The detailed implementation of the above methods and steps has been explained in the aforementioned workflow and will not be repeated here.

[0066] In the foregoing description of this specification, references to terms such as "one embodiment," "another embodiment," or "some embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0067] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0068] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A capacitor array for use in SAR-assisted ramp ADCs, characterized in that, include: First output terminal (VP) and second output terminal (VN); The top plate of the first bridging capacitor (Cbri1) is connected to the first output terminal (VP); The second bridging capacitor (Cbri2) has its base plate connected to the second output terminal (VN); The first SAR capacitor subarray includes multiple first SAR capacitors (Csar2 to Csar7). The first terminal of each first SAR capacitor is connected to a reference voltage or ground via a switch, and the second terminal of each capacitor is connected to the first output terminal (VP). The second SAR capacitor subarray includes multiple second SAR capacitors (Csar9 to Csar14). The first terminal of each second SAR capacitor is connected to a reference voltage or ground via a switch, and the second terminal of each capacitor is connected to the second output terminal (VN). The low-side SAR capacitor (Csar1) has its first terminal connected to the reference voltage or ground via a switch, and its second terminal connected to the base plate of the first bridging capacitor (Cbri1). The first ramp capacitor subarray includes multiple first unit capacitors (Cdig1 to Cdig31). The first terminal of each first unit capacitor is connected to a reference voltage or ground via a switch, and its second terminal is connected to the base plate of the first bridge capacitor (Cbri1). The second ramp capacitor subarray includes multiple second unit capacitors (Cdig35 to Cdig50), the first terminal of each second unit capacitor is connected to a reference voltage or ground via a switch, and the second terminal of each unit capacitor is connected to the top plate of the second bridge capacitor (Cbri2). The third ramp capacitor subarray includes multiple third unit capacitors (Cdig51 to Cdig68), each of which has a first terminal connected to a reference voltage and a second terminal connected to the top plate of the second bridge capacitor (Cbri2). A fixed-level capacitor subarray includes at least one fixed-level capacitor (Cdig32 to Cdig34), the first terminal of each fixed-level capacitor is connected to a reference voltage, and the second terminal of each fixed-level capacitor is connected to the base plate of the first bridging capacitor (Cbri1). And a switching network connecting a portion of the capacitors in the first SAR capacitor subarray and the second SAR capacitor subarray with the second bridging capacitor; The capacitance values ​​of the first SAR capacitors (Csar2 to Csar7), the capacitance values ​​of the second SAR capacitors (Csar9 to Csar14), and the capacitance ratios between the low-order SAR capacitor (Csar1) and the first bridging capacitor (Cbri1) and the first unit capacitors (Cdig1 to Cdig31) are configured to form a non-binary weighted relationship.

2. The capacitor array according to claim 1, characterized in that, The capacitance ratios of the first SAR capacitors (Csar2 to Csar7) are 1:2:4:8:16:32, and the capacitance ratios of the second SAR capacitors (Csar9 to Csar14) are symmetrically set to the capacitance ratios of the first SAR capacitors (Csar2 to Csar7).

3. The capacitor array according to claim 2, characterized in that, The first unit capacitor (Cdig1 to Cdig31), the second unit capacitor (Cdig35 to Cdig50), and the third unit capacitor (Cdig51 to Cdig68) all have the same capacitance value, defined as the unit capacitance value C; the low-position SAR capacitor (Csar1) has a capacitance value of 8C; the first bridging capacitor (Cbri1) and the second bridging capacitor (Cbri2) both have a capacitance value of 6C.

4. The capacitor array according to claim 1, characterized in that, The switching network includes: A switch is connected to the first end of a specific capacitor (Csar8) in the second SAR capacitor subarray, and the second end of the specific capacitor (Csar8) is connected to the top plate of the second bridging capacitor (Cbri2).

5. The capacitor array according to claim 1, characterized in that, It also includes a fixed reference voltage capacitor subarray connected to the top plate of the second bridging capacitor (Cbri2), which is composed of the third ramp capacitor subarray.

6. The capacitor array according to claim 1, characterized in that, The capacitors connected to the base plate side of the first bridging capacitor (Cbri1), including the low-level SAR capacitor (Csar1), the first ramp capacitor subarray, and the fixed-level capacitor subarray, together constitute a low-level weighted subnetwork.

7. The capacitor array according to claim 1, characterized in that, The switching of the first unit capacitor (Cdig1 to Cdig31) in the first ramp capacitor subarray is controlled by the ramp ADC logic after the SAR ADC conversion is completed, and is used to realize the successive comparison of the residual voltage.

8. The capacitor array according to claim 1, characterized in that, The second unit capacitor (Cdig35 to Cdig50) is used as a whole to introduce a voltage offset during the ramp ADC conversion phase to adjust the comparison range of the residual voltage.

9. An analog-to-digital converter, characterized in that, It includes a capacitor array as described in any one of claims 1 to 8.

10. A conversion method applied to a capacitor array as described in any one of claims 1 to 8, characterized in that, Includes the following steps: During the SAR ADC conversion stage, based on the output of the comparator, the SAR logic circuit controls the switch connecting the first SAR capacitor subarray, the second SAR capacitor subarray, and the low-position SAR capacitor to successively approximate the input signal at the first output terminal (VP) and the second output terminal (VN) to generate a residual voltage. During the ramp ADC conversion stage, based on the output of the continuity comparator, the ramp logic circuit controls the switching of the first unit capacitors (Cdig1 to Cdig31) connected in the first ramp capacitor subarray, causing the voltage of the first output terminal (VP) to decrease step by step until the output of the continuity comparator flips. The final digital output code is calculated based on the number of switches turned on during the flip and the offset introduced by the fixed-level capacitor subarray.

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