Memory control method and storage device

Abstract

The application belongs to the field of memory control, and provides a memory control method and a storage device. The method comprises: in response to a data read request for a target page, obtaining a health score of the target page; if the health score is not greater than a first threshold, performing a read sensing operation on the target page using a candidate read voltage offset; and without transmitting complete data of the target page from a page buffer area of a memory module to a memory controller, obtaining an effectiveness evaluation result of the candidate read voltage offset according to a state indication signal obtained from the memory module, which is independent of complete data transmission; and according to the effectiveness evaluation result, selectively initiating or skipping an operation of transmitting the complete data of the target page from the memory module to the memory controller and decoding. In this way, the delay caused by read retries is reduced, and the response speed of data reading is improved.

Description

Technical Field

[0001] This application relates to the field of memory control, and more particularly to a memory control method and a memory device. Background Technology

[0002] NAND flash memory, with its advantages of high density and non-volatility, has become a core storage medium in storage systems ranging from consumer electronics to enterprise-level systems. Especially in demanding applications such as intelligent connected vehicles and industrial control, memory chips not only need to meet high capacity requirements, but also must provide deterministic low latency and high reliability services in complex environments such as extreme temperatures.

[0003] Under stress from programming / erasing cycles, data retention time, and read interference, the threshold voltage distribution of memory cells can shift and broaden, leading to an increase in the original bit error rate. Therefore, when the initial read attempt fails, a read retry mechanism is typically initiated, adjusting the reference read voltage to reread the target page. However, this process often requires traversing a pre-generated retry table containing multiple sets of candidate read voltage offsets. Sometimes, multiple read retries are needed to read the data from the target page, significantly increasing read latency.

[0004] For real-time data access in autonomous driving decision chains or synchronous instruction processing in industrial control systems, excessively high read latency can lead to timeouts in critical data processing and even trigger functional safety risks. Therefore, minimizing the latency overhead caused by read retry is a technical challenge faced by those skilled in the art when designing industrial-grade memory chips. Summary of the Invention

[0005] In view of this, this application provides a memory control method and a storage device to solve or partially solve the above problems.

[0006] This application provides a memory control method applied to a storage device including a memory module and a memory controller. The memory module includes multiple planes, each plane including multiple blocks, and each block including multiple pages. The method includes: in response to a data read request for a target page, obtaining a health score for the target page; if the health score is not greater than a first threshold, performing a read sensing operation on the target page using a candidate read voltage offset; and, without transferring the complete data of the target page from the page cache of the memory module to the memory controller, obtaining a validity evaluation result of the candidate read voltage offset based on a status indication signal obtained from the memory module that is independent of complete data transfer; and, based on the validity evaluation result, selectively initiating or skipping the operation of transferring the complete data of the target page from the memory module to the memory controller and decoding it: if the validity evaluation result is positive, initiating the complete data transfer and decoding; if the validity evaluation result is negative, directly skipping the current complete data transfer and decoding, and continuing to try the next candidate read voltage offset.

[0007] Embodiments of this application further provide a storage device, including a connection interface, a memory module, and a memory controller. The memory controller includes error checking and correction circuitry, a buffer memory, and memory control circuitry, electrically connected to the connection interface and the memory module. The memory module includes multiple planes, each plane including multiple blocks, each block including multiple pages, and the memory controller is configured to: in response to a data read request for a target page, obtain a health score for the target page; if the health score is not greater than a first threshold, perform a read sensing operation on the target page using a candidate read voltage offset; and, without transferring the complete data of the target page from the page buffer of the memory module to the memory controller, obtain a validity evaluation result of the candidate read voltage offset based on a status indication signal obtained from the memory module that is independent of complete data transfer; and, based on the validity evaluation result, selectively initiate or skip the operation of transferring the complete data of the target page from the memory module to the memory controller and decoding it: if the validity evaluation result is positive, initiate the complete data transfer and decoding; if the validity evaluation result is negative, skip the current complete data transfer and decoding and continue to try the next candidate read voltage offset.

[0008] Based on the above, the memory control method and storage device proposed in the embodiments of this application, in response to a data read request for a target page, obtain a health score of the target page; if the health score is not greater than a first threshold, a read sensing operation is performed on the target page using a candidate read voltage offset; and without transferring the complete data of the target page from the page cache of the memory module to the memory controller, a validity evaluation result of the candidate read voltage offset is obtained based on a status indication signal obtained from the memory module that is independent of complete data transfer; based on the validity evaluation result, the operation of transferring the complete data of the target page from the memory module to the memory controller and decoding is selectively initiated or skipped: if the validity evaluation result is positive, the complete data transfer and decoding are initiated; if the validity evaluation result is negative, the current complete data transfer and decoding are skipped directly, and the next candidate read voltage offset is tried. Through the above embodiments, the latency caused by read retries is reduced, the response speed of data reading is improved, and especially in the case of memory module aging, a stable and high-performance service can be provided to the host system.

[0009] To make the above-mentioned objectives, technical solutions and beneficial effects of this application more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, and these are all within the protection scope of this application.

[0011] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of this application; Figure 2 This is a schematic diagram of a memory controller according to an embodiment of this application; Figure 3 This is a schematic diagram of a memory management module according to an embodiment of this application; Figure 4 This is a schematic diagram of a block of a memory module according to an embodiment of this application; Figure 5 This is a schematic diagram illustrating multiple write voltage levels and multiple threshold voltages in a page according to embodiments of this application; Figure 6 This is an overall flowchart of a memory control method according to an embodiment of this application; Figure 7This is a timing diagram illustrating fast evaluation based on status register flag bits according to an embodiment of this application; Figure 8 This is a flowchart illustrating the voltage generation algorithm selection based on health score grading according to an embodiment of this application; Figure 9 This is a schematic diagram illustrating the voltage generation algorithm library and dynamic selection mechanism according to embodiments of this application; Figure 10 This is a timing diagram of retry and early termination shown according to an embodiment of this application; Figure 11 This is a schematic diagram illustrating command queue management in coordination with cache read commands, according to an embodiment of this application; Figure 12 This is a flowchart illustrating a multi-round graded retry strategy according to an embodiment of this application; Figure 13 This is a schematic diagram of a multi-round hierarchical retry state machine according to an embodiment of this application; Figure 14 This is a schematic diagram illustrating the process of calculating and querying health scores in the background according to an embodiment of this application; Figure 15 This is a schematic diagram of the health score background calculation and physical page score table according to an embodiment of this application; Figure 16 This is a schematic diagram illustrating parallel processing of continuous multi-page reads according to embodiments of this application; Figure 17 This is a schematic diagram illustrating word-line level read timing parameter optimization according to an embodiment of this application. Detailed Implementation

[0012] Reference will now be made in detail to exemplary embodiments of this application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0013] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of this application. Please refer to... Figure 1The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, automotive infotainment system, advanced driver assistance system (ADAS), game console, server, or computer system located in a specific carrier (e.g., vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. Furthermore, the storage device 12 can include a solid-state drive (SSD), universal flash storage (UFS), embedded multi-media card (eMMC), USB flash drive, memory card, or other types of non-volatile storage devices. It is particularly suitable for fields with stringent requirements for reliability, data integrity, environmental tolerance, and long-term stability, such as industrial control, edge computing, and automotive electronics.

[0014] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multimedia cards, general-purpose flash memory, Peripheral Component Interconnect Express (PCI Express), Non-Volatile Memory Express (NVM express), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 (e.g., exchange signals, instructions, and / or data) via connection interface 121.

[0015] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include single-level cell (SLC) NAND flash memory modules, multi-level cell (MLC) NAND flash memory modules, triple-level cell (TLC) NAND flash memory modules, quadruple-level cell (QLC) NAND flash memory modules, and / or other memory modules with the same or similar characteristics. For multi-level cell (MLC, TLC, QLC, and PLC) flash memory modules, specially selected and tested flash memory modules that meet the requirements of wide operating temperature (e.g., -40°C to 105°C or higher), high durability, and data retention can be used.

[0016] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices. In one embodiment, memory controller 123 may include a flash memory controller. In particular, for automotive functional safety requirements, the architecture of memory controller 123 may include safety islands, dual-core lockstep, or other redundancy and monitoring mechanisms to ensure the reliability of control logic.

[0017] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited in this application. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0018] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of this application. Please refer to... Figure 1 and Figure 2 The memory controller 123 includes a host system interface 21, a memory interface 22, and a memory control circuit 23. The host system interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0019] Memory control circuitry 23 is connected to host system interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host system interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0020] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and controlled by the memory controller 123 to cache data. For example, the buffer memory 24 can be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122. Specifically, the logical-to-physical mapping table and its higher-level address management unit are typically resident or cached in the buffer memory 24 to support high-speed access and updates. To ensure the reliability and consistency of the mapping table data (described in detail below) in the event of sudden events such as abnormal power failures, the buffer memory 24 may employ a storage medium with power loss protection (PLP) characteristics or incorporate a backup capacitor design to ensure that critical metadata has sufficient time to be written into the memory module 122.

[0021] In one embodiment, the memory controller 123 may further include an error checking and correction circuit 25. The error checking and correction circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the error checking and correction circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code.

[0022] In one embodiment, the memory controller 123 may also include other types of various circuit modules (e.g., power management circuits, etc.), which are not limited in this application.

[0023] In one embodiment, the memory controller 123 may further include a power management circuit 26. The power management circuit 26 is connected to the memory control circuit 23 and is used to control the power supply of the storage device 12. The power management circuit 26 not only manages conventional power consumption, but also meets the complex power sequences and low static power consumption requirements of automotive electronics, and can handle voltage fluctuations during vehicle start-stop processes, ensuring that the storage device 12 operates stably in harsh power environments.

[0024] Figure 3 This is a schematic diagram illustrating a memory management module according to an embodiment of this application. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1)-301(B). Each physical unit includes multiple storage units for non-volatile data storage.

[0025] In one embodiment, an entity unit may include an entity programming unit. In one embodiment, an entity programming unit is also referred to as an entity programming unit. In one embodiment, an entity programming unit may be considered as an entity page.

[0026] In one embodiment, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and this application is not limited thereto. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and this application is not limited thereto.

[0027] In one embodiment, a physical programming unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on a physical programming unit to write data to that physical programming unit, multiple memory cells in that physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to that physical programming unit to change the threshold voltage of at least some of the memory cells in that physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell.

[0028] In one embodiment, an entity erasure unit may include multiple entity programmable units. In another embodiment, an entity erasure unit may be considered as an entity block.

[0029] In one embodiment, multiple programmed units in a physical erase unit can be erased simultaneously. For example, when performing an erase operation on a physical erase unit, an erase voltage can be applied to multiple programmed units in this physical erase unit to change the threshold voltage of at least some of the memory cells in these programmed units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased.

[0030] In one embodiment, the memory control circuit 23 can logically associate entity units 301(0)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(0)-301(A) in the data area 31 all store data (also referred to as user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1)-301(B) in the idle area 32 do not store any data (e.g., valid data).

[0031] In one embodiment, if a physical unit does not store valid data, this physical unit can be associated with the free area 32. Furthermore, physical units in the free area 32 can be erased to clear the data within them. In one embodiment, physical units in the free area 32 are also referred to as idle physical units. In one embodiment, the free area 32 is also referred to as the free pool.

[0032] In one embodiment, in response to the requirements of predictable storage lifetime for industrial and automotive applications, the memory control circuit 23 can implement wear leveling and bad block management strategies, and monitor the number of erase / write cycles, read counts, and data retention time of each physical unit in real time, so as to provide the host system 11 with a health status report and remaining lifetime prediction of the storage device 12, thereby meeting the diagnostic coverage requirements of relevant functional safety standards.

[0033] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used cyclically between the data area 31 and the idle area 32.

[0034] In one embodiment, the memory control circuit 23 may be configured with multiple logic units 302(0)-302(C) to map physical units (i.e., physical units 301(0)-301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0035] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0036] In one embodiment, the memory control circuit 23 may record the mapping relationship between logical units and physical units in at least one management table (also known as a logic-to-physical mapping table, or L2P table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information in this management table (i.e., the logical address to physical address mapping table).

[0037] In one embodiment, Figure 4 This is a schematic diagram of a physical unit (block) 400 in a memory module 122 according to an embodiment of this application, wherein the memory module 122 is a three-dimensional NAND flash memory. Figure 4 As shown, the physical cell 400 includes multiple memory cells (such as the floating gate transistor 402 shown in the figure or other charge trap elements), which form a three-dimensional NAND memory architecture through multiple bit lines (only BL1 to BL3 are shown in the figure) and multiple word lines (such as WL0 to WL2, WL4 to WL6 shown in the figure). Figure 4 In the example of the topmost plane, all the floating gate transistors on word line WL0 constitute at least one data page, all the floating gate transistors on word line WL1 constitute at least another data page, and all the floating gate transistors on word line WL2 constitute at least another data page, and so on. Furthermore, depending on the writing method of the memory module 122, the definition between word line WL0 and data page (logical data page) will also be different. Specifically, when writing using Single-Level Cell (SLC) method, all floating gate transistors on word line WL0 correspond to only a single data page; when writing using Multi-Level Cell (MLC) method, all floating gate transistors on word line WL0 correspond to two data pages; when writing using Triple-Level Cell (TLC) method, all floating gate transistors on word line WL0 correspond to three data pages; and when writing using Quad-Level Cell (QLC) method, all floating gate transistors on word line WL0 correspond to four data pages.

[0038] In one embodiment, Figure 5 This diagram illustrates the use of a three-level memory block as block 400, with multiple write voltage levels L1 to L8 and multiple read voltages Vt1 to Vt7. The read voltages Vt1 to Vt7 can also be referred to as threshold voltages. Figure 5As shown, each floating gate transistor 402 can be programmed to have voltage levels L1 (i.e., (MSB,CSB,LSB) = (1,1,1)), L2 (i.e., (MSB,CSB,LSB) = (1,1,0), L3 (i.e., (MSB,CSB,LSB) = (1,0,0)), L4 (i.e., (MSB,CSB,LSB) = (0,0,0)), and L5 (i.e., (MSB,CSB,LSB) = (1,0,0)). The memory control circuit 23 can read the least significant bit (LSB) of the floating gate transistor 402 using voltage levels L6 (i.e., (MSB,CSB,LSB) = (0,1,1)), L7 (i.e., (MSB,CSB,LSB) = (0,0,1)), or L8 (i.e., (MSB,CSB,LSB) = (1,0,1)). When the memory control circuit 23 needs to read the least significant bit (LSB) in the floating gate transistor 402, the memory control circuit 23 will use read voltages Vt1 and Vt5 to read the floating gate transistor. The memory control circuit 23 uses read voltages Vt2, Vt4, and Vt6 to read the floating gate transistor 402 and generates a "1" or "0" based on its on-state (whether current is generated). Similarly, when the memory control circuit 23 needs to read the intermediate valid bit (CSB) in the floating gate transistor 402, it generates a "1" or "0" based on the on-state (whether current is generated) of the floating gate transistor 402 for decoding by the error checking and correction circuit 25. Similarly, when the memory control circuit 23 needs to read the most significant bit (MSB) in the floating gate transistor 402, the memory control circuit 23 uses read voltages Vt3 and Vt7 to read the floating gate transistor 402, and determines whether the most significant bit is "1" or "0" based on the conduction state of the floating gate transistor 402 (whether current is generated), so that the error checking and correction circuit 25 can perform decoding. In this embodiment, when the floating gate transistor 402 has a voltage level L1, it can be referred to as having an erase state, and when the floating gate transistor 402 has any of the voltage levels L2 to L8, it can be referred to as having a program state.

[0039] It should be noted that, Figure 5 The example shown is only used to illustrate the process of the memory control circuit 23 reading the floating gate transistor 402, and its implementation is not a limitation of the present invention. Specifically, the least significant bit, the middle significant bit, and the most significant bit can have different encoding methods, and the memory control circuit 23 can use additional auxiliary voltage to read the floating gate transistor 402 to provide more information to the error checking and correction circuit 25 for decoding.

[0040] In one embodiment, because the write voltage levels L1 to L8 of the memory module 122 may drift due to data retention, write status, environmental factors, etc., the original read voltages Vt1 to Vt7 may not be able to correctly read the flash memory module 122. Therefore, the manufacturer of the memory module 122 usually provides multiple read retry tables, each of which records at least one read voltage, and no two read levels have exactly the same read voltage. The memory control circuit 23 can load the read retry tables into the buffer memory 24 at power-on to control the flash memory module 122 to use different read voltages Vt1 to Vt7 to read the flash memory module 122, so as to obtain data of better quality and that can be successfully decoded. However, this reread mechanism is a passive retry strategy.

[0041] In related technologies, the passive reread process requires multiple round trips to the memory interface 22. Each retry involves a complete command-address-data transfer cycle, which lengthens the worst-case read latency, causing high tail latency and impacting user experience (such as application startup lag and I / O response jitter). Furthermore, each retry consumes 122 channels of bandwidth in the memory module and repeatedly exhausts hardware resources such as the error checking and correction circuit 25, reducing overall I / O throughput, especially under high load, leading to bandwidth and resource waste. Moreover, existing reread tables are typically static, discrete sets of voltage offsets (values), unable to distinguish the causes of threshold voltage drift (such as long-term aging and short-term noise), and lack determination of the target memory page corresponding to the current read operation, resulting in insufficient or excessive correction.

[0042] To address the issue of increased latency and power consumption caused by multiple invalid read and decode operations due to low-quality pages in existing read retry mechanisms, this application proposes an improved read retry mechanism. The core of this mechanism lies in pre-judging the health of storage pages through a health score and combining this with rapid analysis of status indication signals independent of complete data transmission. This allows for skipping undesirable read attempts before complete data transmission, avoiding unnecessary operations. Consequently, read latency and power consumption can be significantly reduced, improving the read efficiency of the storage device.

[0043] See Figure 6 , Figure 6 This is an overall flowchart of a memory control method provided in an embodiment of this application. The method is executed by a memory controller 123 (or a memory control circuit 23) and includes the following steps: Step S601: In response to a data read request for the target page initiated by the host system 11 or an internal maintenance task, obtain the health score of the target page.

[0044] Specifically, when the memory controller 123 receives a read instruction for a target logical address from the host system 11, it locates the corresponding target physical page using a logical-to-physical address mapping table. Simultaneously, the memory controller 123 retrieves the health score corresponding to the target physical page from a pre-maintained Physical Page Score (PPST) table. This health score is a quantitative indicator used to predict the probability of successfully reading data using the default read voltage. A higher score indicates better page quality, while a lower score indicates a higher likelihood of read errors and the need for read retries. This PPST table is pre-calculated and updated by a background task when the storage device 12 is idle, thereby avoiding complex real-time calculations on critical read paths and minimizing read latency. The specific calculation method for this health score is described in detail in the following embodiments.

[0045] It is important to emphasize that the method in related technologies that evaluates data quality by measuring signal and noise characteristics in real time at the storage device 12 is performed during the read operation after receiving the read command. This requires real-time reading of bit counts under multiple read voltages, which inherently introduces additional latency. In contrast, this embodiment employs a background pre-calculation plus online fast query approach, removing the scoring from the critical read path. Because the scoring is pre-calculated in the background and queried online, this step does not increase latency on the critical read path.

[0046] Step S602: Determine whether the health score is greater than the first threshold. If yes, execute the fast path in step S603; otherwise, execute the retry optimization path in step S604.

[0047] Specifically, the health score acquired by the memory controller 123 is compared with a pre-configured first threshold (e.g., TH_high=80). This first threshold can be dynamically adjusted based on the characteristics of the memory module 122 and the Quality of Service (QoS) requirements of the data storage system 10. This first threshold is stored in the memory module 122 and can be adjusted via firmware upgrades or online calibration.

[0048] Step S603: For high-quality pages with a health score greater than the first threshold, this is a low-latency, fast path. The default read voltage is used to perform the read operation, and the read data is transmitted to the error checking and correction circuit 25 for decoding. Upon successful decoding, data is returned to the host system 11. If decoding fails, the subsequent retry process will continue.

[0049] Step S604: For a health score not greater than a first threshold, a candidate read voltage offset is used to perform a read sensing operation on the target page. This candidate read voltage offset can be a voltage value from a pre-configured optimized voltage sequence or a voltage value dynamically calculated using other algorithms. The core purpose is to directly use the optimized voltage for the first read of a target page pre-judged as a weak page, thereby avoiding the additional latency caused by the high probability of failure and triggering a complete retry process when using the default voltage. The method for generating the optimized voltage sequence will be described in detail in a separate embodiment later.

[0050] Step S605: Without transferring the complete data of the target page from the page cache of memory module 122 to memory controller 123, obtain a validity evaluation result of the candidate read voltage offset based on a status indication signal obtained from memory module 122 that is independent of complete data transfer. This status indication signal is obtained from memory module 122 after the aforementioned read sensing operation is completed and before the complete data of the target page is transferred from the page cache to memory controller 123.

[0051] Traditional methods require waiting for complete data transmission and decoding to determine the success of a read operation. However, this embodiment can predict the validity of a read operation using a status indicator signal even before data transmission has begun or after only a small amount of data has been transmitted. For example, a specific flag bit in the status register of memory module 122 can be read, or partial soft-bit information obtained from memory module 122 can be parsed to estimate the data's bit error rate. If the signal indicates that the current voltage is likely to be successful (e.g., the status flag bit shows a low error rate), subsequent data transmission and decoding continue; if the signal indicates that the current voltage is likely to fail (e.g., the status flag bit shows a high error rate), the entire data transmission and decoding operation is skipped, saving valuable bus bandwidth and decoding resources of the error checking and correction circuit 25.

[0052] While related technologies also attempt to perform evaluation before complete data transmission, their evaluation relies on full signal and noise characteristic measurements (requiring bit counts to be read at multiple voltages), essentially still requiring multiple read operations. This embodiment, however, utilizes the status flag bits or a very small number of soft bits within the memory module 122 to complete the evaluation within microseconds. Its additional overhead is only a few register reads or a small amount of data transmission, far less than the overhead of complete data transmission and decoding.

[0053] Step S606: Based on the validity evaluation result, selectively initiate or skip the operation of transferring the complete data of the target page from the memory module 122 to the memory controller 123 and decoding it: If the validity evaluation result is positive, initiate the corresponding complete data transmission and decoding, and return the data to the host system 11 after successful decoding; if the validity evaluation result is negative, skip the current complete data transmission and decoding, and continue to try the next candidate read voltage offset.

[0054] Specifically, if the status indicator signal is positive (indicating voltage is valid), a complete data transmission and decoding are initiated; if the signal is negative (indicating voltage is invalid), the current complete data transmission and decoding are skipped, and preparation is made to try the next candidate voltage offset. If all candidate voltages have been tried successfully, the deep recovery process begins. Details of the specific implementation of the deep recovery process are described later.

[0055] Through the closed loop of steps S604 to S606 above, this application realizes proactive optimization and fast failure mechanism for weak pages, thereby improving the efficiency of read retry.

[0056] In one embodiment, the validity assessment result of the aforementioned candidate read voltage offset is obtained based on the status indication signal itself, rather than on the success or failure of the decoding of the data read from the target page by the error checking and correction circuit 25 or intermediate parameters (e.g., Syndrome value) generated during the decoding process.

[0057] In one embodiment, the aforementioned status indication signal may include, but is not limited to, at least one of the following forms or a combination thereof: Specific flag bits in the status register of memory module 122 are used to indicate the expected error rate or success probability of the current read operation. Specifically, modern memory modules 122 typically integrate checking logic. After performing a read operation, while loading data into the page cache, memory module 122 can quickly assess the overall quality of the data and reflect the assessment result (e.g., low / high expected error rate) in the status register as one or more flag bits. For example, some manufacturers' memory modules 122 provide flag bits for read reliability or suggest retry in the status register. After detecting that memory module 122 is ready, and before initiating DMA (Direct Memory Access) transfer, memory controller 123 can obtain a prediction of the success probability of the current read by reading and parsing this specific flag bit.

[0058] The memory module 122 obtains soft-bit information or partial data read results that estimate the overall bit error rate trend. Specifically, for the memory device 12 that supports soft-bit reading (the error checking and correction circuit 25 is LDPC ECC), the memory controller 123 can first read a small portion of soft-bit information. This soft-bit information contains statistical characteristics of data reliability, such as the log-likelihood ratio (LLR). By analyzing this partial soft-bit information, the overall data bit error rate trend can be estimated, thereby determining whether the current read voltage is within the valid window without transmitting all the data. In detail, the average absolute value of the LLR can be calculated; if this average value is lower than a certain threshold, it indicates poor signal quality, and the current voltage is likely invalid.

[0059] In addition, a specific representative data module (such as a codeword segment containing key metadata) or a small amount of data (e.g., 4KB or 512 bytes) can be read from the target page. By analyzing the error conditions of this data, the memory controller 123 can infer the RBER (Raw Bit Error Rate) trend of the entire page, thereby assessing the effectiveness of the current read voltage.

[0060] The codeword segment containing key metadata and its verification result are read from the target page. Specifically, in some embodiments, the data of each page can be divided into multiple codewords. The memory controller 123 can first read the first codeword (or a portion thereof) and perform a quick verification (e.g., CRC check or simple parity check). If the verification result of this key segment is poor (e.g., extremely high error rate or verification failure), it can be inferred that the data of the entire page is likely also uncorrectable, thus the data transmission is abandoned prematurely. This method is particularly suitable for scenarios where metadata is concentrated at the beginning of the page in the data layout.

[0061] In one embodiment, the data stored in a page, in addition to user data, typically includes system metadata (such as mapping tables, checksums, etc.). This metadata is often stored in a fixed location on the page and is of high importance. The memory controller 123 can request to read only the codeword segment containing this critical metadata and quickly verify whether the segment can be correctly decoded using its own checksum and CRC (Cyclic Redundancy Check). If the critical metadata cannot be read correctly, the current read voltage can be determined to be invalid, and there is no need to read all the data.

[0062] In one embodiment, when the aforementioned status indication signal is a specific flag bit in the status register of memory module 122, the specific steps for obtaining the validity evaluation result include: after issuing a read retry command based on a certain candidate read voltage offset to memory module 122 (first data page), memory controller 123 begins polling the ready / busy (R / B) flag bit in the status register of the memory module (first data page). When the ready / busy flag bit is detected to have switched from busy to ready, it indicates that the first data page has completed its internal page sensing operation and the data has been loaded into the page buffer. At this time, before the status register information of the memory module (first data page) is reset or before the next command update, the memory controller immediately reads and parses this specific flag bit through a command. By parsing the content of this flag bit, the validity evaluation result of the current candidate read voltage offset can be quickly obtained. This process is completed entirely at the command interface level, without any data transmission, and is very fast. Specifically, the status register in memory module 122 is updated after each new command is issued, so the reading must be completed within the interval between commands.

[0063] See Figure 7 , Figure 7 This is a timing diagram illustrating a fast evaluation based on status register flag bits, as shown in one embodiment of this application. The method is applied to a storage device 12 including a memory module 122. A memory controller 123 (or memory control circuitry 23, hereinafter the same) is configured to execute this method. Figure 7 The timing process of how the memory controller 123 uses specific flag bits in the status register of the memory module 122 to quickly evaluate the validity of candidate read voltage offsets before data transfer is demonstrated.

[0064] like Figure 7 As shown, after the memory controller 123 sends a read command based on the candidate voltage V1, the memory module 122 enters a busy state and performs a page sensing operation (tR). During this period, the memory module 122 senses the data of the target page from the target page into the page buffer, while its internal logic quickly evaluates the overall quality of the data. When the page sensing operation is complete, the ready / busy flag of the memory module 122 switches from busy to ready (e.g., R / B#=1), indicating that the data has been loaded into the page buffer but data transfer has not yet started. At this time, the memory controller 123 immediately reads the specific flag in the status register within a very short time before initiating DMA transfer, parses it, and evaluates the validity of V1.

[0065] If the evaluation result is positive (i.e., valid), a complete data transmission is initiated; if it is negative (i.e., invalid), the current complete data transmission is skipped, and the next candidate voltage V2 is tried. Through this mechanism, this application completes the screening of candidate read voltages within microseconds, thereby avoiding invalid data transmission and decoding overhead.

[0066] It is important to emphasize that the timing requirements of the above operations should be completed within a microsecond-level time window to obtain the most accurate real-time status information, thereby providing a basis for subsequent decisions on whether to initiate DMA transfer. In this way, the memory controller 123 can complete the validity assessment of a retry attempt within a microsecond-level time, at the cost of less time than a complete DMA transfer (which typically takes tens to hundreds of microseconds) and decoding operations.

[0067] In one embodiment, the aforementioned candidate read voltage offset is dynamically generated based on the health score and metadata of the target page. This candidate read voltage offset is a portion of a voltage sequence generated by a multi-dimensional voltage pre-correction algorithm. The voltage sequence contains multiple ordered candidate read voltage offsets, the sequence length of which is dynamically adjusted according to the health score, and the step values ​​between adjacent voltage offsets in the sequence are set according to predetermined rules to gradually approach the predicted optimal voltage window center.

[0068] In one embodiment, the metadata includes at least one of the following: Program / Erase Cycle (P / E Cycle), Data Retention Time, Read DisturbCount, Current Temperature, Historical Raw Bit Error Rate (Historical RBER), and Block Health Grade.

[0069] In one embodiment, the step of generating the aforementioned candidate read voltage offset further includes: selecting a corresponding algorithm from an algorithm library containing at least two voltage generation algorithms based on at least two different principles, according to a preset numerical range in which the health score falls. For example, three quality ranges can be preset (assuming a score range of 0 to 100). Specifically, the high-quality range (score > 80): uses the fast path and does not require this algorithm. The slightly deteriorated range (70 < score ≤ 80): selects the fastest lookup table algorithm. The moderately deteriorated range (30 < score ≤ 70): selects a more accurate physical model compensation algorithm. The severely deteriorated range (score ≤ 30): selects the most applicable machine learning prediction algorithm. This hierarchical decision-making mechanism achieves the best balance between computational overhead and prediction accuracy, ensuring the overall efficiency of the scheme.

[0070] In one embodiment, the step values ​​between adjacent voltage offsets in these voltage sequences are correlated to progressively approximate the center of the predicted optimal voltage window.

[0071] Specifically, the candidate readout voltage offset is not an isolated single voltage value, but a portion of a voltage sequence generated by a multidimensional voltage pre-correction algorithm. This voltage sequence contains multiple ordered candidate readout voltage offsets, denoted as V_REF1, V_REF2, ..., V_REF[N_RR]. This voltage sequence has two important dynamic characteristics: dynamic adjustment of the sequence length and correlation of the step value.

[0072] In detail, regarding the dynamic adjustment of the sequence length, the sequence length N_RR is not fixed but dynamically adjusted based on the health score of the target page. For example, for medium-quality pages with a health score slightly below the first threshold (e.g., a score between 60 and 80), the sequence length can be set to a smaller value (e.g., N_RR=5); for weak pages with a relatively low health score (e.g., a score less than 30), to increase the probability of success, the sequence length can be set to a larger value (e.g., N_RR=8 or even more). This ensures a high success rate while avoiding unnecessary excessive retries on pages of acceptable quality.

[0073] In detail, regarding the correlation of step values, the step values ​​between adjacent voltage offsets in the sequence are not determined in isolation, but are correlated. The purpose is to ensure that the voltage values ​​throughout the sequence gradually approach the center of the optimal read voltage window, determined by the physical characteristics of the memory cells in the current state. For example, if the predicted optimal window center is to the right of the base voltage, the generated sequence might be [base voltage + offset 1, base voltage + offset 2, ...], where offset 1 < offset 2..., forming a monotonically increasing search path and avoiding oscillations in invalid regions. The step value can be an arithmetic or geometric sequence, or a dynamic step size predefined based on historical success experience.

[0074] In one embodiment, the core of the aforementioned multidimensional voltage pre-correction algorithm is a policy decision tree. Based on a preset numerical range in which the health score falls, the algorithm dynamically selects the most suitable algorithm from a library containing at least two voltage generation algorithms based on different principles to generate the aforementioned voltage sequence.

[0075] In one embodiment, the algorithm library includes: a lookup algorithm based on historical successful voltages; a physical model compensation algorithm based on charge loss and interference in memory module storage units; and a prediction algorithm based on a pre-trained and quantized lightweight machine learning model. Specifically, when the health score falls within a preset numerical range indicating that the target page's health status is worse than a second threshold, the machine learning prediction algorithm is selected.

[0076] See Figure 8 , Figure 8 This is a flowchart illustrating the voltage generation algorithm selection based on health score grading, as shown in one embodiment of this application. The method is applied to a storage device 12 including a memory module 122. A memory controller 123 (or memory control circuit 23, hereinafter the same) is configured to execute this method. Figure 8 The document demonstrates the decision-making process of dynamically selecting the corresponding voltage generation algorithm from the algorithm library based on the preset numerical range of the target page's health score.

[0077] like Figure 8 As shown, the health score of the target page is first obtained and compared with multiple preset threshold ranges. This embodiment exemplarily divides the page degradation level into three ranges: mild degradation, moderate degradation, and severe degradation.

[0078] When the health score falls into the slightly deteriorated range, the fastest lookup table algorithm is selected to generate candidate voltage sequences by looking up pre-recorded historical successful voltage offsets.

[0079] When the health score falls into the moderate degradation range, a more accurate physical model compensation algorithm is selected to calculate the voltage offset based on the charge loss and interference physical model of the storage unit.

[0080] When the health score falls into the severely deteriorated range, the most applicable machine learning prediction algorithm is selected, and the optimal voltage offset is predicted by a model that has been trained offline in advance.

[0081] See Figure 9 , Figure 9 This is a schematic diagram of a voltage generation algorithm library and dynamic selection mechanism shown in an embodiment of this application. Figure 9 Further refinement Figure 8 The internal structure of the algorithm library shown illustrates how health scores and metadata jointly drive the dynamic selection of the algorithm library. This method is applied to a storage device 12 containing a memory module 122. A memory controller 123 (or memory control circuitry 23, hereinafter the same) is configured to execute this method. Figure 9 This embodiment demonstrates how a health score-driven algorithm library enables an intelligent voltage generation strategy.

[0082] like Figure 9 As shown, the left side represents the input features, including health scores and metadata (such as programming / erasing counts, data storage time, read interference counts, current temperature, historical raw bit error rate, and block health level). The middle section is the decision-maker, which makes judgments based on the preset numerical range of the health score. The right side contains an algorithm library with three voltage generation algorithms based on different principles: a lookup table algorithm, a physical model compensation algorithm, and a machine learning prediction algorithm.

[0083] The decision-maker selects a corresponding algorithm from the algorithm library based on the interval judgment result of the health score. Simultaneously, metadata is passed as input parameters to the selected algorithm for specific processing. Each algorithm ultimately outputs a voltage sequence containing multiple candidate voltage offsets.

[0084] This hierarchical decision-making mechanism based on the degree of page degradation achieves an optimal balance between computational overhead and prediction accuracy, ensuring the overall efficiency of the solution. Preset numerical ranges and corresponding algorithm selection strategies can be stored as configuration parameters in the firmware and can be adjusted according to the actual characteristics of the memory module 122.

[0085] In one embodiment, a valley search method based on count differences is also proposed, but this voltage generation method is singular and cannot adjust the strategy according to the degree of page degradation.

[0086] In one embodiment, the use of read history tables, predefined tables, and e-boost searches is also proposed, but these methods are fixed serial steps rather than dynamically selecting different algorithms based on the number of error bits.

[0087] In summary, this embodiment achieves intelligent voltage generation through a health score-driven algorithm library.

[0088] In one embodiment, the aforementioned algorithm library includes at least three voltage generation algorithms based on different principles: a lookup algorithm based on historical successful voltages, an empirical method that looks up the voltage offsets of pages successfully read under similar conditions, suitable for mildly degraded pages; a physical model compensation algorithm based on storage cell charge loss and interference, a theoretical calculation method based on the physical characteristics of the memory module 122, which uses a mathematical model to quantify the offset and broadening caused by various stresses on the cell threshold voltage distribution and calculates the voltage offset that needs to be compensated, suitable for moderately degraded pages; and a prediction algorithm based on a pre-trained and quantified lightweight machine learning model, a data-driven method that collects a large amount of optimal read voltage data of the memory module 122 under different wear and interference conditions during offline operation and uses this data to train a machine learning model. During online operation, the current metadata features are input into the model, and the model directly outputs the predicted optimal voltage offset, suitable for severely degraded pages.

[0089] Specifically, when the health score falls within a preset range indicating that the target page's health is worse than a second threshold (e.g., score ≤ 30), the algorithm automatically selects a machine learning prediction algorithm. This is because when a page is severely degraded, the degradation factors are highly complex and interdependent, making it difficult for simple lookup tables or physical models to accurately compensate. The machine learning model is better positioned to capture these complex relationships and thus output the most likely successful read voltage.

[0090] In one embodiment, the specific implementation of the above lookup table algorithm is as follows: During the firmware development phase, extensive post-silicon characteristic testing is conducted on memory module 122 samples under different combinations of metadata (programming / erase counts, data storage time, temperature range, read interference count, historical raw bit error rate, block health level). Predictive tests are performed, and the optimal voltage offset that minimizes the bit error rate under each condition is calculated. These offsets are burned into a multidimensional optimized voltage offset table (OVOT) and stored in the system area of ​​memory module 122. During runtime, the grid interval in the table where the target page is located / falls into is determined based on the target page's current metadata (programming / erase counts, data storage time, temperature range, read interference count, historical raw bit error rate, block health level). A continuously changing voltage offset is calculated through multidimensional linear interpolation (e.g., three-dimensional linear interpolation), and the final output voltage formula is: optimized voltage = base voltage + lookup table offset.

[0091] The advantage of this method lies in its extremely fast computation speed, requiring only a few buffer memory accesses and multiply-accumulate operations. Its additional overhead is merely a few register reads or a small amount of data transfer, far less than the overhead of complete data transfer and decoding. To ensure the accuracy of the lookup table, each dimension is typically divided into multiple intervals (e.g., P / E counts are divided into 0-1K, 1-2K, etc.), and the table is ensured to cover the entire lifecycle.

[0092] In one embodiment, the method further includes: upon successfully reading a target page using a certain read voltage offset, recording the successful voltage offset and its corresponding metadata context. This data from successful cases can be used in subsequent firmware updates to optimize and correct the original table data of the lookup algorithm in the aforementioned algorithm library through offline analysis, thereby achieving continuous iterative evolution of the algorithm.

[0093] Specifically, after successfully reading a target page with a specific read voltage offset, the memory controller 123 records the successful read voltage offset. More importantly, according to the principle of spatial locality of memory, other pages located on the same word line or in the same block typically have similar physical characteristics and degrees of degradation. Therefore, this successful voltage offset can be recorded and used as the preferred reference read voltage offset for subsequent read operations on other pages located on the same word line or in the same block as the target page. This improves read performance when subsequently reading these adjacent pages. Metadata context can be saved simultaneously during recording to determine whether reuse conditions are still valid.

[0094] In one embodiment, the physical model compensation algorithm is constructed based on the physical characteristics of the storage cells. The algorithm calculates several core physical offsets, such as threshold voltage distribution broadening, charge leakage, read interference offset, and temperature correction, and adds them to the base voltage.

[0095] Specifically, the broadening of the threshold voltage distribution in memory cells is caused by tunneling oxide layer damage due to increased programming / erasing cycles, typically proportional to the square root of the P / E cycle count. Charge leakage due to data storage time, caused by charge leakage from the floating gate or charge trapping layer over time, leads to a decrease in threshold voltage, usually exhibiting an exponential decay. Read interference offset, caused by read operations on the same or adjacent word lines, results in threshold voltage drift due to weak programming effects. It is typically related to the hyperbolic tangent of the number of read interference cycles. Voltage correction due to temperature changes, caused by the temperature difference between the ambient temperature during reading and the temperature during programming, affects channel carrier mobility and threshold voltage. It is typically linearly related to the temperature difference.

[0096] In one embodiment, the above-described physical model compensation algorithm can use the following specific mathematical formulas to calculate the various offsets: Threshold voltage distribution broadening = α × sqrt(P / E Cycles / 1000), where sqrt is the square root calculation and the constant 1000 is used to normalize the P / E cycle to thousands of cycles. Charge leakage = β × (1 - exp(-Retention_time / 8760×5))), where Retention_time is in hours, 8760×5 is approximately equal to the number of hours in 5 years, and exp is the natural exponential function; Retention_time is in hours, and 8760 is the number of hours in one year, so 8760×5 represents the baseline storage time of 5 years. Read Disturbance Offset = γ × tanh (Read Disturb Count / 50000), where tanh is the hyperbolic tangent function; the constant 50000 is the normalized base of the read disturbance, based on the typical tolerance setting of memory module 122; Temperature correction amount = δ × (temperature - 25) / 10, where constant 25 is the reference room temperature (°C) and constant 10 is used to convert the temperature difference into units in 10°C increments.

[0097] α is the program / erase cycle impact factor, in millivolts per square root of 1,000 cycles (mV / √kCycle), representing the contribution of each thousand program / erase cycles (P / E Cycles) to the broadening of the threshold voltage distribution; β is the charge leakage saturation factor, in millivolts (mV), representing the maximum possible voltage drift caused by charge leakage due to long-term data storage; γ is the read interference impact factor, in millivolts (mV), representing the maximum magnitude of threshold voltage drift caused by read interference operations; δ is the temperature correction factor, in millivolts per 10°C (mV / 10°C), representing the threshold voltage drift caused by a 10°C change in temperature.

[0098] Among them, α, β, γ, and δ are configurable parameters, whose default values ​​can be determined through post-silicon testing and stored as adjustable parameters in the firmware. In memory control circuit 23 where memory controller 123 does not support direct calculation of transcendental functions such as square roots, exponential functions, and hyperbolic tangents, these operations can be efficiently implemented using a pre-computed lookup table combined with linear interpolation. For example, a square root lookup table can be pre-constructed, and approximate results can be obtained for input values ​​through table lookup or linear interpolation.

[0099] In one embodiment, the coefficients in the above-described physical model compensation algorithm are configurable parameters, stored in a specific parameter storage area of ​​the system area of ​​the memory module 122, and can be dynamically adjusted through online calibration routines.

[0100] Specifically, to enable the physical model compensation algorithm to adapt to differences in process corners and characteristic changes during the aging process of different memory modules 122, its coefficients are not fixed constants (such as 0.1, 0.15, etc.), but are stored as configurable parameters in specific blocks within the memory module 122 (e.g., parameter blocks specifically storing parameters in the system area). The memory controller 123 can dynamically adjust these parameters based on the actual observed decoding error rate through an online calibration routine in the background, ensuring that the algorithm maintains high prediction accuracy throughout the entire lifecycle of the memory module 122. For example, the deviation between the actual voltage offset and the predicted value at successful reads can be periodically calculated, and the coefficients can be adjusted using a least-two algorithm.

[0101] In one embodiment, the above-described machine learning prediction algorithm includes the following implementation steps: First, Z-score normalization is performed on multiple input metadata features (such as programming / erasing counts, data storage time, read interference counts, current temperature, historical raw bit error rate, block health level, etc.), i.e., (feature value - mean) / standard deviation, to eliminate the influence of different feature dimensions and make the model algorithm inference more stable. The mean and standard deviation are calculated from the training dataset during the model training phase and stored as constants in the firmware.

[0102] Secondly, weights and biases are loaded from the pre-trained model parameters stored as constant arrays in the firmware. This model is typically a linear regression model or a small fully connected network trained on a large amount of data in the cloud or on a high-performance server, and then quantized (e.g., from 32-bit floating-point numbers to 8-bit or 16-bit fixed-point numbers) to reduce storage and computational overhead.

[0103] Next, inference calculations are performed to obtain the core parameter: the read voltage shift. This shift represents the amount of compensation needed on the base read voltage to minimize the bit error rate of the current page (i.e., the read voltage shift). Its calculation formula is: Voltage_shift = bias + Σ(Weight_i × Normalized_feature_i). This formula is a standard linear regression (or single-layer neural network) inference formula. In this embodiment, it is used to predict the most suitable read voltage shift based on various metadata parameters of the current page.

[0104] In detail, `Voltage_shift` is the read voltage offset, which is the output value of the formula. It represents the amount of adjustment needed on the base read voltage to minimize the original bit error rate of the current page. The unit is typically the minimum voltage adjustment codeword, such as 0.02V or 0.05V. This value is the ultimate goal of the entire machine learning prediction algorithm. It will be passed to the subsequent voltage boundary checking step, ultimately used to configure the physical read voltage of the target page.

[0105] The bias term is the model's base offset, a constant representing the baseline value of the voltage offset when the influence of all input features is zero. It can be understood as the model's "intercept." During offline training, it is determined along with the weights. After training, it is stored as a constant in the firmware as part of the model parameters.

[0106] Weight _i represents the weight of the i-th feature, indicating the degree and direction of its influence on the final voltage offset. A positive weight indicates that the larger the feature value, the more positive offset is needed; a negative weight indicates a negative offset. It is learned through a large amount of experimental data during the offline training phase. After training, it is stored in the firmware as a constant array as part of the model parameters.

[0107] Normalized_feature_i represents the i-th normalized feature. It is the standardized value of the i-th metadata feature of the current page. This value is calculated in real time. For example, first, multiple metadata features are obtained (such as programming / erasing counts, data storage time, read interference counts, current temperature, historical raw bit error rate, block health level, etc.); then, Z-score normalization (feature value - mean) / standard deviation is performed using the mean and standard deviation of this feature pre-stored in the firmware. This is done to eliminate the influence of different feature dimensions, making the model algorithm inference more stable.

[0108] For the memory controller 123, which lacks a hardware multiply-accumulator (i.e., does not support multiply-accumulate operations), this calculation process can be simulated through software loop unrolling and fixed-point arithmetic. For example, by using 32-bit fixed-point numbers to represent weights and features, multiplying and accumulating, and then using shift operations to restore the correct decimal part, the value of Voltage_shift can be obtained quickly under limited hardware resources.

[0109] Finally, after applying the calculated Voltage_shift to the base voltage, a voltage boundary check must be performed. Since the model may output outliers when input features exceed the training data range, the memory controller 123 clamps the final output voltage V_final = clamp(V_REF_base + Voltage_shift, V_min, V_max) within a safe minimum and maximum voltage range [V_min, V_max] determined by the physical characteristics of the memory module 122. This prevents complete read failures or damage to other memory cells due to excessively high or low voltage settings. V_min and V_max can be obtained from the memory module 122's specifications. This step ensures that the theoretical values ​​inferred from the model can be safely and reliably applied to the memory controller 123.

[0110] In one embodiment, the multi-round retry iteration step for performing the above-described effectiveness evaluation includes: after the memory controller 123 issues a first read command based on the i-th candidate read voltage offset to the memory module 122, the memory controller 123 does not wait for its data transmission and decoding to complete, but immediately prepares to issue a second read command based on the (i+1)-th candidate read voltage offset in parallel. This ensures that the page sensing phase of the (i+1)-th retry overlaps at least partially in time with the data transmission and decoding phase of the i-th retry. This mechanism ensures that the page sensing phase of the (i+1)-th retry (time tR) overlaps at least partially in time with the data transmission (time tDMA) and decoding (time tECC) phases of the i-th retry. Therefore, starting from the second retry, the effective latency of each retry is significantly reduced.

[0111] Specifically, after determining that a retry process needs to be initiated, the memory controller 123 issues a first read command to the memory module 122 based on the i-th candidate voltage V_REF[i]. Crucially, the memory controller 123 predicts, based on the page quality assessment results, that this retry is likely to fail, and therefore does not wait for it to complete, but immediately prepares for the next retry step.

[0112] Immediately afterwards, the memory controller 123 issues a second read command to the memory module 122 based on the (i+1)th candidate read voltage V_REF[i+1]. If the second command is a Cache Read command, the memory module 122 can immediately begin the read sensing operation of the next page after completing the internal transfer preparation of the previous data, without the need for further intervention from the host system 11.

[0113] This mechanism ensures that the page awareness phase (time tR) of the (i+1)th retry completely overlaps in time with the data transmission (time tDMA) and error checking and correction circuit 25 decoding (time tECC) phases of the i-th retry. Therefore, starting from the second retry, the effective delay of each retry is only max(tR, tDMA+tECC), instead of the traditional (tR+tDMA+tECC).

[0114] See Figure 10 , Figure 10 This is a timing diagram illustrating retry and early termination according to an embodiment of this application. The method is applied to a storage device 12 including a memory module 122. A memory controller 123 (or memory control circuitry 23, hereinafter the same) is configured to execute this method. Figure 10 This embodiment demonstrates the timing process of the read retry and early termination mechanism proposed in this embodiment, and... Figure 7 The reading retest shown forms a contrast.

[0115] like Figure 10As shown, after the memory controller 123 issues the first read command based on the candidate voltage V1, it does not wait for the data transmission and decoding to complete, but immediately prepares and issues a second cache read command based on the candidate voltage V2DE. This makes the page awareness phase of V2 completely overlap with the data transmission and decoding phase of V1 in time.

[0116] When the data corresponding to V1 is successfully decoded, the memory controller 123 immediately sends a termination command to the memory module 122 to terminate all ongoing or yet-to-be-started subsequent retry operations (including the issued V2 read command), thereby achieving early termination and reducing overall latency.

[0117] This embodiment effectively overlaps the waiting times of multiple retries, reducing overall latency and thereby reducing tail latency.

[0118] In one embodiment, a command management optimization method for the above-described memory control method is also proposed. Specifically, if, based on the validity evaluation result of a candidate read voltage offset, it is decided to skip the complete data transmission and decoding operation corresponding to the current candidate read voltage offset, and the read command corresponding to the next candidate read voltage offset is a cache read (e.g., a cache read) command, then a special command termination mechanism is adopted.

[0119] Specifically, the memory controller 123 maintains a retry state machine and a command queue. This state machine continuously monitors the completion status of each issued command, the queue status, and the decoding result of each step. When the error checking and correction circuit 25 of any retry step (e.g., using V_REF[k]) successfully decodes, it means the data has been successfully read. At this point, the memory controller 123 immediately sends a termination command (e.g., Reset or a protocol-specific Cache Read Last command) to the memory module 122 to terminate all ongoing or yet-to-be-started subsequent retry steps and clean up the internally maintained retry state machine and command queue, thereby releasing resources promptly and responding to successful read requests as quickly as possible.

[0120] See Figure 11 , Figure 11 This is a schematic diagram illustrating command queue management in conjunction with cache read commands, as shown in one embodiment of this application. The method is applied to a storage device 12 including a memory module 122. A memory controller 123 (or memory control circuitry 23, hereinafter the same) is configured to execute this method. Figure 11 From the perspective of command queue scheduling, this embodiment demonstrates how to dynamically manage the command queue based on the results of rapid evaluation, thereby achieving collaborative optimization with cached read commands. Figure 11It demonstrates how rapid evaluation results can serve as feedback signals to dynamically adjust the state of the command queue, thereby achieving efficient resource utilization.

[0121] like Figure 11 As shown, the memory controller 123 maintains a command queue and sequentially sends multiple cache read commands based on different candidate voltages. The command scheduler retrieves commands from the queue and sends them to the memory module 122. After each cache read command is issued, the memory controller 123 immediately polls the status register to obtain a fast evaluation signal. If the fast evaluation is negative, a termination command is immediately sent to the memory module 122, and all subsequent commands related to that page are simultaneously removed from the command queue to avoid resource waste. If the fast evaluation is positive, the current command is allowed to continue data transfer, while subsequent commands in the command queue can still be scheduled for issuance. When decoding of any retry step is successful, the memory controller 123 immediately sends a termination command and removes all unexecuted subsequent commands from the command queue.

[0122] In one embodiment, after issuing the next cache read command to the memory module 122, the memory controller 123 does not wait for the read operation to complete as would be the case with a regular read process / operation. Instead, provided that the interface protocol supported by the memory module 122 allows for safe termination of the cache read operation, it will immediately issue a termination command (e.g., a Reset command or a specific Cache ReadLast command that can safely terminate the cache read operation) to the memory module 122 based on a prediction (assuming that this operation is also likely to fail). This termination command conforms to the memory interface 22 protocol (e.g., ONFI or Toggle standard). It is important to note that the timing of issuing the termination command must ensure that the memory module 122 has not yet started or begun the operation of the Cache Read command to avoid state machine corruption in the memory module 122. Typically, the termination command can be issued immediately within a very short time (e.g., within a few microseconds) after the Cache Read command is issued.

[0123] The purpose of this operation is to avoid deadlock or data corruption and to quickly restore the memory to a ready state. Specifically, if termination is not timely, when the memory controller 123 determines that the current operation needs to be skipped, the memory module 122 may be busy moving its data into its page buffer. Forcibly terminating at this point and starting the next command could cause the memory interface 22 protocol state machine to malfunction, resulting in deadlock or data corruption. Furthermore, immediate termination allows the memory module 122 to quickly abandon currently performing low-value operations, clear its internal command queue and buffer, and quickly restore it to a ready state to receive new commands, thus preparing for the next, more likely to succeed, retry command. All of these proactive management strategies ensure the high efficiency of the entire retry process.

[0124] In one embodiment, the step of obtaining the validity evaluation result includes multiple rounds of retry iterations. In other words, the step of obtaining the validity evaluation result is itself a multi-round iterative process, and each round can employ a different strategy. That is, the first round of retry is based on a first set of candidate voltage offsets and a first fast evaluation method; If the first round of retry does not yield a positive evaluation result indicating a valid reading of the voltage offset, a second round of retry is initiated. The second round of retry is based on a second set of candidate voltage offsets and a second fast evaluation method. The second fast evaluation method has higher evaluation accuracy than the first fast evaluation method, and the voltage step size of the second set of candidate voltage offsets is smaller than that of the first set of candidate voltage offsets.

[0125] See Figure 12 , Figure 12 This is a flowchart illustrating a multi-round hierarchical retry strategy according to an embodiment of this application. The method is applied to a storage device 12 including a memory module 122. A memory controller 123 (or memory control circuitry 23, hereinafter the same) is configured to execute this method. Figure 12 This demonstrates the complete process of a multi-round, tiered retry strategy, showcasing a progressive logic from coarse-grained fast search to fine-grained precise search and then to deep recovery. It illustrates how to strike a balance between speed and success rate to minimize average retry overhead.

[0126] like Figure 12 As shown, the process begins with the first round of retry. The first round of retry is based on a first group of candidate voltage offsets with a larger step, and uses a first fast evaluation method (e.g., only querying the status register flags) to evaluate validity. If the evaluation is positive, complete data transmission and decoding are initiated, and the process ends.

[0127] If the first retry does not yield a positive evaluation result, a second retry is initiated. The second retry is based on a smaller step size for the second group of candidate voltage offsets and employs a second fast evaluation method (such as combining status register flags and soft bit information) for high-precision evaluation. If the evaluation is positive, complete data transmission and decoding are initiated, and the process ends.

[0128] If the second retry also fails, the deep recovery process begins. Deep recovery no longer relies on a pre-generated voltage sequence; instead, it scans the entire voltage range in very small steps to attempt to salvage the data. If deep recovery succeeds, the process ends; otherwise, the read operation is declared a failure.

[0129] Specifically, a relatively coarse first set of candidate voltage offsets (e.g., with large voltage steps) is used, and a fast, low-overhead first fast evaluation method (e.g., simply querying the status register flags) is employed to determine whether the voltage is valid. This method is fast but may have limited accuracy.

[0130] If the first round of retry fails to yield a positive evaluation result indicating a valid voltage (i.e., all coarse voltages fail quickly), a second round of retry with higher precision is initiated. The second round is based on a finer set of candidate voltage offsets (e.g., smaller voltage steps and higher search density) and employs a second fast evaluation method with higher evaluation precision.

[0131] The advantage of this hierarchical strategy in this embodiment is that for pages that are not particularly poor in quality, a quick, coarse search may be sufficient to locate the relevant information, avoiding the additional overhead of a fine-grained search. Only for truly difficult-to-read pages is a fine-grained search initiated, thus balancing speed and success rate overall. A third or fourth round can be used, but usually two rounds are sufficient.

[0132] See Figure 13 , Figure 13 This is a schematic diagram of a multi-round hierarchical retry state machine according to an embodiment of this application. The method is applied to a storage device 12 including a memory module 122. A memory controller 123 (or a memory control circuit 23, hereinafter the same) is configured to execute this method. Figure 13 From the perspective of state machines, this demonstrates the internal state transition process of a multi-round hierarchical retry strategy, which is a... Figure 12 The flowchart is supplemented with state diagrams. This state machine diagram helps to understand the internal workings of the multi-round hierarchical retry strategy, as well as the transition conditions between each state.

[0133] like Figure 13 As shown, the state machine enters the first retry state from the initial state. In the first retry state, a rapid evaluation of large-step voltages is performed. If the evaluation is positive, the machine directly enters the success state; if the evaluation is negative, the state transitions to the second retry state.

[0134] In the second retry phase, a high-precision evaluation with small voltage steps is performed. If the evaluation is positive, the system enters a success state; if the evaluation is negative, the system transitions to a deep recovery state.

[0135] In deep recovery mode, a full voltage range scan is performed. If a valid voltage is successfully found, the system enters a success state; otherwise, if all voltage attempts fail, the system enters a failure state.

[0136] In one embodiment, during the initialization phase of the storage device 12, the memory controller 123 detects the memory module 122's support for sequential cache read operations using the memory module 122's ID and parameter page. This ensures compatibility between this embodiment and memory modules 122 from various manufacturers.

[0137] In one embodiment, the first fast evaluation method described above is implemented based on querying a specific flag bit in the status register of the memory module 122. Its advantage is speed, but it contains less information. Specifically, the second fast evaluation method combines two information sources: querying the specific flag bit in the status register and obtaining partial soft bit information from the memory module 122 for statistical analysis. For example, after reading a small number of soft bits, the absolute value of its mean LLR (Log likelihood Ratio) can be calculated. If this absolute value is below a certain threshold, it indicates extremely poor signal quality. Even if the current voltage is valid, subsequent complete data may not be decoded by the error checking and correction circuit 25. Although this composite evaluation method increases overhead slightly, it provides higher evaluation accuracy and can more effectively filter out voltages that are truly likely to succeed. Furthermore, the second fast evaluation method can also employ reading partial data and performing CRC checks.

[0138] In the retry process, relevant techniques either use a fixed voltage offset table or a single prediction model. For pages with a health score (degree of degradation), these strategies fail to achieve optimal performance and success rate. For mildly degraded pages, using complex machine learning models or fine-grained voltage searches incurs unnecessary overhead; while for severely degraded pages, simple table lookup methods may fail. Therefore, in one embodiment, a method is proposed that dynamically selects the voltage generation algorithm based on the health score, performs multiple rounds of tiered retries, and uses a different fast evaluation method in each round.

[0139] Specifically, after obtaining the health score of the target page, if the health score is not greater than the first threshold, the memory controller 123 selects the corresponding algorithm from the algorithm library containing at least two voltage generation algorithms with different principles according to the preset value range of the health score, and generates a voltage sequence containing multiple candidate read voltage offsets.

[0140] Then, multiple rounds of retry iterations are performed to obtain the validity evaluation results of the candidate read voltage offset.

[0141] Specifically, the first round of retry involves evaluating the validity of a first group of candidate voltage offsets with larger steps in the voltage sequence, using a first fast evaluation method (e.g., querying only specific flag bits in the status register).

[0142] Second retry: If the first retry does not yield a positive evaluation result indicating a valid read voltage offset, a second retry is initiated. The second retry evaluates validity based on a second group of candidate voltage offsets with smaller steps in the voltage sequence and a second fast evaluation method (e.g., analysis of combined status register flags and partial soft bit information). The second fast evaluation method has higher accuracy than the first fast evaluation method.

[0143] Finally, based on the positive evaluation results obtained from the aforementioned multiple rounds of retry iterations, the operation of transmitting the complete data of the target page from the memory module 122 to the memory controller 123 and decoding it is initiated, and the data is returned to the host system 11 after the complete data transmission is initiated and the decoding is successful.

[0144] Based on this embodiment, a read retry scheme is constructed that proceeds from state awareness to quantitative scoring, then strategy selection (algorithm selection), and finally tiered execution. It not only selects the most suitable voltage generation algorithm based on the degree of page degradation, but also achieves an optimal balance between speed and accuracy through a tiered retry strategy with progressively increasing evaluation accuracy. Unlike a single voltage generation and fixed retry process, it minimizes inefficient / ineffective retry attempts and improves the overall read performance of the storage device 12.

[0145] To improve read retry efficiency, in one embodiment, a read retry scheme integrating "post-event feedback" is incorporated based on the "pre-judgment" and "in-process rapid evaluation" described above. The "post-event feedback" involves fine-tuning the Syndrome value after LDPC decoding by the error checking and correction circuit 25. Ultimately, a read retry scheme incorporating "pre-judgment," "in-process rapid evaluation," and "post-event feedback" is constructed.

[0146] Specifically, after performing the validity assessment described above and obtaining a positive result, the memory controller 123 initiates complete data transmission and decoding. If the decoding is successful, the memory controller 123 records the actual number of error bits in this successful decoding.

[0147] The actual number of error bits is compared with the predicted error rate estimated by the status indication signal. If the deviation exceeds a preset threshold (e.g., the predicted error is low but the actual error is high), the fast evaluation is considered to be biased. At this point, a fine-tuning process can be triggered, which uses intermediate parameters generated during the decoding process (e.g., the LDPC Syndrome value or the number of iterations) to fine-tune the currently successfully used read voltage offset, and records the optimized value after fine-tuning for future reads of this page or other pages on the same word line.

[0148] Furthermore, the set of data (metadata context, success voltage offset, actual number of error bits) is stored as a training sample in buffer memory 24. When the number of samples accumulates to a certain extent, a background low-priority task is started to use these new samples to incrementally learn or fine-tune the machine learning prediction model in the algorithm library, so that the model can better adapt to the actual aging of the current memory module 122.

[0149] This embodiment integrates a "rapid pre-assessment" mechanism with a "precise post-assessment feedback" scheme. This not only verifies and calibrates the accuracy of the rapid assessment but also uses actual page reading (decoding) data for model self-optimization, forming a closed loop of assessment, decoding, feedback, and learning, enabling the scheme to continuously evolve.

[0150] In one embodiment, after issuing a Cache Read command based on the i-th candidate voltage, the memory controller 123 immediately polls the status register to obtain a fast evaluation signal.

[0151] If the rapid evaluation is negative, the memory controller 123 determines that the read attempt is invalid before the data has been transmitted. At this point, instead of waiting for the cache read to complete, it uses the characteristics of the memory interface 22 protocol to send a command that can safely terminate the cache read operation (e.g., the FFh (RESET) command available in some protocols or the vendor-specific Cache Read EXIT command). This aims to quickly reclaim bus and memory module 122 resources, allowing the memory module 122 to immediately begin preparing for the read sensing of the next candidate read voltage without waiting for the currently invalid page data to be read into the page cache.

[0152] If the fast evaluation is positive, the memory controller 123 allows the current Cache Read to continue data transfer. However, during data transfer and decoding, the next Cache Read command will still be issued in advance based on the prediction of the next candidate read voltage (e.g., based on the stepping pattern, it is considered that the next one may also be valid).

[0153] The memory controller 123 maintains a command queue, which is dynamically adjusted based on the results of a fast evaluation. Once a decoding attempt is successful, all unexecuted cache read commands related to retrying that page are immediately cleared.

[0154] Based on this embodiment, for voltages that are quickly evaluated and determined to be invalid, an early termination method other than sending RESET is adopted, which avoids the invalid occupation of internal resources of memory module 122, realizes delay hiding, and thus improves retry efficiency.

[0155] In one embodiment, the step of obtaining the health score of the target page includes: calculating and recording the health score during the idle period of the storage device 12 using a background task based on the target page's metadata, and recording the correspondence between the physical page number of the target page and the health score in a physical page score table. This step is executed asynchronously by the background process and does not block normal read / write command processing.

[0156] See Figure 14 , Figure 14 This is a schematic diagram illustrating the process of calculating and querying a health score in the background, as shown in one embodiment of this application. The method is applied to a storage device 12 including a memory module 122. A memory controller 123 (or a memory control circuit 23, hereinafter the same) is configured to execute this method. Figure 14 The calculation and query mechanism of the health score was demonstrated, emphasizing the decoupling design between the back-end calculation and the online query. Figure 14 This demonstrates how to remove score calculation from the critical read path by using background pre-calculation and online querying, achieving zero-latency quality assessment.

[0157] like Figure 14 As shown, the process is divided into two parts that are executed in parallel: background tasks and online read paths.

[0158] In the background task section, during the idle period of the storage device 12, the memory controller 123 traverses each physical block to obtain the latest metadata of each page (programming / erase count, data storage time, read interference count, current temperature, historical raw bit error rate, etc.). Based on this metadata, it calculates the health score of each page through weighted combination or pre-computed lookup table, and updates the score result to the physical page score table.

[0159] In the online read path section, when a read request for the target page is received, the memory controller 123 directly queries the physical page score table based on the physical page number of the target page to quickly obtain the pre-calculated health score, which is used for subsequent read retry decisions.

[0160] Based on the target page's metadata, a health score is calculated and recorded by a background task that executes during idle periods of storage device 12 and is transparent to requests from host system 11. This health score is then stored in a physical page score table. Online read paths directly look up the table to obtain the score, avoiding real-time computation overhead and achieving zero-latency quality assessment.

[0161] Specifically, firstly, based on the target page's metadata, a background task calculates and records the health score during the idle time of storage device 12. This background task iterates through all active physical blocks, recalculating the health score for each page based on its latest metadata. To improve efficiency, updates can be performed only on blocks that have been recently accessed or whose data storage time, read interference count, current temperature, historical raw bit error rate, or block health level value exceeds a certain threshold.

[0162] Secondly, the correspondence between the physical page number containing the target page and the calculated health score is recorded in a physical page score table. This table is typically stored in buffer memory 24 for fast access and is periodically flushed to memory module 122 to ensure it is not lost in the event of power failure and is available for use upon the next power-on. The score table can be in the form of a hash table or an array, using the physical page number as the key; this embodiment does not impose a specific limitation.

[0163] See Figure 15 , Figure 15 This is a schematic diagram illustrating the background calculation of health score and the physical page score table according to an embodiment of this application. The method is applied to a storage device 12 including a memory module 122. A memory controller 123 (or memory control circuit 23, hereinafter the same) is configured to execute this method. Figure 15 As shown, based on the target page's metadata, a background task that executes during storage device 12's idle periods and is transparent to requests from host system 11 calculates and records this health score, which is then stored in a physical page score table. Online read paths directly look up the table to obtain the score, avoiding real-time computation overhead and achieving zero-latency quality assessment.

[0164] In response to the read request in step S601, the memory controller 123 directly indexes the pre-generated scoring table through the physical page number to quickly obtain the health score, thereby avoiding complex real-time calculations on critical read paths.

[0165] In one embodiment, the metadata used to calculate the health score is a multi-dimensional set designed to comprehensively reflect the physical degradation state of the page. This metadata includes at least one of the following or any combination thereof: number of programming / erasing operations, data storage time, read interference count, current temperature, historical raw bit error rate, and block health level.

[0166] In one embodiment, when the background task calculates the health score, it does so based on a weighted combination of metadata and through a pre-computed lookup table. This lookup table uses hardware-friendly fixed-point arithmetic.

[0167] Specifically, when the storage device 12 is an embedded product, due to the limited resources of the memory controller 123 of such storage devices, this embodiment, when applied to such products, adopts a hardware-friendly implementation method during the background task calculation to achieve efficient calculation of the health score. Specifically, it does not directly perform complex floating-point weighted operations, but rather uses weighted combinations based on metadata. That is, it is implemented through a pre-computed lookup table. For example, different combinations (programming / erase counts, temperature range) can be pre-mapped to a basic score, and then a correction value based on data storage time and read interference count is added through a lookup table. The entire calculation process uses fixed-point arithmetic, avoiding the huge overhead and uncertainty brought by floating-point operations. For example, a 16-bit fixed-point number is used to represent the score, and the integer approximation value of each weighted item is pre-calculated.

[0168] It should be emphasized that the health score in this embodiment is transparent to read requests without blocking the read path of the host system 11, and the calculation process does not increase the latency of the online read path.

[0169] In one embodiment, to further improve the accuracy of the scoring, the health score calculation can also introduce a weighted factor related to the health status of the block to which the target page belongs. This is because pages within the same block typically experience the same process conditions and similar usage environments, thus exhibiting correlation. The health status of the block can be comprehensively assessed based on the block's cumulative uncorrectable error count (UECC) and / or the average number of programming / wiping operations for all pages within the block. If a block has experienced multiple UECC errors, or its average number of programming / wiping operations is significantly higher than other blocks, then the base score of all pages within that block will be multiplied by a decay factor less than 1, making it more likely to be identified as a weak page, thus facilitating preventative optimization. Specifically, the block health factor can be defined as 1 - (UECC count / threshold), or a decay coefficient can be calculated based on the average number of programming / wiping operations.

[0170] It should be noted that the health scoring mechanism of this application is a continuous and comprehensive quantitative value that integrates various metadata (e.g., programming / erasing count, data storage time, read interference count, current temperature, historical raw bit error rate, block health level) to characterize the probability of page read errors and drive the selection of subsequent multi-level optimization strategies, rather than simply using binarization to determine whether it is abnormal.

[0171] In one embodiment, the aforementioned successful read voltage is not simply reused, but also used for self-optimization of the algorithm library. When a target page is successfully read using a candidate read voltage offset, the memory controller 123 records the successful read voltage offset and its corresponding complete metadata context (such as the number of programming / erase cycles, data storage time, read interference count, current temperature, historical raw bit error rate, and block health level).

[0172] In one embodiment, this valuable experience data of success can be used to optimize the offline updates of the lookup table algorithm and as online training samples for machine learning prediction models.

[0173] Specifically, for offline updates of the optimized lookup table algorithm, during firmware upgrades of storage device 12, the accumulated successful data can be aggregated and analyzed to update and optimize preset values ​​in the multidimensional optimized voltage offset table, making the lookup table algorithm more accurate in the next firmware version. For online training samples of the machine learning prediction model, for more advanced storage devices 12, these real-time collected (metadata, successful read voltage) pairs can serve as training samples for online learning, fine-tuning and incrementally learning the lightweight machine learning model deployed on storage device 12, enabling it to better adapt to the aging trajectory and usage patterns of this specific memory module 122. Online learning can be performed in a low-priority background task to update model weights.

[0174] In one embodiment, a statistical and safeguarding method for weak pages is also proposed. Specifically, the memory controller 123 counts the cumulative number of times the read voltage offset adjustment and validity evaluation steps are performed on the target page. This counter records the frequency at which a page is identified as a weak page and enters the optimization path. When this cumulative number exceeds a preset safety threshold, it indicates that the physical block containing the page may be severely worn or interfered with, and is on the verge of frequent errors. At this time, the memory controller 123 actively triggers a read reclamation mechanism to migrate all valid data in the block containing the target page to a free block with higher health through data migration. Then, the original block is erased, thereby solving the problem of frequent errors in the block from the root and ensuring the long-term reliability of the data. The safety threshold can be set according to the data reliability requirements of the storage device 12, for example, 100 times.

[0175] In one embodiment, a deep recovery mechanism is also proposed as a last line of defense for data reliability. Specifically, if one of the following two situations occurs during the read voltage offset adjustment and validity assessment operation: All values ​​in the preset candidate read voltage offset sequence have been tried, and none of them have obtained a positive evaluation result indicating that the voltage is valid (i.e., all voltages are determined to be invalid in the fast evaluation phase).

[0176] Alternatively, although some voltages pass the rapid evaluation, the complete data transmission and decoding operations corresponding to all candidate voltages fail (the error checking and correction circuit 25 cannot correct this).

[0177] In the above scenario, the memory controller 123 executes a deep recovery algorithm based on a full voltage range scan. This algorithm no longer relies on a pre-generated voltage sequence but instead scans over an extremely wide voltage range in very small steps, attempting to find the voltage point where data can be successfully read. This process is time-consuming and is therefore used only as a last resort to salvage data in extreme cases. The scan range can range from Vread_min to Vread_max, with steps typically in the smallest adjustable voltage unit (e.g., 10mV). It is important to emphasize that the minimum adjustable voltage is specific to the memory controller 123 and is not limited to it in this embodiment.

[0178] In one embodiment, a closed-loop maintenance design for metadata is also proposed. Specifically, the entire read retry scheme is a closed-loop logical setting in which metadata is continuously updated and corrected. After successfully completing the read operation on the target page (whether via the default voltage fast path or the optimized retry path), the memory controller 123 updates the historical raw bit error rate (RBER) metadata corresponding to the target page based on the actual number of error bits in this read (feedback from the error checking and correction circuit 25). For example, if the read corrects 20 bit errors, the background will use this new value to smoothly update the historical raw bit error rate average of the page or block. This updated RBER will serve as an important metadata input in the next background scoring calculation task to generate a more accurate health score, thereby enabling the storage device 12 to self-adapt and continuously optimize. The update algorithm includes, but is not limited to, the exponentially weighted moving average algorithm.

[0179] In one embodiment, a parallel optimization design for continuous multi-page read scenarios is also proposed. Specifically, when the memory controller 123 receives an instruction from the host system 11 to continuously read multiple target pages (e.g., sequential read), the optimization strategy of this embodiment can further leverage the advantages of parallelism.

[0180] See Figure 16 , Figure 16This is a schematic diagram illustrating parallel processing of consecutive multi-page reads according to an embodiment of this application. The method is applied to a storage device 12 including a memory module 122. A memory controller 123 (or memory control circuitry 23, hereinafter the same) is configured to execute this method. Figure 16 This demonstrates how parallel optimization can further improve overall throughput in scenarios involving the continuous reading of multiple target pages. In addition, Figure 16 It also demonstrates how to improve parallelism from single-page to multi-page level through multi-plane operations and command queue scheduling, effectively hiding the retry latency of a single page.

[0181] like Figure 16 As shown, in a scenario where the host system 11 requests to continuously read pages A, B, C, and D, the memory controller 123 first obtains the health score of each page. For page A (a high-quality page) with a health score higher than a first threshold, a fast path is used, and the page is directly read and decoded using the default read voltage.

[0182] For pages with low health, an independent retry state machine is started. Through multi-plane operations and command queue scheduling, the retry steps of multiple pages are executed in overlapping time, thereby improving the overall throughput.

[0183] For pages B, C, and D (weak pages) whose health scores are not higher than the first threshold, the memory controller 123 will not process them serially. Instead, it will maintain an independent read retry operation state machine for each page and issue retry commands for different pages in an interleaved manner through the command queue scheduler.

[0184] For example, while page B is performing its first retry page sensing operation, memory controller 123 can simultaneously send its first retry command to page C, allowing the retry processes of different pages to overlap in time. When the retry of any page is successfully decoded, the data of that page can be returned to the host system 11 without affecting the parallel retries of other pages.

[0185] For pages with a health score higher than the first threshold (i.e., high-quality pages) among multiple target pages, the memory controller 123 will use the standard fast path, that is, directly use the default read voltage to read, send the data to the error checking and correction circuit 25 for decoding, and organize the successfully decoded data to prepare to return it to the host system 11.

[0186] For pages with a health score not exceeding a first threshold (i.e., weak pages) among multiple target pages, the memory controller 123 does not process them sequentially. Instead, it initiates separate read voltage offset adjustment and validity assessment operations for each weak page in parallel. This parallelism is achieved through multi-plane operations or deep scheduling of command queues within the memory controller 123. The overlapping execution in time is achieved through multi-plane operations or command queue scheduling.

[0187] For example, while one plane is performing a page-aware phase of retry, a command can be sent to another plane to perform its first optimized read attempt on another weak page, thereby achieving overlapping execution in time and hiding the retry latency of individual pages.

[0188] In one embodiment, the steps of initiating the respective read voltage offset adjustment and validity evaluation operations in parallel include: maintaining an independent read retry operation state machine for each target page and scheduling it through a command queue so that read retry commands for different target pages are executed concurrently in time to hide command delay.

[0189] Specifically, to achieve fine-grained management of parallel retries for multiple weak pages, the memory controller 123 maintains an independent read retry operation state machine for each target page. These state machines each track the retry progress, current voltage value, and validity evaluation result of their corresponding page. The memory controller 123 uses a global command queue scheduler to interleave and orderly transmit these read retry commands from different pages and at different stages onto the bus. In this way, when a page is idle because it is waiting for page awareness, the bus can be immediately used to serve the state machine of another page (e.g., to initiate a new command or read the status register), thereby maximizing the utilization of bus bandwidth and perfectly overlapping multiple independent retry processes on the timeline, improving the overall throughput in multi-page read scenarios. It should be noted that the number of state machines and the command queue depth can be reasonably configured according to the actual hardware of the memory controller 123, and are not limited here.

[0190] In one embodiment, to further improve the retry success rate, it is proposed to dynamically optimize the read timing parameters before performing a retry.

[0191] Specifically, before or simultaneously with initiating the multi-round retry iteration of the aforementioned effectiveness evaluation, a pre-generated read parameter table is queried based on the target page's metadata. This table stores the optimal read timing parameters under different conditions, such as the width of the read enable pulse and the strength of the output driver. The memory controller 123 configures these optimized read timing parameters into the corresponding registers using a setting feature command. Then, with the optimized read timing parameters in effect, the multi-round retry iteration of the effectiveness evaluation is executed. Because the timing parameters are optimized, signal interference can be effectively reduced, providing a more stable physical basis for voltage regulation. After these multi-round retry iterations are completed, in order not to affect subsequent regular reads, the memory controller 123 restores the read timing parameters to their default values.

[0192] See Figure 17 , Figure 17This is a schematic diagram illustrating word-line level read timing parameter optimization according to an embodiment of this application. The method is applied to a storage device 12 including a memory module 122. A memory controller 123 (or memory control circuit 23, hereinafter the same) is configured to execute this method. Figure 17 This demonstrates how fine-grained timing parameter optimization enables differentiated management of memory module 122, maximizing the parallel capabilities of memory device 12.

[0193] like Figure 17 As shown, memory module 122 contains multiple word lines (WL0, WL1, WL2, ... WLn). Due to differences in the physical location (e.g., layer number) and usage history of different word lines, their optimal read timing parameters (e.g., tPRE, tDISCCH) are different.

[0194] The memory controller 123 maintains a word-line-based Read Timing Parameters Table (RPT), which stores the optimized read timing parameters for each word line. These parameters can be dynamically adjusted and updated via an online calibration unit in the background to adapt to the aging of the word lines over time.

[0195] When multiple target pages (distributed on different word lines) need to be retried in parallel, the command scheduler first queries the RPT table to obtain the optimized timing parameters of the word line where each target page is located, and then configures them to the corresponding word lines using the SET FEATURE command. Each word line independently executes its own read retry process under its optimal timing parameters (in conjunction with the embodiments of rapid evaluation and graded retry in this application).

[0196] In one embodiment, the storage device 12 is a multi-die, multi-channel SSD. Because different dies, and even different word lines within the same die, may have different optimal read timing parameters due to differences in their physical location and usage history, the memory controller 123 maintains a word line-based read timing parameter table. This table stores read timing parameters optimized based on the word line's own physical location (e.g., WL layer number, 128L / 176L). These parameters can be dynamically adjusted and updated via an online calibration routine in the background.

[0197] When multiple target pages (distributed on different word lines) need to be retried in parallel, the memory controller 123 can simultaneously issue SET FEATURE commands to multiple word lines to configure their respective optimized read timing parameters. Subsequently, each word line independently executes its own read retry process under its optimal timing parameters (in conjunction with embodiments of this application such as fast evaluation and graded retry).

[0198] Furthermore, when querying the timing parameter table based on word lines, the timing parameters are linearly corrected in conjunction with the current real-time temperature to compensate for the impact of temperature changes on charge migration.

[0199] Based on this embodiment, the granularity of timing parameter optimization is increased to the word line level, enabling differentiated management of the memory module 122. Furthermore, by combining it with parallel operations, the parallel capabilities of the storage device are maximized, further hiding the latency of single retries and improving the overall throughput of the storage device 12.

[0200] However, Figures 6 to 17 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figures 6 to 17 Each step can be implemented as multiple program codes or circuits, and this application does not impose any limitations. Furthermore, Figures 6 to 17 The method can be used in conjunction with the above examples and embodiments, or it can be used alone; this application does not impose any restrictions.

[0201] In summary, the memory control method and storage device proposed in the embodiments of this application, in response to a data read request for a target page, obtain a health score of the target page; if the health score is not greater than a first threshold, a read sensing operation is performed on the target page using a candidate read voltage offset; and without transferring the complete data of the target page from the page cache of the memory module to the memory controller, a validity evaluation result of the candidate read voltage offset is obtained based on a status indication signal obtained from the memory module that is independent of complete data transfer; based on the validity evaluation result, the operation of transferring the complete data of the target page from the memory module to the memory controller and decoding is selectively initiated or skipped: if the validity evaluation result is positive, the complete data transfer and decoding are initiated; if the validity evaluation result is negative, the current complete data transfer and decoding are skipped directly, and the next candidate read voltage offset is tried. Through the above embodiments, the latency caused by read retries is reduced, the response speed of data reading is improved, and especially in the case of memory module aging, a stable and high-performance service can be provided to the host system.

[0202] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A memory control method, characterized in that, Applied to a storage device including a memory module and a memory controller, the method includes: In response to a data read request for the target page, obtain the health score of the target page; If the health score is not greater than the first threshold, then a read sensing operation is performed on the target page using a candidate read voltage offset; and Without transferring the complete data of the target page from the page cache of the memory module to the memory controller, the validity evaluation result of the candidate read voltage offset is obtained from the memory module based on a status indication signal that is independent of the complete data transfer. Based on the validity evaluation result, the operation of transferring the complete data of the target page from the memory module to the memory controller and decoding it can be selectively initiated or skipped: if the validity evaluation result is positive, the complete data transmission and decoding is initiated; if the validity evaluation result is negative, the complete data transmission and decoding is skipped directly, and the next candidate read voltage offset is tried.

2. The memory control method according to claim 1, characterized in that, The status indication signal includes at least one of the following: A specific flag bit in the status register of the memory module is used to indicate the expected error rate or success probability of this read operation; Soft bit information or partial data read results obtained from the memory module for estimating the overall bit error rate trend; The codeword segment containing key metadata and its verification result are read from the target page.

3. The memory control method according to claim 2, characterized in that, When the status indication signal is a specific flag bit in the status register of the memory module, the step of obtaining the validity evaluation result includes: After issuing a read retry command to the memory module, poll a ready / busy flag bit in its status register; When the ready / busy flag is detected to have switched from busy to ready, the specific flag is read and parsed before the status register information is reset or updated.

4. The memory control method according to claim 1, characterized in that, The candidate read voltage offset is dynamically generated based on the health score and metadata of the target page; and the step of generating the candidate read voltage offset further includes: Based on the preset numerical range of the health score, a corresponding algorithm is selected from an algorithm library containing at least two voltage generation algorithms with different principles to generate a voltage sequence containing multiple candidate read voltage offsets. The step value between adjacent voltage offsets in the voltage sequence is set according to a predetermined rule to gradually approach the center of the predicted optimal voltage window.

5. The memory control method according to claim 4, characterized in that, The algorithm library includes at least two of the following algorithms: A lookup table algorithm based on historical successful voltages; A physical model-based compensation algorithm for charge loss and interference in memory module storage units; Prediction algorithms based on pre-trained machine learning models.

6. The memory control method according to claim 5, characterized in that, The table lookup algorithm is implemented in the following way: During the firmware development phase, voltage offsets are pre-calculated for different combinations of metadata ranges through post-silicon characteristic testing and then burned into a multi-dimensional optimized voltage offset table. During runtime, based on the interval into which the current metadata falls, the continuous voltage offset is calculated through multidimensional linear interpolation.

7. The memory control method according to claim 6, characterized in that, Also includes: When a target page is successfully read using a certain read voltage offset, the successful voltage offset and its corresponding metadata context are recorded for use in optimizing the offline update of the lookup algorithm in the algorithm library.

8. The memory control method according to claim 5, characterized in that, The physical model compensation algorithm calculates the voltage offset based on at least one of the following physical terms: The broadening of the threshold voltage distribution due to the number of programming / erasing cycles; Charge leakage due to data storage time; Threshold voltage drift caused by read interference counting; as well as Voltage correction due to temperature changes; The coefficients in the physical model compensation algorithm are configurable parameters, stored in a specific parameter storage area of ​​the memory module, and can be dynamically adjusted through online calibration routines.

9. The memory control method according to claim 5, characterized in that, The machine learning prediction algorithm includes: Normalize multiple metadata features; Load weight parameters from a pre-trained model; Perform a weighted summation to calculate the voltage offset; After applying the calculated voltage offset to the base voltage, a voltage boundary check is performed to clamp the final output voltage within a safe range determined by the physical characteristics of the memory module.

10. The memory control method according to claim 1, characterized in that, The steps of performing the effectiveness assessment include: After issuing a first read command based on the i-th candidate read voltage offset to the memory module, without waiting for data transmission and decoding to complete, it prepares to issue a second read command based on the (i+1)-th candidate read voltage offset in parallel; and When any retry step is successfully decoded, a termination command is immediately sent to the memory module to terminate all subsequent retry steps that are in progress or have not yet started.

11. The memory control method according to claim 10, characterized in that, Also includes: Maintain a retry state machine to continuously monitor command completion and decoding results; When any retry step is successfully decoded, a termination command is immediately sent to the memory module to terminate all subsequent retry steps that are in progress or have not yet started, and to clear the internally maintained retry state machine and command queue.

12. The memory control method according to claim 10, characterized in that, The method further includes: If, based on the validity evaluation result, it is decided to skip the complete data transmission and decoding operation corresponding to the current candidate read voltage offset, and the read command corresponding to the next candidate read voltage offset is a cached read command; After issuing the cache read command, without waiting for its completion, a termination command that conforms to the memory interface protocol and can safely terminate the cache read operation is immediately sent to the memory module to abort the currently ongoing or queued subsequent read retry commands.

13. The memory control method according to claim 1, characterized in that, The steps for obtaining the validity evaluation results include multiple rounds of retry iterations, wherein: The first round of retry is based on the first set of candidate voltage offsets and the first fast evaluation method; If the first round of retry does not yield a positive evaluation result indicating that the reading voltage offset is valid, a second round of retry is initiated. The second round of retry is based on the second set of candidate voltage offsets and the second fast evaluation method. The second fast evaluation method has higher evaluation accuracy than the first fast evaluation method, and the voltage step of the second group of candidate voltage offsets is smaller than that of the first group of candidate voltage offsets.

14. The memory control method according to claim 13, characterized in that, The first fast evaluation method is based on querying a specific flag bit in the status register of the memory module, while the second fast evaluation method is based on querying a specific flag bit in the status register of the memory module and soft bit information obtained from the memory module.

15. The memory control method according to claim 4, characterized in that, The metadata includes at least one of the following: number of programming / erasing operations, data storage time, read interference count, current temperature, historical raw bit error rate, and block health level.

16. The memory control method according to claim 1, characterized in that, Also includes: Before or simultaneously with initiating the multiple retry iterations of the effectiveness assessment, a pre-generated read parameter table is queried based on the metadata of the target page to obtain a read timing parameter; The read timing parameters are configured to the memory module by setting a feature command; The validity assessment is performed in multiple rounds of retry iterations, provided that the read timing parameters are in effect. After the multiple rounds of retry iterations are completed, the read timing parameters are restored to their default values.

17. The memory control method according to claim 1, characterized in that, The step of obtaining the health score of the target page includes: Based on the metadata of the target page, a background task calculates and records the health score during the idle period of the storage device, and records the correspondence between the physical page number containing the target page and the health score in a physical page score table.

18. The memory control method according to claim 17, characterized in that, When the background task calculates the health score, it uses a pre-computed lookup table based on a weighted combination of metadata. The lookup table uses hardware-friendly fixed-point arithmetic.

19. The memory control method according to claim 1, characterized in that, Also includes: If the instruction for the data read request is an instruction to read multiple target pages consecutively; For pages among the multiple target pages whose health score is higher than the first threshold, the data is read and decoded using the default read voltage and then prepared for return. For pages among the multiple target pages whose health score is not higher than the first threshold, their respective read voltage offset adjustment and validity assessment operations are initiated in parallel, wherein overlapping execution in time is achieved through multi-plane operation or command queue scheduling.

20. A storage device, characterized in that, include: A connection interface for electrically connecting to a host system; The memory module includes multiple planes, each plane includes multiple blocks, and each block includes multiple pages; as well as The memory controller includes an error checking and correction circuit, a buffer memory, and a memory control circuit, and is electrically connected to the connection interface and the memory module; The memory controller is configured to perform the memory control method according to any one of claims 1 to 19.

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