A hierarchical error correction method and system for DDR5 memory and a medium

Abstract

The application relates to the technical field of memory data error correction, and provides a layered error correction method and system for DDR5 memory and a medium, which comprises the following steps: configuring initial resource weights for three layered levels of single-bit error correction, double-adjacent error correction and triple-discrete error detection; after reading memory data and corresponding ECC error correction check bits, determining an error category through comparison operation, and dynamically adjusting resource proportions of each level in combination with parameters such as a real-time running frequency of the memory; then, corresponding error correction is completed or triple-discrete error alarm is triggered according to the error type, and the process is continuously cycled. The application can support mixed processing of multiple error types, dynamically allocate resources in an adaptive high-frequency working state, improve the detection and response capability for burst errors, and improve the error detection and correction efficiency.

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