3D chain ferroelectric memory array structure and method of manufacturing the same

Abstract

The application relates to the technical field of semiconductor storage, and discloses a 3D chain ferroelectric storage array structure and a preparation method thereof. The 3D chain ferroelectric storage array structure comprises an alternating medium stack as a base body, a horizontal cavity formed through wet etching, a ring channel transistor prepared in the cavity and surrounding a vertical bit line, and a storage unit formed by integrating a ferroelectric capacitor. The vertical bit line serves as a source-drain electrode, and a horizontal metal gate forms a word line, so that a three-dimensional stacked structure is realized. The preparation process of the application is compatible with the existing NAND process, the gate control capability is effectively improved, the short channel effect is inhibited, and the storage density and the device reliability are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor storage technology, and in particular to a 3D chain-like ferroelectric storage array structure and its fabrication method. Background Technology

[0002] Ferroelectric random access memory (FeRAM) is a non-volatile memory fabricated by integrating ferroelectric thin films with transistor technology. It utilizes the property that the polarization of ferroelectric materials can reverse with an electric field and remain intact even when power is off. It combines the high speed of RAM with the non-volatility of ROM. Ferroelectric memory can perform rapid storage with very low power requirements. Compared to EEPROM and FLASH, it has faster write speeds, lower power consumption, and a higher number of erase / write cycles. Based on these characteristics, ferroelectric memory can be widely used in small smart devices such as mobile phones, smart cards, ATMs, POS machines, and access control systems.

[0003] The circuit structures of ferroelectric memories are mainly divided into the following three types: 1 transistor-1 capacitor (1T1C) current sensing storage, 1 transistor-n capacitor (1TnC) current sensing storage, 1T1C / 1TnC charge sensing storage, and chain-like ferroelectric memory. For example... Figure 1 The diagram shown is a schematic of the ferroelectric memory circuit structure. Figure 1 (a) is a diagram of the 1T1C current sensing storage structure. Figure 1 (b) is a diagram of a 1TnC current sensing storage structure. Figure 1 (c) is a diagram of a 1T1C charge sensing and storage structure. Figure 1 (d) is a diagram of a 1TnC charge sensing and storage structure; based on Figure 1 It can be seen that 1T1C ferroelectric memory occupies a larger area and has a lower storage density compared to 1TnC, but the series capacitor has a charge sharing problem and poor reliability.

[0004] With technological advancements, consumers are demanding increasingly higher levels of device integration. Improving storage density while minimizing cell area has become a crucial research direction for ferroelectric memories. For example... Figure 2The diagram shows a schematic of the circuit structure of a chain-type ferroelectric memory. The principle of writing a "1" is as follows: the transistor WL of the selected memory cell is turned off, while the WL of the other transistors is turned on. BL is supplied with a high level, and PL is supplied with a low level. Therefore, the source and drain electrodes of the unselected transistor cells have the same potential, and the ferroelectricity will not flip. However, since the transistor of the selected memory cell is in the off state, there is a voltage difference between the source and drain electrodes, causing the ferroelectricity to flip, with the polarization direction pointing towards PL. Subsequently, all WLs are turned off. If a "0" is written, BL is supplied with a low level, PL is supplied with a high level, the transistor WL of the selected memory cell is turned off, and the WL of the other transistors is turned on. At this time, the polarization direction points towards BL, and subsequently, all WLs are turned off. During the reading process, the unselected transistors are turned on, and the storage state can be determined based on the voltage change of BL. The advantages of this chain-type memory are high storage density, fast read speed, and lower power consumption.

[0005] Existing publicly available chain-like ferroelectric memory structures use planar transistors, resulting in a large footprint and low density. While stacking multiple layers of chain-like ferroelectric memory can further increase storage density, the cost also doubles. For example, prior art (CN 118301940 A) provides an array structure of a chain-like memory and its fabrication method, such as... Figure 3 The diagram shows a schematic of an existing chain memory array structure. The bit line (BL) is a vertical structure, and the word line (WL) is a horizontal structure, with its transistors having a vertical channel structure. Although this technology is compatible with NAND flash memory and can directly fabricate 3D chain ferroelectric memory, its transistor structure is a vertical channel structure, resulting in weak gate control capability; moreover, a strong electric field easily appears between the source, drain, and gate, causing a short-channel effect, leading to a narrower memory window; and the projected area is relatively large.

[0006] In summary, the existing array structure of chain memory uses vertical channel transistors, which has problems such as weak gate control capability, strong electric field between source, drain and gate leading to short channel effect and narrowing of memory window; at the same time, the projected area of ​​device cell is large, which limits the improvement of memory density under the same process conditions and makes it difficult to meet the development needs of high-density three-dimensional memory. Summary of the Invention

[0007] Therefore, the technical problem to be solved by the present invention is to overcome the problems of weak gate control capability, uneven electric field distribution, easy to induce short channel effect, narrow storage window, large cell projection area, and limited improvement of storage density in the prior art.

[0008] To address the aforementioned technical problems, this invention provides a 3D chain-like ferroelectric memory array structure, comprising: Substrate; Multiple vertical bit lines, perpendicular to the substrate, are arranged in an array on one side surface of the substrate; Multiple horizontal character lines are arranged in an array above one side surface of the substrate, parallel to the substrate. The multiple vertical bit lines and the multiple horizontal word lines are arranged in an intersecting pattern, forming a memory cell at each intersection position; each memory cell is a channel ring transistor; the source and drain of the channel ring transistor are connected in series on the vertical bit lines, and the gate is connected to the horizontal word lines. An insulating dielectric layer fills the spaces between adjacent vertical bit lines; A ferroelectric capacitor layer is disposed between the channel and gate of a ring-channel transistor, and is combined with the ring-channel transistor to form a 1T1C memory cell. In this structure, multiple memory cells on a vertical bit line are connected in series along the vertical bit line direction to form a vertical memory chain. Multiple vertical memory chains are arranged in an array along the horizontal direction to form a 3D chain-like ferroelectric memory array structure.

[0009] Preferably, the annular channel transistor, with the vertical bit line surrounding it as the source and drain, and the horizontal word line surrounding it as the gate, further includes: A channel material layer is disposed around the horizontal alignment line; A gate oxide dielectric layer is disposed on the outside of the channel material layer.

[0010] Preferably, the insulating dielectric layer and the gate oxide dielectric layer are insulating dielectrics, and their materials are silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, or quartz.

[0011] Preferably, each memory cell in the 3D chain ferroelectric memory array structure is divided into two mutually isolated memory cells along a direction perpendicular to the substrate to obtain the first optimized 3D chain ferroelectric memory array structure.

[0012] Preferably, two adjacent vertical memory chains in the 3D chain ferroelectric memory array structure share a single vertical bit line to obtain a second optimized 3D chain ferroelectric memory array structure.

[0013] Preferably, the vertical bit line and the horizontal bit line are a stacked combination of one or more of the following: elemental metal material, mixed metal material, or compound conductive material; The elemental metal material is titanium, platinum, gold, copper, aluminum, nickel, or shale; the mixed metal material is platinum, nickel-gold, nickel-aluminum, or titanium-gold; the compound conductive material is titanium nitride, polycrystalline silicon, or heavily doped polycrystalline silicon.

[0014] This invention provides a method for fabricating a 3D chain-like ferroelectric memory array structure as described above, comprising: A substrate is provided, and a sacrificial structure is deposited on one side surface of the substrate to form a first stacked structure; the sacrificial structure includes a first dielectric layer and a second dielectric layer deposited alternately in a predetermined period from the direction near the substrate to the direction away from the substrate, and a top layer of first dielectric layer; The first stacked structure is etched to form multiple through holes that penetrate the sacrificial structure along a direction perpendicular to the substrate and are arranged in an array. The via is filled with a third dielectric layer and then traced back. The second dielectric layer is etched to form multiple cavities parallel to the substrate based on the remaining first and third dielectric layers; In each cavity, a channel material layer, a gate oxide dielectric layer, and a metal gate are deposited sequentially from the outer surface of the cavity to the outer surface of the cavity to form a ring channel structure transistor and obtain a second stacked structure. Based on a preset pattern, the third dielectric layer in the second stacked structure is etched to separate the annular channel structure transistors connected in the direction parallel to the substrate, forming a segmented structure and obtaining the third stacked structure. The first dielectric layer in the third stacked structure is etched to obtain multiple grooves; drain and source electrode materials are deposited in each groove and then etched back. Etch the first dielectric layer, the second dielectric layer and the third dielectric layer to form a fourth stacked structure; A second dielectric layer is deposited on the outer surface of the fourth stacked structure and patterned etching is performed to form patterned gaps; the patterned gaps are multiple gaps perpendicular to the substrate and penetrating the sacrificial structure; After etching the first dielectric layer to expose the conductive channel layer, an insulating dielectric material is deposited to fill the patterned gaps, and the second dielectric layer is removed. Ferroelectric capacitor material is deposited and etched back to form a ferroelectric capacitor layer, thereby obtaining a 3D chain-like ferroelectric memory array structure.

[0015] Preferably, the first dielectric layer and the second dielectric layer are insulating dielectrics with different etching selectivity ratios, and the third dielectric layer is a conductive material.

[0016] Preferably, the fabrication of the first optimized 3D chain-like ferroelectric memory array structure includes: An etching region is pre-etched on the surface of the 3D chain-like ferroelectric memory array structure on the side away from the substrate; Based on the etched area, along the direction perpendicular to the substrate, each ring channel structure transistor in the 3D chain ferroelectric memory array structure is divided into two independent ring channel structure transistors, forming multiple isolation trenches perpendicular to the substrate. By filling each isolation trench with an insulating medium, the first optimized 3D chain-like ferroelectric memory array structure is obtained.

[0017] Preferably, the fabrication of the second optimized 3D chain-like ferroelectric memory array structure includes: Based on a preset pattern, the third dielectric layer in the second stacked structure is etched to divide the annular channel structure transistors connected in parallel to the substrate direction into pairs of connected structures to obtain the third stacked structure. In this configuration, two interconnected annular channel transistors are located on opposite sides of the same vertical bit line and share the same vertical bit line.

[0018] Compared with the prior art, the above-described technical solution of the present invention has the following advantages: The transistors in the 3D chain-like ferroelectric memory array structure described in this invention employ a ring-channel structure, which, compared to the traditional vertical-channel structure, offers stronger gate control capability, a more uniform electric field distribution, significantly suppresses short-channel effects, effectively widens the memory window, and improves device reliability and cycle durability. Simultaneously, the vertical bit lines serve as both source and drain electrodes, and the horizontal word lines serve as gates, resulting in a compact structure and smaller projected area. This significantly increases the memory density per unit area without increasing the difficulty of photolithography and etching processes. Furthermore, the ferroelectric capacitors are integrated in series, avoiding the charge-sharing problem of traditional parallel structures, leading to more stable storage states and higher read accuracy.

[0019] This invention is based on simple photolithography and uses a splitting method to divide the 3D chain-like ferroelectric memory array structure into two isolated memory sub-arrays along the horizontal direction to obtain a first optimized 3D chain-like ferroelectric memory array structure. The middle is filled with insulating material to achieve electrical isolation. The two isolated sub-arrays can operate independently, further improving the storage density of the 3D chain-like ferroelectric memory array structure.

[0020] This invention enables two adjacent vertical memory chains in a 3D chain-like ferroelectric memory array structure to share a single vertical bit line, resulting in a second optimized 3D chain-like ferroelectric memory array structure. A first memory chain and a second memory chain are respectively arranged on both sides of the shared vertical bit line. The two memory chains are symmetrically distributed along the shared vertical bit line and are respectively connected to their corresponding horizontal word lines, reducing the number of bit lines and further improving the integration density.

[0021] The fabrication method of the 3D chain-like ferroelectric memory array structure of this invention is highly compatible with existing NAND processes, requiring no additional special equipment, thus reducing fabrication costs and improving mass production feasibility. Furthermore, through multi-layer stacking and pattern optimization, this invention can easily achieve N×M×Q three-dimensional array expansion by adjusting the number of vertical bit lines N, the number of horizontal word lines M, and the number of sacrificial layer alternating deposition layers Q. This breaks through the density bottleneck of traditional 1T1C DRAM and is suitable for next-generation memory applications requiring high speed, high density, and high reliability. Attached Figure Description

[0022] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings, wherein: Figure 1 This is a schematic diagram of the ferroelectric memory circuit structure; Figure 1 (a) is a diagram of the 1T1C current sensing storage structure. Figure 1 (b) is a diagram of a 1TnC current sensing storage structure. Figure 1 (c) is a diagram of a 1T1C charge sensing and storage structure. Figure 1 (d) is a diagram of a 1TnC charge sensing storage structure; Figure 2 This is a schematic diagram of the circuit structure of a chain-type ferroelectric storage system; Figure 3 This is a schematic diagram of an existing chain memory array structure; Figure 4 This is a structural diagram of the 3D chain ferroelectric memory array structure provided by the present invention. Figure 5 This is a structural diagram of the first optimized 3D chain ferroelectric memory array structure. Figure 6 This is a structural diagram of the second optimized 3D chain ferroelectric memory array structure. Figure 7 This is a circuit diagram of the chain ferroelectric memory with a 3D chain ferroelectric memory array structure of the present invention; Figure 7 (a) is a circuit diagram showing the bit lines set at the top of the 3D chain ferroelectric memory array structure; Figure 7 (b) is a circuit diagram showing the bit lines set at the bottom of the 3D chain ferroelectric memory array structure; Figure 8 This is a characteristic curve of the ferroelectric capacitor in the 3D chain-like ferroelectric memory array structure provided by the present invention. Figure 9 This is a flowchart of the fabrication method for a 3D chain-like ferroelectric memory array structure; Figure 9 (a) is a schematic diagram of the first stacked structure; Figure 9 (b) is a schematic diagram of the structure after the through-hole is filled with the third dielectric layer and then etched back; Figure 9 (c) is a schematic diagram of the structure forming the cavity; Figure 9 (d) is a schematic diagram of the second stacked structure; Figure 9 (e) is a schematic diagram of the third stacked structure; Figure 9 (f) is a schematic diagram of the structure with multiple grooves obtained by etching the third stacked structure; Figure 9 (g) is a schematic diagram of the structure after depositing drain source electrode material in each groove; Figure 9 (h) is a schematic diagram of the fourth layered structure; Figure 9 (i) is a schematic diagram of a structure that forms a patterned gap based on a fourth stacked structure; Figure 9 (j) is a schematic diagram of the structure after the exposed conductive channel layer; Figure 9 (k) is a schematic diagram of the structure of the deposited insulating dielectric material; Figure 9 (l) is a schematic diagram of the 3D chain-like ferroelectric memory array structure that forms the ferroelectric capacitor layer; Figure 10 This is a flowchart of the fabrication process for the second optimized 3D chain-like ferroelectric memory array structure; Figure 10 (a) is a schematic diagram of the second stacked structure; Figure 10 (b) is a schematic diagram of the third stacked structure; Figure 10 (c) is a schematic diagram of vertical bitline isolation; Figure 10 (d) is a schematic diagram of the second optimized 3D chain ferroelectric memory array structure; In the specification of the 3D chain ferroelectric memory array structure, the following reference numerals are used: 101, vertical bit line; 102, channel material layer; 103, gate oxide dielectric layer; 104, horizontal word line; 105, insulating dielectric layer; 106, ferroelectric capacitor layer; 107, third dielectric layer. The following are explanations of the reference numerals in the accompanying drawings of the specification regarding the fabrication method: 200, substrate; 201, first dielectric layer; 202, second dielectric layer; 203, third dielectric layer; 204, cavity; 205, channel material layer; 206, gate oxide dielectric layer; 207, metal gate; 208, drain / source electrode material; 209, patterned gap; 210, conductive channel layer; 211, insulating dielectric material; 212, ferroelectric capacitor layer. Detailed Implementation

[0023] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0024] Reference Figure 4 As shown, the structural diagram of the 3D chain-like ferroelectric memory array structure of the present invention specifically includes: Substrate; Multiple vertical bit lines 101, perpendicular to the substrate, are arranged in an array on one side surface of the substrate; Multiple horizontal character lines 104 are arranged in an array above one side surface of the substrate, parallel to the substrate. The multiple vertical bit lines and the multiple horizontal word lines are arranged in an intersecting pattern, forming a memory cell at each intersection position; each memory cell is a channel ring transistor; the source and drain of the channel ring transistor are connected in series on the vertical bit lines, and the gate is connected to the horizontal word lines. An insulating dielectric layer 105 is filled between adjacent vertical bit lines; Ferroelectric capacitor layer 106 is disposed between the channel and gate of the ring-channel transistor and is combined with the ring-channel transistor to form a 1T1C memory cell. In this structure, multiple memory cells on a vertical bit line are connected in series along the vertical bit line direction to form a vertical memory chain. Multiple vertical memory chains are arranged in an array along the horizontal direction to form a 3D chain-like ferroelectric memory array structure.

[0025] Specifically, the annular channel transistor, with the vertical bit line surrounding it as the source and drain, and the horizontal word line surrounding it as the gate, further includes: A channel material layer 102 is disposed around the horizontal alignment line; The gate oxide dielectric layer 103 is disposed on the outside of the channel material layer.

[0026] Specifically, in this embodiment, the vertical bit line 101 (BL) of the 3D chain ferroelectric memory array structure also serves as the source and drain electrodes of the transistor, and is a vertical structure; the horizontal word line 104 (WL) of the 3D chain ferroelectric memory array structure also serves as the gate of the transistor, and is a horizontal structure; the transistor is a ring channel structure. The ring channel structure transistor of this embodiment has stronger gate control capability and more uniform electric field distribution, which can reduce the short channel effect, and the projected area is smaller than that of the existing structure, which can further improve the storage density without changing the difficulty of photolithography and etching.

[0027] In this embodiment, the vertical bit line 101, serving as the source / drain electrode, can be made of single-element metals such as titanium, platinum, gold, copper, aluminum, nickel, or shale; mixed metals such as platinum, nickel-gold, nickel-aluminum, or titanium-gold; compound conductive materials such as titanium nitride, polycrystalline silicon, or heavily doped polycrystalline silicon; or a stacked combination of the aforementioned materials. The thickness of the vertical bit line is at the nanometer or micrometer level, preferably 5µm-10µm.

[0028] In this embodiment, the thickness of the conductive channel layer 102 is typically at the nanometer level, preferably 3nm-20nm. The material of the conductive channel layer is an oxide semiconductor material such as indium gallium zinc oxide a-IGZO, indium gallium oxide IGO, indium zinc oxide IZO, indium aluminum oxide IAO, indium aluminum zinc oxide IAZO, indium tin oxide ITO, indium tin gallium oxide ITZO, or two-dimensional materials such as carbon nanotubes, graphene, molybdenum disulfide, and black phosphorus, or group III-V materials such as gallium nitride and aluminum nitride, or semiconductor thin film materials such as silicon nanowires, germanium nanowires, amorphous silicon, and polycrystalline silicon, or a stacked material of the aforementioned materials.

[0029] In this embodiment, the thickness of the gate oxide dielectric layer 103 is typically at the nanometer level, preferably 2nm-20nm; the material of the gate oxide dielectric layer 103 is an insulating dielectric, such as silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, or quartz.

[0030] In this embodiment, the thickness of the insulating dielectric layer 105 is typically at the nanometer level, preferably 2nm-20nm; the material of the insulating dielectric layer is silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, or quartz.

[0031] In this embodiment, the thickness of the ferroelectric capacitor layer 106 is typically at the nanometer level, preferably 2nm-20nm; the ferroelectric capacitor layer is a thin film with ferroelectric properties, and its material is zirconium oxide, hafnium dioxide, aluminum-doped hafnium dioxide, silicon-doped hafnium dioxide, zirconium-doped hafnium dioxide, lanthanum-doped hafnium dioxide, or yttrium-doped hafnium dioxide.

[0032] Reference Figure 5 The diagram shows the structure of the first optimized 3D chain ferroelectric memory array structure of the present invention. In this embodiment, the first optimized 3D chain ferroelectric memory array structure is obtained by dividing each memory cell in the 3D chain ferroelectric memory array structure into two mutually isolated memory cells along a direction perpendicular to the substrate.

[0033] This embodiment utilizes simple photolithography to divide the 3D chain-like ferroelectric memory array structure into two horizontally isolated memory subarrays, obtaining a first optimized 3D chain-like ferroelectric memory array structure. Electrical isolation is achieved by filling the space between the subarrays with insulating material. The two subarrays can operate independently, further increasing the storage density of the 3D chain-like ferroelectric memory array structure.

[0034] Reference Figure 6 The diagram shows the structure of the second optimized 3D chain ferroelectric memory array structure of the present invention. In this embodiment, two adjacent vertical memory chains in the 3D chain ferroelectric memory array structure share a vertical bit line to obtain the second optimized 3D chain ferroelectric memory array structure.

[0035] In the second optimized 3D chain-like ferroelectric memory array structure, based on the grooves formed by etching the first dielectric layer, vertical bit lines are formed by depositing metal and etching back. These bit lines are directly connected to the source and drain electrodes of the memory cells, penetrating the stacked structure perpendicular to the substrate, forming a vertical conductive path for the memory chain, and realizing the electrical interconnection of cells in the same row. Specifically, the vertical bit line 101, a vertical conductive pillar made of metal material, also serves as the source / drain electrode of the transistor, penetrating the stacked structure vertically to realize the electrical interconnection of cells in the same row. The channel material layer 102, the gate oxide dielectric layer 103, and the insulating dielectric layer 105 form a transistor with a ring-shaped channel structure surrounding the vertical bit line, exhibiting strong gate control capability and effectively suppressing short-channel effects. The horizontal word line 104 is a horizontally oriented metal gate extending parallel to the substrate, realizing the gate interconnection of cells in the same row. The ferroelectric capacitor layer 106 is a ferroelectric material layer connected in series with the transistor, used to realize charge storage and non-volatile storage functions. The third dielectric layer 107 provides structural support for the device.

[0036] Specifically, a first storage chain and a second storage chain are respectively set on both sides of the shared vertical bit line. The two storage chains are symmetrically distributed along the shared vertical bit line and are respectively connected to their corresponding horizontal word lines. The second optimized 3D chain-like ferroelectric memory array structure reduces the number of bit lines and further improves the integration.

[0037] Reference Figure 7 The diagram shown is a circuit structure diagram of the chain ferroelectric memory of the 3D chain ferroelectric memory array structure of the present invention. Figure 7 (a) is a circuit diagram showing the bit lines set at the top of the 3D chain ferroelectric memory array structure; Figure 7 (b) is a circuit diagram showing the bit line positioned at the bottom of the 3D chain ferroelectric memory array structure. Specifically, the select transistor can be located above or below the 3D chain ferroelectric memory array, and can be a planar or vertical structure. In this embodiment, the vertical bit line BL is a conductive structure that vertically penetrates the array. It can be located at the top of the memory array and connected to the select transistor, or at the bottom of the array and connected to the select transistor; PL is a horizontal common electrode, which can be located at the top of the array and connected to a unified planar electrode, or at the bottom of the array and connected to a unified planar electrode; BL and PL can be independently configured at the top or bottom of the array, providing flexible layout and facilitating interconnection with peripheral circuits. Its write and read methods are the same as those of traditional chain ferroelectric memories.

[0038] Reference Figure 8The figure shows the characteristic curves of the ferroelectric capacitors in the 3D chain-like ferroelectric memory array structure provided by this invention. The horizontal axis represents the applied voltage V, and the vertical axis represents the polarization intensity P. 0 and 1 correspond to two different storage states, respectively. Chain-like ferroelectric memory has advantages such as high speed, large window size, high storage density, and good cycle durability. This invention adopts a chain-like series structure, where multiple ferroelectric capacitors are connected in series along the vertical bit line, rather than in parallel. This topology effectively avoids the charge sharing problem common in parallel ferroelectric memory structures, ensuring that the charge state of each memory cell is independently controllable, thus improving storage reliability and read / write consistency.

[0039] Based on the above embodiments, the specific fabrication process of the 3D chain-like ferroelectric memory array structure in this embodiment includes: A substrate 200 is provided, and a sacrificial structure is deposited on one side surface of the substrate to form a first stacked structure; the sacrificial structure includes a first dielectric layer 201 and a second dielectric layer 202 deposited alternately in a predetermined period from the direction near the substrate to the direction away from the substrate, as well as a top layer of first dielectric layer 201. The first stacked structure is etched to form multiple through holes that penetrate the sacrificial structure along a direction perpendicular to the substrate and are arranged in an array. The via is filled and etched back using the third dielectric layer 203; The second dielectric layer is etched to form a plurality of cavities 204 parallel to the substrate based on the remaining first and third dielectric layers; In each cavity, a channel material layer 205, a gate oxide dielectric layer 206, and a metal gate 207 are deposited sequentially from near the outer surface of the cavity to far away from the outer surface of the cavity to form a ring channel structure transistor and obtain a second stacked structure. Based on a preset pattern, the third dielectric layer in the second stacked structure is etched to separate the annular channel structure transistors connected in the direction parallel to the substrate, forming a segmented structure and obtaining the third stacked structure. The first dielectric layer in the third stacked structure is etched to obtain multiple grooves; drain source electrode material 208 is deposited in each groove and then etched back. Etching the first dielectric layer 201, the second dielectric layer 202 and the third dielectric layer 203 forms a fourth stacked structure; A second dielectric layer 202 is deposited on the outer surface of the fourth stacked structure and patterned etching is performed to form patterned gaps 209; the patterned gaps are multiple gaps perpendicular to the substrate and penetrating the sacrificial structure. After etching the first dielectric layer to expose the conductive channel layer 210, an insulating dielectric material 211 is deposited to fill the patterned gaps, and the second dielectric layer 202 is removed. Ferroelectric capacitor material is deposited and etched back to form ferroelectric capacitor layer 212, thereby obtaining a 3D chain-like ferroelectric memory array structure.

[0040] Reference Figure 9 The diagram shown is a flowchart of the fabrication method for a 3D chain-like ferroelectric memory array structure. Figure 9 (a) is a schematic diagram of the first stacked structure; Figure 9 (b) is a schematic diagram of the structure after the through-hole is filled with the third dielectric layer and then etched back; Figure 9 (c) is a schematic diagram of the structure forming the cavity; Figure 9 (d) is a schematic diagram of the second stacked structure; Figure 9 (e) is a schematic diagram of the third stacked structure; Figure 9 (f) is a schematic diagram of the structure with multiple grooves obtained by etching the third stacked structure; Figure 9 (g) is a schematic diagram of the structure after depositing drain source electrode material in each groove; Figure 9 (h) is a schematic diagram of the fourth layered structure; Figure 9 (i) is a schematic diagram of a structure that forms a patterned gap based on a fourth stacked structure; Figure 9 (j) is a schematic diagram of the structure after the exposed conductive channel layer; Figure 9 (k) is a schematic diagram of the structure of the deposited insulating dielectric material; Figure 9 (l) is a schematic diagram of the 3D chain-like ferroelectric memory array structure that forms the ferroelectric capacitor layer.

[0041] Specifically, in fabricating a 3D chain-like ferroelectric memory array structure, after alternately depositing a first dielectric layer 201 and a second dielectric layer 202 on a substrate 200 to form a multi-layer stacked dielectric structure, a first opening vertically penetrating the dielectric structure is formed by photolithography and etching. A third dielectric layer 203 is then filled and etched to form vertically distributed conductive pillars. The second dielectric layer 202 is wet-etched through the first opening. Based on the etching selectivity ratio of the first dielectric layer 201 to the third dielectric layer 203, the second dielectric layer 202 is removed, forming a horizontal cavity 204 parallel to the substrate. A channel layer 205, a gate dielectric layer 206, and a metal gate 207 are sequentially deposited within the cavity to form a ring-channel transistor structure surrounding a vertical bit line, with the metal gate constituting a horizontal word line. The third dielectric layer 203 is then photolithographically etched to form a second opening. A second opening with a pre-defined pattern is formed on the third dielectric layer 203, which will then be used for subsequent... The process involves: providing a channel for the fabrication of the trench; wet etching of the first dielectric layer 201 through the second opening to form a trench; depositing source / drain electrode material 208 within the trench and etching it back to form a source / drain electrode structure connected to the vertical bit lines; etching dielectric layers 201, 202, and 203 to divide the stack into multiple independent vertical memory chains, forming basic array units; depositing and patterning the second dielectric layer 202 on the outer surface of the divided structure to form vertical trenches; etching the first dielectric layer 201 and the conductive channel layer 210 to define a preset channel pattern; depositing an insulating dielectric to fill the patterned gaps, and then removing the patterned second dielectric layer 202; depositing and etching back ferroelectric capacitor material to form a ferroelectric capacitor layer 212, ultimately obtaining a 3D chain-like ferroelectric memory array.

[0042] Specifically, the first dielectric layer and the second dielectric layer are insulating dielectrics with different etching selectivity ratios, and the third dielectric layer is a conductive material.

[0043] Based on the above embodiments, in this embodiment of the invention, the fabrication of the first optimized 3D chain-like ferroelectric memory array structure includes: An etching region is pre-etched on the surface of the 3D chain-like ferroelectric memory array structure on the side away from the substrate; Based on the etched area, along the direction perpendicular to the substrate, each ring channel structure transistor in the 3D chain ferroelectric memory array structure is divided into two independent ring channel structure transistors, forming multiple isolation trenches perpendicular to the substrate. By filling each isolation trench with an insulating medium, the first optimized 3D chain-like ferroelectric memory array structure is obtained.

[0044] In this embodiment, the storage array is divided into at least two mutually isolated storage sub-arrays along the vertical or horizontal direction by photolithography and etching processes to further improve storage density.

[0045] Based on the above embodiments, in this embodiment of the invention, the fabrication of the second optimized 3D chain-like ferroelectric memory array structure includes: Based on a preset pattern, the third dielectric layer in the second stacked structure is etched to divide the annular channel structure transistors connected in parallel to the substrate direction into pairs of connected structures to obtain the third stacked structure. In this configuration, two interconnected annular channel transistors are located on opposite sides of the same vertical bit line and share the same vertical bit line.

[0046] Reference Figure 10 The diagram shown is a flowchart of the fabrication process for the second optimized 3D chain-like ferroelectric memory array structure. Figure 10 (a) is a schematic diagram of the second stacked structure; Figure 10 (b) is a schematic diagram of the third stacked structure; Figure 10 (c) is a schematic diagram of vertical bitline isolation; Figure 10 (d) is a schematic diagram of the second optimized 3D chain-like ferroelectric memory array structure. In this embodiment, the first dielectric layer is wet-etched through a second opening to form a groove structure with an array arrangement in the first dielectric layer, reserving space for the subsequent fabrication of bit lines and electrodes. Bit line BL metal material is deposited in the groove, and excess metal is removed by a back-etching process to form a vertical bit line structure corresponding to the vertical memory chain, completing the fabrication and interconnection of source and drain electrodes. BL isolation is performed using the same fabrication method as for the 3D chain-like ferroelectric memory array structure, and the bit lines are patterned and filled with insulating dielectric to achieve electrical isolation between adjacent bit lines, avoid crosstalk, and improve the stability of the array operation. Ferroelectric capacitor material is deposited on the isolated memory cell structure and back-etched to form a ferroelectric capacitor layer connected in series with the transistor, completing the charge storage function of the memory cell and finally obtaining the complete second optimized 3D chain-like ferroelectric memory array structure.

[0047] Based on the above embodiments, the multiple vertical storage chains in this embodiment include N first vertical storage chains arranged along a vertical array and M second vertical storage chains arranged along a second direction array, to form an array structure of N rows × M columns × Q layers. By adjusting the number of storage chains arranged in the array, the storage array of different dimensions can be adjusted.

[0048] This invention can directly fabricate a 3D chain-like ferroelectric memory array structure using a process similar to NAND, which is low-cost and can eliminate the dependence on high-precision photolithography, thus achieving high-density storage; and is expected to break through the bottleneck of traditional 1T1CDRAM and further improve storage density.

[0049] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0050] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0051] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0052] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0053] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A 3D chain-like ferroelectric memory array structure, characterized in that, include: Substrate; Multiple vertical bit lines, perpendicular to the substrate, are arranged in an array on one side surface of the substrate; Multiple horizontal character lines are arranged in an array above one side surface of the substrate, parallel to the substrate. The multiple vertical bit lines and the multiple horizontal word lines are arranged in an intersecting pattern, forming a memory cell at each intersection position; each memory cell is a channel ring transistor; the source and drain of the channel ring transistor are connected in series on the vertical bit lines, and the gate is connected to the horizontal word lines. An insulating dielectric layer fills the spaces between adjacent vertical bit lines; A ferroelectric capacitor layer is disposed between the channel and gate of a ring-channel transistor, and is combined with the ring-channel transistor to form a 1T1C memory cell. In this structure, multiple memory cells on a vertical bit line are connected in series along the vertical bit line direction to form a vertical memory chain. Multiple vertical memory chains are arranged in an array along the horizontal direction to form a 3D chain-like ferroelectric memory array structure.

2. The 3D chain-like ferroelectric memory array structure according to claim 1, characterized in that, The annular channel transistor, with the vertical bit line surrounding it as the source and drain, and the horizontal word line surrounding it as the gate, further includes: A channel material layer is disposed around the horizontal alignment line; A gate oxide dielectric layer is disposed on the outside of the channel material layer.

3. The 3D chain-like ferroelectric memory array structure according to claim 2, characterized in that, The insulating dielectric layer and the gate oxide dielectric layer are insulating dielectrics, and their materials are silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, or quartz.

4. The 3D chain-like ferroelectric memory array structure according to claim 1, characterized in that, Each memory cell in the 3D chain ferroelectric memory array structure is divided into two isolated memory cells along a direction perpendicular to the substrate to obtain the first optimized 3D chain ferroelectric memory array structure.

5. The 3D chain-like ferroelectric memory array structure according to claim 1, characterized in that, By having two adjacent vertical memory chains in a 3D chain ferroelectric memory array structure share a single vertical bit line, a second optimized 3D chain ferroelectric memory array structure is obtained.

6. The 3D chain-like ferroelectric memory array structure according to claim 1, characterized in that, The vertical bit line and the horizontal bit line are a stacked combination of one or more of the following: single metal material, mixed metal material, or compound conductive material. The elemental metal material is titanium, platinum, gold, copper, aluminum, nickel, or shale; the mixed metal material is platinum, nickel-gold, nickel-aluminum, or titanium-gold; the compound conductive material is titanium nitride, polycrystalline silicon, or heavily doped polycrystalline silicon.

7. A method for fabricating a 3D chain-like ferroelectric memory array structure as described in any one of claims 1 to 6, characterized in that, include: A substrate is provided, and a sacrificial structure is deposited on one side surface of the substrate to form a first stacked structure; The sacrificial structure, from the direction near the substrate to the direction away from the substrate, includes a first dielectric layer and a second dielectric layer deposited alternately in a predetermined period, as well as a top layer of the first dielectric layer; The first stacked structure is etched to form multiple through holes that penetrate the sacrificial structure along a direction perpendicular to the substrate and are arranged in an array. The via is filled with a third dielectric layer and then traced back. The second dielectric layer is etched to form multiple cavities parallel to the substrate based on the remaining first and third dielectric layers; In each cavity, a channel material layer, a gate oxide dielectric layer, and a metal gate are deposited sequentially from the outer surface of the cavity to the outer surface of the cavity to form a ring channel structure transistor and obtain a second stacked structure. Based on a preset pattern, the third dielectric layer in the second stacked structure is etched to separate the annular channel structure transistors connected in the direction parallel to the substrate, forming a segmented structure and obtaining the third stacked structure. The first dielectric layer in the third stacked structure is etched to obtain multiple grooves; Deposit drain electrode material in each groove and etch it back; Etch the first dielectric layer, the second dielectric layer and the third dielectric layer to form a fourth stacked structure; A second dielectric layer is deposited on the outer surface of the fourth stacked structure and patterned etching is performed to form patterned gaps; the patterned gaps are multiple gaps perpendicular to the substrate and penetrating the sacrificial structure; After etching the first dielectric layer to expose the conductive channel layer, an insulating dielectric material is deposited to fill the patterned gaps, and the second dielectric layer is removed. Ferroelectric capacitor material is deposited and etched back to form a ferroelectric capacitor layer, thereby obtaining a 3D chain-like ferroelectric memory array structure.

8. The method for fabricating the 3D chain-like ferroelectric memory array structure according to claim 7, characterized in that, The first dielectric layer and the second dielectric layer are insulating dielectrics with different etching selectivity ratios, and the third dielectric layer is a conductive material.

9. The method for fabricating the 3D chain-like ferroelectric memory array structure according to claim 7, characterized in that, The fabrication of the first optimized 3D chain-like ferroelectric memory array structure includes: An etching region is pre-etched on the surface of the 3D chain-like ferroelectric memory array structure on the side away from the substrate; Based on the etched area, along the direction perpendicular to the substrate, each ring channel structure transistor in the 3D chain ferroelectric memory array structure is divided into two independent ring channel structure transistors, forming multiple isolation trenches perpendicular to the substrate. By filling each isolation trench with an insulating medium, the first optimized 3D chain-like ferroelectric memory array structure is obtained.

10. The method for fabricating the 3D chain-like ferroelectric memory array structure according to claim 7, characterized in that, The fabrication of the second optimized 3D chain-like ferroelectric memory array structure includes: Based on a preset pattern, the third dielectric layer in the second stacked structure is etched to divide the annular channel structure transistors connected in parallel to the substrate direction into pairs of connected structures to obtain the third stacked structure. In this configuration, two interconnected annular channel transistors are located on opposite sides of the same vertical bit line and share the same vertical bit line.

Images