Micro-led chip preparation method and micro-led chip

Abstract

The application provides a Micro-LED chip preparation method and a Micro-LED chip, and relates to the technical field of semiconductors.The method comprises the following steps: providing a substrate; sequentially forming an n-type semiconductor layer, an active light-emitting layer, a p-type semiconductor layer and a transparent conductive layer on the substrate; patterning the transparent conductive layer to define a plurality of mutually isolated pixel regions; forming a patterned mask layer on the surface of the patterned transparent conductive layer; performing ion implantation by using the mask layer; and penetrating the transparent conductive layer, the p-type semiconductor layer and the active light-emitting layer in the region not covered by the mask layer by the implanted ions to form an electrically isolated region.The application solves the problem that the traditional dry etching method in the prior art is prone to causing sidewall damage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a Micro-LED chip and a Micro-LED chip. Background Technology

[0002] Micro-LEDs, with their superior characteristics such as high brightness, high contrast, fast response, and long lifespan, are considered the core of next-generation display technology. As chip sizes shrink to the micrometer scale, the ratio of sidewall surface area to volume increases dramatically, making sidewall damage during pixel mesa definition (e.g., inductively coupled plasma reactive ion etching, ICP-RIE) a critical issue. This sidewall damage introduces numerous surface states and defects, becoming non-radiative recombination centers, leading to severe carrier leakage, decreased luminous efficiency, inter-device optical crosstalk, and reliability degradation, severely hindering the development of high-performance, small-size Micro-LEDs.

[0003] Currently, methods such as sidewall passivation (e.g., atomic layer deposition of aluminum oxide), wet chemical treatment, or optimized etching processes are commonly used to mitigate sidewall damage. However, these methods are all "post-treatment" of existing damage and cannot fundamentally eliminate the physical damage to the crystal structure caused by the etching process. Furthermore, these methods are complex and have limited effectiveness. Summary of the Invention

[0004] Based on this, the purpose of this invention is to provide a multi-quantum well layer and its preparation method, an epitaxial wafer and a dual-color LED chip, which aims to solve the problem that traditional dry etching in the prior art is prone to sidewall damage.

[0005] The embodiments of the present invention are implemented as follows: On one hand, embodiments of the present invention propose a method for fabricating a Micro-LED chip, the method comprising: Provide a substrate; An n-type semiconductor layer, an active light-emitting layer, a p-type semiconductor layer, and a transparent conductive layer are sequentially formed on the substrate. The transparent conductive layer is patterned to define multiple isolated pixel regions, and a patterned mask layer is formed on the surface of the patterned transparent conductive layer. Ion implantation is performed, and the implanted ions penetrate the transparent conductive layer, p-type semiconductor layer, and active light-emitting layer in the area not covered by the mask layer to form an electrical isolation region.

[0006] Furthermore, in the above-mentioned Micro-LED chip fabrication method, the ion source used for ion implantation is selected from inert gas ions, arsenic ions, fluorine ions, or nitrogen ions.

[0007] Furthermore, in the above-mentioned Micro-LED chip fabrication method, a multi-energy gradient ion implantation process is adopted, including at least two ion implantations with different implantation energies, and the ion implantation energies decrease sequentially from high to low.

[0008] Furthermore, in the aforementioned Micro-LED chip fabrication method, the total ion implantation dose is 4 × 10⁻⁶. 14 cm 2 Up to 8×10 14 cm 2 .

[0009] Furthermore, in the above-mentioned Micro-LED chip fabrication method, the ion implantation energy is 10keV~40keV.

[0010] Furthermore, in the above-mentioned Micro-LED chip fabrication method, rapid thermal annealing is performed after ion implantation in an inert gas or nitrogen atmosphere.

[0011] Furthermore, in the above-mentioned Micro-LED chip fabrication method, the thermal annealing temperature is 500℃~700℃, and the time is 60S~180S.

[0012] Furthermore, in the above-mentioned Micro-LED chip fabrication method, after the step of ion implantation using the mask layer, the method further includes: A portion of the area is etched to expose the n-type semiconductor layer, forming an n-type contact window, and an n-type electrode electrically connected to the n-type semiconductor layer is formed in the n-type contact window.

[0013] Furthermore, in the above-mentioned Micro-LED chip fabrication method, after the step of forming an n-type electrode electrically connected to the n-type semiconductor layer in the n-type contact window, the method further includes: A common electrode layer is formed that covers the pixel area and is electrically connected to the transparent conductive layer of each pixel. A p-type electrode electrically connected to the common electrode layer is formed on the common electrode layer.

[0014] Another object of the present invention is to provide a Micro-LED chip prepared by the above-described Micro-LED chip preparation method.

[0015] Compared with the prior art, the embodiments of the present invention have at least the following beneficial effects: This invention replaces traditional dry etching with ion implantation to form an electrically isolated region to define the pixel mesa. This eliminates the need for physical etching of the semiconductor layer to remove material, fundamentally avoiding the physical bombardment damage to the device sidewalls caused by dry etching. It also eliminates the numerous surface states and defects introduced by etching, thereby reducing non-radiative recombination centers, carrier leakage, and decreased luminous efficiency. Simultaneously, it suppresses optical crosstalk and reliability degradation between devices, providing a feasible path for the development of high-performance, small-size Micro-LEDs. Since ion implantation only penetrates the transparent conductive layer, p-type semiconductor layer, and active light-emitting layer in areas not covered by the mask layer to form the electrically isolated region, it is an electrical modification of the semiconductor layer rather than a physically destructive process. This eliminates the need for post-processing repair of existing sidewall damage, simplifying the sidewall treatment process. It solves the problems of existing methods such as sidewall passivation, wet chemical treatment, and optimized etching processes, which cannot fundamentally eliminate physical damage to the crystal structure, are complex, and have limited repair effects. This finally solves the problem that traditional dry etching is prone to causing severe sidewall damage when fabricating Micro-LED chips, which leads to decreased luminous efficiency, optical crosstalk, reliability degradation, and the difficulty in fundamentally repairing sidewall damage. Attached Figure Description

[0016] Figure 1 This is a schematic flowchart of a Micro-LED chip fabrication method according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a Micro-LED chip according to an embodiment of the present invention; The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0017] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0018] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0020] This invention uses ion implantation to form an electrical isolation region, replacing the traditional dry etching method to define the pixel mesa. This avoids the physical damage to the sidewalls caused by dry etching from the process source, fundamentally eliminating sidewall defects and non-radiative recombination centers. At the same time, it effectively achieves electrical isolation between pixels, improving the electrical performance, optical efficiency, and reliability of Micro-LED chips. It can also adapt to the needs of chip miniaturization. Furthermore, ion implantation is a standard semiconductor process that is easy to integrate into existing Micro-LED manufacturing processes and is suitable for large-scale production.

[0021] Please see Figure 1 The image shows a method for fabricating a Micro-LED chip according to an embodiment of the present invention. The method includes: Step S10: An n-type semiconductor layer, an active light-emitting layer, a p-type semiconductor layer, and a transparent conductive layer are sequentially formed on the substrate.

[0022] The substrate is the basic support structure of the Micro-LED chip. Suitable substrate materials for semiconductor epitaxial growth include sapphire, silicon, and silicon carbide. Sapphire is a commonly used substrate type in the preparation of gallium nitride-based Micro-LEDs due to its advantages in lattice matching, chemical stability, and light transmittance with gallium nitride-based semiconductor materials, providing a stable growth substrate for the subsequent growth of semiconductor layers.

[0023] Step S12: An n-type semiconductor layer, an active light-emitting layer, a p-type semiconductor layer, and a transparent conductive layer are sequentially formed on the substrate.

[0024] An n-type semiconductor layer, an active light-emitting layer, a p-type semiconductor layer, and a transparent conductive layer are sequentially formed on a substrate. This step is the epitaxial structure and conductive layer fabrication stage of the chip. Each layer is formed sequentially using epitaxial growth and thin film deposition, and good interface bonding and lattice matching are formed between the layers. The n-type and p-type semiconductor layers serve as carrier transport layers, responsible for the transport of electrons and holes, respectively. Gallium nitride-based semiconductor materials are commonly used, and n-type and p-type modifications can be achieved by doping with impurities such as silicon and magnesium. The active light-emitting layer is the core light-emitting region of the Micro-LED chip, and usually adopts a multi-quantum well structure, such as indium gallium nitride / gallium nitride multi-quantum wells. Electrons and holes recombine in this region and release photons to achieve light emission. The transparent conductive layer covers the surface of the p-type semiconductor layer, which can achieve efficient transport of holes to the active light-emitting layer without blocking the light emitted by the active light-emitting layer, ensuring the light emission efficiency of the chip. Indium tin oxide is commonly used as the material, which has high light transmittance and good conductivity.

[0025] Step S12: The transparent conductive layer is patterned to define multiple isolated pixel regions, and a patterned mask layer is formed on the surface of the patterned transparent conductive layer.

[0026] The patterning process employs a semiconductor process combining photolithography and etching. The transparent conductive layer is etched according to a pre-defined pixel array pattern, dividing the continuous transparent conductive layer into multiple independent units. Each independent unit corresponds to a pixel region, achieving physical isolation of the transparent conductive layer in each pixel region and laying the foundation for subsequent electrical isolation between pixels. A patterned mask layer is then formed on the surface of the patterned transparent conductive layer. The mask layer is made of ion-blocking materials such as photoresist and prepared through a photolithography process involving coating, exposure, and development. Its pattern matches the pattern of the pixel region. The mask layer covers the surface of the transparent conductive layer in each pixel region, with the uncovered areas representing the gaps between pixels. This precisely defines the implantation area for subsequent ion implantation, preventing ion implantation from damaging the effective structure of the pixel region.

[0027] Step S13: Ion implantation is performed. The implanted ions penetrate the transparent conductive layer, p-type semiconductor layer and active light-emitting layer in the area not covered by the mask layer to form an electrical isolation region.

[0028] Ion implantation is a process that uses high-energy ion beams to bombard semiconductor materials. With the mask layer providing cover, the high-energy ions can only enter the uncovered gaps between pixels. The ions have enough energy to penetrate the transparent conductive layer, the p-type semiconductor layer, and the active light-emitting layer, creating lattice damage within the semiconductor material in these areas. This damages the material's crystal structure and electrical properties, causing these areas to lose their ability to transport and recombine carriers, thus forming an electrical isolation region and achieving electrical isolation between adjacent pixels. This step eliminates the need for physical etching to remove material from the semiconductor layer, completely avoiding the physical bombardment of the mesa sidewalls by plasma in traditional dry etching. It eliminates sidewall defects and non-radiative recombination centers at the source, solving problems such as carrier leakage, decreased luminous efficiency, and optical crosstalk caused by dry etching. Furthermore, the electrical isolation region formed by ion implantation provides stable isolation and can be adapted to pixel arrays of micrometer-scale or even smaller sizes.

[0029] For example, the ion source used for ion implantation is selected from inert gas ions, arsenic ions, fluorine ions, or nitrogen ions. Inert gas ions are monatomic ions with stable chemical properties. When bombarding semiconductor materials, they only form lattice damage through physical action and do not introduce heteroatoms that affect the chemical properties of the semiconductor material. Argon ions are commonly used inert gas ions. Arsenic ions, fluorine ions, and nitrogen ions are doped ions. While forming lattice damage to achieve electrical isolation, some ions can be doped into the semiconductor material to further modify the electrical properties of the material and improve the isolation effect. Among them, arsenic ions are commonly used n-type doping ions in gallium nitride-based semiconductor processes, while fluorine ions and nitrogen ions can form chemical bonds with gallium nitride-based materials to enhance the stability of lattice damage. In actual fabrication, a single ion source or a combination of ion sources can be selected for ion implantation according to the chip's material system, pixel size, and isolation requirements. By selecting a suitable ion source, stable lattice damage can be formed in the target area after ion implantation, achieving efficient electrical isolation. At the same time, different types of ion sources can be flexibly selected according to actual preparation needs, adapting to different semiconductor material systems and preparation processes. Moreover, the selected ion sources are all commonly used types in semiconductor processes, are easy to obtain, and are compatible with existing ion implantation equipment, reducing the difficulty of process implementation.

[0030] Furthermore, in some optional embodiments of the present invention, a multi-energy gradient ion implantation process is adopted, with the energy being implanted sequentially from high to low. This enables ions to achieve lattice damage at different depths in the semiconductor material, forming a gradient damage region in the vertical direction. This ensures effective isolation across the entire layer from the transparent conductive layer to the active light-emitting layer, avoiding the problem of insufficient shallow or deep isolation caused by single-energy ion implantation. This improves the isolation effect and uniformity of the electrical isolation region. At the same time, gradient energy implantation can reduce excessive damage to the material caused by a single high-energy ion implantation, balancing the isolation effect and the integrity of the material structure.

[0031] A multi-energy gradient ion implantation process is employed, involving at least two ion implantations with different energies, decreasing sequentially from high to low. This process involves multiple implantation operations, each using a different ion energy, with subsequent implantations using lower energies than the previous ones. High-energy ions penetrate deeper into the semiconductor material, primarily causing lattice damage in the deep layers of the active light-emitting layer and p-type semiconductor layer. Medium- and low-energy ions, on the other hand, cause lattice damage in the shallower layers of the semiconductor material, mainly covering the shallow p-type semiconductor layer and the transparent conductive layer. This gradient implantation ensures uniform and continuous lattice damage at different depths in the transparent conductive layer, p-type semiconductor layer, and active light-emitting layer, guaranteeing electrical isolation throughout the entire vertical structure and avoiding isolation blind spots. For example, three ion implantations can be performed, using energies of 40keV, 15keV, and 10keV sequentially, or four ion implantations can be performed, using energies of 40keV, 30keV, 20keV, and 10keV sequentially. The specific number of implantations can be adjusted based on the pixel size and semiconductor layer thickness. In practice, the total dose of ion implantation is 4 × 10⁻⁶. 14 cm 2 Up to 8×10 14 cm 2 Ion implantation dose refers to the number of ions implanted per unit area. The total dose is the sum of the implantation doses in multi-energy gradient ion implantation. Within this dose range, ions can form dense lattice damage in the inter-pixel gap region, disrupting the carrier transport path and achieving efficient electrical isolation; if the dose is below 4 × 10⁻⁶, the ion implantation dose will be less effective. 14 cm 2 The lattice damage formed by ions in the material is relatively sparse, which cannot completely block carrier transport, making it prone to inter-pixel leakage and optical crosstalk; if the dose is higher than 8×10 14 cm 2 Excessive ions can cause severe lattice distortion in semiconductor materials and may even diffuse into adjacent pixel regions, affecting carrier recombination and luminescence performance in those regions. In actual fabrication, the dose of each gradient implantation can be allocated within this range according to the type of ion source and the thickness of the semiconductor layer to ensure that the total dose meets the requirements.

[0032] In addition, in some optional embodiments of the present invention, a rapid thermal annealing process after ion implantation is added. The rapid thermal annealing process can moderately repair the lattice damage caused by ion implantation, reduce the lattice distortion at the edge of the pixel area, and improve the electrical performance and luminous efficiency of the chip. At the same time, annealing in an inert gas or nitrogen atmosphere can prevent the semiconductor material from being oxidized or chemically reacting with other gases at high temperatures, ensuring the chemical stability and structural integrity of the material. It can also rearrange the atoms in the lattice damage area and enhance the stability of the electrical isolation region.

[0033] In an inert gas or nitrogen atmosphere, rapid thermal annealing is performed after ion implantation. After ion implantation, the semiconductor material contains numerous lattice defects and atomic vacancies. Rapid thermal annealing uses high-temperature, short-duration heating to energize and migrate atoms within the material, repairing these lattice defects. Inert gas atmospheres such as argon and helium are chemically stable and do not react with the semiconductor material. A nitrogen atmosphere not only provides protection but also replenishes nitrogen atoms to the gallium nitride-based semiconductor material, repairing nitrogen vacancy defects generated during ion implantation. Rapid thermal annealing only moderately repairs lattice defects, preserving lattice damage in the inter-pixel gap region to ensure electrical isolation. It also repairs minor damage at the pixel edges, reducing non-radiative recombination centers and improving carrier recombination efficiency, thereby increasing the chip's luminous efficiency and reducing reverse leakage current.

[0034] For example, by controlling the temperature at 500℃~700℃ and the time at 60S~180S, the process parameters can achieve moderate repair of lattice defects, taking into account both electrical isolation effect and chip performance improvement. This avoids poor repair effect due to excessively low temperature and short time, or excessively high temperature and long time, which would lead to over-repair of lattice damage between pixels and loss of electrical isolation effect. At the same time, this parameter range is compatible with the thermal stability of gallium nitride-based semiconductor materials and will not cause thermal decomposition or interface separation of materials.

[0035] 500℃ is the temperature at which lattice atoms begin to migrate effectively. Above this temperature, lattice defects caused by ion implantation can be effectively repaired. 700℃ is the upper limit of the safe annealing temperature for gallium nitride-based semiconductor materials. Below this temperature, thermal decomposition or lattice relaxation can be avoided, ensuring the integrity of the epitaxial structure. 60s is the shortest time to achieve effective repair, capable of repairing minor defects at the edge of the pixel region. 180s is the longest time to avoid over-repair; exceeding this time will cause extensive repair of lattice damage between pixels, leading to a decrease in electrical isolation. In actual fabrication, the annealing temperature and time can be adjusted within this range according to the ion implantation dose and energy. For example, when the ion implantation dose is high, the annealing temperature can be appropriately increased or the annealing time extended to achieve sufficient defect repair.

[0036] Furthermore, after the ion implantation step using a mask layer, the process further includes: etching a portion of the area to expose the n-type semiconductor layer, forming an n-type contact window, and forming an n-type electrode electrically connected to the n-type semiconductor layer within the n-type contact window. The etching of the portion of the area employs a dry or wet etching semiconductor process. Following a pre-defined electrode pattern, the epitaxial structure on the surface of the electrical isolation region and part of the n-type semiconductor layer is etched, removing the p-type semiconductor layer and the active light-emitting layer in the target area until the underlying n-type semiconductor layer is exposed. The resulting exposed area is the n-type contact window. A dedicated mask is used during the etching process to protect the structure of the pixel area and the electrical isolation region from damage. The n-type electrode is prepared using thin-film deposition processes such as evaporation and sputtering, using metal materials with good conductivity such as gold, silver, titanium, and aluminum. The metal material forms a good ohmic contact with the n-type semiconductor layer at the n-type contact window, reducing contact resistance and ensuring efficient electron injection from the n-type electrode to the n-type semiconductor layer, providing sufficient electrons for carrier recombination in the active light-emitting layer. Following the step of forming an n-type electrode electrically connected to the n-type semiconductor layer through an n-type contact window, the process further includes: forming a common electrode layer covering the pixel region and electrically connected to the transparent conductive layer of each pixel; and forming a p-type electrode electrically connected to the common electrode layer on the common electrode layer. The common electrode layer is prepared using a transparent conductive material through a thin-film deposition process, with indium tin oxide (ITO) being a commonly used material. After deposition, it covers the surface of all pixel regions and forms a good electrical connection with the transparent conductive layer of each pixel region, achieving electrical interconnection of the p-type ends of each pixel region. The common electrode layer is transparent and does not block the light emitted by the active light-emitting layer, ensuring the chip's light extraction efficiency. The p-type electrode is prepared using processes such as evaporation and sputtering, selecting a metal material with good conductivity. It is prepared at a predetermined position on the common electrode layer, forming a good ohmic contact with the common electrode layer. Holes are injected from the p-type electrode, distributed through the common electrode layer to the transparent conductive layer of each pixel region, then transported to the p-type semiconductor layer, and finally enter the active light-emitting layer to recombine with electrons for light emission. Through the uniform distribution by the common electrode layer, the hole injection amount in each pixel region is ensured to be uniform, improving the light emission consistency of the pixel array.

[0037] On the other hand, please see Figure 2 This invention also proposes a Micro-LED chip, prepared by the aforementioned Micro-LED chip fabrication method. It includes: The substrate 100, and an n-type semiconductor layer 200, an active light-emitting layer 300, a p-type semiconductor layer 400, a transparent conductive layer 500, a common electrode layer 700, an n-type electrode 801, a p-type electrode 802, and an electrical isolation region 900 are sequentially deposited on the substrate.

[0038] In summary, the Micro-LED chip fabrication method and Micro-LED chip in the above embodiments of the present invention, by using ion implantation to form an electrically isolated region instead of traditional dry etching to define the pixel mesa, eliminates the need for physical etching of the semiconductor layer to remove material. This fundamentally avoids the physical bombardment damage to the device sidewalls caused by the dry etching process, eliminates a large number of surface states and defects introduced by etching, thereby reducing the problems of non-radiative recombination centers, carrier leakage, and decreased luminous efficiency. At the same time, it suppresses optical crosstalk and reliability degradation between devices, providing a feasible path for the development of high-performance, small-size Micro-LEDs. Since ion implantation only penetrates the transparent conductive layer, p-type semiconductor layer, and active light-emitting layer in areas not covered by the mask layer to form an electrically isolated region, it is an electrical modification of the semiconductor layer rather than a physically destructive process. It eliminates the need for post-processing repair of existing sidewall damage, simplifying the sidewall processing technology and solving the problems that existing methods such as sidewall passivation, wet chemical treatment, and optimized etching processes cannot fundamentally eliminate physical damage to the crystal structure, are complex, and have limited repair effects. This finally solves the problem that traditional dry etching is prone to causing severe sidewall damage when fabricating Micro-LED chips, which leads to decreased luminous efficiency, optical crosstalk, reliability degradation, and the difficulty in fundamentally repairing sidewall damage.

[0039] To facilitate understanding of the present invention, a more complete description will be given below with reference to relevant embodiments. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0040] Example 1 Embodiment 1 of the present invention provides a method for fabricating a Micro-LED chip, comprising: Provide a substrate; An n-type semiconductor layer, an active light-emitting layer, a p-type semiconductor layer, and a transparent conductive layer are sequentially formed on a substrate; A patterned transparent conductive layer is used to define multiple isolated pixel regions, and a patterned mask layer is formed on the surface of the patterned transparent conductive layer. Using Ar + As the ion source, after coating the photoresist and exposing and developing to form a mask, a three-step gradient ion implantation is performed: energy / dose of 40 keV / 4×10⁻⁶. 14 cm 2 15 keV / 2×10 14 cm 2 10 keV / 2×10 14 cm 2 Total dose 8×10 14 cm 2 ; Then anneal at 600°C for 90 seconds in a nitrogen atmosphere; A portion of the area is etched to expose the n-type semiconductor layer, forming an n-type contact window, and an n-type electrode electrically connected to the n-type semiconductor layer is formed in the n-type contact window; A common electrode layer is formed that covers the pixel area and is electrically connected to the transparent conductive layer of each pixel. A p-type electrode electrically connected to the common electrode layer is formed on the common electrode layer. The device fabrication was completed, with a chip pixel size of 10μm×10μm.

[0041] Example 2 Embodiment 2 of the present invention also proposes a method for fabricating a Micro-LED chip. The difference between the Micro-LED chip fabrication method in this embodiment and the Micro-LED chip fabrication method in Embodiment 1 is that: Using As + As the ion source, the implantation parameters are: 40 keV / 1×10 14 cm 2 30 keV / 1×10 14 cm 2 20 keV / 1×10 14 cm 2 10 keV / 1×10 14 cm 2 Total dose 4×10 14 cm 2 .

[0042] Comparative Example The present invention also proposes a method for fabricating a Micro-LED chip in a comparative example. The difference between the Micro-LED chip fabrication method in this comparative example and the Micro-LED chip fabrication method in Example 1 is as follows: The mesa was formed by etching using the traditional ICP-RIE dry etching method, followed by SiO2 deposition for sidewall passivation.

[0043] The chips prepared in the above embodiments and comparative examples were tested, and the results are shown in Table 1 below: Table 1

[0044] It should be noted that, in order to ensure the reliability of the verification results, the epitaxial wafers prepared according to Examples 1 to 6 and Comparative Example 1 of the present invention should be the same in all aspects except for the parameters mentioned above. For example, the preparation process and parameters of each layer of the epitaxial wafer should be kept consistent.

[0045] It is evident that the Micro-LEDs prepared using the ion implantation process of this invention are significantly superior to traditional dry etching processes in both electrical performance and optical efficiency.

[0046] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for fabricating a Micro-LED chip, characterized in that, The method includes: Provide a substrate; An n-type semiconductor layer, an active light-emitting layer, a p-type semiconductor layer, and a transparent conductive layer are sequentially formed on the substrate. The transparent conductive layer is patterned to define multiple isolated pixel regions, and a patterned mask layer is formed on the surface of the patterned transparent conductive layer. Ion implantation is performed, and the implanted ions penetrate the transparent conductive layer, p-type semiconductor layer, and active light-emitting layer in the area not covered by the mask layer to form an electrical isolation region.

2. The method for fabricating a Micro-LED chip according to claim 1, characterized in that, The ion source used for ion implantation is selected from inert gas ions, arsenic ions, fluorine ions, or nitrogen ions.

3. The method for fabricating a Micro-LED chip according to claim 2, characterized in that, The process employs a multi-energy gradient ion implantation technique, which includes at least two ion implantations with different energies, and the ion implantation energies decrease sequentially from high to low.

4. The method for fabricating a Micro-LED chip according to claim 3, characterized in that, The total dose of ion implantation is 4 × 10 14 cm 2 Up to 8×10 14 cm 2 .

5. The method for fabricating a Micro-LED chip according to claim 3, characterized in that, The ion implantation energy is 10keV~40keV.

6. The method for fabricating a Micro-LED chip according to claim 1, characterized in that, Rapid thermal annealing is performed after ion implantation in an inert gas or nitrogen atmosphere.

7. The method for fabricating a Micro-LED chip according to claim 6, characterized in that, The heat annealing temperature is 500℃~700℃, and the time is 60S~180S.

8. The method for fabricating a Micro-LED chip according to claim 6, characterized in that, Following the step of ion implantation using the mask layer, the method further includes: A portion of the area is etched to expose the n-type semiconductor layer, forming an n-type contact window, and an n-type electrode electrically connected to the n-type semiconductor layer is formed in the n-type contact window.

9. The method for fabricating a Micro-LED chip according to claim 8, characterized in that, The step of forming an n-type electrode electrically connected to the n-type semiconductor layer in the n-type contact window further includes: A common electrode layer is formed that covers the pixel area and is electrically connected to the transparent conductive layer of each pixel. A p-type electrode electrically connected to the common electrode layer is formed on the common electrode layer.

10. A Micro-LED chip, characterized in that, The chip is prepared using the Micro-LED chip preparation method according to any one of claims 1 to 9.

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