Unreliable, out-of-order data transfers over memory interconnect architectures
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NVIDIA CORP
- Filing Date
- 2026-01-16
- Publication Date
- 2026-07-24
AI Technical Summary
In large-scale memory interconnect architectures, unreliable memory STORE commands are prone to loss, leading to network failures and performance degradation, and existing technologies struggle to achieve adaptive routing and end-to-end reliability.
By employing self-synchronization technology and application-layer retransmission mechanisms, the sequentiality and reliability of data at the receiver are ensured by including metadata (such as flags or counters) in the communication write command, and adaptive routing and end-to-end reliability are implemented at the application layer.
It improves the resilience of the memory interconnect architecture to failures, reduces traffic and power consumption, ensures the reliability and order of data transmission, and enhances the fault tolerance of the system.
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