Unreliable, out-of-order data transfers over memory interconnect architectures

CN122450698APending Publication Date: 2026-07-24NVIDIA CORP
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
NVIDIA CORP
Filing Date
2026-01-16
Publication Date
2026-07-24

AI Technical Summary

Technical Problem

In large-scale memory interconnect architectures, unreliable memory STORE commands are prone to loss, leading to network failures and performance degradation, and existing technologies struggle to achieve adaptive routing and end-to-end reliability.

Method used

By employing self-synchronization technology and application-layer retransmission mechanisms, the sequentiality and reliability of data at the receiver are ensured by including metadata (such as flags or counters) in the communication write command, and adaptive routing and end-to-end reliability are implemented at the application layer.

Benefits of technology

It improves the resilience of the memory interconnect architecture to failures, reduces traffic and power consumption, ensures the reliability and order of data transmission, and enhances the fault tolerance of the system.

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Abstract

The present disclosure relates to non-reliable, out-of-order data transfers over a memory interconnect architecture. An inter-process communication method divides a total payload of a first memory command among a plurality of packets and encodes a last transmitted packet of the plurality of packets to include a metadata code in the total payload. The memory command can be transmitted between processes that perform a collective operation. Payloads of the packets are written to memory in a sequential address order such that the metadata code is written to a particular address and a second process generates an acknowledgement to the first memory command to the first process on a condition that the metadata code is read back from the particular address.
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