Satellite integrated electronic platform computer FPGA integration system and method

Abstract

The application provides a satellite integrated electronic platform computer FPGA integrated system, which comprises an FPGA and a peripheral driving circuit connected with the FPGA; wherein the FPGA and the peripheral driving circuit are subjected to board manufacturing after hardware design according to a preset architecture; after the FPGA is programmed with a software program corresponding to the architecture, the FPGA is connected with an MCU through a bus interface to cooperatively form an integrated electronic platform computer, and the MCU controls, rewrites and inquires all functions related to the integrated electronic platform computer through a parallel bus interface in the FPGA. The system is used for designing a satellite-borne computer of an integrated electronic platform, and can simultaneously satisfy functions of the integrated electronic platform, such as satellite management, attitude control, load processing, telemetry and remote control, energy management and the like, in cooperation with the MCU. Meanwhile, the system greatly reduces the physical space of the satellite computer and optimizes information flow transmission.

Description

Technical Field

[0001] This invention relates to the field of satellite integrated electronic platform technology, and in particular to an FPGA integration method and system for onboard computers of integrated electronic platforms. Background Technology

[0002] With increasingly fierce competition in the commercial space sector, the commercial satellite industry is experiencing unprecedented rapid development and profound transformation. By adopting industrial-grade components and standardized, modular production concepts, commercial satellites are emerging due to their low cost and rapid iteration. Commercial satellites are demonstrating significant commercial value in fields such as global internet, weather remote sensing, and navigation.

[0003] As a representative of commercial satellites, internet satellites move internet access services from ground base stations to satellite networks in space. They can provide high-speed, low-latency internet services to ground user terminals. Compared to traditional high-orbit communication satellites, which can only cover about one-third of the Earth's surface, low-orbit internet satellite signals can achieve seamless global coverage. Furthermore, as space-based base stations, internet satellites can quickly intervene and restore critical communication links during natural disasters and when ground communication equipment is paralyzed, making them an important emergency infrastructure. When necessary, they can even directly provide communication services to the military and special agencies.

[0004] Commercial satellites differ from traditional military satellites, often employing compact, precisely designed microsatellites. Their onboard electronic platforms and payloads also require more integrated designs. However, as a core technological component of modern satellites, the integrated electronic platform traditionally uses independent, dedicated boards for information exchange via point-to-point connections. This "divide and conquer" approach leads to difficulties in sharing system resources, resulting in larger, heavier, and more power-hungry devices, as well as complex interfaces and limited scalability and reliability. In traditional integrated electronic platform computers, each board's FPGA needs a communication interface for data transmission, requiring significant space for interface circuitry. This design redundancy and associated design risks necessitate a solution. Therefore, designing a highly integrated integrated electronic platform computer FPGA system is a problem that the industry needs to address. Summary of the Invention

[0005] This invention aims to overcome the aforementioned shortcomings and provide an FPGA-integrated system for designing a spaceborne computer within an integrated electronic platform. This system, in conjunction with an MCU, can simultaneously fulfill the integrated electronic platform's functions of spacecraft management, attitude control, payload processing, telemetry and remote control, and energy management. Furthermore, it significantly reduces the physical space required for the spaceborne computer and optimizes information flow.

[0006] This invention provides a satellite integrated electronic platform computer FPGA integrated system for use in the onboard computer of the integrated electronic platform, characterized in that it includes an FPGA and peripheral driving circuits connected thereto;

[0007] Among them, the FPGA and peripheral driving circuits are manufactured after the hardware design is completed according to the preset architecture;

[0008] After the corresponding architecture software program is programmed into the FPGA, it connects to the MCU through the bus interface and works together with the MCU to form an integrated electronic platform computer. The MCU controls, rewrites and queries all the functions involved in the integrated electronic platform computer through the bus interface inside the FPGA.

[0009] Furthermore, the satellite integrated electronic platform computer FPGA integrated system provided by the present invention is further characterized in that:

[0010] The peripheral driving circuit includes a level conversion module;

[0011] The level conversion module adapts to the signal voltage domain between the FPGA and the peripheral driver circuit, realizing the conversion between differential signals and single-ended level signals, as well as the level matching of digital signals of different voltage levels.

[0012] Furthermore, the satellite integrated electronic platform computer FPGA integrated system provided by the present invention is further characterized in that:

[0013] FPGAs integrate input / control peripheral units;

[0014] Input / control peripheral units include:

[0015] Command user module, autonomous power-on module, magnetic rod module, power distribution board module, wireline temperature acquisition module, analog user module, PPS user / GNSS standalone module, satellite-rocket separation quasi-disabled watchdog command reset module, watchdog module.

[0016] Furthermore, the satellite integrated electronic platform computer FPGA integrated system provided by the present invention is further characterized in that:

[0017] FPGAs integrate output / communication peripheral units;

[0018] Output / communication peripheral units include:

[0019] Communication stand-alone module, CAN bus stand-alone module, measurement and control A / B machine module.

[0020] Furthermore, the satellite integrated electronic platform computer FPGA integrated system provided by the present invention is further characterized in that:

[0021] FPGAs integrate memory units;

[0022] The storage unit includes: MRAM memory, NorFlash memory, and FIFO.

[0023] Furthermore, this invention also provides a method for integrating a satellite integrated electronic platform computer FPGA, characterized in that:

[0024] The FPGA software uses the bus interface as the top layer and distributes the external drive interface circuits around the FPGA to achieve: MCU status monitoring, MCU bus communication, serial communication with the payload unit, payload CAN communication, remote control and telemetry, OC command and heater command output, magnetic torque control, second pulse signal output, wire mesh temperature acquisition, analog signal acquisition, watchdog signal management, MRAM memory access, and NOR Flash memory access and management.

[0025] Furthermore, the aforementioned FPGA integration method for satellite integrated electronic platform computers is further characterized by:

[0026] The MCU accesses all functions of the FPGA via a parallel bus for reading and writing.

[0027] The read operation supports the MCU to access FPGA registers or external memory, and can query FPGA status variables or data in external memory.

[0028] Write operations allow the MCU to modify the state of FPGA registers or external memory. When the data content of the FPGA's internal registers is modified, the function or state will change. Accessing memory changes the stored data value at the corresponding address.

[0029] The function and effects of this invention:

[0030] The design of this invention can work with an MCU to control the entire integrated electronic platform computer, namely, to control and monitor the satellite's mission management, attitude control, payload processing, telemetry and remote control, and energy management.

[0031] This invention uses bus communication, which has a high clock frequency and high throughput.

[0032] The FPGA software of this invention uses the bus interface as the top layer, designing various external interface functions with high integration and management efficiency. External driver interface circuits are distributed around the FPGA, improving board utilization and reducing the overall computer board size to 6U (233mm*160mm). This enhances the communication efficiency between the onboard computer and payload equipment and telemetry and control antenna equipment. Simultaneously, the data transmission process is short, reducing the possibility of interference from cosmic particles during transmission and effectively improving the stability of the data stream. Attached Figure Description

[0033] Figure 1 This forms the top-level framework of the entire system of the present invention, including the connection between the FPGA and external functions.

[0034] Figure 2 Detailed Interface Description of the Invention

[0035] Figure 3 FPGA software design framework Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] like Figure 1-3 As shown, this embodiment provides an FPGA integration system and method for a comprehensive electronic platform, which includes FPGA software, external driving circuitry, and a parallel bus for communication with an MCU.

[0038] After the FPGA and peripheral driving circuits complete the hardware design according to the preset architecture, the PCB is fabricated. After the corresponding architecture software program is programmed into the FPGA, it is connected to the MCU through the parallel bus interface and works together with the MCU to form an integrated electronic platform computer. The MCU controls, rewrites and queries all the functions involved in the integrated electronic platform computer through the bus interface inside the FPGA.

[0039] Specifically, in this embodiment, the FPGA software selected is the Microchip M2S150T. The FPGA software implements the following functions: MCU status monitoring, MCU bus communication, serial communication with the payload unit, payload CAN communication, remote control and telemetry, OC command and heater command output, magnetic torque control, second pulse signal output, wireline temperature acquisition, analog signal acquisition, watchdog signal management, MRAM memory access, and NOR Flash memory access and management.

[0040] The parallel bus includes a 32-bit data bus, a 28-bit address bus, MCU I / O chip select signals, read / write signals, and a Ready signal returned by PFGA.

[0041] The drive circuit includes external circuitry that performs the functions described above:

[0042] In this embodiment, it includes

[0043] (A) Input / control peripherals such as:

[0044] Command User: Receives OC commands and sends them to the M2S150T for execution.

[0045] Autonomous power-on: The power-on process is controlled by the heater's OC signal.

[0046] Magnetic rod: Receives magnetic rod drive signals and executes attitude control related actions.

[0047] Distribution board: Receives digital temperature measurement and machine switching commands to realize power distribution management and status feedback.

[0048] Temperature acquisition of the first-line network: Collect temperature data of the first-line network and send it to the M2S150T.

[0049] Analog users: Data is acquired via AD converters, with a precise reference provided by an AD reference source (2.5V reference).

[0050] PPS users / GNSS standalone units: Receive PPS second pulse signals for time synchronization and timing.

[0051] Star-rocket separation quasi-disabled watchdog instruction reset: Receives star-rocket separation related instructions and triggers reset logic.

[0052] Watchdog: Outputs a feed signal and a bite reset signal to prevent system crashes.

[0053] (B) Output / communication peripherals, such as:

[0054] RS422 communication standalone unit: transmits data to the ground via an asynchronous telemetry channel.

[0055] CAN bus standalone: ​​Enables distributed communication with other devices via the CAN bus.

[0056] Measurement and control A / B unit: Supports functions such as low-speed remote control, synchronous remote control injection, high-speed injection, and synchronous telemetry transmission.

[0057] (C) Storage Module

[0058] MRAM memory: Non-volatile memory used for fast read / write of critical data and power-loss protection (capacities include 2MB and 12MB).

[0059] NorFlash memory: Large-capacity non-volatile storage (32MB) for long-term storage of program code, logs, and historical data.

[0060] Internal FIFO: The M2S150T's built-in buffer unit is used to buffer uplink commands, acquired data and downlink data, smoothing the data flow and avoiding data loss.

[0061] Based on the above design, the uplink data flow is: command / sensor data → internal FIFO → M2S150T → processing / storage; the downlink data flow is: processed data → internal FIFO → RS422 / CAN / measurement and control A / B machine → downlink.

[0062] Based on the above integrated design, multi-source data acquisition is achieved, covering various input types such as commands, temperature, analog quantities, and time synchronization, meeting the needs of aerospace telemetry and control. The dual-redundant telemetry and control A / B unit design enhances system fault tolerance. The combination of multi-level storage balances performance and reliability. The integration of safety mechanisms ensures system safety in extreme scenarios. PPS signals and GNSS timing ensure a unified time base across the entire system.

[0063] In addition, MCU status monitoring includes the MCU's ERROR pin;

[0064] The serial communication interface is externally connected to an RS422 transceiver chip;

[0065] The payload CAN communication interface includes a CAN signal converter interface;

[0066] The remote control and telemetry interface is externally connected to an RS422 transceiver chip.

[0067] The OC command and heater command outputs are externally connected to the ULN2003 control chip;

[0068] The magnetic torque converter control interface is externally connected to the L293D electrical signal conversion chip;

[0069] Second pulse signal output and interface connection to an external LVDS transmitter chip;

[0070] The temperature acquisition interface of the wired network is externally connected to a temperature sensor;

[0071] Analog signal acquisition includes voltage and current value conversion results, and the external interface connects to an AD acquisition chip;

[0072] Watchdog signal management is externally connected to MAX706;

[0073] The MRAM memory read / write interface connects to an external 2MB MRAM memory chip;

[0074] The NOR Flash memory management interface connects to an external 8MB NOR Flash memory chip.

[0075] The external circuit also includes a level conversion module, which adapts to the signal voltage domain between the FPGA and the external driving circuit, realizes the conversion between differential signals and single-ended level signals, and the level matching of digital signals of different voltage levels.

[0076] In this system, the MCU accesses all functions of the FPGA via a parallel bus for read and write operations. The high 16 bits of the parallel bus address are used for function-specific address mapping, while the low 12 bits are used for the specific instruction address mapping for each function. Read operations on the parallel bus allow the MCU to access FPGA registers or external memory, querying FPGA status variables or data in external memory. Write operations on the parallel bus allow the MCU to modify the state of FPGA registers or external memory. When the corresponding data content of an internal FPGA register is modified, the function or state will change; accessing memory changes the stored data value at the corresponding address.

[0077] The internal software logic of the FPGA is as follows:

[0078] 1. MCU status monitoring

[0079] The MCU status is monitored by the FPGA and stored in a register, which is accessible via a parallel bus.

[0080] 2. Serial communication with the payload unit

[0081] Communication with the payload unit is achieved via an asynchronous serial port, the serial port protocol of which can be configured via the bus. Data is sent from the MCU to the FPGA via the bus, and then transmitted by the FPGA; received data is received by the FPGA and stored in a FIFO for access via the parallel bus.

[0082] 3. Load CAN communication

[0083] Output data is written to the FPGA via the bus, and the FPGA frames the corresponding data and outputs it via the CAN bus. Received data is received via the CAN bus and written to the corresponding registers for bus access.

[0084] 4. Remote control and telemetry

[0085] After receiving remote control data, the FPGA stores it in a FIFO for the bus to read; telemetry data is written to the FPGA via the bus, and the FPGA converts the data into telemetry output.

[0086] 5. Output of OC command and heater command

[0087] The MCU writes the instruction sequence number and pulse width into the FPGA via the bus, and the FPGA outputs a level signal after parsing.

[0088] 6. Magnetic torque control

[0089] The MCU writes the rotation direction and time of the magnetic torquer into the FPGA via the bus, and the FPGA outputs a level signal after parsing it.

[0090] 7. Second pulse signal output

[0091] The FPGA uses its own clock to keep time, outputting a pulse signal every second. The MCU can monitor the second pulse function through the bus.

[0092] 8. Temperature data acquisition from the first-line network

[0093] After the MCU initiates a data acquisition command via the parallel bus, the FPGA parses the command and performs wireline temperature acquisition according to the corresponding communication protocol.

[0094] 9. Analog signal acquisition

[0095] The FPGA performs cyclic acquisition of the AD chip and stores the AD data in the register. The MCU accesses the corresponding register address through the parallel bus to read the target AD value.

[0096] 10. Watchdog signal management

[0097] The FPGA monitors information such as the external watchdog reset signal count and stores it in a register. The MCU can access the relevant values ​​through a parallel bus.

[0098] 11. MRAM and NOR Flash memory access

[0099] FPGA can read and write to memory, and at the same time open the channel to the parallel bus, MCU can directly access the corresponding memory location through the bus address to read and write.

[0100] The function and effect of this embodiment:

[0101] Compared to traditional designs, this embodiment summarizes the architectural upgrade of the spaceborne computer board from "distributed interface" to "FPGA bus integration". The core features are high integration, high throughput, high reliability, and miniaturization.

[0102] Specifically, by employing parallel / high-speed serial buses (such as EMIF, CAN, RS422, etc.), with higher clock frequencies and larger data bit widths, the amount of data that can be transmitted per unit time (throughput) is significantly increased compared to traditional point-to-point asynchronous communication. Simultaneously, it directly improves the communication rate between the onboard computer and payload equipment, as well as the telemetry and control antenna equipment, meeting the needs of concurrent data interaction among multiple devices.

[0103] The FPGA bus-based top-level architecture encapsulates all external interfaces (such as analog signal acquisition, command output, serial ports, CAN, telemetry and remote control, etc.) into bus-mounted functional modules, using the FPGA as the core of the bus interface. This unifies the previously scattered interface logic within the FPGA, reducing the need for additional logic chips on the board and significantly improving board integration. Simultaneously, the bus-based unified scheduling of interface resources enables data routing, timing synchronization, and resource reuse, resulting in simpler system management and faster response compared to distributed interfaces.

[0104] Furthermore, by placing the external driver interface circuitry (such as level converters and driver chips) close to the FPGA, the signal path is shortened, reducing the space occupied by wiring. As a result, the overall board size can be compressed to 6U (233mm × 160mm), which not only meets the miniaturization requirements but also facilitates chassis integration and heat dissipation.

[0105] Furthermore, the shorter data transmission path means less exposure time and space for data on the board, reducing the probability of cosmic radiation interference such as single-event effects (SEE). The more organized wiring also reduces signal attenuation, crosstalk, and timing skew, improving the integrity and stability of data transmission and meeting the high reliability requirements of aerospace applications.

Claims

1. A satellite integrated electronic platform computer FPGA integrated system, characterized in that: This includes the FPGA and its connected peripheral driving circuitry; The FPGA and peripheral driving circuits are manufactured after the hardware design is completed according to the preset architecture. After the corresponding architecture software program is programmed into the FPGA, it connects to the MCU through the bus interface and works together with the MCU to form an integrated electronic platform computer. The MCU controls, rewrites and queries all the functions involved in the integrated electronic platform computer through the parallel bus interface inside the FPGA.

2. The satellite integrated electronic platform computer FPGA integrated system as described in claim 1, characterized in that: The peripheral driving circuit includes a level conversion module; The level conversion module is adapted to the signal voltage domain between the FPGA and the peripheral driving circuit, realizing the conversion between differential signals and single-ended level signals, as well as the level matching of digital signals of different voltage levels.

3. The satellite integrated electronic platform computer FPGA integrated system as described in claim 1, characterized in that: The FPGA integrates input / control peripheral units; The input / control peripheral unit includes: Command user module, autonomous power-on module, magnetic rod module, power distribution board module, wireline temperature acquisition module, analog user module, PPS user / GNSS standalone module, satellite-rocket separation quasi-disabled watchdog command reset module, watchdog module.

4. The satellite integrated electronic platform computer FPGA integrated system as described in claim 1, characterized in that: The FPGA integrates output / communication peripheral units; The output / communication peripheral unit includes: Communication stand-alone module, CAN bus stand-alone module, measurement and control A / B machine module.

5. The satellite integrated electronic platform computer FPGA integrated system as described in claim 1, characterized in that: The FPGA integrates a memory unit; The storage unit includes: MRAM memory, NorFlash memory, and FIFO.

6. A method for integrating a satellite integrated electronic platform computer FPGA, characterized in that: The FPGA software uses the bus interface as the top layer and distributes the external drive interface circuits around the FPGA to achieve: MCU status monitoring, MCU bus communication, serial communication with the payload unit, payload CAN communication, remote control and telemetry, OC command and heater command output, magnetic torque control, second pulse signal output, wire mesh temperature acquisition, analog signal acquisition, watchdog signal management, MRAM memory access, and NOR Flash memory access and management.

7. The satellite integrated electronic platform computer FPGA integration method as described in claim 6, characterized in that: The MCU accesses all functions of the FPGA via a parallel bus for reading and writing. The read operation supports the MCU to access FPGA registers or external memory, and can query FPGA status variables or data in external memory. Write operations allow the MCU to modify the state of FPGA registers or external memory. When the data content of the FPGA's internal registers is modified, the function or state will change. Accessing memory changes the stored data value at the corresponding address.

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