Memory device and operating method thereof

Abstract

The disclosure provides a memory device and an operating method thereof. The memory device includes a plurality of word lines coupled to a plurality of memory cells, a peripheral circuit configured to select a first word line from among the plurality of word lines and perform a force drive operation of sequentially applying a first voltage, a force drive voltage, and a stabilization voltage to the first word line, and a control logic circuit configured to control the peripheral circuit, wherein the force drive voltage and the stabilization voltage applied to the first word line are respectively provided from different regulators.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0009364, filed on January 22, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The various embodiments disclosed herein generally relate to an electronic device, and more specifically, to a memory device and a method of operating the same. Background Technology

[0003] A memory device may include an array of memory cells for storing data and peripheral circuitry for performing programming, reading, and erasing operations. The peripheral circuitry includes a voltage generator that generates voltages to drive each component of the memory device.

[0004] The memory device is designed to perform programming, reading, or erasing operations based on commands output from the controller. A reading operation can be performed by applying a read voltage provided by a voltage generator to the word line connected to the selected memory cell.

[0005] During a read operation, the memory device typically applies an underdrive voltage to change the initial voltage of the word line and applies a settling voltage to bring the word line voltage to a target voltage level, thereby stabilizing the word line voltage level. External circuitry uses the underdrive voltage to change the initial voltage state of the word line and then applies the settling voltage to stabilize the word line voltage to the target value.

[0006] The voltage generator includes a regulator that generates both an underdrive voltage and a stabilization voltage. When a stabilization operation is performed on the selected word line, a regulator generates both the stabilization voltage and the underdrive voltage.

[0007] Furthermore, while using a strong underdrive voltage to shorten read operation time can accelerate the initial stabilization process of the word line voltage level, subsequent stabilization may require more time for the word line voltage level to reach the target voltage. Therefore, simply increasing the underdrive voltage is unlikely to effectively reduce the overall stabilization time. Summary of the Invention

[0008] Embodiments of this disclosure provide a memory device and a method of operating the same, which can improve the performance of the memory device.

[0009] According to embodiments of the present disclosure, a memory device may include: a plurality of word lines connected to a plurality of memory cells; peripheral circuitry configured to select a first word line from the plurality of word lines and perform a forced drive operation that sequentially applies a first voltage, a forced drive voltage, and a stable voltage to the first word line; and control logic circuitry configured to control the peripheral circuitry, wherein the forced drive voltage and the stable voltage applied to the first word line are provided from different regulators.

[0010] According to embodiments of the present disclosure, a memory device may include: a plurality of word lines connected to a plurality of memory cells; peripheral circuitry configured to select a first word line from the plurality of word lines and perform a forced drive operation that sequentially applies a first voltage, a forced drive voltage, a first stable voltage, and a second stable voltage to the first word line; and control logic circuitry configured to control the peripheral circuitry performing the forced drive operation, wherein the forced drive voltage and the first stable voltage applied to the first word line are provided from different regulators, and the first stable voltage and the second stable voltage are provided from different regulators.

[0011] According to embodiments of the present disclosure, a memory device may include: a plurality of word lines connected to a plurality of memory cells; a plurality of regulators configured to generate a first voltage, a forced drive voltage, and a stable voltage for forced drive operation; and a line decoder configured to sequentially apply the first voltage, the forced drive voltage, and the stable voltage generated by the plurality of regulators to a selected word line, wherein the forced drive voltage and the stable voltage applied to the selected word line are provided from different regulators. Attached Figure Description

[0012] Figure 1 This is a diagram illustrating a memory device according to an embodiment of the present disclosure; Figure 2 It is shown Figure 1 A diagram showing the storage blocks; Figure 3 It is shown Figure 1 A diagram showing the detailed configuration of the voltage generator, line decoder, and control logic circuitry. Figure 4 It is shown Figure 3 A diagram of the forced drive controller is shown. Figure 5 This is a diagram showing the voltage range of the regulator; Figure 6 This is a diagram illustrating an underdrive operation during a read operation of a memory device according to a first embodiment of the present disclosure; Figure 7This is a diagram illustrating an underdrive operation during a read operation of a memory device according to a second embodiment of the present disclosure; Figure 8 This is a diagram illustrating an overdrive operation during a read operation of a memory device according to a third embodiment of the present disclosure; Figure 9 This is a diagram illustrating an overdrive operation during a read operation of a memory device according to a fourth embodiment of the present disclosure; Figure 10 This is a diagram illustrating a memory card system using a memory device according to an embodiment of the present disclosure; and Figure 11 This is a diagram illustrating a solid-state drive (SSD) system using a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0013] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this specification are for illustrative purposes only. These embodiments based on the concepts can be implemented in various forms, and the description is not limited to the embodiments described in this specification.

[0014] While terms such as "first" and "second" may be used to describe various components, these components should not be construed as limited to these terms. These terms are used only to distinguish one component from another.

[0015] Figure 1 This is a diagram illustrating a memory device 100 according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1 A diagram of the storage block shown.

[0016] Reference Figure 1 and Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic circuitry 130.

[0017] Memory cell array 110 includes first to j-th memory blocks BLK1 to BLKj. First to j-th memory blocks BLK1 to BLKj are connected to row decoder 121 via row lines RL. First to j-th memory blocks BLK1 to BLKj are connected to page buffer group 123 via first to n-th bit lines BL1 to BLn. Each of the first to j-th memory blocks BLK1 to BLKj includes multiple cell strings ST, and each of the multiple cell strings ST includes multiple memory cells. In an embodiment, the multiple memory cells are non-volatile memory cells. Memory cells connected to the same word line can be defined as a single page PG. Therefore, a memory block can include multiple pages.

[0018] The first to j-th storage blocks BLK1 to BLKj can be configured to be identical to each other. Therefore, the structure of a storage block, such as the structure of the first storage block BLK1, will be described in detail below.

[0019] Reference Figure 2 The first memory block BLK1 includes a string of cells ST connecting the first to nth bit lines BL1 to BLn with the source line SL. Since the first to nth bit lines BL1 to BLn extend along the Y direction and are spaced apart from each other along the X direction, the string of cells ST can also be spaced apart from each other along both the X and Y directions. For example, the string of cells ST can be connected between the first bit line BL1 and the source line SL, and the string of cells ST can be arranged between the second bit line BL2 and the source line SL. In this way, the string of cells ST can be arranged between the nth bit line BLn and the source line SL. The string of cells ST can extend along the Z direction.

[0020] The following description uses a cell string ST connected to the nth bit line BLn as an example. The cell string ST may include a source selection transistor SST, first to i-th memory cells MC1 to MCi, and a drain selection transistor DST. Although Figure 2 The first memory block BLK1 is schematically shown to describe the structure of the memory block, but the number of source selection transistors SST, the number of first to i memory cells MC1 to MCi, and the number of drain selection transistors DST included in the cell string ST can be changed according to the memory device.

[0021] The gates of the source selection transistors SST included in different cell strings can be connected to the first or second source selection line SSL1 or SSL2, the gates of the first to the i-th memory cells MC1 to MCi can be connected to the first to the i-th word lines WL1 to WLi, and the gates of the drain selection transistors DST can be connected to one of the first to the fourth drain selection lines DSL1 to DSL4.

[0022] The following describes the connections to the first memory block BLK1 in more detail. Source select transistors (SSTs) arranged along the X-direction can be connected to the same source select line, while source select transistors (SSTs) arranged along the Y-direction can be connected to separate source select lines. For example, a portion of the source select transistors (SSTs) arranged along the Y-direction can be connected to the first source select line SSL1, and the remainder can be connected to the second source select line SSL2. The second source select line SSL2 is separate from the first source select line SSL1. Therefore, the voltage applied to the first source select line SSL1 can be the same as or different from the voltage applied to the second source select line SSL2.

[0023] Memory cells formed in the same layer among the first to the i-th memory cells MC1 to MCI can be connected to the same word line. For example, the first memory cells MC1 included in different cell strings ST can be connected to the first word line WL1, and the i-th memory cells MCI included in different cell strings ST can be connected to the i-th word line WLi. A group of memory cells included in different cell strings ST and connected to the same word line forms a page PG. Programming and reading operations can be performed on a per-page (PG) basis, while pre-programming and erasing operations can be performed on a per-block basis. Operations performed on a block-by-block basis can be performed on all pages included in the selected block.

[0024] Drain select transistors (DSTs) arranged along the Y direction can be connected to first to fourth drain select lines DSL1 to DSL4, which are separate from each other. More specifically, drain select transistors (DSTs) arranged along the X direction can be connected to the same drain select line, while drain select transistors (DSTs) arranged along the Y direction can be connected to first to fourth drain select lines DSL1 to DSL4, which are separate from each other. Because the first to fourth drain select lines DSL1 to DSL4 are separate from each other, different voltages can be applied to the first to fourth drain select lines DSL1 to DSL4.

[0025] Reference Figure 1 and Figure 2 The row line RL may include source select lines SSL1 and SSL2, multiple word lines WL1 to WLi, and drain select lines DSL1 to DSL4. The source select lines SSL1 and SSL2, the multiple word lines WL1 to WLi, and the drain select lines DSL1 to DSL4 can be connected to each of the first to j-th memory blocks BLK1 to BLKj. Each of the bit lines BL1 to BLn can be connected to at least one cell string.

[0026] Depending on the number of bits of data to be stored, the memory cells included in the memory cell array 110 can be programmed using a multi-level cell (MLC), triple-level cell (TLC), or quad-level cell (QLC) scheme. Each memory cell programmed using the MLC scheme can store two bits of data. Each memory cell programmed using the TLC scheme can store three bits of data. Each memory cell programmed using the QLC scheme can store four bits of data. The programming method of the memory cells can vary depending on the memory device. In addition to the above schemes, a scheme in which five or more bits of data are programmed in a single memory cell can also be used.

[0027] The control logic circuit 130 can control the peripheral circuit 120 to perform programming, reading, or erasing operations on selected areas of the memory cell array 110. For example, the peripheral circuit 120 can apply various operating voltages to the row lines RL and the first to nth bit lines BL1 to BLn in response to the control of the control logic circuit 130, or can selectively discharge the row lines RL and the first to nth bit lines BL1 to BLn.

[0028] The peripheral circuitry 120 may include a row decoder 121, a voltage generator 122, a page buffer group 123, a column decoder 124, an input / output circuit 125, and a sensing circuit 126.

[0029] The row decoder 121 is connected to the memory cell array 110 via row lines RL. The row line RL may include at least one source select line, multiple word lines, and at least one drain select line. In an embodiment, the word lines may include normal word lines and dummy word lines.

[0030] The row decoder 121 decodes the row address RADD received from the control logic circuit 130. The row decoder 121 selects at least one of the memory blocks BLK1 to BLKj based on the decoded address. Furthermore, the row decoder 121 can transmit the operating voltage Vop generated by the voltage generator 122 to the row line RL of the selected memory block, based on the decoded address.

[0031] For example, during a programming operation, the line decoder 121 can apply a programming voltage to the selected word line and a programming pass voltage to the unselected word line, the programming pass voltage being lower than the programming voltage. During a programming verification operation, the line decoder 121 can apply a verification voltage to the selected word line and a verification pass voltage to the unselected word line, the verification pass voltage being higher than the verification voltage. During a reading operation, the line decoder 121 can apply a read voltage to the selected word line and a read pass voltage to the unselected word line, the read pass voltage being higher than the read voltage.

[0032] The erase operation of memory device 100 is performed on a block-by-block basis. During the erase operation, line decoder 121 can select a memory block based on the decoded address. During the erase operation, line decoder 121 can apply 0V or ground voltage to the word line connected to the selected memory block, or it can float the word line.

[0033] Voltage generator 122 operates in response to control of control logic circuit 130. Voltage generator 122 generates multiple voltages by utilizing the external power supply voltage provided to memory device 100. Specifically, voltage generator 122 can generate various operating voltages Vop for programming, reading, and erasing operations in response to the operation signal OPSIG generated by control logic circuit 130. For example, voltage generator 122 can generate programming voltage, verification voltage, pass voltage, read voltage, erase voltage, etc., in response to control of control logic circuit 130.

[0034] Page buffer group 123 includes first to nth page buffers PB1 to PBn. The first to nth page buffers PB1 to PBn are connected to memory cell array 110 via first to nth bit lines BL1 to BLn. The first to nth page buffers PB1 to PBn operate in response to control logic circuitry 130. More specifically, the first to nth page buffers PB1 to PBn may operate in response to page buffer control signal PBSIGNALS. For example, during a read or verification operation, the first to nth page buffers PB1 to PBn may temporarily store data received via the first to nth bit lines BL1 to BLn, or may sense the voltage or current of the first to nth bit lines BL1 to BLn.

[0035] More specifically, during programming operations, when a programming voltage is applied to the selected word line, the first to nth page buffers PB1 to PBn can transmit the data DATA received through the input / output circuit 125 to the selected memory cell via the first to nth bit lines BL1 to BLn. The memory cell of the selected page is programmed according to the transmitted data DATA. During programming verification operations, the first to nth page buffers PB1 to PBn read page data by sensing the voltage or current received from the selected memory cell via the first to nth bit lines BL1 to BLn.

[0036] During the read operation, the first to nth page buffers PB1 to PBn read data DATA from the memory cell of the selected page through the first to nth bit lines BL1 to BLn, and output the read data DATA to the input / output circuit 125 under the control of the column decoder 124.

[0037] During the erase operation, the first to nth page buffers PB1 to PBn can either float the first to nth bit lines BL1 to BLn or apply an erase voltage to the first to nth bit lines BL1 to BLn.

[0038] The column decoder 124 can transfer data between the input / output circuitry 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 can exchange data with the first to nth page buffers PB1 to PBn via the data lines DL, or it can exchange data with the input / output circuitry 125 via the column lines CL.

[0039] The input / output circuit 125 can transmit the command CMD and address ADDR received from the memory controller to the control logic circuit 130, or it can exchange data DATA with the column decoder 124.

[0040] The sensing circuit 126 can generate a reference current in response to the allowable bit signal VRYBIT during a read or verification operation, and can compare the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current to output a pass signal PASS or a failure signal FAIL.

[0041] Control logic circuit 130 can output operation signals OPSIG, row address RADD, page buffer control signals PBSIGNALS, and enable bit signal VRYBIT in response to command CMD and address ADDR to control peripheral circuit 120. For example, control logic circuit 130 can control the read operation on the selected memory block in response to a sub-block read command and address. Furthermore, control logic circuit 130 can control the erase operation on the selected sub-blocks included in the selected memory block in response to a sub-block erase command and address. Additionally, control logic circuit 130 can determine whether the verification operation passed or failed in response to pass signal PASS or failure signal FAIL.

[0042] Figure 3 It is shown Figure 1 A diagram showing the detailed configuration of the voltage generator 122, the line decoder 121, and the control logic circuit 130.

[0043] Reference Figure 3 The voltage generator 122 may include multiple regulators 122-1 to 122-n. The multiple regulators 122-1 to 122-n can generate an operating voltage Vop and apply the operating voltage Vop to multiple word lines WL1 to WLm. The multiple regulators can generate voltages of different ranges.

[0044] The line decoder 121 includes a switch control signal generator 1211 and multiple switch circuits SW_1 to SW_n. The multiple switch circuits SW_1 to SW_n can be connected to multiple regulators 122-1 to 122-n of the voltage generator 122.

[0045] The switch control signal generator 1211 can generate switch control signals for controlling a plurality of switch circuits SW_1 to SW_n in response to the selection signal SEL of the control logic circuit 130. The selection signal SEL may include signals for selecting the switch circuit to be turned on and the switch circuit to be turned off from the plurality of switch circuits SW_1 to SW_n.

[0046] Multiple switching circuits SW_1 to SW_n can be connected to one of multiple word lines WL1 to WLm. Furthermore, multiple switching circuits SW_1 to SW_n can be connected to multiple regulators 122-1 to 122-n. Multiple switching circuits SW_1 to SW_n can connect multiple word lines WL1 to WLm to multiple regulators 122-1 to 122-n.

[0047] For example, the first switching circuit SW_1 can connect the first word line WL_1 to multiple regulators 122-1 to 122-n. The first word line WL_1 can receive operating voltage from the multiple regulators 122-1 to 122-n through the first switching circuit SW_1.

[0048] For example, the second switching circuit SW_2 can connect the second word line WL_2 to multiple regulators 122-1 to 122-n. The second word line WL_2 can receive operating voltage from the multiple regulators 122-1 to 122-n through the second switching circuit SW_2.

[0049] The control logic circuit 130 can control the voltage generator 122, the line decoder 121, and the input / output circuit 125. The control logic circuit 130 can generate various signals in response to commands CMD and addresses ADDR transmitted from external devices to control the peripheral circuit 120.

[0050] Figure 4 It is shown Figure 3 The diagram shows the forced drive controller 131. Figure 5 This is a diagram showing the voltage range of the regulator.

[0051] Reference Figure 4 and Figure 5 The forced drive controller 131 includes a regulator setting unit 1311, a regulator information storage unit 1312, a timing control unit 1313, and a control signal generation unit 1314. The regulator setting unit 1311, the regulator information storage unit 1312, the timing control unit 1313, and the control signal generation unit 1314 include all the circuitry, systems, software, firmware, and devices required for their respective operation and functions.

[0052] The regulator setting unit 1311 can select a temporary drive regulator IReg based on the forced drive voltage range information, the settling voltage range information, and the command information.

[0053] The conventional drive regulator NReg generates the drive voltage, while the temporary drive regulator IReg generates a forced drive voltage, such as one of overdrive or underdrive. Each of the conventional drive regulator NReg and the temporary drive regulator IReg can also generate other types of voltage. Figure 4 and Figure 5 The regular drive regulator NReg has already been set up, so the method for setting up the temporary drive regulator IReg will be described.

[0054] More specifically, the regulator setting unit 1311 can select a temporary drive regulator whose voltage range corresponds to the forced drive voltage or stable voltage information based on the forced drive voltage range information, the stable voltage range information, and the voltage generation range information of each of the plurality of regulators, wherein the voltage generation range information of each of the plurality of regulators is stored in the regulator information storage unit 1312.

[0055] Furthermore, the regulator setting unit 1311 can select a regulator that is unrelated to command execution as a temporary drive regulator from among the regulators whose voltage range corresponds to the forced drive voltage, based on the forced drive voltage information and the voltage range information of each regulator stored in the regulator information storage unit 1312.

[0056] Forced drive voltage information can refer to information about overdrive or underdrive voltage. Stabilized voltage information can refer to information about the stabilized voltage. Voltage range information for each regulator can refer to the voltage range that can be generated as set for each regulator.

[0057] For example, when a forced drive is performed during a read operation, the regulator setting unit 1311 can select a regulator that is related to the erase operation, unrelated to the read operation, and whose voltage range corresponds to the forced drive voltage or stable voltage information as a temporary drive regulator.

[0058] When the regulator setting unit 1311 searches for both the regulator corresponding to the forced drive voltage range information and the regulator corresponding to the stable voltage range information among the regulators that have never participated in executing the corresponding command, the regulator setting unit 1311 may preferentially select the regulator corresponding to the forced drive voltage range information as the temporary drive regulator.

[0059] like Figure 5As shown, the regulator information storage unit 1312 stores regulator voltage generation range information for each of the plurality of regulators, specifying the voltage generation range that each regulator can generate. For example, the bias voltage generation range of the p-th regulator Reg p can be between -5V and 5V, and the bias voltage generation range of the k-th regulator Reg k can be between -1V and 3V. The regulator information storage unit 1312 can provide information related to the regulator voltage generation range of each of the plurality of regulators to the regulator setting unit 1311.

[0060] The timing control unit 1313 controls the switching timing of the temporary drive regulator IReg and the regular drive regulator NReg. The timing control unit 1313 provides the switching timing information for the temporary drive regulator IReg and the regular drive regulator NReg based on predetermined switching timing information, which is based on the difference between the stable voltage and the forced drive voltage. Furthermore, the timing control unit 1313 can correct the switching timing information based on information about the selected temporary drive regulator IReg generated by the regulator setting unit 1311.

[0061] Based on the switching timing between the temporary drive regulator IReg and the regular drive regulator NReg, the control signal generation unit 1314 sends a signal to the switch control signal generator 1211 ( Figure 3 ) provides control signals. Switch control signal generator 1211 ( Figure 3 It can control multiple switching circuits SW_1 to SW_n based on the control signals provided from the control signal generation unit 1314.

[0062] Figures 6 to 9 This is a diagram illustrating the forced drive operation during a read operation of a memory device according to the first to fourth embodiments of the present disclosure.

[0063] The dashed line in the word line voltage (VLocalWL) curve indicates the case where the forced drive voltage and the stable voltage are generated by a single regulator, while the solid line indicates the case where the forced drive voltage and the stable voltage are generated by separate regulators.

[0064] exist Figure 6 and Figure 7 In the word line voltage (VLocalWL) curve, the dashed or solid line that is relatively high in the same time period can represent the voltage of the word line that is far away from the voltage source, while the dashed or solid line that is relatively low in the same time period can represent the voltage of the word line that is close to the voltage source.

[0065] exist Figure 8 and Figure 9In the word line voltage (VLocalWL) curve, the lower dashed or solid lines in the same time period can represent the voltage of word lines far from the voltage source, while the upper dashed or solid lines can represent the voltage of word lines close to the voltage source.

[0066] In the graph, VSELWL represents the regulator selection signal, which is used to provide voltage to the selected word line. VReg1, VIReg, and VNReg represent the voltages provided by the first regulator Reg1, the temporary drive regulator IReg, and the regular drive regulator NReg, respectively.

[0067] The forced drive voltage can be either an underdrive voltage Vud or an overdrive voltage Vod. Additionally, the conventional drive regulator NReg generates either a stable voltage Vst or a forced drive voltage (Vud or Vod). The temporary drive regulator IReg generates a voltage other than that generated by the conventional drive regulator NReg.

[0068] Figure 6 This is a diagram illustrating an underdrive operation during a read operation of a memory device according to a first embodiment of the present disclosure. (Refer to...) Figure 6 The first regulator Reg1 provides the first voltage V1, the temporary drive regulator IReg provides the underdrive voltage Vud, and the regular drive regulator NReg provides the stable voltage Vst.

[0069] Control logic circuit 130 ( Figure 3 ) can control line decoder 121 ( Figure 3 The voltage source supplying voltage to the selected word line can be switched from the first regulator Reg1 to the temporary drive regulator IReg, or from the temporary drive regulator IReg to the regular drive regulator NReg. In other words, the line decoder 121 can immediately change the voltage applied to the selected word line by switching the voltage source supplying voltage to the selected word line from the first regulator Reg1 to the temporary drive regulator IReg, and from the temporary drive regulator IReg to the regular drive regulator NReg.

[0070] Reference Figure 6 During the (1-1)th time period p11 from time point (1-1) to time point (1-2) t12, the peripheral circuit 120 ( Figure 1 A first voltage V1 can be applied to the selected word line. The first voltage V1 can be provided by a first regulator Reg1. For example, the first voltage V1 can be a pass voltage when an underdrive operation is performed during a read operation of the selected word line.

[0071] During the (1-2)th time period p12 from time point (1-2) to time point (1-3) t13, the peripheral circuit 120 ( Figure 1 An underdrive voltage Vud can be applied to the selected word line. The underdrive voltage Vud can be provided from the temporary drive regulator IReg.

[0072] For example, when an underdrive operation is performed during the read operation of the selected word line, after the pass voltage is applied during the (1-1)th time period p11, the line decoder 121 ( Figure 3 The regulator that supplies voltage to the selected word line can be switched from the first regulator Reg1 to the temporary drive regulator IReg. Once switched from the first regulator Reg1 to the temporary drive regulator IReg, the underdrive voltage Vud generated by the temporary drive regulator IReg is supplied to the selected word line.

[0073] During the (1-3)th time period p13 from time point (1-3) to time point (1-4) t14, the peripheral circuit 120 ( Figure 1 A stable voltage Vst can be applied to the selected word line. The stable voltage Vst can be provided by a conventional drive regulator NReg.

[0074] For example, when an underdrive operation is performed during a read operation of the selected word line, after the underdrive voltage Vud generated by the temporary drive regulator IReg is provided to the selected word line, the regulator providing the voltage to the selected word line switches from the temporary drive regulator IReg to the regular drive regulator NReg at time point (1-3) t13. Starting from time point (1-3) t13, the stable voltage Vst generated by the regular drive regulator NReg is provided to the selected word line.

[0075] The conventional drive regulator NReg can generate a stable voltage Vst from time point t13, earlier than time point (1-3). For example, the conventional drive regulator NReg can generate a stable voltage Vst from time point t12, before providing voltage to the selected word line. The conventional drive regulator NReg can provide a stable voltage Vst to the selected word line immediately from time point t13, corresponding to the switching time point, by generating the stable voltage Vst earlier than time point t13, i.e., the switching time point.

[0076] Conventional memory devices perform underdrive operation on the selected word line by applying an underdrive voltage and a stabilizing voltage provided by a regulator to the selected word line. In conventional memory devices, when a strong underdrive voltage is applied to the word line to shorten the underdrive operation time, the time required for the regulator to generate the stabilizing voltage may increase. That is, the stabilizing period p13' may end at time point (1-4') t14'. Therefore, in conventional memory devices, it is difficult to shorten the underdrive operation time.

[0077] In the memory device according to a first embodiment of the present disclosure, the underdrive voltage and the stabilizing voltage for underdrive operation of the selected word line are generated from different regulators and provided to the selected word line. Therefore, since the underdrive voltage and the stabilizing voltage are applied to the selected word line from different regulators, the underdrive operation time of the memory device can be reduced.

[0078] Figure 7 This is a diagram illustrating an underdrive operation during a read operation of a memory device according to a second embodiment of the present disclosure. Figure 7 In this process, the first regulator Reg1 provides the first voltage V1, the conventional drive regulator NReg provides the underdrive voltage Vud and the second stable voltage Vst2, and the temporary drive regulator IReg provides the first stable voltage Vst1.

[0079] Control logic circuit 130 ( Figure 3 ) can control line decoder 121 ( Figure 3 Switch from the first regulator Reg1 to the regular drive regulator NReg, switch from the regular drive regulator NReg to the temporary drive regulator IReg, or switch from the temporary drive regulator IReg to the regular drive regulator NReg. Figure 3 The line decoder 121 can immediately change the voltage applied to the selected word line by switching the first regulator Reg1, the regular drive regulator NReg, and the temporary drive regulator IReg.

[0080] Reference Figure 7 During the (2-1)th time period p21 from time point (2-1) to time point (2-2) t22, the peripheral circuit 120 ( Figure 1 A first voltage V1 can be applied to the selected word line. The first voltage V1 can be provided from the first regulator Reg1. For example, when an underdrive operation is performed during a read operation of the selected word line, the first voltage V1 can be a pass voltage.

[0081] During the (2-2)th time period p22 from time point (2-2) to time point (2-3) t23, the peripheral circuit 120 ( Figure 1An underdrive voltage Vud can be applied to the selected word line. The underdrive voltage Vud can be provided by a conventional drive regulator NReg.

[0082] For example, when an underdrive operation is performed during the read operation of the selected word line, after the pass voltage is applied during the (2-1)th period p21, the line decoder 121 ( Figure 3 The regulator supplying voltage to the selected word line can be switched from the first regulator Reg1 to the conventional drive regulator NReg. As the first regulator Reg1 switches to the conventional drive regulator NReg, the underdrive voltage Vud generated by the conventional drive regulator NReg is immediately supplied to the selected word line.

[0083] During the (2-3)th time period p23 from time point (2-3) to time point (2-4) t24, the peripheral circuit 120 ( Figure 1 A first stable voltage Vst1 can be applied to the selected word line. The first stable voltage Vst1 is provided by a temporary drive regulator IReg. The temporary drive regulator IReg can generate the first stable voltage Vst1 from time point t23 earlier than time point (2-3). The temporary drive regulator IReg can generate the first stable voltage Vst1 earlier than time point t23 corresponding to the switching time point, so as to immediately provide the first stable voltage Vst1 to the selected word line from time point t23 (2-3).

[0084] During the (2-4)th time period p24 from time point (2-4) to time point (2-5) t25, the peripheral circuit 120 ( Figure 1 The second stable voltage Vst2 can be applied to the selected word line. The conventional drive regulator NReg can provide the second stable voltage Vst2. The conventional drive regulator NReg can generate the second stable voltage Vst2 before time point t24 (2-4).

[0085] The second stable voltage Vst2 can be the same voltage as the first stable voltage Vst1. The temporary drive regulator IReg, which provides the first stable voltage Vst1, temporarily provides this voltage. The regular drive regulator NReg can instead perform the operations performed by the temporary drive regulator IReg.

[0086] When the underdriven voltage Vud is generated during time period (2-2) p22 and supplied to the conventional drive regulator NReg of the selected word line, and the first stable voltage Vst1 is supplied to the selected word line in the subsequent time period (2-3) p23, the transition from the underdriven voltage Vud to the first stable voltage Vst1 takes time. (See reference...) Figure 7The dashed line in the graph, compared to the solid line indicating the transition, shows a delay in the transition of the voltage (VNReg) generated by the conventional drive regulator NReg from the underdrive voltage Vud to the second stable voltage Vst2. This transition occurs later than time point t23 (2-3). The dashed line in the word line voltage (VLocalWL) graph indicates the case where the forced drive voltage and stable voltage are generated by a single regulator, while the solid line indicates the case where the forced drive voltage and stable voltage are generated by separate regulators. Therefore, in this embodiment... Figure 1 In the peripheral circuit 120, the temporary drive regulator IReg stably provides a first stable voltage Vst1 to the selected word line during the (2-3) period p23 until the regular drive regulator NReg provides a second stable voltage Vst2 to the selected word line. Finally, the regular drive regulator NReg can stably provide the second stable voltage Vst2 to the selected word line.

[0087] In other words, when an underdrive operation is performed during the read operation of the selected word line, after the underdrive voltage Vud generated by the regular drive regulator NReg is provided to the selected word line, the regulator providing voltage to the selected word line switches from the regular drive regulator NReg to the temporary drive regulator IReg at time point (2-3) t23. Therefore, starting from time point (2-3) t23, the first stable voltage generated by the temporary drive regulator IReg is provided to the selected word line. At time point (2-4) t24, the regulator providing voltage to the selected word line switches from the temporary drive regulator IReg to the regular drive regulator NReg. Therefore, starting from time point (2-4) t24, the second stable voltage Vst2 generated by the regular drive regulator NReg is provided to the selected word line.

[0088] In conventional memory devices, underdrive voltage and stabilization voltage are generated by a regulator and supplied to the selected word line to perform an underdrive operation. In conventional memory devices, when a stronger underdrive voltage is applied to the word line to shorten the underdrive operation time, the time required for the regulator generating the stronger underdrive voltage to switch from the underdrive voltage to the stabilization voltage increases. The stabilization period p23' may end at time point t25 (2-5). Therefore, in conventional memory devices, it is difficult to shorten the underdrive operation time.

[0089] When the memory device according to the second embodiment of this disclosure performs an underdrive operation on the selected word line, the underdrive voltage and the stabilizing voltage are generated from different regulators and provided to the selected word line. Therefore, by providing the underdrive voltage and the stabilizing voltage to the selected word line from separate regulators that generate different voltages, rather than from a single regulator, the underdrive operation time of the memory device can be easily reduced.

[0090] Figure 8 This is a diagram illustrating an overdrive operation during a read operation of a memory device according to a third embodiment of the present disclosure. Figure 8 As shown, in order to perform an overdrive operation during the read operation of the selected word line, the first regulator Reg1 provides a first voltage, the temporary drive regulator IReg provides an overdrive voltage, and the regular drive regulator NReg provides a stable voltage.

[0091] Line decoder 121 ( Figure 3 ) can be used in control logic circuit 130 ( Figure 3 Under the control of ), it switches from the first regulator Reg1 to the temporary drive regulator IReg, from the temporary drive regulator IReg to the regular drive regulator NReg, or from the regular drive regulator NReg to the temporary drive regulator IReg. Figure 3 The line decoder 121 can immediately change the voltage applied to the selected word line by switching the first regulator Reg1, the regular drive regulator NReg, and the temporary drive regulator IReg that provide voltage to the selected word line.

[0092] Reference Figure 8 During the (3-1)th time period p31 from time point (3-1) to time point (3-2) t32, the peripheral circuit 120 ( Figure 1 A first voltage V1 can be applied to the selected word line. The first voltage V1 can be provided from the first regulator Reg1. For example, the first voltage V1 can be a pass voltage when a drive operation is performed during a read operation of the selected word line.

[0093] During the (3-2)th time period p32 from time point (3-2) to time point (3-3) t33, the peripheral circuit 120 ( Figure 1 An overdrive voltage Vod can be applied to the selected word line. The overdrive voltage Vod can be provided by a temporary drive regulator IReg.

[0094] For example, when a drive operation is performed during the read operation of the selected word line, after a pass voltage is applied to the selected word line during the (3-1) period p31, the line decoder 121 ( Figure 3 The regulator that supplies voltage to the selected word line can be switched from the first regulator Reg1 to the temporary drive regulator IReg. Once switched from the first regulator Reg1 to the temporary drive regulator IReg, the overdrive voltage generated by the temporary drive regulator IReg is supplied to the selected word line.

[0095] During the (3-3)th time period p33 from time point (3-3) to time point (3-4) t34, the peripheral circuit 120 ( Figure 1 A stable voltage Vst can be applied to the selected word line. The stable voltage Vst can be provided from the conventional drive regulator NReg.

[0096] For example, when an overdrive operation is performed during a read operation of the selected word line, after the overdrive voltage Vod generated by the temporary drive regulator IReg is provided to the selected word line, the regulator providing the voltage to the selected word line switches from the temporary drive regulator IReg to the regular drive regulator NReg at time point (3-3) t33. Starting from time point (3-3) t33, the stable voltage Vst generated by the regular drive regulator NReg is provided to the selected word line.

[0097] The conventional drive regulator NReg can generate a stable voltage Vst from time point t33 earlier than time point (3-3). For example, the conventional drive regulator NReg can generate a stable voltage Vst from time point t32 (3-2) before providing voltage to the selected word line. The conventional drive regulator NReg can provide a stable voltage Vst to the selected word line immediately from time point t33 (3-3) by generating the stable voltage Vst earlier than time point t33 (3-3) corresponding to the switching time point.

[0098] Conventional memory devices perform overdrive operations on selected word lines by applying an overdrive voltage and a stabilizing voltage provided by a regulator to the selected word line. In conventional memory devices, when a strong overdrive voltage is applied to the word line to shorten the overdrive operation time, the time required for the regulator to generate and provide the stabilizing voltage increases, causing the stabilizing period p33' to potentially end at time point t34' (3-4'). Therefore, shortening the overdrive operation time of a conventional memory device is not easy.

[0099] When the memory device according to the third embodiment of this disclosure performs an overdrive operation on the selected word line, the overdrive voltage and the stabilizing voltage are generated and provided to the selected word line by different regulators. Therefore, by providing the overdrive voltage and stabilizing voltage to the selected word line from separate regulators that generate different voltages, rather than a single regulator, the overdrive operation time of the memory device can be easily reduced.

[0100] Figure 9 This is a diagram illustrating an overdrive operation during a read operation of a memory device according to a fourth embodiment of the present disclosure. Figure 9In order to perform an overdrive operation on the selected word line, the first regulator Reg1 provides a first voltage V1, the regular drive regulator NReg provides an overdrive voltage Vod and a second stable voltage Vst2, and the temporary drive regulator IReg provides a first stable voltage Vst1.

[0101] Figure 3 The control logic circuit 130 in the middle can control Figure 3 The line decoder 121 switches from the first regulator Reg1 to the regular drive regulator NReg, from the regular drive regulator NReg to the temporary drive regulator IReg, or from the temporary drive regulator IReg to the regular drive regulator NReg. The line decoder 121 can immediately change the voltage applied to the selected word line by switching the first regulator Reg1, the regular drive regulator NReg, and the temporary drive regulator IReg.

[0102] Reference Figure 9 During the (4-1)th time period p41 from time point (4-1) to time point (4-2) t42, the peripheral circuit 120 ( Figure 1 A first voltage V1 can be applied to the selected word line. The first voltage V1 can be provided from the first regulator Reg1. For example, the first voltage V1 can be a pass voltage when a drive operation is performed during a read operation of the selected word line.

[0103] During the (4-2)th time period p42 from time point (4-2) to time point (4-3) t43, the peripheral circuit 120 ( Figure 1 An overdrive voltage Vod can be applied to the selected word line. The overdrive voltage Vod can be provided from the conventional drive regulator NReg.

[0104] For example, when a drive operation is performed during the read operation of the selected word line, after the pass voltage is applied during the (4-1)th period p41, the line decoder 121 ( Figure 3 The first regulator Reg1, which supplies voltage to the selected word line, can be switched to the conventional drive regulator NReg. As the first regulator Reg1 switches to the conventional drive regulator NReg, the overdrive voltage Vod generated by the conventional drive regulator NReg is immediately supplied to the selected word line.

[0105] During the (4-3)th time period p43 from time point (4-3) to time point (4-4) t44, the peripheral circuit 120 ( Figure 1The first stable voltage Vst1 can be applied to the selected word line. The temporary drive regulator IReg can provide the first stable voltage Vst1. The temporary drive regulator IReg can generate the first stable voltage Vst1 from a time point before time point t43 (4-3). The temporary drive regulator IReg can provide the first stable voltage Vst1 to the selected word line immediately from time point t43 (4-3) corresponding to the switching time point by generating the first stable voltage Vst1 earlier than time point t43 (4-3) – i.e., the switching time point).

[0106] During the (4-4)th time period p44 from time point (4-4) to time point (4-5) t45, the peripheral circuit 120 ( Figure 1 The second stable voltage Vst2 can be applied to the selected word line. The conventional drive regulator NReg can provide the second stable voltage Vst2. The conventional drive regulator NReg can generate the second stable voltage Vst2 starting from a time point before time point t44 (4-4).

[0107] The second stable voltage Vst2 can be the same voltage as the first stable voltage Vst1. Since the temporary drive regulator IReg provides the first stable voltage Vst1, the conventional drive regulator NReg can replace the literally temporarily driven temporary drive regulator IReg to perform the operations performed by the temporary drive regulator IReg.

[0108] Since the conventional drive regulator NReg generates the drive voltage Vod and supplies it to the selected word line during time period (4-2) p42, it may not be able to quickly provide the first stable voltage Vst1 to the selected word line during the immediately following time period (4-3) p43. Therefore, the temporary drive regulator IReg may only provide the first stable voltage Vst1 to the selected word line during time period (4-3) p43 until the conventional drive regulator NReg provides the second stable voltage Vst2 to the selected word line. Finally, the conventional drive regulator NReg stably provides the second stable voltage Vst2 to the selected word line.

[0109] For example, when an overdrive operation is performed during a read operation of the selected word line, the overdrive voltage Vod generated by the regular drive regulator NReg is provided to the selected word line, and the regulator providing the voltage to the selected word line switches from the regular drive regulator NReg to the temporary drive regulator IReg at time point (4-3) t43. Therefore, starting from time point (4-3) t43, a first stable voltage generated by the temporary drive regulator IReg is provided to the selected word line. At time point (4-4) t44, the regulator providing the voltage to the selected word line switches from the temporary drive regulator IReg to the regular drive regulator NReg. Therefore, starting from time point (4-4) t44, a second stable voltage Vst2 generated by the regular drive regulator NReg is provided to the selected word line.

[0110] Conventional memory devices perform overdrive operations on selected word lines by applying an overdrive voltage and a stabilizing voltage generated and supplied by a regulator to the selected word line. In conventional memory devices, when a stronger overdrive voltage is applied to the word line to shorten the overdrive operation time, the time taken for the regulator to generate the stabilizing voltage and supply it to the selected word line may increase. That is, the stabilizing period p43' may end at time point t45' (4-5').

[0111] Therefore, it is difficult to shorten the overdrive operation time of traditional memory devices.

[0112] When the memory device according to the fourth embodiment of this disclosure performs an overdrive operation on the selected word line, the overdrive voltage and the stabilizing voltage are generated from different regulators and provided to the selected word line. Therefore, the overdrive voltage and the stabilizing voltage are provided from separate regulators that generate different voltages, rather than from a single regulator, and are immediately applied to the selected word line, thereby easily reducing the overdrive operation time of the memory device.

[0113] Figure 10 This is a diagram illustrating a memory card system 3000 using a memory device according to an embodiment of the present disclosure.

[0114] Reference Figure 10 The memory card system 3000 may include a controller 3100, a memory device 3200, and a connector 3300.

[0115] Controller 3100 may be coupled to memory device 3200. Controller 3100 may access memory device 3200. For example, controller 3100 may control programming, reading, or erasing operations, or background operations, of memory device 3200. Controller 3100 may be configured to provide an interface between memory device 3200 and a host. Controller 3100 may be configured to drive firmware for controlling memory device 3200. For example, controller 3100 may include components such as random access memory (RAM), a host interface, a memory interface, and ECC circuitry.

[0116] Controller 3100 can communicate with external devices via connector 3300. Controller 3100 can communicate with external devices (e.g., a host) based on specific communication protocols. For example, controller 3100 can communicate with external devices via at least one of various communication standards or interfaces such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), WiFi, Bluetooth, and High Speed ​​Non-Volatile Memory (NVMe) protocols. In embodiments, connector 3300 may be defined by at least one of the aforementioned communication standards or interfaces.

[0117] Memory device 3200 may include a plurality of memory cells and can be configured according to... Figure 1 The memory device 100 shown is configured in the same manner.

[0118] The controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to form a memory card, such as a PCMCIA card, a compact flash memory (CF) card, a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, micro MMC or eMMC), an SD card (SD, mini SD, micro SD or SDHC), a universal flash memory (UFS), etc.

[0119] Figure 11 This is a block diagram illustrating a solid-state drive (SSD) system 4000 using a memory device according to an embodiment of the present disclosure.

[0120] Reference Figure 11The SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 can exchange signals with the host 4100 through a signal connector 4001 and can receive power through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0121] Controller 4210 can control multiple memory devices 4221 to 422n in response to signals received from host 4100. In embodiments, the signals may be based on the interface between host 4100 and SSD 4200. For example, the signals may be defined by at least one of various communication standards or interfaces such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), WiFi, Bluetooth, and High Speed ​​Non-Volatile Memory (NVMe) interfaces.

[0122] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n can be configured to store data according to... Figure 1 The memory device 100 shown is configured in the same manner.

[0123] Auxiliary power supply 4230 can be connected to host 4100 via power connector 4002. Auxiliary power supply 4230 can utilize power from host 4100 for power supply and charging. When the power supply to host 4100 is unstable, auxiliary power supply 4230 can supply power to SSD 4200. In embodiments, auxiliary power supply 4230 can be located inside or outside SSD 4200. For example, auxiliary power supply 4230 can be located within the motherboard and provide auxiliary power to SSD 4200.

[0124] Buffer memory 4240 can be used as a buffer memory for SSD 4200. For example, buffer memory 4240 can temporarily store data received from host 4100, or data received from multiple memory devices 4221 to 422n, or it can temporarily store metadata (e.g., mapping tables) of memory devices 4221 to 422n. Buffer memory 4240 can include volatile memory, such as DRAM, SDRAM, DDRSD RAM, and LPDDR SDRAM, or non-volatile memory, such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0125] According to embodiments of this disclosure, the performance of a memory device can be improved by reducing the settling time of read operations.

[0126] The above description is intended to enable those skilled in the art to make, use, and practice the technical features of this disclosure, and has been provided as examples in the context of specific applications and their requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the principles described herein can be applied to other embodiments and applications without departing from the scope of this disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered in a descriptive sense only and not as limiting the scope of the technology. The technical scope of this disclosure is not limited to the embodiments and the accompanying drawings. Furthermore, embodiments can be combined to form other embodiments.

Claims

1. A memory device, comprising: Multiple word lines connect to multiple memory cells; The peripheral circuit selects a first word line from the plurality of word lines and performs a forced drive operation, wherein the forced drive operation sequentially applies a first voltage, a forced drive voltage, and a stable voltage to the first word line. as well as The control logic circuit controls the peripheral circuit. The forced drive voltage and the stable voltage applied to the first word line are provided from different regulators.

2. The memory device according to claim 1, wherein, The forced drive voltage is one of underdrive voltage and overdrive voltage.

3. The memory device according to claim 1, wherein, The peripheral circuit includes the different regulators, which include: A conventional drive regulator generates one of the stable voltage and the forced drive voltage; and A temporary drive regulator generates another of the stable voltage and the forced drive voltage.

4. The memory device according to claim 3, wherein, When the conventional drive regulator that generates the forced drive voltage is switched to the temporary drive regulator, the temporary drive regulator generates the stable voltage before the switch.

5. The memory device according to claim 3, wherein, When the temporary drive regulator that generates the forced drive voltage is switched to the conventional drive regulator, the conventional drive regulator generates the stable voltage before the switch.

6. The memory device according to claim 3, wherein, The control logic circuit includes a forced drive controller, which sets the temporary drive regulator by considering the voltage range of the stable voltage, the voltage range of the forced drive voltage, and the voltage generation range information of each of the conventional drive regulator and the temporary drive regulator.

7. The memory device according to claim 6, wherein, The forced drive controller includes a regulator information storage unit, which stores the voltage generation range information of each of the conventional drive regulator and the temporary drive regulator.

8. A memory device, comprising: Multiple word lines connect to multiple memory cells; The peripheral circuit selects a first word line from the plurality of word lines and performs a forced drive operation, wherein the forced drive operation sequentially applies a first voltage, a forced drive voltage, a first stable voltage, and a second stable voltage to the first word line. as well as The control logic circuit controls the peripheral circuit to execute the forced drive operation. The forced drive voltage and the first stable voltage applied to the first word line are provided from different regulators, and the first stable voltage and the second stable voltage are provided from different regulators.

9. The memory device according to claim 8, wherein, The forced drive voltage is one of underdrive voltage and overdrive voltage.

10. The memory device according to claim 8, wherein, The peripheral circuit includes the different regulators, which include: A conventional drive regulator generates the forced drive voltage and the second stable voltage; and A temporary drive regulator is used to generate the first stable voltage.

11. The memory device according to claim 10, wherein, When the conventional drive regulator that generates the forced drive voltage is switched to the temporary drive regulator, the temporary drive regulator generates the first stable voltage before the switch.

12. The memory device according to claim 10, wherein, When the temporary drive regulator that generates the first stable voltage is switched to the regular drive regulator, the regular drive regulator generates the second stable voltage before the switch.

13. The memory device according to claim 10, wherein, The control logic circuit includes a forced drive controller, which sets the temporary drive regulator by considering the voltage range of the first stable voltage and the voltage generation range information of each of the conventional drive regulator and the temporary drive regulator.

14. A method of operating a memory device, the method comprising: Select a word line from multiple word lines; as well as Perform a forced drive operation on the selected word line. The forced drive operation includes: Apply a forced drive voltage to the selected word line; and Apply a stable voltage to the selected word line. The forced drive voltage and the stable voltage applied to the selected word line are provided from different regulators.

15. The method according to claim 14, wherein, The forced drive voltage is one of underdrive voltage and overdrive voltage.

16. The method of claim 14, wherein, One of the forced drive voltage and the stable voltage is provided from a conventional drive regulator. The other of the forced drive voltage and the stable voltage is provided from the temporary drive regulator, and The conventional drive regulator and the temporary drive regulator are included in the different regulators.

17. The method according to claim 16, wherein, When the conventional drive regulator that generates the forced drive voltage is switched to the temporary drive regulator, the temporary drive regulator generates the stable voltage before the switch.

18. The method according to claim 16, wherein, When the temporary drive regulator that generates the forced drive voltage is switched to the conventional drive regulator, the conventional drive regulator generates the stable voltage before the switch.

19. The method of claim 16, further comprising: The temporary drive regulator is configured by taking into account the voltage range of the stable voltage, the voltage range of the forced drive voltage, and the voltage generation range information of each of the conventional drive regulator and the temporary drive regulator.

20. The method of claim 19, further comprising: Store the voltage generation range information for each of the conventional drive regulator and the temporary drive regulator.

21. A memory device, comprising: Multiple word lines connect to multiple memory cells; Multiple regulators generate a first voltage, a forced drive voltage, and a stable voltage for forced drive operation; as well as The line decoder sequentially applies the first voltage, the forced drive voltage, and the stable voltage generated by the plurality of regulators to the selected word line; The forced drive voltage and the stable voltage applied to the selected word line are provided from different regulators.

22. The memory device according to claim 21, wherein, The forced drive voltage is one of underdrive voltage and overdrive voltage.

23. The memory device of claim 21, wherein, The different regulators include: A conventional drive regulator generates one of the stable voltage and the forced drive voltage; and A temporary drive regulator generates another of the stable voltage and the forced drive voltage.

24. The memory device according to claim 23, wherein, When the conventional drive regulator that generates the forced drive voltage is switched to the temporary drive regulator, the temporary drive regulator generates the stable voltage before the switch.

25. The memory device according to claim 23, wherein, When the temporary drive regulator that generates the forced drive voltage is switched to the conventional drive regulator, the conventional drive regulator generates the stable voltage before the switch.

26. The memory device according to claim 23, wherein, The control logic circuit includes a forced drive controller, which sets the temporary drive regulator by considering the voltage range of the stable voltage, the voltage range of the forced drive voltage, and the voltage generation range information of each of the conventional drive regulator and the temporary drive regulator.

27. The memory device according to claim 26, wherein, The forced drive controller includes a regulator information storage unit, which stores voltage generation range information for each of the plurality of regulators.

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