Test package structure and test method

Abstract

The present application provides a test method, comprising: placing a test package structure on a control board, wherein the test package structure comprises: a substrate; a test die disposed on the substrate, and the test die comprises a capacitor element and a resistor element, wherein a capacitance value of the capacitor element and a resistance value of the resistor element are respectively same as a load capacitance and a load resistance of a terminal of a die of a semiconductor package structure; and a measurement point disposed on the substrate and between the capacitor element and the resistor element; measuring signal integrity at the measurement point of the test package structure; determining whether the signal integrity is acceptable; and bonding the semiconductor package structure to the control board when the signal integrity is acceptable. Based on this configuration, stability and efficiency of the test method can be improved.

Description

Technical Field

[0001] This invention relates to a test packaging structure and test method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of random access semiconductor memory that stores each bit of data in a single memory cell. DRAM is known for its high speed, high density, and excellent scalability. However, as DRAM production scales up, its manufacturing process becomes more difficult and more prone to defects. For example, some designs may limit the accuracy of signal integrity testing. Therefore, there is a need for reliable semiconductor device equipment and manufacturing methods. Summary of the Invention

[0003] An embodiment of the present invention provides a testing method, comprising: placing a test package structure on a control board, wherein the test package structure includes: a substrate; a test wafer disposed on the substrate, and the test wafer includes a capacitor element and a resistor element, wherein the capacitance value of the capacitor element and the resistance value of the resistor element are the same as the load capacitance and load resistance of the terminals of the semiconductor package structure wafer, respectively; and a measurement point disposed on the substrate and located between the capacitor element and the resistor element; measuring signal integrity at the measurement point of the test package structure; determining whether the signal integrity is acceptable; and when the signal integrity is acceptable, bonding the semiconductor package structure to the control board.

[0004] In some embodiments, the capacitance value of the capacitor element and the resistance value of the resistor element are adjustable.

[0005] In some embodiments, the method further includes adjusting the capacitance value of the capacitor element and the resistance value of the resistor element so that the capacitance value of the capacitor element and the resistance value of the resistor element are the same as the load capacitance and load resistance of the terminals of the semiconductor package structure, respectively.

[0006] In some embodiments, the top surface of the test wafer is higher than the top surface of the measurement point.

[0007] In some embodiments, the terminals of the wafer in the semiconductor package structure are covered by a packaging material.

[0008] In some embodiments, the test package structure further includes bumps, wherein the measurement points are exposed on opposite sides of the bumps.

[0009] In some embodiments, the test wafer and the bump are located on opposite sides of the substrate.

[0010] In some embodiments, the length of the transmission path between the measurement point of the test package structure and the control board is substantially the same as the length of the transmission path between the terminal of the wafer of the semiconductor package structure and the control board.

[0011] In some embodiments, the transmission path between the terminals of the wafer in the semiconductor package structure and the control board includes bumps, interconnect structures of the substrate, and bonding wires.

[0012] In some embodiments, the capacitor element and the resistor element are electrically connected at a measurement point.

[0013] In some embodiments, the method further includes removing the test package structure from the control board before bonding the semiconductor package structure to the control board.

[0014] In some embodiments, the method further includes: redesigning the wiring of the semiconductor package structure when the signal integrity is determined to be unacceptable.

[0015] In some embodiments, when the waveform of the signal detected by the measurement point of the self-test package structure is distorted, the signal integrity is determined to be unacceptable.

[0016] In some embodiments, when the waveform of the signal detected by the measurement point of the self-test package structure is different from the waveform of the input signal from the control board, the signal integrity is determined to be unacceptable.

[0017] In some embodiments, when the signal delay between the signal detected by the measurement point of the self-test package structure and the input signal from the control board exceeds a predetermined specification, the signal integrity is determined to be unacceptable.

[0018] An embodiment of the present invention provides a test package structure, comprising: a substrate; a test wafer disposed on the substrate, the test wafer including a first capacitor element and a first resistor element; and a measurement point disposed on the substrate and located between the first capacitor element and the first resistor element, wherein the measurement point is exposed.

[0019] In some embodiments, the first capacitor element and the first resistor element are respectively an adjustable capacitor and an adjustable resistor.

[0020] In some embodiments, the measurement point faces the direction opposite to that of the substrate.

[0021] In some embodiments, a bump is further included, wherein the measurement point is exposed on the opposite side of the bump.

[0022] In some embodiments, the system further includes a second capacitor element and a second resistor element, respectively located below the first capacitor element and the first resistor element, and above the substrate, wherein the second capacitor element and the second resistor element are electrically connected to the first capacitor element and the first resistor element. Attached Figure Description

[0023] A better understanding of the various aspects of the invention will be achieved by reading the following detailed description in conjunction with the accompanying drawings. Please note that, in accordance with industry standard practice, the various features in the drawings are not drawn to scale. In fact, for ease of explanation, the dimensions of the features may be arbitrarily enlarged or reduced.

[0024] Figure 1 This is a schematic diagram of a semiconductor device according to some embodiments of the present invention.

[0025] Figure 2 This is a schematic diagram of a memory unit according to some embodiments of the present invention.

[0026] Figures 3A to 3G This is a schematic diagram illustrating different steps in a semiconductor packaging structure manufacturing method according to some embodiments of the present invention.

[0027] Figures 4A to 4C This is a schematic diagram illustrating different steps of a test packaging structure manufacturing method according to some embodiments of the present invention.

[0028] Figure 5A This is a flowchart illustrating a method for testing a semiconductor package structure using a test package structure, based on certain embodiments of the present invention.

[0029] Figure 5B A schematic diagram showing the package structure set up on the control board for testing.

[0030] Figure 5C A schematic diagram showing the semiconductor package structure mounted on the control board.

[0031] Figure 6A This is a schematic diagram of a semiconductor packaging structure according to some embodiments of the present invention.

[0032] Figure 6B This is a schematic diagram of a test packaging structure according to some embodiments of the present invention. Detailed Implementation

[0033] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, some of which illustrate exemplary embodiments. However, this disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art. It is worth noting that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0034] It should be understood that although terms such as first, second, third, etc., may be used herein to describe various elements, components, regions, layers, and / or segments, these elements, components, regions, layers, and / or segments should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or segment from another element, component, region, layer, or segment. Therefore, the first element, component, region, layer, or segment discussed below may also be referred to as a second element, component, region, layer, or segment without departing from the teachings of this invention.

[0035] Additionally, for ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper,” and similar terms are used to describe the relationship of one element or feature to another, as illustrated in the figure. It should be understood that spatial relative terms are intended to cover different orientations of the device in use or operation beyond those shown in the figure. For example, if the device in the figure is flipped, an element described as “below” or “below” other elements or features would be positioned “above” other elements or features. Thus, the exemplary term “below” can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0036] As used herein, “approximately,” “about,” “roughly,” or “substantially” can generally mean within 20%, 10%, or 5% of a given value or range. The values ​​given herein are approximate, meaning that the terms “approximately,” “about,” “roughly,” or “substantially” can be inferred unless explicitly stated otherwise. However, those skilled in the art will recognize that the values ​​or ranges listed throughout the description are merely examples and can decrease or vary as integrated circuits shrink in size.

[0037] This document describes exemplary embodiments with reference to cross-sectional views, which are schematic diagrams of idealized exemplary embodiments (and intermediate structures). Therefore, variations in the illustrated shapes are expected due to, for example, manufacturing techniques and / or tolerances. Thus, the exemplary embodiments should not be construed as limited to the specific shapes of the areas shown herein, but rather include, for example, shape deviations due to manufacturing processes. For example, an injection area illustrated as rectangular will typically have circular or curved features and / or an injection concentration gradient at its edges, rather than a binary variation from the injection area to the non-injection area. Similarly, a buried area formed by injection can result in some injection in the area between the buried area and the surface through which the injection is carried out. Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device and are not intended to limit the scope of the invention.

[0038] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by those skilled in the art. It should also be understood that terms, such as those defined in common dictionaries, should be interpreted in accordance with their meaning in the relevant technical field, and should not be interpreted in an idealized or overly formalistic manner unless explicitly defined herein.

[0039] The exemplary embodiments will now be explained in detail with reference to the accompanying drawings.

[0040] Figure 1 This is a schematic diagram of a memory array according to some embodiments of the present invention. In some embodiments, the semiconductor device 10 includes a plurality of memory cells 11 arranged in a rectangular matrix. Figure 1 A simple 4x4 cell matrix example is shown; however, other memory matrices may contain thousands of cells in height and width. In some embodiments, the semiconductor device 10 may be dynamic random access memory (dynamic RAM or DRAM).

[0041] Each row of memory units 11 is connected by word lines 20, while each column of memory units 11 is connected by bit lines 30. Multiple word lines 20 can extend horizontally and are parallel to each other. Furthermore, the word lines 20 can be separated by approximately equal spacing. On the other hand, multiple bit lines 30 can extend vertically. Similar to the word lines 20, the bit lines 30 are parallel to each other and can also be separated by approximately equal spacing.

[0042] Figure 2 This is a schematic diagram of a memory unit according to some embodiments of the present invention. Specifically, Figure 2 for Figure 1A partial enlarged view. In some embodiments, the memory cell 11 includes an access transistor 11T and a storage capacitor 11C electrically connected to the access transistor 11T.

[0043] In some embodiments, the access transistor 11T is an NMOS transistor and is configured to control the channel to the memory cell 11 by turning its gate on or off. In some embodiments, the storage capacitor 11C is configured to store information based on the state of the charge stored within it. When the storage capacitor 11C is in an empty state (i.e., no charge), it represents a logic value of 0; when the storage capacitor 11C is in a fully charged state, it represents a logic value of 1. The memory cell 11 stores bit data through the two extreme states of charge in the storage capacitor 11C.

[0044] In some embodiments, the word line 20 connected to the access transistor 11T is used to control its gate by applying a voltage to the gate of the access transistor 11T. In some embodiments, the bit line 30 is configured perpendicularly to the word line 20 and is also connected to the access transistor 11T. When the gate of the access transistor 11T is turned on, the access transistor 11T connects the storage capacitor 11C to the bit line 30, so that the logic value stored in the storage capacitor 11C can be read on the bit line 30.

[0045] Figures 3A to 3G This is a schematic diagram illustrating different steps of a semiconductor packaging structure manufacturing method according to some embodiments of the present invention. Specifically, Figures 3A to 3G This is a schematic cross-sectional view of a semiconductor package structure 100 according to a partial embodiment. A method for manufacturing the semiconductor package structure 100 according to a partial embodiment will be described below.

[0046] Reference Figure 3A A carrier member 110 is provided. In some embodiments, the carrier member 110 may include a substrate 112 and an interconnect structure 114 located within the substrate 112. In some embodiments, the carrier member 110 may be a printed circuit board (PCB).

[0047] In some embodiments, the interconnect structure 114 may include a bottom conductive line 114a located on the bottom surface of the substrate 112, a top conductive line 114b located on the top surface of the substrate 112, and an internal circuit 114c extending through the substrate 112 and electrically connecting the bottom conductive line 114a and the top conductive line 114b.

[0048] In some embodiments, the conductive lines 114a, 114b and the internal circuit 114c may contain various conductive materials, such as metals, metal alloys and / or solderable materials, such as gold (Au), copper (Cu), aluminum (Al).

[0049] Reference Figure 3BAn opening 125 is formed in the support member 110. In some embodiments, the opening 125 may be formed, for example, by a drilling process, to penetrate the support member 110. In some embodiments, the shape of the opening 125 may be square or rectangular when viewed from a top viewpoint, but is not limited thereto. The function of the opening 125 is to facilitate wiring connections between the support member 110 and subsequently formed elements.

[0050] Reference Figure 3C The wafer 130 is secured to the support member 110 using an adhesive material 120. In some embodiments, the adhesive material 120 may be cured by heating, ultraviolet light, or room temperature, depending on its type, to strengthen the adhesion support between the wafer 130 and the support member 110. In some embodiments, the wafer 130 may be a memory device, such as a DRAM wafer.

[0051] In some embodiments, the wafer 130 may include an active surface AS and a back surface BS disposed opposite to and spaced apart from the active surface AS. More specifically, a plurality of terminals 132 are disposed on the active surface AS, and these terminals 132 are exposed through an opening 125 when the wafer 130 is attached to the carrier member 110. That is, the wafer 130 is attached to the carrier member 110 face-down.

[0052] In some embodiments, the terminals 132 may be signal inputs, signal outputs, power inputs, or other suitable terminals of the wafer 130. In some embodiments, the signals may be DQ, DQS, CLK, CMD / ADDR. In some embodiments, the back surface BS of the wafer 130 is a passive surface. That is, the back surface BS of the wafer 130 may not have conductive terminals (e.g., terminal 132).

[0053] Reference Figure 3D A wire bonder can be used to bond the bonding wires 134 from the terminals 132 of the wafer 130 to the corresponding bottom conductive lines 114a of the carrier member 110, thereby forming an electrical connection between the terminals 132 of the wafer 130 and the carrier member 110. In some embodiments, the connection of these bonding wires 134 may include any known method, such as ultrasonic bonding, thermo-press bonding, or thermo-ultrasonic bonding.

[0054] In some embodiments, the bonding wires 134 may pass through the opening 125 of the support member 110. In some embodiments, the bonding wires 134 may comprise various conductive materials, such as metals, metal alloys, and / or other suitable materials, such as gold (Au), copper (Cu), aluminum (Al).

[0055] Reference Figure 3EA first encapsulation material 140 is formed on the carrier member 110 to encapsulate the wafer 130. In some embodiments, the first encapsulation material 140 can be formed by depositing a molding compound, such as a solid thermosetting resin, on the carrier member 110. Heat and / or pressure can then be applied to the molding compound. When it becomes liquid, the molding compound becomes fluid and can be propelled by capillary action and / or pressure flow. The fluid molding compound can cover the upper surfaces of the wafer 130, the adhesive material 120, and the carrier member 110, as well as the side surfaces of the wafer 130 and the adhesive material 120. Subsequently, when the molding compound cools and returns to a solid state, the first encapsulation material 140 is formed. The first encapsulation material 140 protects the wafer 130 and the carrier member 110 from external environmental influences, such as moisture, dust, and mechanical damage.

[0056] Reference Figure 3F Multiple bumps 150 are disposed on the bottom conductive line 114a of the support member 110. In some embodiments, the bumps on the support member 110 may be formed by ball grid array (BGA) technology, which utilizes an array of metal balls as a means of providing external electrical connections.

[0057] First, solder paste (not shown) is applied to the bottom conductive line 114a. In some embodiments, the solder paste can be applied by brushing, spraying, stenciling, or other methods. The solder paste typically contains acidic components to remove the oxide layer barrier and provides adhesion to help prevent movement during the process. Once the solder paste is applied, the bumps 150 can be brought into contact with the solder paste using, for example, a pick-and-place operation, but any suitable placement method can also be used. After the bumps 150 are in contact with the solder paste, a reflow process can be performed, heating the solder paste to a suitable predetermined temperature. This reflow process allows the bumps 150 to form a physical bond with the bottom conductive line 114a through the solder paste. In some embodiments, the solder paste not only provides a soldering function but also serves as a conductive medium between the bumps 150 and the support member 110. Therefore, the bumps 150 can form an electrical connection with the support member 110 through the solder paste.

[0058] Next, a second encapsulation material 160 is formed on the carrier member 110 to encapsulate the terminals 132 and bonding wires 134 of the chip 130. The bonding wires 134, the terminals 132 of the chip 130, and the exposed bottom surface of the chip 130 (which is relatively fragile) are preferably covered and encapsulated by the second encapsulation material 160.

[0059] In some embodiments, the second encapsulation material 160 can be formed by injecting an underfill compound into the opening 125. The underfill compound covers the exposed bottom surface of the wafer 130 and encapsulates the package terminals 132 and bonding wires 134. In some embodiments, the second encapsulation material 160 may be made of the same material as the first encapsulation material 140. In other embodiments, the second encapsulation material 160 may be made of a different material than the first encapsulation material 140. In some embodiments, the second encapsulation material may be made of a material such as a plastic material (e.g., epoxy resin).

[0060] The second encapsulation material 160 is used to protect the bonding wires 134 from mechanical or electrical impacts. In some embodiments, the second encapsulation material 160 contacts the carrier member 110, the adhesive material 120, and the wafer 130, but does not contact the bumps 150. In some embodiments, forming the second encapsulation material 160 may enclose the terminals 132. In some embodiments, forming the second encapsulation material 160 may also be performed before the bumps 150 are mounted to the carrier member 110. Once the second encapsulation material 160 is formed, the fabrication of the semiconductor package structure 100 is substantially complete.

[0061] Reference Figure 3G The semiconductor package structure 100 can be attached to a control board, such as a printed circuit board (PCB) 170. In some embodiments, the semiconductor package structure 100 can be mounted to the PCB 170 using surface mount technology (SMT). For example, the bumps 150 are first aligned with corresponding bonding positions on the upper surface of the PCB 170. Next, the semiconductor package structure 100 is placed on the PCB 170 so that the bumps 150 contact the upper surface of the PCB 170. Subsequently, a reflow process can be performed to molten the bumps 150. Thus, the molten bumps 150 can adhere to the upper surface of the PCB 170. The surface tension of the bumps 150 allows them to maintain their correct position on the PCB 170 before cooling and solidifying.

[0062] In some embodiments, PCB 170 may be a control circuit board. For example, when chip 130 is a memory chip, PCB 170 may be a memory controller circuit board. PCB 170 can provide various control signals to terminals 132 of chip 130. In some embodiments, signals transmitted from PCB 170 to chip 130 may be distorted or delayed after transmission. For example, such as... Figure 3G As shown by the dashed line, the signal transmitted from PCB 170 to chip 130 can be transmitted via transmission path P1.

[0063] In this embodiment, the transmission path P1 starts from PCB 170, passes sequentially through bump 150, bottom conductive line 114a, internal circuit 114c, top conductive line 114b, internal circuit 114c, bottom conductive line 114a, bonding wire 134, and finally to terminal 132.

[0064] Because the second encapsulation material 160 completely covers the terminals 132, probes may have difficulty contacting these terminals 132 to measure the signal integrity of the chip 130. Therefore, a test package structure 200 can be fabricated to simulate the behavior of the semiconductor package structure 100 and perform signal integrity testing.

[0065] Figures 4A to 4C This is a schematic diagram illustrating different steps of a test packaging structure manufacturing method according to some embodiments of the present invention. Specifically, Figures 4A to 4C This is a cross-sectional schematic diagram of a test package structure 200 according to a partial embodiment. The manufacturing method of the test package structure 200 according to a partial embodiment will be described below.

[0066] Reference Figure 4A A support member 210 is provided. In some embodiments, the support member 210 may include a substrate 212 and an interconnect structure 214 located within the substrate 212.

[0067] In some embodiments, the interconnect structure 214 may include a bottom conductive line 214a located on the bottom surface of the substrate 212, a top conductive line 214b located on the top surface of the substrate 112, and an internal circuit 214c extending through the substrate 212 and electrically connecting the bottom conductive line 214a and the top conductive line 214b. In some embodiments, the conductive lines 214a, 214b and the internal circuit 214c may contain various conductive materials, such as metals, metal alloys and / or solderable materials such as gold (Au), copper (Cu), aluminum (Al).

[0068] In some embodiments, the carrier member 210 of the test package structure 200 may have a similar circuit design to the carrier member 110 of the semiconductor package structure 100, but with different wiring methods.

[0069] Reference Figure 4B A capacitor element 220 and a resistor element 222 are disposed on the conductive line 214b of the support member 210. Specifically, the capacitor element 220 and the resistor element 222 are respectively disposed on opposite sides of the top conductive line 214b of the support member 210. Therefore, the central region of the top conductive line 214b remains exposed. In some embodiments, the capacitor element 220 and the resistor element 222 are electrically connected in parallel. In some embodiments, the exposed area of ​​the top conductive line 214b can be used as a measurement point MP for testing the package structure 200.

[0070] In some embodiments, the test package structure 200 may exhibit electrical behavior similar to that of the wafer 130 of the semiconductor package structure 100. In some embodiments, the test package structure 200 has substantially the same passive characteristics as the wafer 130 of the semiconductor package structure 100. For example, each set of capacitor elements 220 and resistor elements 222 has the same load characteristics as the corresponding terminals 132 of the wafer 130.

[0071] More specifically, after the chip 130 is manufactured, each terminal 132 may have a specific load resistance and load capacitance; and each set of capacitor elements 220 and resistor elements 222 may have resistance and capacitance values ​​that are approximately the same as those of the corresponding terminals 132 in the chip 130. Therefore, in terms of the overall signal load, the combination of capacitor elements 220 and resistor elements 222 will not produce a significant difference from the chip 130. The combination of capacitor elements 220 and resistor elements 222 can be referred to as test chip 224.

[0072] In some embodiments, the capacitor element 220 is an adjustable capacitor, and the resistor element 222 is an adjustable resistor. That is, the capacitance value of the capacitor element 220 and the resistance value of the resistor element 222 can be adjusted to the same values ​​as the load resistance and load capacitance of the corresponding terminal 132 in the wafer 130.

[0073] More specifically, the measurement point MP can serve as a signal integrity (SI) measurement point. In some embodiments, the measurement point MP can be probed to measure the signal quality (e.g., DQ, DQS, CLK, CMD / ADDR) of the test chip 224 to test whether the test chip 224 meets specific electrical requirements. In some embodiments, the signal measured at the measurement point MP is very close to the signal of the test chip 224 and can approximately correspond to the signal of the corresponding terminal 132 of the chip 130 in the semiconductor package structure 100.

[0074] In some embodiments, the measurement point MP is exposed. That is, the measurement point MP faces upward and is exposed to the elements. Figure 4C The formed bump 250 is on the opposite side. The exposure of this measurement point MP facilitates probe contact and supports more accurate signal quality measurements.

[0075] In some embodiments, the upper surface of the measurement point MP may not be coplanar with the upper surface of the test wafer 224 (i.e., the upper surfaces of the capacitor element 220 and the resistor element 222). In some embodiments, the upper surface of the measurement point MP is lower than the upper surface of the test wafer 224.

[0076] Reference Figure 4CMultiple bumps 250 are disposed on the bottom conductive line 214a of the support member 210. In some embodiments, the bumps 250 are formed on the support member 210 by ball grid array (BGA) technology, which uses an array of metal balls as a means of providing external electrical connections.

[0077] First, solder paste (not shown) is applied to the bottom conductive line 214a. In some embodiments, the solder paste can be applied by brushing, spraying, stenciling, or other methods. The solder paste typically contains acidic components to remove the oxide layer barrier and has adhesive properties to help prevent movement during the process. Once the solder paste is in place, the bumps 250 can be brought into physical contact with the solder paste using, for example, a pick-and-place operation, but any suitable placement method can also be used. After the bumps 250 are in contact with the solder paste, a reflow process can be performed, heating the solder paste to a suitable predetermined temperature. This reflow process forms a physical bond between the bumps 250 and the bottom conductive line 214a through the solder paste. In some embodiments, the solder paste not only provides a soldering function but also serves as a conductive medium between the bumps 250 and the support member 210. Therefore, the bumps 250 can form an electrical connection with the support member 210 through the solder paste.

[0078] In some embodiments, the bumps 250 may be bumps, solder pillars, copper pillars with solder caps, or other suitable conductive bonding structures. The bumps 250 may form an electrical connection with the interconnect structure 214 within the support member 210.

[0079] The design of the transmission path P2 of the test package structure 200 is to simulate the design of the transmission path P1 of the semiconductor package structure 100. Therefore, the signal measured at the measurement point MP of the test package structure 200 is approximately the same as the signal measured at the terminal 132 of the semiconductor package structure 100.

[0080] In some embodiments, the length of the transmission path P2 between the bump 250 and the measurement point MP in the test package structure 200 (e.g., the length from the bump 250 to the bottom conductive line 214a, to the internal circuitry 214c, to the top conductive line 214b, and then to the measurement point MP) and Figure 3G The transmission path P1 shown has approximately the same length.

[0081] In some embodiments, the test package structure 200 does not contain active components, such as memory devices, logic devices, or other possible active components.

[0082] Figure 5A This is a flowchart illustrating a method for testing semiconductor package structures using a test package structure, according to certain embodiments of the present invention. Specifically, Figure 5AA method M10 is described for testing a semiconductor package structure 100 using a test package structure 200. The method M10 may include the following steps: steps S100, S200, S300, S400, S450 and S500.

[0083] This document provides operational flows for various embodiments. The order in which some or all of the operations are described should not be construed as implying a necessary sequential dependency. Based on this description, it is understood that other different arrangements may also be used. Furthermore, it should be understood that not all embodiments necessarily include all operational steps, and some embodiments may not require all operations.

[0084] Method M10 begins with step S100, in which the test package structure is placed on the control board. Figure 5B This is a schematic diagram showing a test package structure, according to some embodiments of the present invention, placed on a control board. (Refer to...) Figure 5B The test package structure 200 can be placed on a control board, such as PCB 170. In some embodiments, the PCB 170 can be an external circuit board used to generate and transmit electrical signals (such as logic signals, commands, or timing pulses) to the chip.

[0085] In some embodiments, when the capacitor element 220 and the resistor element 222 are respectively an adjustable capacitor and an adjustable resistor, the method may include adjusting the capacitance and resistance values ​​of the capacitor element 220 and the resistor element 222 so that they are the same as the load capacitance and load resistance of the corresponding terminal 132 of the wafer 130, respectively. In some embodiments, the load capacitance and load resistance of the corresponding terminal 132 of the wafer 130 can be obtained through the manufacturing specifications of the wafer 130.

[0086] Method M10 then proceeds to step S200, where signals are input to the test package structure via an operational control board. Specifically, the operational PCB 170 inputs signals to the test package structure 200. In some embodiments, these signals may be DQ, DQS, CLK, or CMD / ADDR.

[0087] In some embodiments, the signal is transmitted along the transmission path P2 of the test package structure 200. The transmission path P2 starts from the bump 250, passes sequentially through the bottom conductive line 214a, the internal circuit 214c, the top conductive line 214b, and finally reaches the measurement point MP, where signal integrity measurement can be performed.

[0088] Method M10 continues to step S300, where signal integrity measurement is performed at the measurement point of the test package structure. Specifically, signal integrity measurement can be performed at the measurement point MP of the test package structure 200. In some embodiments, the measurement point MP can be probed to measure the signal quality input to the test package structure 200 in step S200.

[0089] Method M10 proceeds to step S400, where it is determined whether the signal integrity is acceptable. Specifically, the signal quality of the test chip 224 in the test package structure 200 is determined to test whether the test chip 224 meets specific electrical requirements. In some embodiments, the signal measured at measurement point MP is very close to the signal of the test chip 224 and can approximate the signal of the chip 130 in the semiconductor package structure 100. Whether the signal integrity is acceptable can be determined according to a preset specification.

[0090] In some embodiments, signal integrity is deemed acceptable when the signal waveform detected by the measurement point MP is not distorted. In some embodiments, signal integrity is deemed acceptable when the signal waveform detected by the measurement point MP is identical to the input signal waveform from the PCB 170. In some embodiments, signal integrity is deemed acceptable when the delay between the signal detected by the measurement point MP and the input signal from the PCB 170 falls within a preset specification range.

[0091] If method M10 enters the "Yes" process, it proceeds to step S500 to redesign the integrated circuit (IC). Specifically, the test package structure can be removed from the control board. For example, if the signal integrity of the test chip 224 of the test package structure 200 is determined to be acceptable, the test package structure 200 can be removed from the PCB 170.

[0092] Next, the semiconductor package structure can be bonded to the control board. Figure 5C This is a schematic diagram showing a semiconductor package structure placed on a control board. (Refer to...) Figure 5C The semiconductor package structure 100, which has been previously tested by the test package structure 200, can be bonded to the control board. In some embodiments, the PCB 170 bonded to the semiconductor package structure 100 can be the same PCB 170 previously bonded to the test package structure 200.

[0093] In some embodiments, the length of the transmission path P1 of the semiconductor package structure 100 is approximately the same as the length of the transmission path P2 of the test package structure 200. In principle, the signal integrity of the semiconductor package structure 100 should also be acceptable.

[0094] Conversely, if method M10 enters the "No" process in step S400, it proceeds to step S450 to redesign the wiring of the semiconductor package structure. Specifically, if the signal integrity of the test chip 224 of the test package structure 200 is determined to be unacceptable, it may be necessary to redesign the wiring of the interconnect structure 114 of the semiconductor package structure 100.

[0095] In some embodiments, signal integrity is deemed unacceptable when the signal waveform detected by the measurement point MP is distorted. In some embodiments, signal integrity is deemed unacceptable when the signal waveform detected by the measurement point MP differs from the input signal waveform from the PCB 170. In some embodiments, signal integrity is deemed unacceptable when the delay between the signal detected by the measurement point MP and the input signal from the PCB 170 exceeds a preset specification range.

[0096] Figure 6A This is a schematic diagram of a semiconductor packaging structure according to other embodiments of the present invention. Specifically, Figure 6A The semiconductor package structure 101 is shown according to other embodiments of the present invention. Figure 6A The semiconductor package structure 101 shown is Figure 3G The semiconductor package structure shown is similar to 100, so the same components will be identified by the same number, and the relevant details will not be repeated for the sake of simplicity.

[0097] Reference Figure 6A The semiconductor package structure 101 includes stacked wafers 130a, 130b, and 130c, wherein each wafer 130a, 130b, and 130c includes terminals 132a, 132b, and 132c, respectively. More specifically, terminal 132a of wafer 130a is connected to bonding wire 134, terminal 132b of wafer 130b is connected to wafer 130a, and terminal 132c of wafer 130c is connected to wafer 130b.

[0098] In some embodiments, terminals 132a, 132b, and 132c are electrically connected to each other via TSVs (through-silicon vias) 134a, 134b, and 134c within wafers 130a, 130b, and 130c, respectively. In some embodiments, the TSVs 134a, 134b, and 134c comprise conductive material penetrating wafers 130a, 130b, and 130c.

[0099] In some embodiments, when the semiconductor package structure 101 is placed on a PCB (e.g. Figure 5C When transmitted from the PCB to the chip 130 on the PCB 170 shown, the signal may be distorted or delayed after transmission. For example, as Figure 6A As shown by the dashed line, the signal transmitted from the PCB to the chip 130 can be transmitted via the transmission path P3.

[0100] In this embodiment, the transmission path P3 starts from the PCB (not shown) and sequentially passes through bump 150, bottom conductive line 114a, internal circuit 114c, top conductive line 114b, internal circuit 114c, bottom conductive line 114a, bonding wire 134, terminal 132a, TSV 134a, terminal 132b, TSV 134b, terminal 132c, and finally to TSV 134c.

[0101] Figure 6B This is a schematic diagram of a test packaging structure according to other embodiments of the present invention. Specifically, Figure 6B The test package structure 201 is shown as another embodiment of the present invention. Figure 6B The test package structure 201 shown is... Figure 4C The test package structure shown is similar to 200, so the same components will be identified by the same number, and the relevant details will not be repeated for the sake of simplicity.

[0102] Reference Figure 6B The test package structure 201 includes a first capacitor element 220a and a first resistor element 222a located in the first layer L1, a second capacitor element 220b and a second resistor element 222b located above the first layer L1 and in the second layer L2, and a third capacitor element 220c and a third resistor element 222c located above the second layer L2 and in the third layer L3. The combination of capacitor elements 220a, 220b, 220c and resistor elements 222a, 222b, 222c can be referred to as test wafer 224.

[0103] In some embodiments, the first capacitor element 220a and the first resistor element 222a are covered by a first passivation layer 226a. In some embodiments, the second capacitor element 220b and the second resistor element 222b are covered by a second passivation layer 226b formed on the first passivation layer 226a. In some embodiments, the first passivation layer 226a and the second passivation layer 226b are made of a dielectric material.

[0104] In some embodiments, the top conductive line 214b includes a portion 214b1 formed on the first passivation layer 226a, and this portion 214b1 is electrically connected to the second capacitor element 220b and the second resistor element 222b. In some embodiments, the top conductive line 214b also includes another portion 214b2 formed on the second passivation layer 226b, and this portion 214b2 is electrically connected to the third capacitor element 220c and the third resistor element 222c.

[0105] In some embodiments, a portion 214b2 of the top conductive line 214b, the third capacitor element 220c, and the third resistor element 222c are exposed; in contrast, the first capacitor element 220a, the first resistor element 222a, the second capacitor element 220b, and the second resistor element 222b are embedded in the first passivation layer 226a or the second passivation layer 226b.

[0106] In some embodiments, each pair of capacitor elements 220a, 220b, 220c and their corresponding resistor elements 222a, 222b, 222c are electrically connected in parallel. In some embodiments, the exposed area of ​​a portion 214b2 of the top conductive line 214b can be used as a measurement point MP for testing the package structure 201.

[0107] In some embodiments, the test package structure 201 may electrically exhibit behavior similar to that of the wafer 130 of the semiconductor package structure 101. In some embodiments, the test package structure 201 has substantially the same passive characteristics as the wafer 130 of the semiconductor package structure 101. For example, the combination of capacitor element 220a and resistor element 222a has the same load characteristics as the corresponding terminal 132a of the wafer 130; the combination of capacitor element 220b and resistor element 222b has the same load characteristics as the corresponding terminal 132b of the wafer 130; and the combination of capacitor element 220c and resistor element 222c has the same load characteristics as the corresponding terminal 132c of the wafer 130.

[0108] More specifically, after the chip 130 is manufactured, each of its terminals 132a, 132b, and 132c may have specific load resistance and load capacitance. Similarly, each combination of capacitor elements 220a, 220b, and 220c with its corresponding resistor elements 222a, 222b, and 222c may have resistance and capacitance values ​​approximately the same as those of the corresponding terminals 132a, 132b, and 132c on the chip 130. Therefore, in terms of overall signal load, the combinations of capacitor elements 220a, 220b, and 220c with resistor elements 222a, 222b, and 222c will not produce significant differences compared to the chip 130.

[0109] In some embodiments, capacitors 220a, 220b, and 220c are all adjustable capacitors, and resistors 222a, 222b, and 222c are all adjustable resistors. That is, the capacitance values ​​of capacitors 220a, 220b, and 220c, and the resistance values ​​of resistors 222a, 222b, and 222c, can be adjusted to the same values ​​as the load resistance and load capacitance of the terminals 132a, 132b, and 132c corresponding to the wafer 130.

[0110] More specifically, the measurement point MP can serve as a signal integrity (SI) measurement point. In some embodiments, the measurement point MP can be probed to measure the signal quality (e.g., DQ, DQS, CLK, CMD / ADDR) of the test chip 224 to test whether the test chip 224 meets specific electrical requirements. In some embodiments, the signal measured at the measurement point MP is very close to the signal of the test chip 224 and can approximate the signal of the corresponding terminal 132c of the chip 130 in the semiconductor package structure 101.

[0111] In some embodiments, the measurement point MP is exposed. That is, the measurement point MP faces upward and is exposed on the side opposite to the bump 250. The exposure of the measurement point MP facilitates probe contact and supports more accurate signal quality measurements.

[0112] In some embodiments, the upper surface of the measurement point MP may not be coplanar with the upper surface of the test wafer 224 (i.e., the upper surfaces of the capacitor element 220c and the resistor element 222c). In some embodiments, the upper surface of the measurement point MP is lower than the upper surface of the test wafer 224.

[0113] The design of the transmission path P4 of the test package structure 201 is to simulate the design of the transmission path P3 of the semiconductor package structure 101. Therefore, the signal measured at the measurement point MP of the test package structure 201 is approximately the same as the signal measured at the terminal 132c of the semiconductor package structure 101.

[0114] In some embodiments, the length of the transmission path P4 between the bump 250 and the measurement point MP in the test package structure 201 (e.g., the length from the bump 250 to the bottom conductive line 214a, to the internal circuit 214c, to the top conductive line 214b, to the internal circuit 214c, to a portion 214b1 of the top conductive line 214b, to the internal circuit 214c, and then to a portion 214b2 of the top conductive line 214b or the measurement point MP) and Figure 6A The transmission path P3 shown has approximately the same length.

[0115] In some embodiments, the test package structure 201 does not contain active components, such as memory devices, logic devices, or other possible active components.

[0116] Figure 5A The method M10 shown for testing semiconductor package structures using test package structures can also be applied to... Figure 6A The semiconductor package structure 101 shown and Figure 6B The test package structure 201 is shown.

[0117] Although the invention has been described in considerable detail with reference to certain embodiments, other embodiments may exist. Therefore, the spirit and scope of the appended claims should not be limited to the embodiments described herein.

[0118] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of this disclosure. In view of the foregoing, the present invention is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims.

[0119] [Symbol Explanation] 10: Semiconductor devices 11: Memory Unit 11T: Access Transistor 11C: Storage capacitor 20: Character Line 30: Bit line 100: Semiconductor Packaging Structure 101: Semiconductor Packaging Structure 110: Load-bearing components 112: Substrate 114: Interconnection Structure 114a: Conductive wire 114b: Conductive wire 114c: Internal circuitry 120: Adhesive material 125: Opening 130: Chip 130a: Chip 130b: Chip 130c: Chip 132: Terminal 132a: terminal 132b: terminal 132c: terminal 134: Bond wire 134a, 134b, 134c: TSV 140: First packaging material 150: Bump 160: Second packaging material 170: Printed Circuit Board (PCB) 200: Test package structure 201: Test Package Structure 210: Load-bearing components 212: Substrate 214: Interconnection Structure 214a: Conductive wire 214b: Conductive wire 214b1, 214b2: Partial 214c: Internal circuitry 220, 220a, 220b, 220c: Capacitor components 222, 222a, 222b, 222c: Resistive elements 224: Test chip 226a: Passivation layer 226b: Passivation layer 250: Bump BS: Back AS: Active Surface MP: Measurement point P1, P2, P3, P4: Transmission paths L1, L2, L3: Hierarchical levels M10: Method S100, S200, S300, S400, S450, S500: Steps.

Claims

1. A testing method, characterized in that, include: The test package structure is placed on the control board, wherein the test package structure includes: substrate; A test chip is disposed on the substrate, and the test chip includes a capacitor element and a resistor element, wherein the capacitance value of the capacitor element and the resistance value of the resistor element are the same as the load capacitance and load resistance of the terminals of the semiconductor package structure, respectively; and The measurement point is disposed on the substrate and located between the capacitor element and the resistor element; The signal integrity is measured at this measurement point of the test package structure; Determine whether the integrity of the signal is acceptable; and When the signal integrity is acceptable, the semiconductor package structure is bonded to the control board.

2. The method according to claim 1, wherein the capacitance value of the capacitor element and the resistance value of the resistor element are adjustable.

3. The method according to claim 2, further comprising adjusting the capacitance value of the capacitor element and the resistance value of the resistor element, such that the capacitance value of the capacitor element and the resistance value of the resistor element are the same as the load capacitance and the load resistance of the terminal of the wafer of the semiconductor package structure, respectively.

4. The method of claim 1, wherein the top surface of the test wafer is higher than the top surface of the measurement point.

5. The method of claim 1, wherein the terminal of the wafer in the semiconductor package structure is covered by a packaging material.

6. The method of claim 1, wherein the test package structure further includes a bump, wherein the measurement point is exposed on the opposite side of the bump.

7. The method of claim 6, wherein the test wafer and the bump are located on opposite sides of the substrate.

8. The method of claim 1, wherein the length of the transmission path between the measurement point of the test package structure and the control board is substantially the same as the length of the transmission path between the terminal of the wafer of the semiconductor package structure and the control board.

9. The method of claim 8, wherein the transmission path between the terminal of the wafer of the semiconductor package structure and the control board includes bumps, interconnection structures of the substrate, and bonding wires.

10. The method of claim 1, wherein the capacitive element and the resistive element are electrically connected through the measurement point.

11. The method of claim 1, further comprising: The test package structure is removed from the control board before it is bonded to the control board.

12. The method of claim 1, further comprising: When the signal integrity is deemed unacceptable, the wiring of the semiconductor package structure is redesigned.

13. The method of claim 12, wherein when the waveform of the signal detected from the measurement point of the test package structure is distorted, the signal integrity is determined to be unacceptable.

14. The method of claim 12, wherein when the waveform of the signal detected from the measurement point of the test package structure is different from the waveform of the input signal from the control board, the signal integrity is determined to be unacceptable.

15. The method of claim 12, wherein when the signal delay between the signal detected at the measurement point of the test package structure and the input signal from the control board exceeds a predetermined specification, the signal integrity is determined to be unacceptable.

16. A test packaging structure, characterized in that, include: substrate; The test chip is disposed on the substrate, and the test chip includes a first capacitor element and a first resistor element; as well as A measurement point is disposed on the substrate and located between the first capacitor element and the first resistor element, wherein the measurement point is exposed.

17. The test package structure according to claim 16, wherein the first capacitor element and the first resistor element are respectively an adjustable capacitor and an adjustable resistor.

18. The test package structure of claim 16, wherein the measurement point faces a direction opposite to that of the substrate.

19. The test package structure of claim 16, further comprising a bump, wherein the measurement point is exposed on the opposite side of the bump.

20. The test package structure according to claim 16, further comprising a second capacitor element and a second resistor element, respectively located below the first capacitor element and the first resistor element, and above the substrate, wherein the second capacitor element and the second resistor element are electrically connected to the first capacitor element and the first resistor element.

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